Searched refs:reg3 (Results 1 - 25 of 30) sorted by relevance

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/external/linux-tools-perf/perf-3.12.0/arch/arm/lib/
H A Dmemcpy.S23 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
24 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
27 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
28 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
39 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
40 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/external/valgrind/main/none/tests/s390x/
H A Dcksm.c27 register uint64_t reg3 asm("3") = len;
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
36 len = reg3;
/external/pixman/pixman/
H A Dpixman-android-neon.S93 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
98 bilinear_load_8888 reg3, reg4, tmp2
99 vmull.u8 acc2, reg3, d28
H A Dpixman-arm-neon-asm.h92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits variable
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]! variable
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]! variable
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand variable
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]!
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand variable
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&]!
H A Dpixman-arm-simd-asm.h99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0 variable
105 op&r&cond WK&reg3, [base], #4 variable
107 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base variable
129 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
H A Dpixman-arm-neon-asm-bilinear.S109 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
114 bilinear_load_8888 reg3, reg4, tmp2
115 vmull.u8 acc2, reg3, d28
130 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
142 convert_0565_to_x888 acc2, reg3, reg2, reg1
143 vzip.u8 reg1, reg3
145 vzip.u8 reg3, reg4
149 vmull.u8 acc2, reg3, d28
H A Dpixman-arm-simd-asm.S374 .macro over_8888_8888_check_transparent numbytes, reg0, reg1, reg2, reg3
381 teqeq WK&reg3, #0
H A Dpixman-arm-neon-asm.S2868 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
2873 bilinear_load_8888 reg3, reg4, tmp2
2874 vmull.u8 acc2, reg3, d28
2889 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
2901 convert_0565_to_x888 acc2, reg3, reg2, reg1
2902 vzip.u8 reg1, reg3
2904 vzip.u8 reg3, reg4
2908 vmull.u8 acc2, reg3, d28
/external/vixl/src/a64/
H A Dmacro-assembler-a64.cc1416 const Register& reg3,
1418 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1428 const FPRegister& reg3,
1430 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1447 const Register& reg3,
1449 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1456 const FPRegister& reg3,
1458 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
1465 const CPURegister& reg3,
1470 const CPURegister regs[] = {reg1, reg2, reg3, reg
[all...]
H A Dassembler-a64.h283 const CPURegister& reg3 = NoReg,
297 const CPURegister& reg3 = NoCPUReg,
310 CPURegister reg3 = NoCPUReg,
312 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
314 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
H A Dmacro-assembler-a64.h1321 const Register& reg3 = NoReg,
1325 const FPRegister& reg3 = NoFPReg,
1335 const Register& reg3 = NoReg,
1339 const FPRegister& reg3 = NoFPReg,
1343 const CPURegister& reg3 = NoCPUReg,
H A Dassembler-a64.cc2246 const CPURegister& reg3, const CPURegister& reg4,
2255 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
2283 const CPURegister& reg3, const CPURegister& reg4,
2289 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
2245 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
2282 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
/external/chromium_org/third_party/skia/gm/
H A Dbitmaprect.cpp247 static skiagm::GMRegistry reg3(MyFactory3);
H A Dgradients.cpp454 static GMRegistry reg3(MyFactory3);
H A Dgradients_2pt_conical.cpp380 static GMRegistry reg3(MyFactory3);
/external/skia/gm/
H A Dbitmaprect.cpp247 static skiagm::GMRegistry reg3(MyFactory3);
H A Dgradients.cpp454 static GMRegistry reg3(MyFactory3);
H A Dgradients_2pt_conical.cpp380 static GMRegistry reg3(MyFactory3);
/external/chromium_org/v8/src/arm64/
H A Dassembler-arm64.h412 Register reg3 = NoReg,
420 const CPURegister& reg3 = NoReg,
433 const CPURegister& reg3 = NoCPUReg,
450 CPURegister reg3 = NoCPUReg,
452 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
454 ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
H A Dassembler-arm64.cc205 Register reg3, Register reg4) {
206 CPURegList regs(reg1, reg2, reg3, reg4);
218 const CPURegister& reg3, const CPURegister& reg4,
227 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
255 const CPURegister& reg3, const CPURegister& reg4,
261 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
204 GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4) argument
217 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
254 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
/external/chromium_org/third_party/sqlite/src/src/
H A Dbuild.c865 int reg1, reg2, reg3; local
879 reg3 = ++pParse->nMem;
880 sqlite3VdbeAddOp3(v, OP_ReadCookie, iDb, reg3, BTREE_FILE_FORMAT);
882 j1 = sqlite3VdbeAddOp1(v, OP_If, reg3);
885 sqlite3VdbeAddOp2(v, OP_Integer, fileFormat, reg3);
886 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_FILE_FORMAT, reg3);
887 sqlite3VdbeAddOp2(v, OP_Integer, ENC(db), reg3);
888 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_TEXT_ENCODING, reg3);
910 sqlite3VdbeAddOp2(v, OP_Null, 0, reg3);
911 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg
[all...]
/external/chromium_org/third_party/libvpx/source/libvpx/vp9/common/arm/neon/
H A Dvp9_idct32x32_add_neon.asm241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
278 vqrshrn.s32 $reg3, q11, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
287 DO_BUTTERFLY d28, d29, d26, d27, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
/external/chromium_org/v8/src/arm/
H A Dmacro-assembler-arm.h49 Register reg3 = no_reg,
58 Register reg3 = no_reg,
H A Dmacro-assembler-arm.cc3960 Register reg3,
3967 if (reg3.is_valid()) regs |= reg3.bit();
4011 Register reg3,
4016 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid();
4021 if (reg3.is_valid()) regs |= reg3.bit();
/external/libvpx/libvpx/vp9/common/arm/neon/
H A Dvp9_idct32x32_add_neon.asm241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
278 vqrshrn.s32 $reg3, q11, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
287 DO_BUTTERFLY d28, d29, d26, d27, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4

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