Searched defs:inst (Results 1 - 25 of 362) sorted by relevance

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/external/chromium_org/native_client_sdk/src/libraries/ppapi_simple/
H A Dps_main.cc12 void* PSMainCreate(PP_Instance inst, PSMainFunc_t func) { argument
13 PSInstance* pInst = new PSInstance(inst);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c523 const struct rc_instruction *inst,
527 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
574 switch (inst->U.I.TexSrcTarget) {
591 switch (inst->U.I.TexSrcTarget) {
522 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
H A Dradeon_dataflow_swizzles.c35 struct rc_instruction * inst, unsigned src)
43 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED)
47 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split);
50 struct rc_instruction * mov = rc_insert_new_instruction(c, inst->Prev);
58 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src];
59 mov->U.I.PreSub = inst->U.I.PreSub;
79 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY;
80 inst->U.I.SrcReg[src].Index = tempreg;
81 inst->U.I.SrcReg[src].Swizzle = 0;
82 inst
34 rewrite_source(struct radeon_compiler * c, struct rc_instruction * inst, unsigned src) argument
92 struct rc_instruction * inst; local
[all...]
H A Dradeon_pair_dead_sources.c20 struct rc_instruction * inst,
28 inst->U.P.RGB.Src[sub->Arg[i].Source].Used = 1;
32 inst->U.P.Alpha.Src[sub->Arg[i].Source].Used = 1;
43 struct rc_instruction * inst; local
44 for (inst = c->Program.Instructions.Next;
45 inst != &c->Program.Instructions;
46 inst = inst->Next) {
48 if (inst->Type == RC_INSTRUCTION_NORMAL)
53 inst
19 mark_used( struct rc_instruction * inst, struct rc_pair_sub_instruction * sub) argument
[all...]
H A Dradeon_rename_regs.c50 struct rc_instruction * inst; local
56 for(inst = c->Program.Instructions.Next;
57 inst != &c->Program.Instructions;
58 inst = inst->Next) {
59 if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP)
H A Dr3xx_fragprog.c57 struct rc_sub_instruction * inst = &rci->U.I; local
59 const struct rc_opcode_info *info = rc_get_opcode_info(inst->Opcode);
61 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth)
64 if (inst->DstReg.WriteMask & RC_MASK_Z) {
65 inst->DstReg.WriteMask = RC_MASK_W;
67 inst->DstReg.WriteMask = 0;
76 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
/external/clang/test/Index/
H A Dcursor-ref-names.cpp17 Sub inst; local
18 inst.func();
19 inst[1];
20 inst.operator[](1);
22 inst.Base<int>::operator[](1);
30 // CHECK: cursor-ref-names.cpp:17:9: VarDecl=inst:17:9 (Definition) Extent=[17:5 - 17:13]
35 // CHECK: cursor-ref-names.cpp:18:5: DeclRefExpr=inst:17:9 Extent=[18:5 - 18:9]
37 // CHECK: cursor-ref-names.cpp:19:5: DeclRefExpr=inst:17:9 Extent=[19:5 - 19:9]
41 // CHECK: cursor-ref-names.cpp:20:5: DeclRefExpr=inst:17:9 Extent=[20:5 - 20:9]
44 // CHECK: cursor-ref-names.cpp:22:5: DeclRefExpr=inst
[all...]
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c523 const struct rc_instruction *inst,
527 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
574 switch (inst->U.I.TexSrcTarget) {
591 switch (inst->U.I.TexSrcTarget) {
522 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
H A Dradeon_dataflow_swizzles.c35 struct rc_instruction * inst, unsigned src)
43 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED)
47 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split);
50 struct rc_instruction * mov = rc_insert_new_instruction(c, inst->Prev);
58 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src];
59 mov->U.I.PreSub = inst->U.I.PreSub;
79 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY;
80 inst->U.I.SrcReg[src].Index = tempreg;
81 inst->U.I.SrcReg[src].Swizzle = 0;
82 inst
34 rewrite_source(struct radeon_compiler * c, struct rc_instruction * inst, unsigned src) argument
92 struct rc_instruction * inst; local
[all...]
H A Dradeon_pair_dead_sources.c20 struct rc_instruction * inst,
28 inst->U.P.RGB.Src[sub->Arg[i].Source].Used = 1;
32 inst->U.P.Alpha.Src[sub->Arg[i].Source].Used = 1;
43 struct rc_instruction * inst; local
44 for (inst = c->Program.Instructions.Next;
45 inst != &c->Program.Instructions;
46 inst = inst->Next) {
48 if (inst->Type == RC_INSTRUCTION_NORMAL)
53 inst
19 mark_used( struct rc_instruction * inst, struct rc_pair_sub_instruction * sub) argument
[all...]
H A Dradeon_rename_regs.c50 struct rc_instruction * inst; local
56 for(inst = c->Program.Instructions.Next;
57 inst != &c->Program.Instructions;
58 inst = inst->Next) {
59 if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP)
H A Dr3xx_fragprog.c57 struct rc_sub_instruction * inst = &rci->U.I; local
59 const struct rc_opcode_info *info = rc_get_opcode_info(inst->Opcode);
61 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth)
64 if (inst->DstReg.WriteMask & RC_MASK_Z) {
65 inst->DstReg.WriteMask = RC_MASK_W;
67 inst->DstReg.WriteMask = 0;
76 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
/external/chromium_org/third_party/mesa/src/src/mesa/program/
H A Dprogram_parse_extra.c39 struct prog_instruction *inst)
41 inst->CondUpdate = 0;
42 inst->CondDst = 0;
43 inst->SaturateMode = SATURATE_OFF;
44 inst->Precision = FLOAT32;
53 inst->Precision = FLOAT16;
57 inst->Precision = FLOAT32;
61 inst->Precision = FIXED12;
74 inst->CondUpdate = 1;
85 inst
37 _mesa_parse_instruction_suffix(const struct asm_parser_state *state, const char *suffix, struct prog_instruction *inst) argument
[all...]
/external/mesa3d/src/mesa/program/
H A Dprogram_parse_extra.c39 struct prog_instruction *inst)
41 inst->CondUpdate = 0;
42 inst->CondDst = 0;
43 inst->SaturateMode = SATURATE_OFF;
44 inst->Precision = FLOAT32;
53 inst->Precision = FLOAT16;
57 inst->Precision = FLOAT32;
61 inst->Precision = FIXED12;
74 inst->CondUpdate = 1;
85 inst
37 _mesa_parse_instruction_suffix(const struct asm_parser_state *state, const char *suffix, struct prog_instruction *inst) argument
[all...]
/external/chromium_org/sdch/open-vcdiff/src/
H A Dcodetable.cc30 const char* VCDiffInstructionName(VCDiffInstructionType inst) { argument
31 switch (inst) {
41 VCD_ERROR << "Unexpected instruction type " << inst << VCD_ENDL;
189 unsigned char inst,
195 // Check upper limits of inst and mode. inst, size, and mode are
197 if (inst > VCD_LAST_INSTRUCTION_TYPE) {
200 << static_cast<int>(inst) << VCD_ENDL;
211 if ((inst == VCD_NOOP) && (size != 0)) {
218 if ((inst !
188 ValidateOpcode(int opcode, unsigned char inst, unsigned char size, unsigned char mode, unsigned char max_mode, const char* first_or_second) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_action.h82 const struct tgsi_full_instruction * inst; member in struct:lp_build_emit_data
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_fs_copy_propagation.cpp35 fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry) argument
37 if (inst->src[arg].file != entry->dst.file ||
38 inst->src[arg].reg != entry->dst.reg ||
39 inst->src[arg].reg_offset != entry->dst.reg_offset) {
44 if (inst->conditional_mod &&
45 inst->src[arg].type == BRW_REGISTER_TYPE_UD &&
51 if (intel->gen == 6 && inst->is_math() &&
55 inst->src[arg].file = entry->src.file;
56 inst->src[arg].reg = entry->src.reg;
57 inst
[all...]
H A Dbrw_fs_cse.cpp46 is_expression(const fs_inst *const inst) argument
48 switch (inst->opcode) {
90 for (fs_inst *inst = block->start;
91 inst != block->end->next;
92 inst = (fs_inst *) inst->next) {
95 if (is_expression(inst) && !inst->predicated && inst->mlen == 0 &&
96 !inst
[all...]
H A Dbrw_vec4_copy_propagation.cpp40 is_direct_copy(vec4_instruction *inst) argument
42 return (inst->opcode == BRW_OPCODE_MOV &&
43 !inst->predicate &&
44 inst->dst.file == GRF &&
45 !inst->saturate &&
46 !inst->dst.reladdr &&
47 !inst->src[0].reladdr &&
48 inst->dst.type == inst->src[0].type);
52 is_dominated_by_previous_instruction(vec4_instruction *inst) argument
61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4]) argument
163 try_copy_propagation(struct intel_context *intel, vec4_instruction *inst, int arg, src_reg *values[4]) argument
241 vec4_instruction *inst = (vec4_instruction *)node; local
[all...]
H A Dbrw_wm_pass1.c38 struct brw_wm_instruction *inst)
42 if (inst->writemask & (1<<i)) {
43 if (!inst->dst[i]->contributes_to_output) {
44 inst->writemask &= ~(1<<i);
45 inst->dst[i] = 0;
50 return inst->writemask;
70 struct brw_wm_instruction *inst,
77 struct brw_wm_ref *ref = inst->src[arg][i];
84 inst->src[arg][i] = NULL;
122 struct brw_wm_instruction *inst local
37 get_tracked_mask(struct brw_wm_compile *c, struct brw_wm_instruction *inst) argument
69 track_arg(struct brw_wm_compile *c, struct brw_wm_instruction *inst, GLuint arg, GLuint readmask) argument
[all...]
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_action.h82 const struct tgsi_full_instruction * inst; member in struct:lp_build_emit_data
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_fs_copy_propagation.cpp35 fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry) argument
37 if (inst->src[arg].file != entry->dst.file ||
38 inst->src[arg].reg != entry->dst.reg ||
39 inst->src[arg].reg_offset != entry->dst.reg_offset) {
44 if (inst->conditional_mod &&
45 inst->src[arg].type == BRW_REGISTER_TYPE_UD &&
51 if (intel->gen == 6 && inst->is_math() &&
55 inst->src[arg].file = entry->src.file;
56 inst->src[arg].reg = entry->src.reg;
57 inst
[all...]
H A Dbrw_fs_cse.cpp46 is_expression(const fs_inst *const inst) argument
48 switch (inst->opcode) {
90 for (fs_inst *inst = block->start;
91 inst != block->end->next;
92 inst = (fs_inst *) inst->next) {
95 if (is_expression(inst) && !inst->predicated && inst->mlen == 0 &&
96 !inst
[all...]
H A Dbrw_vec4_copy_propagation.cpp40 is_direct_copy(vec4_instruction *inst) argument
42 return (inst->opcode == BRW_OPCODE_MOV &&
43 !inst->predicate &&
44 inst->dst.file == GRF &&
45 !inst->saturate &&
46 !inst->dst.reladdr &&
47 !inst->src[0].reladdr &&
48 inst->dst.type == inst->src[0].type);
52 is_dominated_by_previous_instruction(vec4_instruction *inst) argument
61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4]) argument
163 try_copy_propagation(struct intel_context *intel, vec4_instruction *inst, int arg, src_reg *values[4]) argument
241 vec4_instruction *inst = (vec4_instruction *)node; local
[all...]
/external/chromium_org/third_party/webrtc/modules/audio_coding/codecs/pcm16b/
H A Dpcm16b.c65 int16_t WebRtcPcm16b_DecodeW16(void *inst, argument
85 (void)(inst = NULL);

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