/external/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 65 DwarfLLVMRegPair Key = { RegNum, 0 }; 67 if (I == M+Size || I->FromReg != RegNum) 72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { 76 DwarfLLVMRegPair Key = { RegNum, 0 }; 78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); 82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { 83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 84 if (I == L2SEHRegs.end()) return (int)RegNum; [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 381 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 384 int getLLVMRegNum(unsigned RegNum, bool isEH) const; 388 int getSEHRegNum(unsigned RegNum) const;
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 173 unsigned RegNum; member in struct:__anon25114::AArch64Operand::RegOp 178 unsigned RegNum; member in struct:__anon25114::AArch64Operand::VectorListOp 353 return Reg.RegNum; 358 return VectorList.RegNum; 885 Reg.RegNum); 889 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); 894 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum); 1588 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { argument 1590 Op->Reg.RegNum = RegNum; 1598 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, char ElementKind, SMLoc S, SMLoc E, MCContext &Ctx) argument 1876 unsigned RegNum = isVector ? matchVectorRegName(Name) local 1901 unsigned RegNum = matchRegisterNameAlias(lowerCase, false); local 1931 unsigned RegNum = matchRegisterNameAlias(Head, true); local 2930 unsigned RegNum = matchRegisterNameAlias(Tok.getString().lower(), false); local 4050 unsigned RegNum = tryParseRegister(); local [all...] |
/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 158 unsigned RegNum; member in struct:__anon25293::SparcOperand::RegOp 205 return Reg.RegNum; 299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, argument 302 Op->Reg.RegNum = RegNum; 324 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; 347 Op.Reg.RegNum = Reg;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 267 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); local 269 FPUBitmask |= (3 << RegNum); 275 FPUBitmask |= (1 << RegNum); 282 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); local 283 CPUBitmask |= (1 << RegNum);
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/external/clang/lib/Basic/ |
H A D | TargetInfo.cpp | 346 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) 399 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames)
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 444 unsigned RegNum; member in struct:__anon25150::ARMOperand::RegOp 449 unsigned RegNum; member in struct:__anon25150::ARMOperand::VectorListOp 478 unsigned RegNum; member in struct:__anon25150::ARMOperand::PostIdxRegOp 643 return Reg.RegNum; 1404 .contains(VectorList.RegNum)); 1421 .contains(VectorList.RegNum)); 1448 .contains(VectorList.RegNum)); 1706 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; local 1707 Inst.addOperand(MCOperand::CreateReg(RegNum)); 2121 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2512 CreateCCOut(unsigned RegNum, SMLoc S) argument 2529 CreateReg(unsigned RegNum, SMLoc S, SMLoc E) argument 2617 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument 2631 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument 2643 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) argument 2693 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument 2890 unsigned RegNum = MatchRegisterName(lowerCase); local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDILCFGStructurizer.cpp | 236 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, 238 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum); 515 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, 521 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); 526 int NewOpcode, int RegNum) { 531 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); 514 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, DebugLoc DL) argument 525 insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum) argument
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/external/clang/include/clang/Basic/ |
H A D | TargetInfo.h | 596 const unsigned RegNum; member in struct:clang::TargetInfo::AddlRegName
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 1545 unsigned RegNum = GetX86RegNum(MO) << 4; local 1547 RegNum |= 1 << 7; 1555 RegNum |= Val; 1558 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
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/external/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 1470 unsigned RegNum = getX86RegNum(MO.getReg()) << 4; 1472 RegNum |= 1 << 7; 1480 RegNum |= Val; 1483 emitConstant(RegNum, 1);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 1293 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); local 1295 RegNum < 16); 1296 Binary |= 0x1 << RegNum;
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H A D | ARMLoadStoreOptimizer.cpp | 747 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); local 753 ((isNotVFP && RegNum > PRegNum) || 754 ((Count < Limit) && RegNum == PRegNum+1)) && 759 PRegNum = RegNum;
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 177 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass); 1592 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { argument 1593 if (RegNum > 1597 return getReg(RegClass, RegNum);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum); 383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum); 384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum); 385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum); 386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum); 383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum); 384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum); 385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum); 386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1279 unsigned RegNum = Registers[i]->EnumValue; local 1280 if (AllocatableRegs.count(RegNum)) 1283 UberSetIDs.join(0, RegNum);
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 1002 if (unsigned RegNum = MO2.getReg()) { 1004 printRegName(O, RegNum);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 668 unsigned RegNum = RegMap[Reg]; local 690 Ret |= (RegNum & 0x0FFFFFFF);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 2069 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local 2073 // allocated yet. RegNum is actually an index into ArgRegs, which means we 2074 // need to skip a register if RegNum is odd. 2075 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 2076 State.AllocateReg(ArgRegs[RegNum]); 2097 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local 2101 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 2102 State.AllocateReg(ArgRegs[RegNum]); [all...] |