mir_graph.h revision 1fd4821f6b3ac57a44c2ce91025686da4641d197
1/* 2 * Copyright (C) 2013 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_MIR_GRAPH_H_ 18#define ART_COMPILER_DEX_MIR_GRAPH_H_ 19 20#include <stdint.h> 21 22#include "dex_file.h" 23#include "dex_instruction.h" 24#include "compiler_ir.h" 25#include "invoke_type.h" 26#include "mir_field_info.h" 27#include "mir_method_info.h" 28#include "utils/arena_bit_vector.h" 29#include "utils/growable_array.h" 30#include "utils/scoped_arena_containers.h" 31#include "reg_location.h" 32#include "reg_storage.h" 33 34namespace art { 35 36class GlobalValueNumbering; 37 38enum InstructionAnalysisAttributePos { 39 kUninterestingOp = 0, 40 kArithmeticOp, 41 kFPOp, 42 kSingleOp, 43 kDoubleOp, 44 kIntOp, 45 kLongOp, 46 kBranchOp, 47 kInvokeOp, 48 kArrayOp, 49 kHeavyweightOp, 50 kSimpleConstOp, 51 kMoveOp, 52 kSwitch 53}; 54 55#define AN_NONE (1 << kUninterestingOp) 56#define AN_MATH (1 << kArithmeticOp) 57#define AN_FP (1 << kFPOp) 58#define AN_LONG (1 << kLongOp) 59#define AN_INT (1 << kIntOp) 60#define AN_SINGLE (1 << kSingleOp) 61#define AN_DOUBLE (1 << kDoubleOp) 62#define AN_FLOATMATH (1 << kFPOp) 63#define AN_BRANCH (1 << kBranchOp) 64#define AN_INVOKE (1 << kInvokeOp) 65#define AN_ARRAYOP (1 << kArrayOp) 66#define AN_HEAVYWEIGHT (1 << kHeavyweightOp) 67#define AN_SIMPLECONST (1 << kSimpleConstOp) 68#define AN_MOVE (1 << kMoveOp) 69#define AN_SWITCH (1 << kSwitch) 70#define AN_COMPUTATIONAL (AN_MATH | AN_ARRAYOP | AN_MOVE | AN_SIMPLECONST) 71 72enum DataFlowAttributePos { 73 kUA = 0, 74 kUB, 75 kUC, 76 kAWide, 77 kBWide, 78 kCWide, 79 kDA, 80 kIsMove, 81 kSetsConst, 82 kFormat35c, 83 kFormat3rc, 84 kFormatExtended, // Extended format for extended MIRs. 85 kNullCheckSrc0, // Null check of uses[0]. 86 kNullCheckSrc1, // Null check of uses[1]. 87 kNullCheckSrc2, // Null check of uses[2]. 88 kNullCheckOut0, // Null check out outgoing arg0. 89 kDstNonNull, // May assume dst is non-null. 90 kRetNonNull, // May assume retval is non-null. 91 kNullTransferSrc0, // Object copy src[0] -> dst. 92 kNullTransferSrcN, // Phi null check state transfer. 93 kRangeCheckSrc1, // Range check of uses[1]. 94 kRangeCheckSrc2, // Range check of uses[2]. 95 kRangeCheckSrc3, // Range check of uses[3]. 96 kFPA, 97 kFPB, 98 kFPC, 99 kCoreA, 100 kCoreB, 101 kCoreC, 102 kRefA, 103 kRefB, 104 kRefC, 105 kUsesMethodStar, // Implicit use of Method*. 106 kUsesIField, // Accesses an instance field (IGET/IPUT). 107 kUsesSField, // Accesses a static field (SGET/SPUT). 108 kDoLVN, // Worth computing local value numbers. 109}; 110 111#define DF_NOP UINT64_C(0) 112#define DF_UA (UINT64_C(1) << kUA) 113#define DF_UB (UINT64_C(1) << kUB) 114#define DF_UC (UINT64_C(1) << kUC) 115#define DF_A_WIDE (UINT64_C(1) << kAWide) 116#define DF_B_WIDE (UINT64_C(1) << kBWide) 117#define DF_C_WIDE (UINT64_C(1) << kCWide) 118#define DF_DA (UINT64_C(1) << kDA) 119#define DF_IS_MOVE (UINT64_C(1) << kIsMove) 120#define DF_SETS_CONST (UINT64_C(1) << kSetsConst) 121#define DF_FORMAT_35C (UINT64_C(1) << kFormat35c) 122#define DF_FORMAT_3RC (UINT64_C(1) << kFormat3rc) 123#define DF_FORMAT_EXTENDED (UINT64_C(1) << kFormatExtended) 124#define DF_NULL_CHK_0 (UINT64_C(1) << kNullCheckSrc0) 125#define DF_NULL_CHK_1 (UINT64_C(1) << kNullCheckSrc1) 126#define DF_NULL_CHK_2 (UINT64_C(1) << kNullCheckSrc2) 127#define DF_NULL_CHK_OUT0 (UINT64_C(1) << kNullCheckOut0) 128#define DF_NON_NULL_DST (UINT64_C(1) << kDstNonNull) 129#define DF_NON_NULL_RET (UINT64_C(1) << kRetNonNull) 130#define DF_NULL_TRANSFER_0 (UINT64_C(1) << kNullTransferSrc0) 131#define DF_NULL_TRANSFER_N (UINT64_C(1) << kNullTransferSrcN) 132#define DF_RANGE_CHK_1 (UINT64_C(1) << kRangeCheckSrc1) 133#define DF_RANGE_CHK_2 (UINT64_C(1) << kRangeCheckSrc2) 134#define DF_RANGE_CHK_3 (UINT64_C(1) << kRangeCheckSrc3) 135#define DF_FP_A (UINT64_C(1) << kFPA) 136#define DF_FP_B (UINT64_C(1) << kFPB) 137#define DF_FP_C (UINT64_C(1) << kFPC) 138#define DF_CORE_A (UINT64_C(1) << kCoreA) 139#define DF_CORE_B (UINT64_C(1) << kCoreB) 140#define DF_CORE_C (UINT64_C(1) << kCoreC) 141#define DF_REF_A (UINT64_C(1) << kRefA) 142#define DF_REF_B (UINT64_C(1) << kRefB) 143#define DF_REF_C (UINT64_C(1) << kRefC) 144#define DF_UMS (UINT64_C(1) << kUsesMethodStar) 145#define DF_IFIELD (UINT64_C(1) << kUsesIField) 146#define DF_SFIELD (UINT64_C(1) << kUsesSField) 147#define DF_LVN (UINT64_C(1) << kDoLVN) 148 149#define DF_HAS_USES (DF_UA | DF_UB | DF_UC) 150 151#define DF_HAS_DEFS (DF_DA) 152 153#define DF_HAS_NULL_CHKS (DF_NULL_CHK_0 | \ 154 DF_NULL_CHK_1 | \ 155 DF_NULL_CHK_2 | \ 156 DF_NULL_CHK_OUT0) 157 158#define DF_HAS_RANGE_CHKS (DF_RANGE_CHK_1 | \ 159 DF_RANGE_CHK_2 | \ 160 DF_RANGE_CHK_3) 161 162#define DF_HAS_NR_CHKS (DF_HAS_NULL_CHKS | \ 163 DF_HAS_RANGE_CHKS) 164 165#define DF_A_IS_REG (DF_UA | DF_DA) 166#define DF_B_IS_REG (DF_UB) 167#define DF_C_IS_REG (DF_UC) 168#define DF_IS_GETTER_OR_SETTER (DF_IS_GETTER | DF_IS_SETTER) 169#define DF_USES_FP (DF_FP_A | DF_FP_B | DF_FP_C) 170#define DF_NULL_TRANSFER (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N) 171enum OatMethodAttributes { 172 kIsLeaf, // Method is leaf. 173 kHasLoop, // Method contains simple loop. 174}; 175 176#define METHOD_IS_LEAF (1 << kIsLeaf) 177#define METHOD_HAS_LOOP (1 << kHasLoop) 178 179// Minimum field size to contain Dalvik v_reg number. 180#define VREG_NUM_WIDTH 16 181 182#define INVALID_SREG (-1) 183#define INVALID_VREG (0xFFFFU) 184#define INVALID_OFFSET (0xDEADF00FU) 185 186#define MIR_IGNORE_NULL_CHECK (1 << kMIRIgnoreNullCheck) 187#define MIR_NULL_CHECK_ONLY (1 << kMIRNullCheckOnly) 188#define MIR_IGNORE_RANGE_CHECK (1 << kMIRIgnoreRangeCheck) 189#define MIR_RANGE_CHECK_ONLY (1 << kMIRRangeCheckOnly) 190#define MIR_IGNORE_CLINIT_CHECK (1 << kMIRIgnoreClInitCheck) 191#define MIR_INLINED (1 << kMIRInlined) 192#define MIR_INLINED_PRED (1 << kMIRInlinedPred) 193#define MIR_CALLEE (1 << kMIRCallee) 194#define MIR_IGNORE_SUSPEND_CHECK (1 << kMIRIgnoreSuspendCheck) 195#define MIR_DUP (1 << kMIRDup) 196 197#define BLOCK_NAME_LEN 80 198 199typedef uint16_t BasicBlockId; 200static const BasicBlockId NullBasicBlockId = 0; 201static constexpr bool kLeafOptimization = false; 202 203/* 204 * In general, vreg/sreg describe Dalvik registers that originated with dx. However, 205 * it is useful to have compiler-generated temporary registers and have them treated 206 * in the same manner as dx-generated virtual registers. This struct records the SSA 207 * name of compiler-introduced temporaries. 208 */ 209struct CompilerTemp { 210 int32_t v_reg; // Virtual register number for temporary. 211 int32_t s_reg_low; // SSA name for low Dalvik word. 212}; 213 214enum CompilerTempType { 215 kCompilerTempVR, // A virtual register temporary. 216 kCompilerTempSpecialMethodPtr, // Temporary that keeps track of current method pointer. 217}; 218 219// When debug option enabled, records effectiveness of null and range check elimination. 220struct Checkstats { 221 int32_t null_checks; 222 int32_t null_checks_eliminated; 223 int32_t range_checks; 224 int32_t range_checks_eliminated; 225}; 226 227// Dataflow attributes of a basic block. 228struct BasicBlockDataFlow { 229 ArenaBitVector* use_v; 230 ArenaBitVector* def_v; 231 ArenaBitVector* live_in_v; 232 ArenaBitVector* phi_v; 233 int32_t* vreg_to_ssa_map_exit; 234 ArenaBitVector* ending_check_v; // For null check and class init check elimination. 235}; 236 237/* 238 * Normalized use/def for a MIR operation using SSA names rather than vregs. Note that 239 * uses/defs retain the Dalvik convention that long operations operate on a pair of 32-bit 240 * vregs. For example, "ADD_LONG v0, v2, v3" would have 2 defs (v0/v1) and 4 uses (v2/v3, v4/v5). 241 * Following SSA renaming, this is the primary struct used by code generators to locate 242 * operand and result registers. This is a somewhat confusing and unhelpful convention that 243 * we may want to revisit in the future. 244 * 245 * TODO: 246 * 1. Add accessors for uses/defs and make data private 247 * 2. Change fp_use/fp_def to a bit array (could help memory usage) 248 * 3. Combine array storage into internal array and handled via accessors from 1. 249 */ 250struct SSARepresentation { 251 int32_t* uses; 252 bool* fp_use; 253 int32_t* defs; 254 bool* fp_def; 255 int16_t num_uses_allocated; 256 int16_t num_defs_allocated; 257 int16_t num_uses; 258 int16_t num_defs; 259 260 static uint32_t GetStartUseIndex(Instruction::Code opcode); 261}; 262 263/* 264 * The Midlevel Intermediate Representation node, which may be largely considered a 265 * wrapper around a Dalvik byte code. 266 */ 267struct MIR { 268 /* 269 * TODO: remove embedded DecodedInstruction to save space, keeping only opcode. Recover 270 * additional fields on as-needed basis. Question: how to support MIR Pseudo-ops; probably 271 * need to carry aux data pointer. 272 */ 273 struct DecodedInstruction { 274 uint32_t vA; 275 uint32_t vB; 276 uint64_t vB_wide; /* for k51l */ 277 uint32_t vC; 278 uint32_t arg[5]; /* vC/D/E/F/G in invoke or filled-new-array */ 279 Instruction::Code opcode; 280 281 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) { 282 } 283 284 /* 285 * Given a decoded instruction representing a const bytecode, it updates 286 * the out arguments with proper values as dictated by the constant bytecode. 287 */ 288 bool GetConstant(int64_t* ptr_value, bool* wide) const; 289 290 static bool IsPseudoMirOp(Instruction::Code opcode) { 291 return static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst); 292 } 293 294 static bool IsPseudoMirOp(int opcode) { 295 return opcode >= static_cast<int>(kMirOpFirst); 296 } 297 298 bool IsInvoke() const { 299 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kInvoke) == Instruction::kInvoke); 300 } 301 302 bool IsStore() const { 303 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kStore) == Instruction::kStore); 304 } 305 306 bool IsLoad() const { 307 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kLoad) == Instruction::kLoad); 308 } 309 310 bool IsConditionalBranch() const { 311 return !IsPseudoMirOp(opcode) && (Instruction::FlagsOf(opcode) == (Instruction::kContinue | Instruction::kBranch)); 312 } 313 314 /** 315 * @brief Is the register C component of the decoded instruction a constant? 316 */ 317 bool IsCFieldOrConstant() const { 318 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kRegCFieldOrConstant) == Instruction::kRegCFieldOrConstant); 319 } 320 321 /** 322 * @brief Is the register C component of the decoded instruction a constant? 323 */ 324 bool IsBFieldOrConstant() const { 325 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kRegBFieldOrConstant) == Instruction::kRegBFieldOrConstant); 326 } 327 328 bool IsCast() const { 329 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kCast) == Instruction::kCast); 330 } 331 332 /** 333 * @brief Does the instruction clobber memory? 334 * @details Clobber means that the instruction changes the memory not in a punctual way. 335 * Therefore any supposition on memory aliasing or memory contents should be disregarded 336 * when crossing such an instruction. 337 */ 338 bool Clobbers() const { 339 return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kClobber) == Instruction::kClobber); 340 } 341 342 bool IsLinear() const { 343 return !IsPseudoMirOp(opcode) && (Instruction::FlagsOf(opcode) & (Instruction::kAdd | Instruction::kSubtract)) != 0; 344 } 345 } dalvikInsn; 346 347 NarrowDexOffset offset; // Offset of the instruction in code units. 348 uint16_t optimization_flags; 349 int16_t m_unit_index; // From which method was this MIR included 350 BasicBlockId bb; 351 MIR* next; 352 SSARepresentation* ssa_rep; 353 union { 354 // Incoming edges for phi node. 355 BasicBlockId* phi_incoming; 356 // Establish link from check instruction (kMirOpCheck) to the actual throwing instruction. 357 MIR* throw_insn; 358 // Branch condition for fused cmp or select. 359 ConditionCode ccode; 360 // IGET/IPUT lowering info index, points to MIRGraph::ifield_lowering_infos_. Due to limit on 361 // the number of code points (64K) and size of IGET/IPUT insn (2), this will never exceed 32K. 362 uint32_t ifield_lowering_info; 363 // SGET/SPUT lowering info index, points to MIRGraph::sfield_lowering_infos_. Due to limit on 364 // the number of code points (64K) and size of SGET/SPUT insn (2), this will never exceed 32K. 365 uint32_t sfield_lowering_info; 366 // INVOKE data index, points to MIRGraph::method_lowering_infos_. 367 uint32_t method_lowering_info; 368 } meta; 369 370 explicit MIR():offset(0), optimization_flags(0), m_unit_index(0), bb(NullBasicBlockId), 371 next(nullptr), ssa_rep(nullptr) { 372 memset(&meta, 0, sizeof(meta)); 373 } 374 375 uint32_t GetStartUseIndex() const { 376 return SSARepresentation::GetStartUseIndex(dalvikInsn.opcode); 377 } 378 379 MIR* Copy(CompilationUnit *c_unit); 380 MIR* Copy(MIRGraph* mir_Graph); 381 382 static void* operator new(size_t size, ArenaAllocator* arena) { 383 return arena->Alloc(sizeof(MIR), kArenaAllocMIR); 384 } 385 static void operator delete(void* p) {} // Nop. 386}; 387 388struct SuccessorBlockInfo; 389 390struct BasicBlock { 391 BasicBlockId id; 392 BasicBlockId dfs_id; 393 NarrowDexOffset start_offset; // Offset in code units. 394 BasicBlockId fall_through; 395 BasicBlockId taken; 396 BasicBlockId i_dom; // Immediate dominator. 397 uint16_t nesting_depth; 398 BBType block_type:4; 399 BlockListType successor_block_list_type:4; 400 bool visited:1; 401 bool hidden:1; 402 bool catch_entry:1; 403 bool explicit_throw:1; 404 bool conditional_branch:1; 405 bool terminated_by_return:1; // Block ends with a Dalvik return opcode. 406 bool dominates_return:1; // Is a member of return extended basic block. 407 bool use_lvn:1; // Run local value numbering on this block. 408 MIR* first_mir_insn; 409 MIR* last_mir_insn; 410 BasicBlockDataFlow* data_flow_info; 411 ArenaBitVector* dominators; 412 ArenaBitVector* i_dominated; // Set nodes being immediately dominated. 413 ArenaBitVector* dom_frontier; // Dominance frontier. 414 GrowableArray<BasicBlockId>* predecessors; 415 GrowableArray<SuccessorBlockInfo*>* successor_blocks; 416 417 void AppendMIR(MIR* mir); 418 void AppendMIRList(MIR* first_list_mir, MIR* last_list_mir); 419 void AppendMIRList(const std::vector<MIR*>& insns); 420 void PrependMIR(MIR* mir); 421 void PrependMIRList(MIR* first_list_mir, MIR* last_list_mir); 422 void PrependMIRList(const std::vector<MIR*>& to_add); 423 void InsertMIRAfter(MIR* current_mir, MIR* new_mir); 424 void InsertMIRListAfter(MIR* insert_after, MIR* first_list_mir, MIR* last_list_mir); 425 MIR* FindPreviousMIR(MIR* mir); 426 void InsertMIRBefore(MIR* insert_before, MIR* list); 427 void InsertMIRListBefore(MIR* insert_before, MIR* first_list_mir, MIR* last_list_mir); 428 bool RemoveMIR(MIR* mir); 429 bool RemoveMIRList(MIR* first_list_mir, MIR* last_list_mir); 430 431 BasicBlock* Copy(CompilationUnit* c_unit); 432 BasicBlock* Copy(MIRGraph* mir_graph); 433 434 /** 435 * @brief Reset the optimization_flags field of each MIR. 436 */ 437 void ResetOptimizationFlags(uint16_t reset_flags); 438 439 /** 440 * @brief Hide the BasicBlock. 441 * @details Set it to kDalvikByteCode, set hidden to true, remove all MIRs, 442 * remove itself from any predecessor edges, remove itself from any 443 * child's predecessor growable array. 444 */ 445 void Hide(CompilationUnit* c_unit); 446 447 /** 448 * @brief Is ssa_reg the last SSA definition of that VR in the block? 449 */ 450 bool IsSSALiveOut(const CompilationUnit* c_unit, int ssa_reg); 451 452 /** 453 * @brief Replace the edge going to old_bb to now go towards new_bb. 454 */ 455 bool ReplaceChild(BasicBlockId old_bb, BasicBlockId new_bb); 456 457 /** 458 * @brief Update the predecessor growable array from old_pred to new_pred. 459 */ 460 void UpdatePredecessor(BasicBlockId old_pred, BasicBlockId new_pred); 461 462 /** 463 * @brief Used to obtain the next MIR that follows unconditionally. 464 * @details The implementation does not guarantee that a MIR does not 465 * follow even if this method returns nullptr. 466 * @param mir_graph the MIRGraph. 467 * @param current The MIR for which to find an unconditional follower. 468 * @return Returns the following MIR if one can be found. 469 */ 470 MIR* GetNextUnconditionalMir(MIRGraph* mir_graph, MIR* current); 471 bool IsExceptionBlock() const; 472 473 static void* operator new(size_t size, ArenaAllocator* arena) { 474 return arena->Alloc(sizeof(BasicBlock), kArenaAllocBB); 475 } 476 static void operator delete(void* p) {} // Nop. 477}; 478 479/* 480 * The "blocks" field in "successor_block_list" points to an array of elements with the type 481 * "SuccessorBlockInfo". For catch blocks, key is type index for the exception. For switch 482 * blocks, key is the case value. 483 */ 484struct SuccessorBlockInfo { 485 BasicBlockId block; 486 int key; 487}; 488 489/** 490 * @class ChildBlockIterator 491 * @brief Enable an easy iteration of the children. 492 */ 493class ChildBlockIterator { 494 public: 495 /** 496 * @brief Constructs a child iterator. 497 * @param bb The basic whose children we need to iterate through. 498 * @param mir_graph The MIRGraph used to get the basic block during iteration. 499 */ 500 ChildBlockIterator(BasicBlock* bb, MIRGraph* mir_graph); 501 BasicBlock* Next(); 502 503 private: 504 BasicBlock* basic_block_; 505 MIRGraph* mir_graph_; 506 bool visited_fallthrough_; 507 bool visited_taken_; 508 bool have_successors_; 509 GrowableArray<SuccessorBlockInfo*>::Iterator successor_iter_; 510}; 511 512/* 513 * Collection of information describing an invoke, and the destination of 514 * the subsequent MOVE_RESULT (if applicable). Collected as a unit to enable 515 * more efficient invoke code generation. 516 */ 517struct CallInfo { 518 int num_arg_words; // Note: word count, not arg count. 519 RegLocation* args; // One for each word of arguments. 520 RegLocation result; // Eventual target of MOVE_RESULT. 521 int opt_flags; 522 InvokeType type; 523 uint32_t dex_idx; 524 uint32_t index; // Method idx for invokes, type idx for FilledNewArray. 525 uintptr_t direct_code; 526 uintptr_t direct_method; 527 RegLocation target; // Target of following move_result. 528 bool skip_this; 529 bool is_range; 530 DexOffset offset; // Offset in code units. 531 MIR* mir; 532}; 533 534 535const RegLocation bad_loc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0, RegStorage(), INVALID_SREG, 536 INVALID_SREG}; 537 538class MIRGraph { 539 public: 540 MIRGraph(CompilationUnit* cu, ArenaAllocator* arena); 541 ~MIRGraph(); 542 543 /* 544 * Examine the graph to determine whether it's worthwile to spend the time compiling 545 * this method. 546 */ 547 bool SkipCompilation(std::string* skip_message); 548 549 /* 550 * Should we skip the compilation of this method based on its name? 551 */ 552 bool SkipCompilationByName(const std::string& methodname); 553 554 /* 555 * Parse dex method and add MIR at current insert point. Returns id (which is 556 * actually the index of the method in the m_units_ array). 557 */ 558 void InlineMethod(const DexFile::CodeItem* code_item, uint32_t access_flags, 559 InvokeType invoke_type, uint16_t class_def_idx, 560 uint32_t method_idx, jobject class_loader, const DexFile& dex_file); 561 562 /* Find existing block */ 563 BasicBlock* FindBlock(DexOffset code_offset) { 564 return FindBlock(code_offset, false, false, NULL); 565 } 566 567 const uint16_t* GetCurrentInsns() const { 568 return current_code_item_->insns_; 569 } 570 571 const uint16_t* GetInsns(int m_unit_index) const { 572 return m_units_[m_unit_index]->GetCodeItem()->insns_; 573 } 574 575 unsigned int GetNumBlocks() const { 576 return num_blocks_; 577 } 578 579 size_t GetNumDalvikInsns() const { 580 return cu_->code_item->insns_size_in_code_units_; 581 } 582 583 ArenaBitVector* GetTryBlockAddr() const { 584 return try_block_addr_; 585 } 586 587 BasicBlock* GetEntryBlock() const { 588 return entry_block_; 589 } 590 591 BasicBlock* GetExitBlock() const { 592 return exit_block_; 593 } 594 595 BasicBlock* GetBasicBlock(unsigned int block_id) const { 596 return (block_id == NullBasicBlockId) ? NULL : block_list_.Get(block_id); 597 } 598 599 size_t GetBasicBlockListCount() const { 600 return block_list_.Size(); 601 } 602 603 GrowableArray<BasicBlock*>* GetBlockList() { 604 return &block_list_; 605 } 606 607 GrowableArray<BasicBlockId>* GetDfsOrder() { 608 return dfs_order_; 609 } 610 611 GrowableArray<BasicBlockId>* GetDfsPostOrder() { 612 return dfs_post_order_; 613 } 614 615 GrowableArray<BasicBlockId>* GetDomPostOrder() { 616 return dom_post_order_traversal_; 617 } 618 619 int GetDefCount() const { 620 return def_count_; 621 } 622 623 ArenaAllocator* GetArena() { 624 return arena_; 625 } 626 627 void EnableOpcodeCounting() { 628 opcode_count_ = static_cast<int*>(arena_->Alloc(kNumPackedOpcodes * sizeof(int), 629 kArenaAllocMisc)); 630 } 631 632 void ShowOpcodeStats(); 633 634 DexCompilationUnit* GetCurrentDexCompilationUnit() const { 635 return m_units_[current_method_]; 636 } 637 638 /** 639 * @brief Dump a CFG into a dot file format. 640 * @param dir_prefix the directory the file will be created in. 641 * @param all_blocks does the dumper use all the basic blocks or use the reachable blocks. 642 * @param suffix does the filename require a suffix or not (default = nullptr). 643 */ 644 void DumpCFG(const char* dir_prefix, bool all_blocks, const char* suffix = nullptr); 645 646 bool HasFieldAccess() const { 647 return (merged_df_flags_ & (DF_IFIELD | DF_SFIELD)) != 0u; 648 } 649 650 bool HasStaticFieldAccess() const { 651 return (merged_df_flags_ & DF_SFIELD) != 0u; 652 } 653 654 bool HasInvokes() const { 655 // NOTE: These formats include the rare filled-new-array/range. 656 return (merged_df_flags_ & (DF_FORMAT_35C | DF_FORMAT_3RC)) != 0u; 657 } 658 659 void DoCacheFieldLoweringInfo(); 660 661 const MirIFieldLoweringInfo& GetIFieldLoweringInfo(MIR* mir) const { 662 DCHECK_LT(mir->meta.ifield_lowering_info, ifield_lowering_infos_.Size()); 663 return ifield_lowering_infos_.GetRawStorage()[mir->meta.ifield_lowering_info]; 664 } 665 666 const MirSFieldLoweringInfo& GetSFieldLoweringInfo(MIR* mir) const { 667 DCHECK_LT(mir->meta.sfield_lowering_info, sfield_lowering_infos_.Size()); 668 return sfield_lowering_infos_.GetRawStorage()[mir->meta.sfield_lowering_info]; 669 } 670 671 void DoCacheMethodLoweringInfo(); 672 673 const MirMethodLoweringInfo& GetMethodLoweringInfo(MIR* mir) { 674 DCHECK_LT(mir->meta.method_lowering_info, method_lowering_infos_.Size()); 675 return method_lowering_infos_.GetRawStorage()[mir->meta.method_lowering_info]; 676 } 677 678 void ComputeInlineIFieldLoweringInfo(uint16_t field_idx, MIR* invoke, MIR* iget_or_iput); 679 680 void InitRegLocations(); 681 682 void RemapRegLocations(); 683 684 void DumpRegLocTable(RegLocation* table, int count); 685 686 void BasicBlockOptimization(); 687 688 GrowableArray<BasicBlockId>* GetTopologicalSortOrder() { 689 DCHECK(topological_order_ != nullptr); 690 return topological_order_; 691 } 692 693 GrowableArray<BasicBlockId>* GetTopologicalSortOrderLoopEnds() { 694 DCHECK(topological_order_loop_ends_ != nullptr); 695 return topological_order_loop_ends_; 696 } 697 698 GrowableArray<BasicBlockId>* GetTopologicalSortOrderIndexes() { 699 DCHECK(topological_order_indexes_ != nullptr); 700 return topological_order_indexes_; 701 } 702 703 GrowableArray<std::pair<uint16_t, bool>>* GetTopologicalSortOrderLoopHeadStack() { 704 DCHECK(topological_order_loop_head_stack_ != nullptr); 705 return topological_order_loop_head_stack_; 706 } 707 708 bool IsConst(int32_t s_reg) const { 709 return is_constant_v_->IsBitSet(s_reg); 710 } 711 712 bool IsConst(RegLocation loc) const { 713 return loc.orig_sreg < 0 ? false : IsConst(loc.orig_sreg); 714 } 715 716 int32_t ConstantValue(RegLocation loc) const { 717 DCHECK(IsConst(loc)); 718 return constant_values_[loc.orig_sreg]; 719 } 720 721 int32_t ConstantValue(int32_t s_reg) const { 722 DCHECK(IsConst(s_reg)); 723 return constant_values_[s_reg]; 724 } 725 726 int64_t ConstantValueWide(RegLocation loc) const { 727 DCHECK(IsConst(loc)); 728 return (static_cast<int64_t>(constant_values_[loc.orig_sreg + 1]) << 32) | 729 Low32Bits(static_cast<int64_t>(constant_values_[loc.orig_sreg])); 730 } 731 732 bool IsConstantNullRef(RegLocation loc) const { 733 return loc.ref && loc.is_const && (ConstantValue(loc) == 0); 734 } 735 736 int GetNumSSARegs() const { 737 return num_ssa_regs_; 738 } 739 740 void SetNumSSARegs(int new_num) { 741 /* 742 * TODO: It's theoretically possible to exceed 32767, though any cases which did 743 * would be filtered out with current settings. When orig_sreg field is removed 744 * from RegLocation, expand s_reg_low to handle all possible cases and remove DCHECK(). 745 */ 746 DCHECK_EQ(new_num, static_cast<int16_t>(new_num)); 747 num_ssa_regs_ = new_num; 748 } 749 750 unsigned int GetNumReachableBlocks() const { 751 return num_reachable_blocks_; 752 } 753 754 int GetUseCount(int vreg) const { 755 return use_counts_.Get(vreg); 756 } 757 758 int GetRawUseCount(int vreg) const { 759 return raw_use_counts_.Get(vreg); 760 } 761 762 int GetSSASubscript(int ssa_reg) const { 763 return ssa_subscripts_->Get(ssa_reg); 764 } 765 766 RegLocation GetRawSrc(MIR* mir, int num) { 767 DCHECK(num < mir->ssa_rep->num_uses); 768 RegLocation res = reg_location_[mir->ssa_rep->uses[num]]; 769 return res; 770 } 771 772 RegLocation GetRawDest(MIR* mir) { 773 DCHECK_GT(mir->ssa_rep->num_defs, 0); 774 RegLocation res = reg_location_[mir->ssa_rep->defs[0]]; 775 return res; 776 } 777 778 RegLocation GetDest(MIR* mir) { 779 RegLocation res = GetRawDest(mir); 780 DCHECK(!res.wide); 781 return res; 782 } 783 784 RegLocation GetSrc(MIR* mir, int num) { 785 RegLocation res = GetRawSrc(mir, num); 786 DCHECK(!res.wide); 787 return res; 788 } 789 790 RegLocation GetDestWide(MIR* mir) { 791 RegLocation res = GetRawDest(mir); 792 DCHECK(res.wide); 793 return res; 794 } 795 796 RegLocation GetSrcWide(MIR* mir, int low) { 797 RegLocation res = GetRawSrc(mir, low); 798 DCHECK(res.wide); 799 return res; 800 } 801 802 RegLocation GetBadLoc() { 803 return bad_loc; 804 } 805 806 int GetMethodSReg() const { 807 return method_sreg_; 808 } 809 810 /** 811 * @brief Used to obtain the number of compiler temporaries being used. 812 * @return Returns the number of compiler temporaries. 813 */ 814 size_t GetNumUsedCompilerTemps() const { 815 size_t total_num_temps = compiler_temps_.Size(); 816 DCHECK_LE(num_non_special_compiler_temps_, total_num_temps); 817 return total_num_temps; 818 } 819 820 /** 821 * @brief Used to obtain the number of non-special compiler temporaries being used. 822 * @return Returns the number of non-special compiler temporaries. 823 */ 824 size_t GetNumNonSpecialCompilerTemps() const { 825 return num_non_special_compiler_temps_; 826 } 827 828 /** 829 * @brief Used to set the total number of available non-special compiler temporaries. 830 * @details Can fail setting the new max if there are more temps being used than the new_max. 831 * @param new_max The new maximum number of non-special compiler temporaries. 832 * @return Returns true if the max was set and false if failed to set. 833 */ 834 bool SetMaxAvailableNonSpecialCompilerTemps(size_t new_max) { 835 if (new_max < GetNumNonSpecialCompilerTemps()) { 836 return false; 837 } else { 838 max_available_non_special_compiler_temps_ = new_max; 839 return true; 840 } 841 } 842 843 /** 844 * @brief Provides the number of non-special compiler temps available. 845 * @details Even if this returns zero, special compiler temps are guaranteed to be available. 846 * @return Returns the number of available temps. 847 */ 848 size_t GetNumAvailableNonSpecialCompilerTemps(); 849 850 /** 851 * @brief Used to obtain an existing compiler temporary. 852 * @param index The index of the temporary which must be strictly less than the 853 * number of temporaries. 854 * @return Returns the temporary that was asked for. 855 */ 856 CompilerTemp* GetCompilerTemp(size_t index) const { 857 return compiler_temps_.Get(index); 858 } 859 860 /** 861 * @brief Used to obtain the maximum number of compiler temporaries that can be requested. 862 * @return Returns the maximum number of compiler temporaries, whether used or not. 863 */ 864 size_t GetMaxPossibleCompilerTemps() const { 865 return max_available_special_compiler_temps_ + max_available_non_special_compiler_temps_; 866 } 867 868 /** 869 * @brief Used to obtain a new unique compiler temporary. 870 * @param ct_type Type of compiler temporary requested. 871 * @param wide Whether we should allocate a wide temporary. 872 * @return Returns the newly created compiler temporary. 873 */ 874 CompilerTemp* GetNewCompilerTemp(CompilerTempType ct_type, bool wide); 875 876 bool MethodIsLeaf() { 877 return attributes_ & METHOD_IS_LEAF; 878 } 879 880 RegLocation GetRegLocation(int index) { 881 DCHECK((index >= 0) && (index < num_ssa_regs_)); 882 return reg_location_[index]; 883 } 884 885 RegLocation GetMethodLoc() { 886 return reg_location_[method_sreg_]; 887 } 888 889 bool IsBackedge(BasicBlock* branch_bb, BasicBlockId target_bb_id) { 890 return ((target_bb_id != NullBasicBlockId) && 891 (GetBasicBlock(target_bb_id)->start_offset <= branch_bb->start_offset)); 892 } 893 894 bool IsBackwardsBranch(BasicBlock* branch_bb) { 895 return IsBackedge(branch_bb, branch_bb->taken) || IsBackedge(branch_bb, branch_bb->fall_through); 896 } 897 898 void CountBranch(DexOffset target_offset) { 899 if (target_offset <= current_offset_) { 900 backward_branches_++; 901 } else { 902 forward_branches_++; 903 } 904 } 905 906 int GetBranchCount() { 907 return backward_branches_ + forward_branches_; 908 } 909 910 // Is this vreg in the in set? 911 bool IsInVReg(int vreg) { 912 return (vreg >= cu_->num_regs); 913 } 914 915 void DumpCheckStats(); 916 MIR* FindMoveResult(BasicBlock* bb, MIR* mir); 917 int SRegToVReg(int ssa_reg) const; 918 void VerifyDataflow(); 919 void CheckForDominanceFrontier(BasicBlock* dom_bb, const BasicBlock* succ_bb); 920 void EliminateNullChecksAndInferTypesStart(); 921 bool EliminateNullChecksAndInferTypes(BasicBlock* bb); 922 void EliminateNullChecksAndInferTypesEnd(); 923 bool EliminateClassInitChecksGate(); 924 bool EliminateClassInitChecks(BasicBlock* bb); 925 void EliminateClassInitChecksEnd(); 926 bool ApplyGlobalValueNumberingGate(); 927 bool ApplyGlobalValueNumbering(BasicBlock* bb); 928 void ApplyGlobalValueNumberingEnd(); 929 /* 930 * Type inference handling helpers. Because Dalvik's bytecode is not fully typed, 931 * we have to do some work to figure out the sreg type. For some operations it is 932 * clear based on the opcode (i.e. ADD_FLOAT v0, v1, v2), but for others (MOVE), we 933 * may never know the "real" type. 934 * 935 * We perform the type inference operation by using an iterative walk over 936 * the graph, propagating types "defined" by typed opcodes to uses and defs in 937 * non-typed opcodes (such as MOVE). The Setxx(index) helpers are used to set defined 938 * types on typed opcodes (such as ADD_INT). The Setxx(index, is_xx) form is used to 939 * propagate types through non-typed opcodes such as PHI and MOVE. The is_xx flag 940 * tells whether our guess of the type is based on a previously typed definition. 941 * If so, the defined type takes precedence. Note that it's possible to have the same sreg 942 * show multiple defined types because dx treats constants as untyped bit patterns. 943 * The return value of the Setxx() helpers says whether or not the Setxx() action changed 944 * the current guess, and is used to know when to terminate the iterative walk. 945 */ 946 bool SetFp(int index, bool is_fp); 947 bool SetFp(int index); 948 bool SetCore(int index, bool is_core); 949 bool SetCore(int index); 950 bool SetRef(int index, bool is_ref); 951 bool SetRef(int index); 952 bool SetWide(int index, bool is_wide); 953 bool SetWide(int index); 954 bool SetHigh(int index, bool is_high); 955 bool SetHigh(int index); 956 957 bool PuntToInterpreter() { 958 return punt_to_interpreter_; 959 } 960 961 void SetPuntToInterpreter(bool val) { 962 punt_to_interpreter_ = val; 963 } 964 965 char* GetDalvikDisassembly(const MIR* mir); 966 void ReplaceSpecialChars(std::string& str); 967 std::string GetSSAName(int ssa_reg); 968 std::string GetSSANameWithConst(int ssa_reg, bool singles_only); 969 void GetBlockName(BasicBlock* bb, char* name); 970 const char* GetShortyFromTargetIdx(int); 971 void DumpMIRGraph(); 972 CallInfo* NewMemCallInfo(BasicBlock* bb, MIR* mir, InvokeType type, bool is_range); 973 BasicBlock* NewMemBB(BBType block_type, int block_id); 974 MIR* NewMIR(); 975 MIR* AdvanceMIR(BasicBlock** p_bb, MIR* mir); 976 BasicBlock* NextDominatedBlock(BasicBlock* bb); 977 bool LayoutBlocks(BasicBlock* bb); 978 void ComputeTopologicalSortOrder(); 979 BasicBlock* CreateNewBB(BBType block_type); 980 981 bool InlineSpecialMethodsGate(); 982 void InlineSpecialMethodsStart(); 983 void InlineSpecialMethods(BasicBlock* bb); 984 void InlineSpecialMethodsEnd(); 985 986 /** 987 * @brief Perform the initial preparation for the Method Uses. 988 */ 989 void InitializeMethodUses(); 990 991 /** 992 * @brief Perform the initial preparation for the Constant Propagation. 993 */ 994 void InitializeConstantPropagation(); 995 996 /** 997 * @brief Perform the initial preparation for the SSA Transformation. 998 */ 999 void SSATransformationStart(); 1000 1001 /** 1002 * @brief Insert a the operands for the Phi nodes. 1003 * @param bb the considered BasicBlock. 1004 * @return true 1005 */ 1006 bool InsertPhiNodeOperands(BasicBlock* bb); 1007 1008 /** 1009 * @brief Perform the cleanup after the SSA Transformation. 1010 */ 1011 void SSATransformationEnd(); 1012 1013 /** 1014 * @brief Perform constant propagation on a BasicBlock. 1015 * @param bb the considered BasicBlock. 1016 */ 1017 void DoConstantPropagation(BasicBlock* bb); 1018 1019 /** 1020 * @brief Count the uses in the BasicBlock 1021 * @param bb the BasicBlock 1022 */ 1023 void CountUses(struct BasicBlock* bb); 1024 1025 static uint64_t GetDataFlowAttributes(Instruction::Code opcode); 1026 static uint64_t GetDataFlowAttributes(MIR* mir); 1027 1028 /** 1029 * @brief Combine BasicBlocks 1030 * @param the BasicBlock we are considering 1031 */ 1032 void CombineBlocks(BasicBlock* bb); 1033 1034 void ClearAllVisitedFlags(); 1035 1036 void AllocateSSAUseData(MIR *mir, int num_uses); 1037 void AllocateSSADefData(MIR *mir, int num_defs); 1038 void CalculateBasicBlockInformation(); 1039 void InitializeBasicBlockData(); 1040 void ComputeDFSOrders(); 1041 void ComputeDefBlockMatrix(); 1042 void ComputeDominators(); 1043 void CompilerInitializeSSAConversion(); 1044 void InsertPhiNodes(); 1045 void DoDFSPreOrderSSARename(BasicBlock* block); 1046 1047 /* 1048 * IsDebugBuild sanity check: keep track of the Dex PCs for catch entries so that later on 1049 * we can verify that all catch entries have native PC entries. 1050 */ 1051 std::set<uint32_t> catches_; 1052 1053 // TODO: make these private. 1054 RegLocation* reg_location_; // Map SSA names to location. 1055 SafeMap<unsigned int, unsigned int> block_id_map_; // Block collapse lookup cache. 1056 1057 static const char* extended_mir_op_names_[kMirOpLast - kMirOpFirst]; 1058 static const uint32_t analysis_attributes_[kMirOpLast]; 1059 1060 void HandleSSADef(int* defs, int dalvik_reg, int reg_index); 1061 bool InferTypeAndSize(BasicBlock* bb, MIR* mir, bool changed); 1062 1063 // Used for removing redudant suspend tests 1064 void AppendGenSuspendTestList(BasicBlock* bb) { 1065 if (gen_suspend_test_list_.Size() == 0 || 1066 gen_suspend_test_list_.Get(gen_suspend_test_list_.Size() - 1) != bb) { 1067 gen_suspend_test_list_.Insert(bb); 1068 } 1069 } 1070 1071 /* This is used to check if there is already a method call dominating the 1072 * source basic block of a backedge and being dominated by the target basic 1073 * block of the backedge. 1074 */ 1075 bool HasSuspendTestBetween(BasicBlock* source, BasicBlockId target_id); 1076 1077 protected: 1078 int FindCommonParent(int block1, int block2); 1079 void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1, 1080 const ArenaBitVector* src2); 1081 void HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v, 1082 ArenaBitVector* live_in_v, int dalvik_reg_id); 1083 void HandleDef(ArenaBitVector* def_v, int dalvik_reg_id); 1084 void HandleExtended(ArenaBitVector* use_v, ArenaBitVector* def_v, 1085 ArenaBitVector* live_in_v, 1086 const MIR::DecodedInstruction& d_insn); 1087 bool DoSSAConversion(BasicBlock* bb); 1088 bool InvokeUsesMethodStar(MIR* mir); 1089 int ParseInsn(const uint16_t* code_ptr, MIR::DecodedInstruction* decoded_instruction); 1090 bool ContentIsInsn(const uint16_t* code_ptr); 1091 BasicBlock* SplitBlock(DexOffset code_offset, BasicBlock* orig_block, 1092 BasicBlock** immed_pred_block_p); 1093 BasicBlock* FindBlock(DexOffset code_offset, bool split, bool create, 1094 BasicBlock** immed_pred_block_p); 1095 void ProcessTryCatchBlocks(); 1096 bool IsBadMonitorExitCatch(NarrowDexOffset monitor_exit_offset, NarrowDexOffset catch_offset); 1097 BasicBlock* ProcessCanBranch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1098 int flags, const uint16_t* code_ptr, const uint16_t* code_end); 1099 BasicBlock* ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1100 int flags); 1101 BasicBlock* ProcessCanThrow(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1102 int flags, ArenaBitVector* try_block_addr, const uint16_t* code_ptr, 1103 const uint16_t* code_end); 1104 int AddNewSReg(int v_reg); 1105 void HandleSSAUse(int* uses, int dalvik_reg, int reg_index); 1106 void DataFlowSSAFormat35C(MIR* mir); 1107 void DataFlowSSAFormat3RC(MIR* mir); 1108 void DataFlowSSAFormatExtended(MIR* mir); 1109 bool FindLocalLiveIn(BasicBlock* bb); 1110 bool VerifyPredInfo(BasicBlock* bb); 1111 BasicBlock* NeedsVisit(BasicBlock* bb); 1112 BasicBlock* NextUnvisitedSuccessor(BasicBlock* bb); 1113 void MarkPreOrder(BasicBlock* bb); 1114 void RecordDFSOrders(BasicBlock* bb); 1115 void ComputeDomPostOrderTraversal(BasicBlock* bb); 1116 void SetConstant(int32_t ssa_reg, int value); 1117 void SetConstantWide(int ssa_reg, int64_t value); 1118 int GetSSAUseCount(int s_reg); 1119 bool BasicBlockOpt(BasicBlock* bb); 1120 bool BuildExtendedBBList(struct BasicBlock* bb); 1121 bool FillDefBlockMatrix(BasicBlock* bb); 1122 void InitializeDominationInfo(BasicBlock* bb); 1123 bool ComputeblockIDom(BasicBlock* bb); 1124 bool ComputeBlockDominators(BasicBlock* bb); 1125 bool SetDominators(BasicBlock* bb); 1126 bool ComputeBlockLiveIns(BasicBlock* bb); 1127 bool ComputeDominanceFrontier(BasicBlock* bb); 1128 1129 void CountChecks(BasicBlock* bb); 1130 void AnalyzeBlock(BasicBlock* bb, struct MethodStats* stats); 1131 bool ComputeSkipCompilation(struct MethodStats* stats, bool skip_default, 1132 std::string* skip_message); 1133 1134 CompilationUnit* const cu_; 1135 GrowableArray<int>* ssa_base_vregs_; 1136 GrowableArray<int>* ssa_subscripts_; 1137 // Map original Dalvik virtual reg i to the current SSA name. 1138 int* vreg_to_ssa_map_; // length == method->registers_size 1139 int* ssa_last_defs_; // length == method->registers_size 1140 ArenaBitVector* is_constant_v_; // length == num_ssa_reg 1141 int* constant_values_; // length == num_ssa_reg 1142 // Use counts of ssa names. 1143 GrowableArray<uint32_t> use_counts_; // Weighted by nesting depth 1144 GrowableArray<uint32_t> raw_use_counts_; // Not weighted 1145 unsigned int num_reachable_blocks_; 1146 unsigned int max_num_reachable_blocks_; 1147 GrowableArray<BasicBlockId>* dfs_order_; 1148 GrowableArray<BasicBlockId>* dfs_post_order_; 1149 GrowableArray<BasicBlockId>* dom_post_order_traversal_; 1150 GrowableArray<BasicBlockId>* topological_order_; 1151 // Indexes in topological_order_ need to be only as big as the BasicBlockId. 1152 COMPILE_ASSERT(sizeof(BasicBlockId) == sizeof(uint16_t), assuming_16_bit_BasicBlockId); 1153 // For each loop head, remember the past-the-end index of the end of the loop. 0 if not loop head. 1154 GrowableArray<uint16_t>* topological_order_loop_ends_; 1155 // Map BB ids to topological_order_ indexes. 0xffff if not included (hidden or null block). 1156 GrowableArray<uint16_t>* topological_order_indexes_; 1157 // Stack of the loop head indexes and recalculation flags for RepeatingTopologicalSortIterator. 1158 GrowableArray<std::pair<uint16_t, bool>>* topological_order_loop_head_stack_; 1159 int* i_dom_list_; 1160 ArenaBitVector** def_block_matrix_; // num_dalvik_register x num_blocks. 1161 std::unique_ptr<ScopedArenaAllocator> temp_scoped_alloc_; 1162 uint16_t* temp_insn_data_; 1163 uint32_t temp_bit_vector_size_; 1164 ArenaBitVector* temp_bit_vector_; 1165 std::unique_ptr<GlobalValueNumbering> temp_gvn_; 1166 static const int kInvalidEntry = -1; 1167 GrowableArray<BasicBlock*> block_list_; 1168 ArenaBitVector* try_block_addr_; 1169 BasicBlock* entry_block_; 1170 BasicBlock* exit_block_; 1171 unsigned int num_blocks_; 1172 const DexFile::CodeItem* current_code_item_; 1173 GrowableArray<uint16_t> dex_pc_to_block_map_; // FindBlock lookup cache. 1174 std::vector<DexCompilationUnit*> m_units_; // List of methods included in this graph 1175 typedef std::pair<int, int> MIRLocation; // Insert point, (m_unit_ index, offset) 1176 std::vector<MIRLocation> method_stack_; // Include stack 1177 int current_method_; 1178 DexOffset current_offset_; // Offset in code units 1179 int def_count_; // Used to estimate size of ssa name storage. 1180 int* opcode_count_; // Dex opcode coverage stats. 1181 int num_ssa_regs_; // Number of names following SSA transformation. 1182 std::vector<BasicBlockId> extended_basic_blocks_; // Heads of block "traces". 1183 int method_sreg_; 1184 unsigned int attributes_; 1185 Checkstats* checkstats_; 1186 ArenaAllocator* arena_; 1187 int backward_branches_; 1188 int forward_branches_; 1189 GrowableArray<CompilerTemp*> compiler_temps_; 1190 size_t num_non_special_compiler_temps_; 1191 size_t max_available_non_special_compiler_temps_; 1192 size_t max_available_special_compiler_temps_; 1193 bool punt_to_interpreter_; // Difficult or not worthwhile - just interpret. 1194 uint64_t merged_df_flags_; 1195 GrowableArray<MirIFieldLoweringInfo> ifield_lowering_infos_; 1196 GrowableArray<MirSFieldLoweringInfo> sfield_lowering_infos_; 1197 GrowableArray<MirMethodLoweringInfo> method_lowering_infos_; 1198 static const uint64_t oat_data_flow_attributes_[kMirOpLast]; 1199 GrowableArray<BasicBlock*> gen_suspend_test_list_; // List of blocks containing suspend tests 1200 1201 friend class ClassInitCheckEliminationTest; 1202 friend class GlobalValueNumberingTest; 1203 friend class LocalValueNumberingTest; 1204 friend class TopologicalSortOrderTest; 1205}; 1206 1207} // namespace art 1208 1209#endif // ART_COMPILER_DEX_MIR_GRAPH_H_ 1210