codegen_arm.h revision 63999683329612292d534e6be09dbde9480f1250
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_ 18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_ 19 20#include "arm_lir.h" 21#include "dex/compiler_internals.h" 22 23namespace art { 24 25class ArmMir2Lir FINAL : public Mir2Lir { 26 public: 27 ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 28 29 // Required for target - codegen helpers. 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 31 RegLocation rl_dest, int lit); 32 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 33 LIR* CheckSuspendUsingLoad() OVERRIDE; 34 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; 35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 36 OpSize size, VolatileKind is_volatile) OVERRIDE; 37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 38 OpSize size) OVERRIDE; 39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 42 OpSize size, VolatileKind is_volatile) OVERRIDE; 43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 44 OpSize size) OVERRIDE; 45 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 46 47 // Required for target - register utilities. 48 RegStorage TargetReg(SpecialTargetRegister reg); 49 RegStorage GetArgMappingToPhysicalReg(int arg_num); 50 RegLocation GetReturnAlt(); 51 RegLocation GetReturnWideAlt(); 52 RegLocation LocCReturn(); 53 RegLocation LocCReturnRef(); 54 RegLocation LocCReturnDouble(); 55 RegLocation LocCReturnFloat(); 56 RegLocation LocCReturnWide(); 57 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 58 void AdjustSpillMask(); 59 void ClobberCallerSave(); 60 void FreeCallTemps(); 61 void LockCallTemps(); 62 void MarkPreservedSingle(int v_reg, RegStorage reg); 63 void MarkPreservedDouble(int v_reg, RegStorage reg); 64 void CompilerInitializeRegAlloc(); 65 66 // Required for target - miscellaneous. 67 void AssembleLIR(); 68 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); 69 int AssignInsnOffsets(); 70 void AssignOffsets(); 71 static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); 72 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 73 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 74 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 75 const char* GetTargetInstFmt(int opcode); 76 const char* GetTargetInstName(int opcode); 77 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 78 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 79 uint64_t GetTargetInstFlags(int opcode); 80 size_t GetInsnSize(LIR* lir) OVERRIDE; 81 bool IsUnconditionalBranch(LIR* lir); 82 83 // Get the register class for load/store of a field. 84 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 85 86 // Required for target - Dalvik-level generators. 87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 88 RegLocation rl_src1, RegLocation rl_src2); 89 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 90 RegLocation rl_index, RegLocation rl_dest, int scale); 91 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 92 RegLocation rl_src, int scale, bool card_mark); 93 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 94 RegLocation rl_src1, RegLocation rl_shift); 95 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 96 RegLocation rl_src2); 97 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 98 RegLocation rl_src2); 99 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 100 RegLocation rl_src2); 101 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 102 RegLocation rl_src2); 103 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 104 RegLocation rl_src2); 105 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 106 RegLocation rl_src2); 107 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 108 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 109 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 110 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 111 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 112 bool GenInlinedSqrt(CallInfo* info); 113 bool GenInlinedPeek(CallInfo* info, OpSize size); 114 bool GenInlinedPoke(CallInfo* info, OpSize size); 115 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 116 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 117 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 118 RegLocation rl_src2); 119 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 120 RegLocation rl_src2); 121 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 122 RegLocation rl_src2); 123 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 124 RegLocation rl_src2, bool is_div); 125 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 126 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 127 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 128 void GenDivZeroCheckWide(RegStorage reg); 129 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 130 void GenExitSequence(); 131 void GenSpecialExitSequence(); 132 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 133 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 134 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 135 void GenSelect(BasicBlock* bb, MIR* mir); 136 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 137 int32_t true_val, int32_t false_val, RegStorage rs_dest, 138 int dest_reg_class) OVERRIDE; 139 bool GenMemBarrier(MemBarrierKind barrier_kind); 140 void GenMonitorEnter(int opt_flags, RegLocation rl_src); 141 void GenMonitorExit(int opt_flags, RegLocation rl_src); 142 void GenMoveException(RegLocation rl_dest); 143 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 144 int first_bit, int second_bit); 145 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 146 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 147 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 148 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 149 150 // Required for target - single operation generators. 151 LIR* OpUnconditionalBranch(LIR* target); 152 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 153 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 154 LIR* OpCondBranch(ConditionCode cc, LIR* target); 155 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 156 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 157 LIR* OpIT(ConditionCode cond, const char* guide); 158 void UpdateIT(LIR* it, const char* new_guide); 159 void OpEndIT(LIR* it); 160 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 161 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 162 LIR* OpReg(OpKind op, RegStorage r_dest_src); 163 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 164 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 165 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 166 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 167 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 168 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 169 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 170 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 171 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 172 LIR* OpTestSuspend(LIR* target); 173 LIR* OpVldm(RegStorage r_base, int count); 174 LIR* OpVstm(RegStorage r_base, int count); 175 void OpRegCopyWide(RegStorage dest, RegStorage src); 176 177 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); 178 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 179 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 180 int shift); 181 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 182 static const ArmEncodingMap EncodingMap[kArmLast]; 183 int EncodeShift(int code, int amount); 184 int ModifiedImmediate(uint32_t value); 185 ArmConditionCode ArmConditionEncoding(ConditionCode code); 186 bool InexpensiveConstantInt(int32_t value); 187 bool InexpensiveConstantFloat(int32_t value); 188 bool InexpensiveConstantLong(int64_t value); 189 bool InexpensiveConstantDouble(int64_t value); 190 RegStorage AllocPreservedDouble(int s_reg); 191 RegStorage AllocPreservedSingle(int s_reg); 192 193 bool WideGPRsAreAliases() OVERRIDE { 194 return false; // Wide GPRs are formed by pairing. 195 } 196 bool WideFPRsAreAliases() OVERRIDE { 197 return false; // Wide FPRs are formed by pairing. 198 } 199 200 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; 201 size_t GetInstructionOffset(LIR* lir); 202 203 private: 204 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val, 205 ConditionCode ccode); 206 LIR* LoadFPConstantValue(int r_dest, int value); 207 LIR* LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base, 208 int displacement, RegStorage r_src_dest, 209 RegStorage r_work = RegStorage::InvalidReg()); 210 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 211 void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 212 void AssignDataOffsets(); 213 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 214 bool is_div, bool check_zero); 215 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); 216 typedef struct { 217 OpKind op; 218 uint32_t shift; 219 } EasyMultiplyOp; 220 bool GetEasyMultiplyOp(int lit, EasyMultiplyOp* op); 221 bool GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops); 222 void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops); 223 224 static constexpr ResourceMask GetRegMaskArm(RegStorage reg); 225 static constexpr ResourceMask EncodeArmRegList(int reg_list); 226 static constexpr ResourceMask EncodeArmRegFpcsList(int reg_list); 227}; 228 229} // namespace art 230 231#endif // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_ 232