codegen_arm.h revision 8c18c2aaedb171f9b03ec49c94b0e33449dc411b 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
19
20#include "arm_lir.h"
21#include "dex/compiler_internals.h"
22
23namespace art {
24
25class ArmMir2Lir FINAL : public Mir2Lir {
26  public:
27    ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen helpers.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
33    LIR* CheckSuspendUsingLoad() OVERRIDE;
34    RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
35    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
36                      OpSize size, VolatileKind is_volatile) OVERRIDE;
37    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
38                         OpSize size) OVERRIDE;
39    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
42                       OpSize size, VolatileKind is_volatile) OVERRIDE;
43    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
44                          OpSize size) OVERRIDE;
45    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
46
47    // Required for target - register utilities.
48    RegStorage TargetReg(SpecialTargetRegister reg);
49    RegStorage GetArgMappingToPhysicalReg(int arg_num);
50    RegLocation GetReturnAlt();
51    RegLocation GetReturnWideAlt();
52    RegLocation LocCReturn();
53    RegLocation LocCReturnRef();
54    RegLocation LocCReturnDouble();
55    RegLocation LocCReturnFloat();
56    RegLocation LocCReturnWide();
57    ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
58    void AdjustSpillMask();
59    void ClobberCallerSave();
60    void FreeCallTemps();
61    void LockCallTemps();
62    void MarkPreservedSingle(int v_reg, RegStorage reg);
63    void MarkPreservedDouble(int v_reg, RegStorage reg);
64    void CompilerInitializeRegAlloc();
65
66    // Required for target - miscellaneous.
67    void AssembleLIR();
68    uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);
69    int AssignInsnOffsets();
70    void AssignOffsets();
71    static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
72    void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
73    void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
74                                  ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
75    const char* GetTargetInstFmt(int opcode);
76    const char* GetTargetInstName(int opcode);
77    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
78    ResourceMask GetPCUseDefEncoding() const OVERRIDE;
79    uint64_t GetTargetInstFlags(int opcode);
80    size_t GetInsnSize(LIR* lir) OVERRIDE;
81    bool IsUnconditionalBranch(LIR* lir);
82
83    // Get the register class for load/store of a field.
84    RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
85
86    // Required for target - Dalvik-level generators.
87    void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
88                        RegLocation rl_src2) OVERRIDE;
89    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
90                           RegLocation rl_src1, RegLocation rl_src2);
91    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
92                     RegLocation rl_index, RegLocation rl_dest, int scale);
93    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
94                     RegLocation rl_src, int scale, bool card_mark);
95    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
96                           RegLocation rl_src1, RegLocation rl_shift);
97    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
98                          RegLocation rl_src2);
99    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
100                         RegLocation rl_src2);
101    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
102                  RegLocation rl_src2);
103    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
104    bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE;
105    bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE;
106    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
107    bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long);
108    bool GenInlinedSqrt(CallInfo* info);
109    bool GenInlinedPeek(CallInfo* info, OpSize size);
110    bool GenInlinedPoke(CallInfo* info, OpSize size);
111    bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE;
112    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
113    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
114    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
115    void GenDivZeroCheckWide(RegStorage reg);
116    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
117    void GenExitSequence();
118    void GenSpecialExitSequence();
119    void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
120    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
121    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
122    void GenSelect(BasicBlock* bb, MIR* mir);
123    void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
124                          int32_t true_val, int32_t false_val, RegStorage rs_dest,
125                          int dest_reg_class) OVERRIDE;
126    bool GenMemBarrier(MemBarrierKind barrier_kind);
127    void GenMonitorEnter(int opt_flags, RegLocation rl_src);
128    void GenMonitorExit(int opt_flags, RegLocation rl_src);
129    void GenMoveException(RegLocation rl_dest);
130    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
131                                       int first_bit, int second_bit);
132    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
133    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
134    void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
135    void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
136
137    // Required for target - single operation generators.
138    LIR* OpUnconditionalBranch(LIR* target);
139    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
140    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
141    LIR* OpCondBranch(ConditionCode cc, LIR* target);
142    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
143    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
144    LIR* OpIT(ConditionCode cond, const char* guide);
145    void UpdateIT(LIR* it, const char* new_guide);
146    void OpEndIT(LIR* it);
147    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
148    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
149    LIR* OpReg(OpKind op, RegStorage r_dest_src);
150    void OpRegCopy(RegStorage r_dest, RegStorage r_src);
151    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
152    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
153    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
154    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
155    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
156    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
157    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
158    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
159    LIR* OpTestSuspend(LIR* target);
160    LIR* OpVldm(RegStorage r_base, int count);
161    LIR* OpVstm(RegStorage r_base, int count);
162    void OpRegCopyWide(RegStorage dest, RegStorage src);
163
164    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
165    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
166    LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
167                          int shift);
168    LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
169    static const ArmEncodingMap EncodingMap[kArmLast];
170    int EncodeShift(int code, int amount);
171    int ModifiedImmediate(uint32_t value);
172    ArmConditionCode ArmConditionEncoding(ConditionCode code);
173    bool InexpensiveConstantInt(int32_t value);
174    bool InexpensiveConstantFloat(int32_t value);
175    bool InexpensiveConstantLong(int64_t value);
176    bool InexpensiveConstantDouble(int64_t value);
177    RegStorage AllocPreservedDouble(int s_reg);
178    RegStorage AllocPreservedSingle(int s_reg);
179
180    bool WideGPRsAreAliases() OVERRIDE {
181      return false;  // Wide GPRs are formed by pairing.
182    }
183    bool WideFPRsAreAliases() OVERRIDE {
184      return false;  // Wide FPRs are formed by pairing.
185    }
186
187    LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
188    size_t GetInstructionOffset(LIR* lir);
189
190  private:
191    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
192    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
193                    RegLocation rl_src2);
194    void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,
195                                  ConditionCode ccode);
196    LIR* LoadFPConstantValue(int r_dest, int value);
197    LIR* LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base,
198                                              int displacement, RegStorage r_src_dest,
199                                              RegStorage r_work = RegStorage::InvalidReg());
200    void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
201    void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
202    void AssignDataOffsets();
203    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
204                          bool is_div, bool check_zero);
205    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
206    typedef struct {
207      OpKind op;
208      uint32_t shift;
209    } EasyMultiplyOp;
210    bool GetEasyMultiplyOp(int lit, EasyMultiplyOp* op);
211    bool GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops);
212    void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops);
213
214    static constexpr ResourceMask GetRegMaskArm(RegStorage reg);
215    static constexpr ResourceMask EncodeArmRegList(int reg_list);
216    static constexpr ResourceMask EncodeArmRegFpcsList(int reg_list);
217};
218
219}  // namespace art
220
221#endif  // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
222