codegen_arm.h revision f9d6aede77c700118e225f8312cd888262b77862 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
19
20#include "arm_lir.h"
21#include "dex/compiler_internals.h"
22
23namespace art {
24
25class ArmMir2Lir FINAL : public Mir2Lir {
26  public:
27    ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen helpers.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
33    LIR* CheckSuspendUsingLoad() OVERRIDE;
34    RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE;
35    RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE;
36    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37                      OpSize size, VolatileKind is_volatile) OVERRIDE;
38    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39                         OpSize size) OVERRIDE;
40    LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
41                             RegStorage r_dest, OpSize size) OVERRIDE;
42    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
43    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
44    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
45                       OpSize size, VolatileKind is_volatile) OVERRIDE;
46    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
47                          OpSize size) OVERRIDE;
48    LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
49                              RegStorage r_src, OpSize size) OVERRIDE;
50    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
51
52    // Required for target - register utilities.
53    RegStorage TargetReg(SpecialTargetRegister reg);
54    RegStorage GetArgMappingToPhysicalReg(int arg_num);
55    RegLocation GetReturnAlt();
56    RegLocation GetReturnWideAlt();
57    RegLocation LocCReturn();
58    RegLocation LocCReturnRef();
59    RegLocation LocCReturnDouble();
60    RegLocation LocCReturnFloat();
61    RegLocation LocCReturnWide();
62    ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
63    void AdjustSpillMask();
64    void ClobberCallerSave();
65    void FreeCallTemps();
66    void LockCallTemps();
67    void MarkPreservedSingle(int v_reg, RegStorage reg);
68    void MarkPreservedDouble(int v_reg, RegStorage reg);
69    void CompilerInitializeRegAlloc();
70
71    // Required for target - miscellaneous.
72    void AssembleLIR();
73    uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);
74    int AssignInsnOffsets();
75    void AssignOffsets();
76    static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
77    void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
78    void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
79                                  ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
80    const char* GetTargetInstFmt(int opcode);
81    const char* GetTargetInstName(int opcode);
82    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
83    ResourceMask GetPCUseDefEncoding() const OVERRIDE;
84    uint64_t GetTargetInstFlags(int opcode);
85    size_t GetInsnSize(LIR* lir) OVERRIDE;
86    bool IsUnconditionalBranch(LIR* lir);
87
88    // Check support for volatile load/store of a given size.
89    bool SupportsVolatileLoadStore(OpSize size) OVERRIDE;
90    // Get the register class for load/store of a field.
91    RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
92
93    // Required for target - Dalvik-level generators.
94    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
95                           RegLocation rl_src1, RegLocation rl_src2);
96    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
97                     RegLocation rl_index, RegLocation rl_dest, int scale);
98    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
99                     RegLocation rl_src, int scale, bool card_mark);
100    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
101                           RegLocation rl_src1, RegLocation rl_shift);
102    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
103                    RegLocation rl_src2);
104    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105                    RegLocation rl_src2);
106    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107                    RegLocation rl_src2);
108    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
109                          RegLocation rl_src2);
110    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
111                         RegLocation rl_src2);
112    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
113                  RegLocation rl_src2);
114    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
115    bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE;
116    bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE;
117    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
118    bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long);
119    bool GenInlinedSqrt(CallInfo* info);
120    bool GenInlinedPeek(CallInfo* info, OpSize size);
121    bool GenInlinedPoke(CallInfo* info, OpSize size);
122    void GenNotLong(RegLocation rl_dest, RegLocation rl_src);
123    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
124    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
125                   RegLocation rl_src2);
126    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
127                    RegLocation rl_src2);
128    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
129                    RegLocation rl_src2);
130    void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
131                       RegLocation rl_src2, bool is_div);
132    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
133    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
134    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
135    void GenDivZeroCheckWide(RegStorage reg);
136    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
137    void GenExitSequence();
138    void GenSpecialExitSequence();
139    void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
140    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
141    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
142    void GenSelect(BasicBlock* bb, MIR* mir);
143    bool GenMemBarrier(MemBarrierKind barrier_kind);
144    void GenMonitorEnter(int opt_flags, RegLocation rl_src);
145    void GenMonitorExit(int opt_flags, RegLocation rl_src);
146    void GenMoveException(RegLocation rl_dest);
147    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
148                                       int first_bit, int second_bit);
149    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
150    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
151    void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
152    void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
153
154    // Required for target - single operation generators.
155    LIR* OpUnconditionalBranch(LIR* target);
156    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
157    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
158    LIR* OpCondBranch(ConditionCode cc, LIR* target);
159    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
160    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
161    LIR* OpIT(ConditionCode cond, const char* guide);
162    void UpdateIT(LIR* it, const char* new_guide);
163    void OpEndIT(LIR* it);
164    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
165    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
166    LIR* OpReg(OpKind op, RegStorage r_dest_src);
167    void OpRegCopy(RegStorage r_dest, RegStorage r_src);
168    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
169    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
170    LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
171    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
172    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
173    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
174    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
175    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
176    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
177    LIR* OpTestSuspend(LIR* target);
178    LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE;
179    LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE;
180    LIR* OpVldm(RegStorage r_base, int count);
181    LIR* OpVstm(RegStorage r_base, int count);
182    void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
183    void OpRegCopyWide(RegStorage dest, RegStorage src);
184    void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE;
185    void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE;
186
187    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
188    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
189    LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
190                          int shift);
191    LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
192    static const ArmEncodingMap EncodingMap[kArmLast];
193    int EncodeShift(int code, int amount);
194    int ModifiedImmediate(uint32_t value);
195    ArmConditionCode ArmConditionEncoding(ConditionCode code);
196    bool InexpensiveConstantInt(int32_t value);
197    bool InexpensiveConstantFloat(int32_t value);
198    bool InexpensiveConstantLong(int64_t value);
199    bool InexpensiveConstantDouble(int64_t value);
200    RegStorage AllocPreservedDouble(int s_reg);
201    RegStorage AllocPreservedSingle(int s_reg);
202
203    bool WideGPRsAreAliases() OVERRIDE {
204      return false;  // Wide GPRs are formed by pairing.
205    }
206    bool WideFPRsAreAliases() OVERRIDE {
207      return false;  // Wide FPRs are formed by pairing.
208    }
209
210  private:
211    void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,
212                                  ConditionCode ccode);
213    LIR* LoadFPConstantValue(int r_dest, int value);
214    LIR* LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base,
215                                              int displacement, RegStorage r_src_dest,
216                                              RegStorage r_work = RegStorage::InvalidReg());
217    void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
218    void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
219    void AssignDataOffsets();
220    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
221                          bool is_div, bool check_zero);
222    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
223    typedef struct {
224      OpKind op;
225      uint32_t shift;
226    } EasyMultiplyOp;
227    bool GetEasyMultiplyOp(int lit, EasyMultiplyOp* op);
228    bool GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops);
229    void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops);
230
231    static constexpr ResourceMask GetRegMaskArm(RegStorage reg);
232    static constexpr ResourceMask EncodeArmRegList(int reg_list);
233    static constexpr ResourceMask EncodeArmRegFpcsList(int reg_list);
234};
235
236}  // namespace art
237
238#endif  // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
239