int_arm.cc revision bebee4fd10e5db6cb07f59bc0f73297c900ea5f0
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the Thumb2 ISA. */ 18 19#include "arm_lir.h" 20#include "codegen_arm.h" 21#include "dex/quick/mir_to_lir-inl.h" 22#include "dex/reg_storage_eq.h" 23#include "entrypoints/quick/quick_entrypoints.h" 24#include "mirror/array.h" 25 26namespace art { 27 28LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { 29 OpRegReg(kOpCmp, src1, src2); 30 return OpCondBranch(cond, target); 31} 32 33/* 34 * Generate a Thumb2 IT instruction, which can nullify up to 35 * four subsequent instructions based on a condition and its 36 * inverse. The condition applies to the first instruction, which 37 * is executed if the condition is met. The string "guide" consists 38 * of 0 to 3 chars, and applies to the 2nd through 4th instruction. 39 * A "T" means the instruction is executed if the condition is 40 * met, and an "E" means the instruction is executed if the condition 41 * is not met. 42 */ 43LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { 44 int mask; 45 int mask3 = 0; 46 int mask2 = 0; 47 int mask1 = 0; 48 ArmConditionCode code = ArmConditionEncoding(ccode); 49 int cond_bit = code & 1; 50 int alt_bit = cond_bit ^ 1; 51 52 // Note: case fallthroughs intentional 53 switch (strlen(guide)) { 54 case 3: 55 mask1 = (guide[2] == 'T') ? cond_bit : alt_bit; 56 case 2: 57 mask2 = (guide[1] == 'T') ? cond_bit : alt_bit; 58 case 1: 59 mask3 = (guide[0] == 'T') ? cond_bit : alt_bit; 60 break; 61 case 0: 62 break; 63 default: 64 LOG(FATAL) << "OAT: bad case in OpIT"; 65 } 66 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | 67 (1 << (3 - strlen(guide))); 68 return NewLIR2(kThumb2It, code, mask); 69} 70 71void ArmMir2Lir::UpdateIT(LIR* it, const char* new_guide) { 72 int mask; 73 int mask3 = 0; 74 int mask2 = 0; 75 int mask1 = 0; 76 ArmConditionCode code = static_cast<ArmConditionCode>(it->operands[0]); 77 int cond_bit = code & 1; 78 int alt_bit = cond_bit ^ 1; 79 80 // Note: case fallthroughs intentional 81 switch (strlen(new_guide)) { 82 case 3: 83 mask1 = (new_guide[2] == 'T') ? cond_bit : alt_bit; 84 case 2: 85 mask2 = (new_guide[1] == 'T') ? cond_bit : alt_bit; 86 case 1: 87 mask3 = (new_guide[0] == 'T') ? cond_bit : alt_bit; 88 break; 89 case 0: 90 break; 91 default: 92 LOG(FATAL) << "OAT: bad case in UpdateIT"; 93 } 94 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | 95 (1 << (3 - strlen(new_guide))); 96 it->operands[1] = mask; 97} 98 99void ArmMir2Lir::OpEndIT(LIR* it) { 100 // TODO: use the 'it' pointer to do some checks with the LIR, for example 101 // we could check that the number of instructions matches the mask 102 // in the IT instruction. 103 CHECK(it != nullptr); 104 GenBarrier(); 105} 106 107/* 108 * 64-bit 3way compare function. 109 * mov rX, #-1 110 * cmp op1hi, op2hi 111 * blt done 112 * bgt flip 113 * sub rX, op1lo, op2lo (treat as unsigned) 114 * beq done 115 * ite hi 116 * mov(hi) rX, #-1 117 * mov(!hi) rX, #1 118 * flip: 119 * neg rX 120 * done: 121 */ 122void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 123 LIR* target1; 124 LIR* target2; 125 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 126 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 127 RegStorage t_reg = AllocTemp(); 128 LoadConstant(t_reg, -1); 129 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 130 LIR* branch1 = OpCondBranch(kCondLt, NULL); 131 LIR* branch2 = OpCondBranch(kCondGt, NULL); 132 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 133 LIR* branch3 = OpCondBranch(kCondEq, NULL); 134 135 LIR* it = OpIT(kCondHi, "E"); 136 NewLIR2(kThumb2MovI8M, t_reg.GetReg(), ModifiedImmediate(-1)); 137 LoadConstant(t_reg, 1); 138 OpEndIT(it); 139 140 target2 = NewLIR0(kPseudoTargetLabel); 141 OpRegReg(kOpNeg, t_reg, t_reg); 142 143 target1 = NewLIR0(kPseudoTargetLabel); 144 145 RegLocation rl_temp = LocCReturn(); // Just using as template, will change 146 rl_temp.reg.SetReg(t_reg.GetReg()); 147 StoreValue(rl_dest, rl_temp); 148 FreeTemp(t_reg); 149 150 branch1->target = target1; 151 branch2->target = target2; 152 branch3->target = branch1->target; 153} 154 155void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 156 int64_t val, ConditionCode ccode) { 157 int32_t val_lo = Low32Bits(val); 158 int32_t val_hi = High32Bits(val); 159 DCHECK_GE(ModifiedImmediate(val_lo), 0); 160 DCHECK_GE(ModifiedImmediate(val_hi), 0); 161 LIR* taken = &block_label_list_[bb->taken]; 162 LIR* not_taken = &block_label_list_[bb->fall_through]; 163 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 164 RegStorage low_reg = rl_src1.reg.GetLow(); 165 RegStorage high_reg = rl_src1.reg.GetHigh(); 166 167 if (val == 0 && (ccode == kCondEq || ccode == kCondNe)) { 168 RegStorage t_reg = AllocTemp(); 169 NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), low_reg.GetReg(), high_reg.GetReg(), 0); 170 FreeTemp(t_reg); 171 OpCondBranch(ccode, taken); 172 return; 173 } 174 175 switch (ccode) { 176 case kCondEq: 177 case kCondNe: 178 OpCmpImmBranch(kCondNe, high_reg, val_hi, (ccode == kCondEq) ? not_taken : taken); 179 break; 180 case kCondLt: 181 OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); 182 OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); 183 ccode = kCondUlt; 184 break; 185 case kCondLe: 186 OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); 187 OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); 188 ccode = kCondLs; 189 break; 190 case kCondGt: 191 OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); 192 OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); 193 ccode = kCondHi; 194 break; 195 case kCondGe: 196 OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); 197 OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); 198 ccode = kCondUge; 199 break; 200 default: 201 LOG(FATAL) << "Unexpected ccode: " << ccode; 202 } 203 OpCmpImmBranch(ccode, low_reg, val_lo, taken); 204} 205 206void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 207 int32_t true_val, int32_t false_val, RegStorage rs_dest, 208 int dest_reg_class) { 209 // TODO: Generalize the IT below to accept more than one-instruction loads. 210 DCHECK(InexpensiveConstantInt(true_val)); 211 DCHECK(InexpensiveConstantInt(false_val)); 212 213 if ((true_val == 0 && code == kCondEq) || 214 (false_val == 0 && code == kCondNe)) { 215 OpRegRegReg(kOpSub, rs_dest, left_op, right_op); 216 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 217 LIR* it = OpIT(kCondNe, ""); 218 LoadConstant(rs_dest, code == kCondEq ? false_val : true_val); 219 OpEndIT(it); 220 return; 221 } 222 223 OpRegReg(kOpCmp, left_op, right_op); // Same? 224 LIR* it = OpIT(code, "E"); // if-convert the test 225 LoadConstant(rs_dest, true_val); // .eq case - load true 226 LoadConstant(rs_dest, false_val); // .eq case - load true 227 OpEndIT(it); 228} 229 230void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { 231 RegLocation rl_result; 232 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 233 RegLocation rl_dest = mir_graph_->GetDest(mir); 234 // Avoid using float regs here. 235 RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; 236 RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; 237 rl_src = LoadValue(rl_src, src_reg_class); 238 ConditionCode ccode = mir->meta.ccode; 239 if (mir->ssa_rep->num_uses == 1) { 240 // CONST case 241 int true_val = mir->dalvikInsn.vB; 242 int false_val = mir->dalvikInsn.vC; 243 rl_result = EvalLoc(rl_dest, result_reg_class, true); 244 // Change kCondNe to kCondEq for the special cases below. 245 if (ccode == kCondNe) { 246 ccode = kCondEq; 247 std::swap(true_val, false_val); 248 } 249 bool cheap_false_val = InexpensiveConstantInt(false_val); 250 if (cheap_false_val && ccode == kCondEq && (true_val == 0 || true_val == -1)) { 251 OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val); 252 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 253 LIR* it = OpIT(true_val == 0 ? kCondNe : kCondUge, ""); 254 LoadConstant(rl_result.reg, false_val); 255 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 256 } else if (cheap_false_val && ccode == kCondEq && true_val == 1) { 257 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, 1); 258 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 259 LIR* it = OpIT(kCondLs, ""); 260 LoadConstant(rl_result.reg, false_val); 261 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 262 } else if (cheap_false_val && InexpensiveConstantInt(true_val)) { 263 OpRegImm(kOpCmp, rl_src.reg, 0); 264 LIR* it = OpIT(ccode, "E"); 265 LoadConstant(rl_result.reg, true_val); 266 LoadConstant(rl_result.reg, false_val); 267 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 268 } else { 269 // Unlikely case - could be tuned. 270 RegStorage t_reg1 = AllocTypedTemp(false, result_reg_class); 271 RegStorage t_reg2 = AllocTypedTemp(false, result_reg_class); 272 LoadConstant(t_reg1, true_val); 273 LoadConstant(t_reg2, false_val); 274 OpRegImm(kOpCmp, rl_src.reg, 0); 275 LIR* it = OpIT(ccode, "E"); 276 OpRegCopy(rl_result.reg, t_reg1); 277 OpRegCopy(rl_result.reg, t_reg2); 278 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 279 } 280 } else { 281 // MOVE case 282 RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]]; 283 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]; 284 rl_true = LoadValue(rl_true, result_reg_class); 285 rl_false = LoadValue(rl_false, result_reg_class); 286 rl_result = EvalLoc(rl_dest, result_reg_class, true); 287 OpRegImm(kOpCmp, rl_src.reg, 0); 288 LIR* it = nullptr; 289 if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { // Is the "true" case already in place? 290 it = OpIT(NegateComparison(ccode), ""); 291 OpRegCopy(rl_result.reg, rl_false.reg); 292 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { // False case in place? 293 it = OpIT(ccode, ""); 294 OpRegCopy(rl_result.reg, rl_true.reg); 295 } else { // Normal - select between the two. 296 it = OpIT(ccode, "E"); 297 OpRegCopy(rl_result.reg, rl_true.reg); 298 OpRegCopy(rl_result.reg, rl_false.reg); 299 } 300 OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact 301 } 302 StoreValue(rl_dest, rl_result); 303} 304 305void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { 306 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); 307 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); 308 // Normalize such that if either operand is constant, src2 will be constant. 309 ConditionCode ccode = mir->meta.ccode; 310 if (rl_src1.is_const) { 311 std::swap(rl_src1, rl_src2); 312 ccode = FlipComparisonOrder(ccode); 313 } 314 if (rl_src2.is_const) { 315 rl_src2 = UpdateLocWide(rl_src2); 316 // Do special compare/branch against simple const operand if not already in registers. 317 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 318 if ((rl_src2.location != kLocPhysReg) && 319 ((ModifiedImmediate(Low32Bits(val)) >= 0) && (ModifiedImmediate(High32Bits(val)) >= 0))) { 320 GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); 321 return; 322 } 323 } 324 LIR* taken = &block_label_list_[bb->taken]; 325 LIR* not_taken = &block_label_list_[bb->fall_through]; 326 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 327 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 328 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 329 switch (ccode) { 330 case kCondEq: 331 OpCondBranch(kCondNe, not_taken); 332 break; 333 case kCondNe: 334 OpCondBranch(kCondNe, taken); 335 break; 336 case kCondLt: 337 OpCondBranch(kCondLt, taken); 338 OpCondBranch(kCondGt, not_taken); 339 ccode = kCondUlt; 340 break; 341 case kCondLe: 342 OpCondBranch(kCondLt, taken); 343 OpCondBranch(kCondGt, not_taken); 344 ccode = kCondLs; 345 break; 346 case kCondGt: 347 OpCondBranch(kCondGt, taken); 348 OpCondBranch(kCondLt, not_taken); 349 ccode = kCondHi; 350 break; 351 case kCondGe: 352 OpCondBranch(kCondGt, taken); 353 OpCondBranch(kCondLt, not_taken); 354 ccode = kCondUge; 355 break; 356 default: 357 LOG(FATAL) << "Unexpected ccode: " << ccode; 358 } 359 OpRegReg(kOpCmp, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 360 OpCondBranch(ccode, taken); 361} 362 363/* 364 * Generate a register comparison to an immediate and branch. Caller 365 * is responsible for setting branch target field. 366 */ 367LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { 368 LIR* branch; 369 ArmConditionCode arm_cond = ArmConditionEncoding(cond); 370 /* 371 * A common use of OpCmpImmBranch is for null checks, and using the Thumb 16-bit 372 * compare-and-branch if zero is ideal if it will reach. However, because null checks 373 * branch forward to a slow path, they will frequently not reach - and thus have to 374 * be converted to a long form during assembly (which will trigger another assembly 375 * pass). Here we estimate the branch distance for checks, and if large directly 376 * generate the long form in an attempt to avoid an extra assembly pass. 377 * TODO: consider interspersing slowpaths in code following unconditional branches. 378 */ 379 bool skip = ((target != NULL) && (target->opcode == kPseudoThrowTarget)); 380 skip &= ((cu_->code_item->insns_size_in_code_units_ - current_dalvik_offset_) > 64); 381 if (!skip && reg.Low8() && (check_value == 0) && 382 ((arm_cond == kArmCondEq) || (arm_cond == kArmCondNe))) { 383 branch = NewLIR2((arm_cond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz, 384 reg.GetReg(), 0); 385 } else { 386 OpRegImm(kOpCmp, reg, check_value); 387 branch = NewLIR2(kThumbBCond, 0, arm_cond); 388 } 389 branch->target = target; 390 return branch; 391} 392 393LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 394 LIR* res; 395 int opcode; 396 // If src or dest is a pair, we'll be using low reg. 397 if (r_dest.IsPair()) { 398 r_dest = r_dest.GetLow(); 399 } 400 if (r_src.IsPair()) { 401 r_src = r_src.GetLow(); 402 } 403 if (r_dest.IsFloat() || r_src.IsFloat()) 404 return OpFpRegCopy(r_dest, r_src); 405 if (r_dest.Low8() && r_src.Low8()) 406 opcode = kThumbMovRR; 407 else if (!r_dest.Low8() && !r_src.Low8()) 408 opcode = kThumbMovRR_H2H; 409 else if (r_dest.Low8()) 410 opcode = kThumbMovRR_H2L; 411 else 412 opcode = kThumbMovRR_L2H; 413 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 414 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 415 res->flags.is_nop = true; 416 } 417 return res; 418} 419 420void ArmMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { 421 if (r_dest != r_src) { 422 LIR* res = OpRegCopyNoInsert(r_dest, r_src); 423 AppendLIR(res); 424 } 425} 426 427void ArmMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { 428 if (r_dest != r_src) { 429 bool dest_fp = r_dest.IsFloat(); 430 bool src_fp = r_src.IsFloat(); 431 DCHECK(r_dest.Is64Bit()); 432 DCHECK(r_src.Is64Bit()); 433 if (dest_fp) { 434 if (src_fp) { 435 OpRegCopy(r_dest, r_src); 436 } else { 437 NewLIR3(kThumb2Fmdrr, r_dest.GetReg(), r_src.GetLowReg(), r_src.GetHighReg()); 438 } 439 } else { 440 if (src_fp) { 441 NewLIR3(kThumb2Fmrrd, r_dest.GetLowReg(), r_dest.GetHighReg(), r_src.GetReg()); 442 } else { 443 // Handle overlap 444 if (r_src.GetHighReg() == r_dest.GetLowReg()) { 445 DCHECK_NE(r_src.GetLowReg(), r_dest.GetHighReg()); 446 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 447 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 448 } else { 449 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 450 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 451 } 452 } 453 } 454 } 455} 456 457// Table of magic divisors 458struct MagicTable { 459 uint32_t magic; 460 uint32_t shift; 461 DividePattern pattern; 462}; 463 464static const MagicTable magic_table[] = { 465 {0, 0, DivideNone}, // 0 466 {0, 0, DivideNone}, // 1 467 {0, 0, DivideNone}, // 2 468 {0x55555556, 0, Divide3}, // 3 469 {0, 0, DivideNone}, // 4 470 {0x66666667, 1, Divide5}, // 5 471 {0x2AAAAAAB, 0, Divide3}, // 6 472 {0x92492493, 2, Divide7}, // 7 473 {0, 0, DivideNone}, // 8 474 {0x38E38E39, 1, Divide5}, // 9 475 {0x66666667, 2, Divide5}, // 10 476 {0x2E8BA2E9, 1, Divide5}, // 11 477 {0x2AAAAAAB, 1, Divide5}, // 12 478 {0x4EC4EC4F, 2, Divide5}, // 13 479 {0x92492493, 3, Divide7}, // 14 480 {0x88888889, 3, Divide7}, // 15 481}; 482 483// Integer division by constant via reciprocal multiply (Hacker's Delight, 10-4) 484bool ArmMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 485 RegLocation rl_src, RegLocation rl_dest, int lit) { 486 if ((lit < 0) || (lit >= static_cast<int>(sizeof(magic_table)/sizeof(magic_table[0])))) { 487 return false; 488 } 489 DividePattern pattern = magic_table[lit].pattern; 490 if (pattern == DivideNone) { 491 return false; 492 } 493 494 RegStorage r_magic = AllocTemp(); 495 LoadConstant(r_magic, magic_table[lit].magic); 496 rl_src = LoadValue(rl_src, kCoreReg); 497 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 498 RegStorage r_hi = AllocTemp(); 499 RegStorage r_lo = AllocTemp(); 500 501 // rl_dest and rl_src might overlap. 502 // Reuse r_hi to save the div result for reminder case. 503 RegStorage r_div_result = is_div ? rl_result.reg : r_hi; 504 505 NewLIR4(kThumb2Smull, r_lo.GetReg(), r_hi.GetReg(), r_magic.GetReg(), rl_src.reg.GetReg()); 506 switch (pattern) { 507 case Divide3: 508 OpRegRegRegShift(kOpSub, r_div_result, r_hi, rl_src.reg, EncodeShift(kArmAsr, 31)); 509 break; 510 case Divide5: 511 OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31); 512 OpRegRegRegShift(kOpRsub, r_div_result, r_lo, r_hi, 513 EncodeShift(kArmAsr, magic_table[lit].shift)); 514 break; 515 case Divide7: 516 OpRegReg(kOpAdd, r_hi, rl_src.reg); 517 OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31); 518 OpRegRegRegShift(kOpRsub, r_div_result, r_lo, r_hi, 519 EncodeShift(kArmAsr, magic_table[lit].shift)); 520 break; 521 default: 522 LOG(FATAL) << "Unexpected pattern: " << pattern; 523 } 524 525 if (!is_div) { 526 // div_result = src / lit 527 // tmp1 = div_result * lit 528 // dest = src - tmp1 529 RegStorage tmp1 = r_lo; 530 EasyMultiplyOp ops[2]; 531 532 bool canEasyMultiply = GetEasyMultiplyTwoOps(lit, ops); 533 DCHECK_NE(canEasyMultiply, false); 534 535 GenEasyMultiplyTwoOps(tmp1, r_div_result, ops); 536 OpRegRegReg(kOpSub, rl_result.reg, rl_src.reg, tmp1); 537 } 538 539 StoreValue(rl_dest, rl_result); 540 return true; 541} 542 543// Try to convert *lit to 1 RegRegRegShift/RegRegShift form. 544bool ArmMir2Lir::GetEasyMultiplyOp(int lit, ArmMir2Lir::EasyMultiplyOp* op) { 545 if (IsPowerOfTwo(lit)) { 546 op->op = kOpLsl; 547 op->shift = LowestSetBit(lit); 548 return true; 549 } 550 551 if (IsPowerOfTwo(lit - 1)) { 552 op->op = kOpAdd; 553 op->shift = LowestSetBit(lit - 1); 554 return true; 555 } 556 557 if (IsPowerOfTwo(lit + 1)) { 558 op->op = kOpRsub; 559 op->shift = LowestSetBit(lit + 1); 560 return true; 561 } 562 563 op->op = kOpInvalid; 564 op->shift = 0; 565 return false; 566} 567 568// Try to convert *lit to 1~2 RegRegRegShift/RegRegShift forms. 569bool ArmMir2Lir::GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops) { 570 GetEasyMultiplyOp(lit, &ops[0]); 571 if (GetEasyMultiplyOp(lit, &ops[0])) { 572 ops[1].op = kOpInvalid; 573 ops[1].shift = 0; 574 return true; 575 } 576 577 int lit1 = lit; 578 uint32_t shift = LowestSetBit(lit1); 579 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { 580 ops[1].op = kOpLsl; 581 ops[1].shift = shift; 582 return true; 583 } 584 585 lit1 = lit - 1; 586 shift = LowestSetBit(lit1); 587 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { 588 ops[1].op = kOpAdd; 589 ops[1].shift = shift; 590 return true; 591 } 592 593 lit1 = lit + 1; 594 shift = LowestSetBit(lit1); 595 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { 596 ops[1].op = kOpRsub; 597 ops[1].shift = shift; 598 return true; 599 } 600 601 return false; 602} 603 604// Generate instructions to do multiply. 605// Additional temporary register is required, 606// if it need to generate 2 instructions and src/dest overlap. 607void ArmMir2Lir::GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops) { 608 // tmp1 = ( src << shift1) + [ src | -src | 0 ] 609 // dest = (tmp1 << shift2) + [ src | -src | 0 ] 610 611 RegStorage r_tmp1; 612 if (ops[1].op == kOpInvalid) { 613 r_tmp1 = r_dest; 614 } else if (r_dest.GetReg() != r_src.GetReg()) { 615 r_tmp1 = r_dest; 616 } else { 617 r_tmp1 = AllocTemp(); 618 } 619 620 switch (ops[0].op) { 621 case kOpLsl: 622 OpRegRegImm(kOpLsl, r_tmp1, r_src, ops[0].shift); 623 break; 624 case kOpAdd: 625 OpRegRegRegShift(kOpAdd, r_tmp1, r_src, r_src, EncodeShift(kArmLsl, ops[0].shift)); 626 break; 627 case kOpRsub: 628 OpRegRegRegShift(kOpRsub, r_tmp1, r_src, r_src, EncodeShift(kArmLsl, ops[0].shift)); 629 break; 630 default: 631 DCHECK_EQ(ops[0].op, kOpInvalid); 632 break; 633 } 634 635 switch (ops[1].op) { 636 case kOpInvalid: 637 return; 638 case kOpLsl: 639 OpRegRegImm(kOpLsl, r_dest, r_tmp1, ops[1].shift); 640 break; 641 case kOpAdd: 642 OpRegRegRegShift(kOpAdd, r_dest, r_src, r_tmp1, EncodeShift(kArmLsl, ops[1].shift)); 643 break; 644 case kOpRsub: 645 OpRegRegRegShift(kOpRsub, r_dest, r_src, r_tmp1, EncodeShift(kArmLsl, ops[1].shift)); 646 break; 647 default: 648 LOG(FATAL) << "Unexpected opcode passed to GenEasyMultiplyTwoOps"; 649 break; 650 } 651} 652 653bool ArmMir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 654 EasyMultiplyOp ops[2]; 655 656 if (!GetEasyMultiplyTwoOps(lit, ops)) { 657 return false; 658 } 659 660 rl_src = LoadValue(rl_src, kCoreReg); 661 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 662 663 GenEasyMultiplyTwoOps(rl_result.reg, rl_src.reg, ops); 664 StoreValue(rl_dest, rl_result); 665 return true; 666} 667 668RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 669 RegLocation rl_src2, bool is_div, bool check_zero) { 670 LOG(FATAL) << "Unexpected use of GenDivRem for Arm"; 671 return rl_dest; 672} 673 674RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) { 675 LOG(FATAL) << "Unexpected use of GenDivRemLit for Arm"; 676 return rl_dest; 677} 678 679RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { 680 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 681 682 // Put the literal in a temp. 683 RegStorage lit_temp = AllocTemp(); 684 LoadConstant(lit_temp, lit); 685 // Use the generic case for div/rem with arg2 in a register. 686 // TODO: The literal temp can be freed earlier during a modulus to reduce reg pressure. 687 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); 688 FreeTemp(lit_temp); 689 690 return rl_result; 691} 692 693RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, 694 bool is_div) { 695 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 696 if (is_div) { 697 // Simple case, use sdiv instruction. 698 OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2); 699 } else { 700 // Remainder case, use the following code: 701 // temp = reg1 / reg2 - integer division 702 // temp = temp * reg2 703 // dest = reg1 - temp 704 705 RegStorage temp = AllocTemp(); 706 OpRegRegReg(kOpDiv, temp, reg1, reg2); 707 OpRegReg(kOpMul, temp, reg2); 708 OpRegRegReg(kOpSub, rl_result.reg, reg1, temp); 709 FreeTemp(temp); 710 } 711 712 return rl_result; 713} 714 715bool ArmMir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) { 716 DCHECK_EQ(cu_->instruction_set, kThumb2); 717 if (is_long) { 718 return false; 719 } 720 RegLocation rl_src1 = info->args[0]; 721 RegLocation rl_src2 = info->args[1]; 722 rl_src1 = LoadValue(rl_src1, kCoreReg); 723 rl_src2 = LoadValue(rl_src2, kCoreReg); 724 RegLocation rl_dest = InlineTarget(info); 725 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 726 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 727 LIR* it = OpIT((is_min) ? kCondGt : kCondLt, "E"); 728 OpRegReg(kOpMov, rl_result.reg, rl_src2.reg); 729 OpRegReg(kOpMov, rl_result.reg, rl_src1.reg); 730 OpEndIT(it); 731 StoreValue(rl_dest, rl_result); 732 return true; 733} 734 735bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { 736 RegLocation rl_src_address = info->args[0]; // long address 737 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 738 RegLocation rl_dest = InlineTarget(info); 739 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 740 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 741 if (size == k64) { 742 // Fake unaligned LDRD by two unaligned LDR instructions on ARMv7 with SCTLR.A set to 0. 743 if (rl_address.reg.GetReg() != rl_result.reg.GetLowReg()) { 744 Load32Disp(rl_address.reg, 0, rl_result.reg.GetLow()); 745 Load32Disp(rl_address.reg, 4, rl_result.reg.GetHigh()); 746 } else { 747 Load32Disp(rl_address.reg, 4, rl_result.reg.GetHigh()); 748 Load32Disp(rl_address.reg, 0, rl_result.reg.GetLow()); 749 } 750 StoreValueWide(rl_dest, rl_result); 751 } else { 752 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 753 // Unaligned load with LDR and LDRSH is allowed on ARMv7 with SCTLR.A set to 0. 754 LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile); 755 StoreValue(rl_dest, rl_result); 756 } 757 return true; 758} 759 760bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { 761 RegLocation rl_src_address = info->args[0]; // long address 762 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 763 RegLocation rl_src_value = info->args[2]; // [size] value 764 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 765 if (size == k64) { 766 // Fake unaligned STRD by two unaligned STR instructions on ARMv7 with SCTLR.A set to 0. 767 RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); 768 StoreBaseDisp(rl_address.reg, 0, rl_value.reg.GetLow(), k32, kNotVolatile); 769 StoreBaseDisp(rl_address.reg, 4, rl_value.reg.GetHigh(), k32, kNotVolatile); 770 } else { 771 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 772 // Unaligned store with STR and STRSH is allowed on ARMv7 with SCTLR.A set to 0. 773 RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); 774 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile); 775 } 776 return true; 777} 778 779void ArmMir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { 780 LOG(FATAL) << "Unexpected use of OpLea for Arm"; 781} 782 783void ArmMir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { 784 LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm"; 785} 786 787void ArmMir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { 788 UNIMPLEMENTED(FATAL) << "Should not be called."; 789} 790 791// Generate a CAS with memory_order_seq_cst semantics. 792bool ArmMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { 793 DCHECK_EQ(cu_->instruction_set, kThumb2); 794 // Unused - RegLocation rl_src_unsafe = info->args[0]; 795 RegLocation rl_src_obj = info->args[1]; // Object - known non-null 796 RegLocation rl_src_offset = info->args[2]; // long low 797 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 798 RegLocation rl_src_expected = info->args[4]; // int, long or Object 799 // If is_long, high half is in info->args[5] 800 RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object 801 // If is_long, high half is in info->args[7] 802 RegLocation rl_dest = InlineTarget(info); // boolean place for result 803 804 // We have only 5 temporary registers available and actually only 4 if the InlineTarget 805 // above locked one of the temps. For a straightforward CAS64 we need 7 registers: 806 // r_ptr (1), new_value (2), expected(2) and ldrexd result (2). If neither expected nor 807 // new_value is in a non-temp core register we shall reload them in the ldrex/strex loop 808 // into the same temps, reducing the number of required temps down to 5. We shall work 809 // around the potentially locked temp by using LR for r_ptr, unconditionally. 810 // TODO: Pass information about the need for more temps to the stack frame generation 811 // code so that we can rely on being able to allocate enough temps. 812 DCHECK(!GetRegInfo(rs_rARM_LR)->IsTemp()); 813 MarkTemp(rs_rARM_LR); 814 FreeTemp(rs_rARM_LR); 815 LockTemp(rs_rARM_LR); 816 bool load_early = true; 817 if (is_long) { 818 RegStorage expected_reg = rl_src_expected.reg.IsPair() ? rl_src_expected.reg.GetLow() : 819 rl_src_expected.reg; 820 RegStorage new_val_reg = rl_src_new_value.reg.IsPair() ? rl_src_new_value.reg.GetLow() : 821 rl_src_new_value.reg; 822 bool expected_is_core_reg = rl_src_expected.location == kLocPhysReg && !expected_reg.IsFloat(); 823 bool new_value_is_core_reg = rl_src_new_value.location == kLocPhysReg && !new_val_reg.IsFloat(); 824 bool expected_is_good_reg = expected_is_core_reg && !IsTemp(expected_reg); 825 bool new_value_is_good_reg = new_value_is_core_reg && !IsTemp(new_val_reg); 826 827 if (!expected_is_good_reg && !new_value_is_good_reg) { 828 // None of expected/new_value is non-temp reg, need to load both late 829 load_early = false; 830 // Make sure they are not in the temp regs and the load will not be skipped. 831 if (expected_is_core_reg) { 832 FlushRegWide(rl_src_expected.reg); 833 ClobberSReg(rl_src_expected.s_reg_low); 834 ClobberSReg(GetSRegHi(rl_src_expected.s_reg_low)); 835 rl_src_expected.location = kLocDalvikFrame; 836 } 837 if (new_value_is_core_reg) { 838 FlushRegWide(rl_src_new_value.reg); 839 ClobberSReg(rl_src_new_value.s_reg_low); 840 ClobberSReg(GetSRegHi(rl_src_new_value.s_reg_low)); 841 rl_src_new_value.location = kLocDalvikFrame; 842 } 843 } 844 } 845 846 // Prevent reordering with prior memory operations. 847 GenMemBarrier(kAnyStore); 848 849 RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); 850 RegLocation rl_new_value; 851 if (!is_long) { 852 rl_new_value = LoadValue(rl_src_new_value); 853 } else if (load_early) { 854 rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg); 855 } 856 857 if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { 858 // Mark card for object assuming new value is stored. 859 MarkGCCard(rl_new_value.reg, rl_object.reg); 860 } 861 862 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 863 864 RegStorage r_ptr = rs_rARM_LR; 865 OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg); 866 867 // Free now unneeded rl_object and rl_offset to give more temps. 868 ClobberSReg(rl_object.s_reg_low); 869 FreeTemp(rl_object.reg); 870 ClobberSReg(rl_offset.s_reg_low); 871 FreeTemp(rl_offset.reg); 872 873 RegLocation rl_expected; 874 if (!is_long) { 875 rl_expected = LoadValue(rl_src_expected); 876 } else if (load_early) { 877 rl_expected = LoadValueWide(rl_src_expected, kCoreReg); 878 } else { 879 // NOTE: partially defined rl_expected & rl_new_value - but we just want the regs. 880 RegStorage low_reg = AllocTemp(); 881 RegStorage high_reg = AllocTemp(); 882 rl_new_value.reg = RegStorage::MakeRegPair(low_reg, high_reg); 883 rl_expected = rl_new_value; 884 } 885 886 // do { 887 // tmp = [r_ptr] - expected; 888 // } while (tmp == 0 && failure([r_ptr] <- r_new_value)); 889 // result = tmp != 0; 890 891 RegStorage r_tmp = AllocTemp(); 892 LIR* target = NewLIR0(kPseudoTargetLabel); 893 894 LIR* it = nullptr; 895 if (is_long) { 896 RegStorage r_tmp_high = AllocTemp(); 897 if (!load_early) { 898 LoadValueDirectWide(rl_src_expected, rl_expected.reg); 899 } 900 NewLIR3(kThumb2Ldrexd, r_tmp.GetReg(), r_tmp_high.GetReg(), r_ptr.GetReg()); 901 OpRegReg(kOpSub, r_tmp, rl_expected.reg.GetLow()); 902 OpRegReg(kOpSub, r_tmp_high, rl_expected.reg.GetHigh()); 903 if (!load_early) { 904 LoadValueDirectWide(rl_src_new_value, rl_new_value.reg); 905 } 906 // Make sure we use ORR that sets the ccode 907 if (r_tmp.Low8() && r_tmp_high.Low8()) { 908 NewLIR2(kThumbOrr, r_tmp.GetReg(), r_tmp_high.GetReg()); 909 } else { 910 NewLIR4(kThumb2OrrRRRs, r_tmp.GetReg(), r_tmp.GetReg(), r_tmp_high.GetReg(), 0); 911 } 912 FreeTemp(r_tmp_high); // Now unneeded 913 914 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 915 it = OpIT(kCondEq, "T"); 916 NewLIR4(kThumb2Strexd /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetLowReg(), rl_new_value.reg.GetHighReg(), r_ptr.GetReg()); 917 918 } else { 919 NewLIR3(kThumb2Ldrex, r_tmp.GetReg(), r_ptr.GetReg(), 0); 920 OpRegReg(kOpSub, r_tmp, rl_expected.reg); 921 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 922 it = OpIT(kCondEq, "T"); 923 NewLIR4(kThumb2Strex /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetReg(), r_ptr.GetReg(), 0); 924 } 925 926 // Still one conditional left from OpIT(kCondEq, "T") from either branch 927 OpRegImm(kOpCmp /* eq */, r_tmp, 1); 928 OpEndIT(it); 929 930 OpCondBranch(kCondEq, target); 931 932 if (!load_early) { 933 FreeTemp(rl_expected.reg); // Now unneeded. 934 } 935 936 // Prevent reordering with subsequent memory operations. 937 GenMemBarrier(kLoadAny); 938 939 // result := (tmp1 != 0) ? 0 : 1; 940 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 941 OpRegRegImm(kOpRsub, rl_result.reg, r_tmp, 1); 942 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 943 it = OpIT(kCondUlt, ""); 944 LoadConstant(rl_result.reg, 0); /* cc */ 945 FreeTemp(r_tmp); // Now unneeded. 946 OpEndIT(it); // Barrier to terminate OpIT. 947 948 StoreValue(rl_dest, rl_result); 949 950 // Now, restore lr to its non-temp status. 951 Clobber(rs_rARM_LR); 952 UnmarkTemp(rs_rARM_LR); 953 return true; 954} 955 956LIR* ArmMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { 957 return RawLIR(current_dalvik_offset_, kThumb2LdrPcRel12, reg.GetReg(), 0, 0, 0, 0, target); 958} 959 960LIR* ArmMir2Lir::OpVldm(RegStorage r_base, int count) { 961 return NewLIR3(kThumb2Vldms, r_base.GetReg(), rs_fr0.GetReg(), count); 962} 963 964LIR* ArmMir2Lir::OpVstm(RegStorage r_base, int count) { 965 return NewLIR3(kThumb2Vstms, r_base.GetReg(), rs_fr0.GetReg(), count); 966} 967 968void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 969 RegLocation rl_result, int lit, 970 int first_bit, int second_bit) { 971 OpRegRegRegShift(kOpAdd, rl_result.reg, rl_src.reg, rl_src.reg, 972 EncodeShift(kArmLsl, second_bit - first_bit)); 973 if (first_bit != 0) { 974 OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); 975 } 976} 977 978void ArmMir2Lir::GenDivZeroCheckWide(RegStorage reg) { 979 DCHECK(reg.IsPair()); // TODO: support k64BitSolo. 980 RegStorage t_reg = AllocTemp(); 981 NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), reg.GetLowReg(), reg.GetHighReg(), 0); 982 FreeTemp(t_reg); 983 GenDivZeroCheck(kCondEq); 984} 985 986// Test suspend flag, return target of taken suspend branch 987LIR* ArmMir2Lir::OpTestSuspend(LIR* target) { 988#ifdef ARM_R4_SUSPEND_FLAG 989 NewLIR2(kThumbSubRI8, rs_rARM_SUSPEND.GetReg(), 1); 990 return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target); 991#else 992 RegStorage t_reg = AllocTemp(); 993 LoadBaseDisp(rs_rARM_SELF, Thread::ThreadFlagsOffset<4>().Int32Value(), 994 t_reg, kUnsignedHalf); 995 LIR* cmp_branch = OpCmpImmBranch((target == NULL) ? kCondNe : kCondEq, t_reg, 996 0, target); 997 FreeTemp(t_reg); 998 return cmp_branch; 999#endif 1000} 1001 1002// Decrement register and branch on condition 1003LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { 1004 // Combine sub & test using sub setflags encoding here 1005 OpRegRegImm(kOpSub, reg, reg, 1); // For value == 1, this should set flags. 1006 DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); 1007 return OpCondBranch(c_code, target); 1008} 1009 1010bool ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 1011#if ANDROID_SMP != 0 1012 // Start off with using the last LIR as the barrier. If it is not enough, then we will generate one. 1013 LIR* barrier = last_lir_insn_; 1014 1015 int dmb_flavor; 1016 // TODO: revisit Arm barrier kinds 1017 switch (barrier_kind) { 1018 case kAnyStore: dmb_flavor = kISH; break; 1019 case kLoadAny: dmb_flavor = kISH; break; 1020 case kStoreStore: dmb_flavor = kISHST; break; 1021 case kAnyAny: dmb_flavor = kISH; break; 1022 default: 1023 LOG(FATAL) << "Unexpected MemBarrierKind: " << barrier_kind; 1024 dmb_flavor = kSY; // quiet gcc. 1025 break; 1026 } 1027 1028 bool ret = false; 1029 1030 // If the same barrier already exists, don't generate another. 1031 if (barrier == nullptr 1032 || (barrier != nullptr && (barrier->opcode != kThumb2Dmb || barrier->operands[0] != dmb_flavor))) { 1033 barrier = NewLIR1(kThumb2Dmb, dmb_flavor); 1034 ret = true; 1035 } 1036 1037 // At this point we must have a memory barrier. Mark it as a scheduling barrier as well. 1038 DCHECK(!barrier->flags.use_def_invalid); 1039 barrier->u.m.def_mask = &kEncodeAll; 1040 return ret; 1041#else 1042 return false; 1043#endif 1044} 1045 1046void ArmMir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { 1047 LOG(FATAL) << "Unexpected use GenNotLong()"; 1048} 1049 1050void ArmMir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1051 RegLocation rl_src2, bool is_div) { 1052 LOG(FATAL) << "Unexpected use GenDivRemLong()"; 1053} 1054 1055void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { 1056 rl_src = LoadValueWide(rl_src, kCoreReg); 1057 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1058 RegStorage z_reg = AllocTemp(); 1059 LoadConstantNoClobber(z_reg, 0); 1060 // Check for destructive overlap 1061 if (rl_result.reg.GetLowReg() == rl_src.reg.GetHighReg()) { 1062 RegStorage t_reg = AllocTemp(); 1063 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); 1064 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, t_reg); 1065 FreeTemp(t_reg); 1066 } else { 1067 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); 1068 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, rl_src.reg.GetHigh()); 1069 } 1070 FreeTemp(z_reg); 1071 StoreValueWide(rl_dest, rl_result); 1072} 1073 1074void ArmMir2Lir::GenMulLong(Instruction::Code opcode, RegLocation rl_dest, 1075 RegLocation rl_src1, RegLocation rl_src2) { 1076 /* 1077 * tmp1 = src1.hi * src2.lo; // src1.hi is no longer needed 1078 * dest = src1.lo * src2.lo; 1079 * tmp1 += src1.lo * src2.hi; 1080 * dest.hi += tmp1; 1081 * 1082 * To pull off inline multiply, we have a worst-case requirement of 7 temporary 1083 * registers. Normally for Arm, we get 5. We can get to 6 by including 1084 * lr in the temp set. The only problematic case is all operands and result are 1085 * distinct, and none have been promoted. In that case, we can succeed by aggressively 1086 * freeing operand temp registers after they are no longer needed. All other cases 1087 * can proceed normally. We'll just punt on the case of the result having a misaligned 1088 * overlap with either operand and send that case to a runtime handler. 1089 */ 1090 RegLocation rl_result; 1091 if (BadOverlap(rl_src1, rl_dest) || (BadOverlap(rl_src2, rl_dest))) { 1092 ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pLmul); 1093 FlushAllRegs(); 1094 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 1095 rl_result = GetReturnWide(kCoreReg); 1096 StoreValueWide(rl_dest, rl_result); 1097 return; 1098 } 1099 1100 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1101 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1102 1103 int reg_status = 0; 1104 RegStorage res_lo; 1105 RegStorage res_hi; 1106 bool dest_promoted = rl_dest.location == kLocPhysReg && rl_dest.reg.Valid() && 1107 !IsTemp(rl_dest.reg.GetLow()) && !IsTemp(rl_dest.reg.GetHigh()); 1108 bool src1_promoted = !IsTemp(rl_src1.reg.GetLow()) && !IsTemp(rl_src1.reg.GetHigh()); 1109 bool src2_promoted = !IsTemp(rl_src2.reg.GetLow()) && !IsTemp(rl_src2.reg.GetHigh()); 1110 // Check if rl_dest is *not* either operand and we have enough temp registers. 1111 if ((rl_dest.s_reg_low != rl_src1.s_reg_low && rl_dest.s_reg_low != rl_src2.s_reg_low) && 1112 (dest_promoted || src1_promoted || src2_promoted)) { 1113 // In this case, we do not need to manually allocate temp registers for result. 1114 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1115 res_lo = rl_result.reg.GetLow(); 1116 res_hi = rl_result.reg.GetHigh(); 1117 } else { 1118 res_lo = AllocTemp(); 1119 if ((rl_src1.s_reg_low == rl_src2.s_reg_low) || src1_promoted || src2_promoted) { 1120 // In this case, we have enough temp registers to be allocated for result. 1121 res_hi = AllocTemp(); 1122 reg_status = 1; 1123 } else { 1124 // In this case, all temps are now allocated. 1125 // res_hi will be allocated after we can free src1_hi. 1126 reg_status = 2; 1127 } 1128 } 1129 1130 // Temporarily add LR to the temp pool, and assign it to tmp1 1131 MarkTemp(rs_rARM_LR); 1132 FreeTemp(rs_rARM_LR); 1133 RegStorage tmp1 = rs_rARM_LR; 1134 LockTemp(rs_rARM_LR); 1135 1136 if (rl_src1.reg == rl_src2.reg) { 1137 DCHECK(res_hi.Valid()); 1138 DCHECK(res_lo.Valid()); 1139 NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src1.reg.GetHighReg()); 1140 NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src1.reg.GetLowReg(), 1141 rl_src1.reg.GetLowReg()); 1142 OpRegRegRegShift(kOpAdd, res_hi, res_hi, tmp1, EncodeShift(kArmLsl, 1)); 1143 } else { 1144 NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetHighReg()); 1145 if (reg_status == 2) { 1146 DCHECK(!res_hi.Valid()); 1147 DCHECK_NE(rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); 1148 DCHECK_NE(rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1149 // Will force free src1_hi, so must clobber. 1150 Clobber(rl_src1.reg); 1151 FreeTemp(rl_src1.reg.GetHigh()); 1152 res_hi = AllocTemp(); 1153 } 1154 DCHECK(res_hi.Valid()); 1155 DCHECK(res_lo.Valid()); 1156 NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src2.reg.GetLowReg(), 1157 rl_src1.reg.GetLowReg()); 1158 NewLIR4(kThumb2Mla, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetHighReg(), 1159 tmp1.GetReg()); 1160 NewLIR4(kThumb2AddRRR, res_hi.GetReg(), tmp1.GetReg(), res_hi.GetReg(), 0); 1161 if (reg_status == 2) { 1162 FreeTemp(rl_src1.reg.GetLow()); 1163 } 1164 } 1165 1166 // Now, restore lr to its non-temp status. 1167 FreeTemp(tmp1); 1168 Clobber(rs_rARM_LR); 1169 UnmarkTemp(rs_rARM_LR); 1170 1171 if (reg_status != 0) { 1172 // We had manually allocated registers for rl_result. 1173 // Now construct a RegLocation. 1174 rl_result = GetReturnWide(kCoreReg); // Just using as a template. 1175 rl_result.reg = RegStorage::MakeRegPair(res_lo, res_hi); 1176 } 1177 1178 StoreValueWide(rl_dest, rl_result); 1179} 1180 1181void ArmMir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1182 RegLocation rl_src2) { 1183 LOG(FATAL) << "Unexpected use of GenAddLong for Arm"; 1184} 1185 1186void ArmMir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1187 RegLocation rl_src2) { 1188 LOG(FATAL) << "Unexpected use of GenSubLong for Arm"; 1189} 1190 1191void ArmMir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1192 RegLocation rl_src2) { 1193 LOG(FATAL) << "Unexpected use of GenAndLong for Arm"; 1194} 1195 1196void ArmMir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1197 RegLocation rl_src2) { 1198 LOG(FATAL) << "Unexpected use of GenOrLong for Arm"; 1199} 1200 1201void ArmMir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 1202 RegLocation rl_src2) { 1203 LOG(FATAL) << "Unexpected use of genXoLong for Arm"; 1204} 1205 1206/* 1207 * Generate array load 1208 */ 1209void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1210 RegLocation rl_index, RegLocation rl_dest, int scale) { 1211 RegisterClass reg_class = RegClassBySize(size); 1212 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1213 int data_offset; 1214 RegLocation rl_result; 1215 bool constant_index = rl_index.is_const; 1216 rl_array = LoadValue(rl_array, kRefReg); 1217 if (!constant_index) { 1218 rl_index = LoadValue(rl_index, kCoreReg); 1219 } 1220 1221 if (rl_dest.wide) { 1222 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1223 } else { 1224 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1225 } 1226 1227 // If index is constant, just fold it into the data offset 1228 if (constant_index) { 1229 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1230 } 1231 1232 /* null object? */ 1233 GenNullCheck(rl_array.reg, opt_flags); 1234 1235 bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); 1236 RegStorage reg_len; 1237 if (needs_range_check) { 1238 reg_len = AllocTemp(); 1239 /* Get len */ 1240 Load32Disp(rl_array.reg, len_offset, reg_len); 1241 MarkPossibleNullPointerException(opt_flags); 1242 } else { 1243 ForceImplicitNullCheck(rl_array.reg, opt_flags); 1244 } 1245 if (rl_dest.wide || rl_dest.fp || constant_index) { 1246 RegStorage reg_ptr; 1247 if (constant_index) { 1248 reg_ptr = rl_array.reg; // NOTE: must not alter reg_ptr in constant case. 1249 } else { 1250 // No special indexed operation, lea + load w/ displacement 1251 reg_ptr = AllocTempRef(); 1252 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); 1253 FreeTemp(rl_index.reg); 1254 } 1255 rl_result = EvalLoc(rl_dest, reg_class, true); 1256 1257 if (needs_range_check) { 1258 if (constant_index) { 1259 GenArrayBoundsCheck(mir_graph_->ConstantValue(rl_index), reg_len); 1260 } else { 1261 GenArrayBoundsCheck(rl_index.reg, reg_len); 1262 } 1263 FreeTemp(reg_len); 1264 } 1265 LoadBaseDisp(reg_ptr, data_offset, rl_result.reg, size, kNotVolatile); 1266 MarkPossibleNullPointerException(opt_flags); 1267 if (!constant_index) { 1268 FreeTemp(reg_ptr); 1269 } 1270 if (rl_dest.wide) { 1271 StoreValueWide(rl_dest, rl_result); 1272 } else { 1273 StoreValue(rl_dest, rl_result); 1274 } 1275 } else { 1276 // Offset base, then use indexed load 1277 RegStorage reg_ptr = AllocTempRef(); 1278 OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); 1279 FreeTemp(rl_array.reg); 1280 rl_result = EvalLoc(rl_dest, reg_class, true); 1281 1282 if (needs_range_check) { 1283 GenArrayBoundsCheck(rl_index.reg, reg_len); 1284 FreeTemp(reg_len); 1285 } 1286 LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size); 1287 MarkPossibleNullPointerException(opt_flags); 1288 FreeTemp(reg_ptr); 1289 StoreValue(rl_dest, rl_result); 1290 } 1291} 1292 1293/* 1294 * Generate array store 1295 * 1296 */ 1297void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1298 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 1299 RegisterClass reg_class = RegClassBySize(size); 1300 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1301 bool constant_index = rl_index.is_const; 1302 1303 int data_offset; 1304 if (size == k64 || size == kDouble) { 1305 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1306 } else { 1307 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1308 } 1309 1310 // If index is constant, just fold it into the data offset. 1311 if (constant_index) { 1312 data_offset += mir_graph_->ConstantValue(rl_index) << scale; 1313 } 1314 1315 rl_array = LoadValue(rl_array, kRefReg); 1316 if (!constant_index) { 1317 rl_index = LoadValue(rl_index, kCoreReg); 1318 } 1319 1320 RegStorage reg_ptr; 1321 bool allocated_reg_ptr_temp = false; 1322 if (constant_index) { 1323 reg_ptr = rl_array.reg; 1324 } else if (IsTemp(rl_array.reg) && !card_mark) { 1325 Clobber(rl_array.reg); 1326 reg_ptr = rl_array.reg; 1327 } else { 1328 allocated_reg_ptr_temp = true; 1329 reg_ptr = AllocTempRef(); 1330 } 1331 1332 /* null object? */ 1333 GenNullCheck(rl_array.reg, opt_flags); 1334 1335 bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); 1336 RegStorage reg_len; 1337 if (needs_range_check) { 1338 reg_len = AllocTemp(); 1339 // NOTE: max live temps(4) here. 1340 /* Get len */ 1341 Load32Disp(rl_array.reg, len_offset, reg_len); 1342 MarkPossibleNullPointerException(opt_flags); 1343 } else { 1344 ForceImplicitNullCheck(rl_array.reg, opt_flags); 1345 } 1346 /* at this point, reg_ptr points to array, 2 live temps */ 1347 if (rl_src.wide || rl_src.fp || constant_index) { 1348 if (rl_src.wide) { 1349 rl_src = LoadValueWide(rl_src, reg_class); 1350 } else { 1351 rl_src = LoadValue(rl_src, reg_class); 1352 } 1353 if (!constant_index) { 1354 OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); 1355 } 1356 if (needs_range_check) { 1357 if (constant_index) { 1358 GenArrayBoundsCheck(mir_graph_->ConstantValue(rl_index), reg_len); 1359 } else { 1360 GenArrayBoundsCheck(rl_index.reg, reg_len); 1361 } 1362 FreeTemp(reg_len); 1363 } 1364 1365 StoreBaseDisp(reg_ptr, data_offset, rl_src.reg, size, kNotVolatile); 1366 MarkPossibleNullPointerException(opt_flags); 1367 } else { 1368 /* reg_ptr -> array data */ 1369 OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); 1370 rl_src = LoadValue(rl_src, reg_class); 1371 if (needs_range_check) { 1372 GenArrayBoundsCheck(rl_index.reg, reg_len); 1373 FreeTemp(reg_len); 1374 } 1375 StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); 1376 MarkPossibleNullPointerException(opt_flags); 1377 } 1378 if (allocated_reg_ptr_temp) { 1379 FreeTemp(reg_ptr); 1380 } 1381 if (card_mark) { 1382 MarkGCCard(rl_src.reg, rl_array.reg); 1383 } 1384} 1385 1386 1387void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, 1388 RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) { 1389 rl_src = LoadValueWide(rl_src, kCoreReg); 1390 // Per spec, we only care about low 6 bits of shift amount. 1391 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; 1392 if (shift_amount == 0) { 1393 StoreValueWide(rl_dest, rl_src); 1394 return; 1395 } 1396 if (BadOverlap(rl_src, rl_dest)) { 1397 GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); 1398 return; 1399 } 1400 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1401 switch (opcode) { 1402 case Instruction::SHL_LONG: 1403 case Instruction::SHL_LONG_2ADDR: 1404 if (shift_amount == 1) { 1405 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), rl_src.reg.GetLow()); 1406 OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), rl_src.reg.GetHigh()); 1407 } else if (shift_amount == 32) { 1408 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg); 1409 LoadConstant(rl_result.reg.GetLow(), 0); 1410 } else if (shift_amount > 31) { 1411 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetLow(), shift_amount - 32); 1412 LoadConstant(rl_result.reg.GetLow(), 0); 1413 } else { 1414 OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); 1415 OpRegRegRegShift(kOpOr, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), rl_src.reg.GetLow(), 1416 EncodeShift(kArmLsr, 32 - shift_amount)); 1417 OpRegRegImm(kOpLsl, rl_result.reg.GetLow(), rl_src.reg.GetLow(), shift_amount); 1418 } 1419 break; 1420 case Instruction::SHR_LONG: 1421 case Instruction::SHR_LONG_2ADDR: 1422 if (shift_amount == 32) { 1423 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1424 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31); 1425 } else if (shift_amount > 31) { 1426 OpRegRegImm(kOpAsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32); 1427 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31); 1428 } else { 1429 RegStorage t_reg = AllocTemp(); 1430 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount); 1431 OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(), 1432 EncodeShift(kArmLsl, 32 - shift_amount)); 1433 FreeTemp(t_reg); 1434 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); 1435 } 1436 break; 1437 case Instruction::USHR_LONG: 1438 case Instruction::USHR_LONG_2ADDR: 1439 if (shift_amount == 32) { 1440 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1441 LoadConstant(rl_result.reg.GetHigh(), 0); 1442 } else if (shift_amount > 31) { 1443 OpRegRegImm(kOpLsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32); 1444 LoadConstant(rl_result.reg.GetHigh(), 0); 1445 } else { 1446 RegStorage t_reg = AllocTemp(); 1447 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount); 1448 OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(), 1449 EncodeShift(kArmLsl, 32 - shift_amount)); 1450 FreeTemp(t_reg); 1451 OpRegRegImm(kOpLsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); 1452 } 1453 break; 1454 default: 1455 LOG(FATAL) << "Unexpected case"; 1456 } 1457 StoreValueWide(rl_dest, rl_result); 1458} 1459 1460void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode, 1461 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 1462 if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) { 1463 if (!rl_src2.is_const) { 1464 // Don't bother with special handling for subtract from immediate. 1465 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1466 return; 1467 } 1468 } else { 1469 // Normalize 1470 if (!rl_src2.is_const) { 1471 DCHECK(rl_src1.is_const); 1472 std::swap(rl_src1, rl_src2); 1473 } 1474 } 1475 if (BadOverlap(rl_src1, rl_dest)) { 1476 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1477 return; 1478 } 1479 DCHECK(rl_src2.is_const); 1480 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1481 uint32_t val_lo = Low32Bits(val); 1482 uint32_t val_hi = High32Bits(val); 1483 int32_t mod_imm_lo = ModifiedImmediate(val_lo); 1484 int32_t mod_imm_hi = ModifiedImmediate(val_hi); 1485 1486 // Only a subset of add/sub immediate instructions set carry - so bail if we don't fit 1487 switch (opcode) { 1488 case Instruction::ADD_LONG: 1489 case Instruction::ADD_LONG_2ADDR: 1490 case Instruction::SUB_LONG: 1491 case Instruction::SUB_LONG_2ADDR: 1492 if ((mod_imm_lo < 0) || (mod_imm_hi < 0)) { 1493 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1494 return; 1495 } 1496 break; 1497 default: 1498 break; 1499 } 1500 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1501 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1502 // NOTE: once we've done the EvalLoc on dest, we can no longer bail. 1503 switch (opcode) { 1504 case Instruction::ADD_LONG: 1505 case Instruction::ADD_LONG_2ADDR: 1506 NewLIR3(kThumb2AddRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo); 1507 NewLIR3(kThumb2AdcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi); 1508 break; 1509 case Instruction::OR_LONG: 1510 case Instruction::OR_LONG_2ADDR: 1511 if ((val_lo != 0) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) { 1512 OpRegRegImm(kOpOr, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); 1513 } 1514 if ((val_hi != 0) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) { 1515 OpRegRegImm(kOpOr, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); 1516 } 1517 break; 1518 case Instruction::XOR_LONG: 1519 case Instruction::XOR_LONG_2ADDR: 1520 OpRegRegImm(kOpXor, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); 1521 OpRegRegImm(kOpXor, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); 1522 break; 1523 case Instruction::AND_LONG: 1524 case Instruction::AND_LONG_2ADDR: 1525 if ((val_lo != 0xffffffff) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) { 1526 OpRegRegImm(kOpAnd, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); 1527 } 1528 if ((val_hi != 0xffffffff) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) { 1529 OpRegRegImm(kOpAnd, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); 1530 } 1531 break; 1532 case Instruction::SUB_LONG_2ADDR: 1533 case Instruction::SUB_LONG: 1534 NewLIR3(kThumb2SubRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo); 1535 NewLIR3(kThumb2SbcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi); 1536 break; 1537 default: 1538 LOG(FATAL) << "Unexpected opcode " << opcode; 1539 } 1540 StoreValueWide(rl_dest, rl_result); 1541} 1542 1543} // namespace art 1544