arm64_lir.h revision 2eba1fa7e9e5f91e18ae3778d529520bd2c78d55
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ 19 20#include "dex/compiler_internals.h" 21 22namespace art { 23 24/* 25 * TODO(Arm64): the comments below are outdated. 26 * 27 * Runtime register usage conventions. 28 * 29 * r0-r3: Argument registers in both Dalvik and C/C++ conventions. 30 * However, for Dalvik->Dalvik calls we'll pass the target's Method* 31 * pointer in r0 as a hidden arg0. Otherwise used as codegen scratch 32 * registers. 33 * r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit 34 * r4 : (rA64_SUSPEND) is reserved (suspend check/debugger assist) 35 * r5 : Callee save (promotion target) 36 * r6 : Callee save (promotion target) 37 * r7 : Callee save (promotion target) 38 * r8 : Callee save (promotion target) 39 * r9 : (rA64_SELF) is reserved (pointer to thread-local storage) 40 * r10 : Callee save (promotion target) 41 * r11 : Callee save (promotion target) 42 * r12 : Scratch, may be trashed by linkage stubs 43 * r13 : (sp) is reserved 44 * r14 : (lr) is reserved 45 * r15 : (pc) is reserved 46 * 47 * 5 core temps that codegen can use (r0, r1, r2, r3, r12) 48 * 7 core registers that can be used for promotion 49 * 50 * Floating pointer registers 51 * s0-s31 52 * d0-d15, where d0={s0,s1}, d1={s2,s3}, ... , d15={s30,s31} 53 * 54 * s16-s31 (d8-d15) preserved across C calls 55 * s0-s15 (d0-d7) trashed across C calls 56 * 57 * s0-s15/d0-d7 used as codegen temp/scratch 58 * s16-s31/d8-d31 can be used for promotion. 59 * 60 * Calling convention 61 * o On a call to a Dalvik method, pass target's Method* in r0 62 * o r1-r3 will be used for up to the first 3 words of arguments 63 * o Arguments past the first 3 words will be placed in appropriate 64 * out slots by the caller. 65 * o If a 64-bit argument would span the register/memory argument 66 * boundary, it will instead be fully passed in the frame. 67 * o Maintain a 16-byte stack alignment 68 * 69 * Stack frame diagram (stack grows down, higher addresses at top): 70 * 71 * +------------------------+ 72 * | IN[ins-1] | {Note: resides in caller's frame} 73 * | . | 74 * | IN[0] | 75 * | caller's Method* | 76 * +========================+ {Note: start of callee's frame} 77 * | spill region | {variable sized - will include lr if non-leaf.} 78 * +------------------------+ 79 * | ...filler word... | {Note: used as 2nd word of V[locals-1] if long] 80 * +------------------------+ 81 * | V[locals-1] | 82 * | V[locals-2] | 83 * | . | 84 * | . | 85 * | V[1] | 86 * | V[0] | 87 * +------------------------+ 88 * | 0 to 3 words padding | 89 * +------------------------+ 90 * | OUT[outs-1] | 91 * | OUT[outs-2] | 92 * | . | 93 * | OUT[0] | 94 * | cur_method* | <<== sp w/ 16-byte alignment 95 * +========================+ 96 */ 97 98// First FP callee save. 99#define A64_FP_CALLEE_SAVE_BASE 8 100 101// Temporary macros, used to mark code which wants to distinguish betweek zr/sp. 102#define A64_REG_IS_SP(reg_num) ((reg_num) == rwsp || (reg_num) == rsp) 103#define A64_REG_IS_ZR(reg_num) ((reg_num) == rwzr || (reg_num) == rxzr) 104#define A64_REGSTORAGE_IS_SP_OR_ZR(rs) (((rs).GetRegNum() & 0x1f) == 0x1f) 105 106enum Arm64ResourceEncodingPos { 107 kArm64GPReg0 = 0, 108 kArm64RegLR = 30, 109 kArm64RegSP = 31, 110 kArm64FPReg0 = 32, 111 kArm64RegEnd = 64, 112}; 113 114#define IS_SIGNED_IMM(size, value) \ 115 ((value) >= -(1 << ((size) - 1)) && (value) < (1 << ((size) - 1))) 116#define IS_SIGNED_IMM7(value) IS_SIGNED_IMM(7, value) 117#define IS_SIGNED_IMM9(value) IS_SIGNED_IMM(9, value) 118#define IS_SIGNED_IMM12(value) IS_SIGNED_IMM(12, value) 119#define IS_SIGNED_IMM19(value) IS_SIGNED_IMM(19, value) 120#define IS_SIGNED_IMM21(value) IS_SIGNED_IMM(21, value) 121 122// Quick macro used to define the registers. 123#define A64_REGISTER_CODE_LIST(R) \ 124 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 125 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 126 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 127 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 128 129// Registers (integer) values. 130enum A64NativeRegisterPool { 131# define A64_DEFINE_REGISTERS(nr) \ 132 rw##nr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | nr, \ 133 rx##nr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | nr, \ 134 rf##nr = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | nr, \ 135 rd##nr = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | nr, 136 A64_REGISTER_CODE_LIST(A64_DEFINE_REGISTERS) 137#undef A64_DEFINE_REGISTERS 138 139 rxzr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0x3f, 140 rwzr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0x3f, 141 rsp = rx31, 142 rwsp = rw31, 143 144 // Aliases which are not defined in "ARM Architecture Reference, register names". 145 rxIP0 = rx16, 146 rxIP1 = rx17, 147 rxSUSPEND = rx19, 148 rxSELF = rx18, 149 rxLR = rx30, 150 /* 151 * FIXME: It's a bit awkward to define both 32 and 64-bit views of these - we'll only ever use 152 * the 64-bit view. However, for now we'll define a 32-bit view to keep these from being 153 * allocated as 32-bit temp registers. 154 */ 155 rwIP0 = rw16, 156 rwIP1 = rw17, 157 rwSUSPEND = rw19, 158 rwSELF = rw18, 159 rwLR = rw30, 160}; 161 162#define A64_DEFINE_REGSTORAGES(nr) \ 163 constexpr RegStorage rs_w##nr(RegStorage::kValid | rw##nr); \ 164 constexpr RegStorage rs_x##nr(RegStorage::kValid | rx##nr); \ 165 constexpr RegStorage rs_f##nr(RegStorage::kValid | rf##nr); \ 166 constexpr RegStorage rs_d##nr(RegStorage::kValid | rd##nr); 167A64_REGISTER_CODE_LIST(A64_DEFINE_REGSTORAGES) 168#undef A64_DEFINE_REGSTORAGES 169 170constexpr RegStorage rs_xzr(RegStorage::kValid | rxzr); 171constexpr RegStorage rs_wzr(RegStorage::kValid | rwzr); 172constexpr RegStorage rs_xIP0(RegStorage::kValid | rxIP0); 173constexpr RegStorage rs_wIP0(RegStorage::kValid | rwIP0); 174constexpr RegStorage rs_xIP1(RegStorage::kValid | rxIP1); 175constexpr RegStorage rs_wIP1(RegStorage::kValid | rwIP1); 176// Reserved registers. 177constexpr RegStorage rs_xSUSPEND(RegStorage::kValid | rxSUSPEND); 178constexpr RegStorage rs_xSELF(RegStorage::kValid | rxSELF); 179constexpr RegStorage rs_sp(RegStorage::kValid | rsp); 180constexpr RegStorage rs_xLR(RegStorage::kValid | rxLR); 181// TODO: eliminate the need for these. 182constexpr RegStorage rs_wSUSPEND(RegStorage::kValid | rwSUSPEND); 183constexpr RegStorage rs_wSELF(RegStorage::kValid | rwSELF); 184constexpr RegStorage rs_wsp(RegStorage::kValid | rwsp); 185constexpr RegStorage rs_wLR(RegStorage::kValid | rwLR); 186 187// RegisterLocation templates return values (following the hard-float calling convention). 188const RegLocation arm_loc_c_return = 189 {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_w0, INVALID_SREG, INVALID_SREG}; 190const RegLocation arm_loc_c_return_ref = 191 {kLocPhysReg, 0, 0, 0, 0, 0, 1, 0, 1, rs_x0, INVALID_SREG, INVALID_SREG}; 192const RegLocation arm_loc_c_return_wide = 193 {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_x0, INVALID_SREG, INVALID_SREG}; 194const RegLocation arm_loc_c_return_float = 195 {kLocPhysReg, 0, 0, 0, 1, 0, 0, 0, 1, rs_f0, INVALID_SREG, INVALID_SREG}; 196const RegLocation arm_loc_c_return_double = 197 {kLocPhysReg, 1, 0, 0, 1, 0, 0, 0, 1, rs_d0, INVALID_SREG, INVALID_SREG}; 198 199/** 200 * @brief Shift-type to be applied to a register via EncodeShift(). 201 */ 202enum A64ShiftEncodings { 203 kA64Lsl = 0x0, 204 kA64Lsr = 0x1, 205 kA64Asr = 0x2, 206 kA64Ror = 0x3 207}; 208 209/** 210 * @brief Extend-type to be applied to a register via EncodeExtend(). 211 */ 212enum A64RegExtEncodings { 213 kA64Uxtb = 0x0, 214 kA64Uxth = 0x1, 215 kA64Uxtw = 0x2, 216 kA64Uxtx = 0x3, 217 kA64Sxtb = 0x4, 218 kA64Sxth = 0x5, 219 kA64Sxtw = 0x6, 220 kA64Sxtx = 0x7 221}; 222 223#define ENCODE_NO_SHIFT (EncodeShift(kA64Lsl, 0)) 224#define ENCODE_NO_EXTEND (EncodeExtend(kA64Uxtx, 0)) 225/* 226 * The following enum defines the list of supported A64 instructions by the 227 * assembler. Their corresponding EncodingMap positions will be defined in 228 * assemble_arm64.cc. 229 */ 230enum ArmOpcode { 231 kA64First = 0, 232 kA64Adc3rrr = kA64First, // adc [00011010000] rm[20-16] [000000] rn[9-5] rd[4-0]. 233 kA64Add4RRdT, // add [s001000100] imm_12[21-10] rn[9-5] rd[4-0]. 234 kA64Add4rrro, // add [00001011000] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 235 kA64Add4RRre, // add [00001011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] rd[4-0]. 236 kA64Adr2xd, // adr [0] immlo[30-29] [10000] immhi[23-5] rd[4-0]. 237 kA64And3Rrl, // and [00010010] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 238 kA64And4rrro, // and [00001010] shift[23-22] [N=0] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 239 kA64Asr3rrd, // asr [0001001100] immr[21-16] imms[15-10] rn[9-5] rd[4-0]. 240 kA64Asr3rrr, // asr alias of "sbfm arg0, arg1, arg2, {#31/#63}". 241 kA64B2ct, // b.cond [01010100] imm_19[23-5] [0] cond[3-0]. 242 kA64Blr1x, // blr [1101011000111111000000] rn[9-5] [00000]. 243 kA64Br1x, // br [1101011000011111000000] rn[9-5] [00000]. 244 kA64Brk1d, // brk [11010100001] imm_16[20-5] [00000]. 245 kA64B1t, // b [00010100] offset_26[25-0]. 246 kA64Cbnz2rt, // cbnz[00110101] imm_19[23-5] rt[4-0]. 247 kA64Cbz2rt, // cbz [00110100] imm_19[23-5] rt[4-0]. 248 kA64Cmn3rro, // cmn [s0101011] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] [11111]. 249 kA64Cmn3Rre, // cmn [s0101011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] [11111]. 250 kA64Cmn3RdT, // cmn [00110001] shift[23-22] imm_12[21-10] rn[9-5] [11111]. 251 kA64Cmp3rro, // cmp [s1101011] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] [11111]. 252 kA64Cmp3Rre, // cmp [s1101011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] [11111]. 253 kA64Cmp3RdT, // cmp [01110001] shift[23-22] imm_12[21-10] rn[9-5] [11111]. 254 kA64Csel4rrrc, // csel[s0011010100] rm[20-16] cond[15-12] [00] rn[9-5] rd[4-0]. 255 kA64Csinc4rrrc, // csinc [s0011010100] rm[20-16] cond[15-12] [01] rn[9-5] rd[4-0]. 256 kA64Csinv4rrrc, // csinv [s1011010100] rm[20-16] cond[15-12] [00] rn[9-5] rd[4-0]. 257 kA64Csneg4rrrc, // csneg [s1011010100] rm[20-16] cond[15-12] [01] rn[9-5] rd[4-0]. 258 kA64Dmb1B, // dmb [11010101000000110011] CRm[11-8] [10111111]. 259 kA64Eor3Rrl, // eor [s10100100] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 260 kA64Eor4rrro, // eor [s1001010] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 261 kA64Extr4rrrd, // extr[s00100111N0] rm[20-16] imm_s[15-10] rn[9-5] rd[4-0]. 262 kA64Fabs2ff, // fabs[000111100s100000110000] rn[9-5] rd[4-0]. 263 kA64Fadd3fff, // fadd[000111100s1] rm[20-16] [001010] rn[9-5] rd[4-0]. 264 kA64Fcmp1f, // fcmp[000111100s100000001000] rn[9-5] [01000]. 265 kA64Fcmp2ff, // fcmp[000111100s1] rm[20-16] [001000] rn[9-5] [00000]. 266 kA64Fcvtzs2wf, // fcvtzs [000111100s111000000000] rn[9-5] rd[4-0]. 267 kA64Fcvtzs2xf, // fcvtzs [100111100s111000000000] rn[9-5] rd[4-0]. 268 kA64Fcvt2Ss, // fcvt [0001111000100010110000] rn[9-5] rd[4-0]. 269 kA64Fcvt2sS, // fcvt [0001111001100010010000] rn[9-5] rd[4-0]. 270 kA64Fcvtms2ws, // fcvtms [0001111000110000000000] rn[9-5] rd[4-0]. 271 kA64Fcvtms2xS, // fcvtms [1001111001110000000000] rn[9-5] rd[4-0]. 272 kA64Fdiv3fff, // fdiv[000111100s1] rm[20-16] [000110] rn[9-5] rd[4-0]. 273 kA64Fmax3fff, // fmax[000111100s1] rm[20-16] [010010] rn[9-5] rd[4-0]. 274 kA64Fmin3fff, // fmin[000111100s1] rm[20-16] [010110] rn[9-5] rd[4-0]. 275 kA64Fmov2ff, // fmov[000111100s100000010000] rn[9-5] rd[4-0]. 276 kA64Fmov2fI, // fmov[000111100s1] imm_8[20-13] [10000000] rd[4-0]. 277 kA64Fmov2sw, // fmov[0001111000100111000000] rn[9-5] rd[4-0]. 278 kA64Fmov2Sx, // fmov[1001111001100111000000] rn[9-5] rd[4-0]. 279 kA64Fmov2ws, // fmov[0001111001101110000000] rn[9-5] rd[4-0]. 280 kA64Fmov2xS, // fmov[1001111001101111000000] rn[9-5] rd[4-0]. 281 kA64Fmul3fff, // fmul[000111100s1] rm[20-16] [000010] rn[9-5] rd[4-0]. 282 kA64Fneg2ff, // fneg[000111100s100001010000] rn[9-5] rd[4-0]. 283 kA64Frintp2ff, // frintp [000111100s100100110000] rn[9-5] rd[4-0]. 284 kA64Frintm2ff, // frintm [000111100s100101010000] rn[9-5] rd[4-0]. 285 kA64Frintn2ff, // frintn [000111100s100100010000] rn[9-5] rd[4-0]. 286 kA64Frintz2ff, // frintz [000111100s100101110000] rn[9-5] rd[4-0]. 287 kA64Fsqrt2ff, // fsqrt[000111100s100001110000] rn[9-5] rd[4-0]. 288 kA64Fsub3fff, // fsub[000111100s1] rm[20-16] [001110] rn[9-5] rd[4-0]. 289 kA64Ldrb3wXd, // ldrb[0011100101] imm_12[21-10] rn[9-5] rt[4-0]. 290 kA64Ldrb3wXx, // ldrb[00111000011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 291 kA64Ldrsb3rXd, // ldrsb[001110011s] imm_12[21-10] rn[9-5] rt[4-0]. 292 kA64Ldrsb3rXx, // ldrsb[0011 1000 1s1] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 293 kA64Ldrh3wXF, // ldrh[0111100101] imm_12[21-10] rn[9-5] rt[4-0]. 294 kA64Ldrh4wXxd, // ldrh[01111000011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 295 kA64Ldrsh3rXF, // ldrsh[011110011s] imm_12[21-10] rn[9-5] rt[4-0]. 296 kA64Ldrsh4rXxd, // ldrsh[011110001s1] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0] 297 kA64Ldr2fp, // ldr [0s011100] imm_19[23-5] rt[4-0]. 298 kA64Ldr2rp, // ldr [0s011000] imm_19[23-5] rt[4-0]. 299 kA64Ldr3fXD, // ldr [1s11110100] imm_12[21-10] rn[9-5] rt[4-0]. 300 kA64Ldr3rXD, // ldr [1s111000010] imm_9[20-12] [01] rn[9-5] rt[4-0]. 301 kA64Ldr4fXxG, // ldr [1s111100011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 302 kA64Ldr4rXxG, // ldr [1s111000011] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 303 kA64LdrPost3rXd, // ldr [1s111000010] imm_9[20-12] [01] rn[9-5] rt[4-0]. 304 kA64Ldp4ffXD, // ldp [0s10110101] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 305 kA64Ldp4rrXD, // ldp [s010100101] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 306 kA64LdpPost4rrXD, // ldp [s010100011] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 307 kA64Ldur3fXd, // ldur[1s111100010] imm_9[20-12] [00] rn[9-5] rt[4-0]. 308 kA64Ldur3rXd, // ldur[1s111000010] imm_9[20-12] [00] rn[9-5] rt[4-0]. 309 kA64Ldxr2rX, // ldxr[1s00100001011111011111] rn[9-5] rt[4-0]. 310 kA64Ldaxr2rX, // ldaxr[1s00100001011111111111] rn[9-5] rt[4-0]. 311 kA64Lsl3rrr, // lsl [s0011010110] rm[20-16] [001000] rn[9-5] rd[4-0]. 312 kA64Lsr3rrd, // lsr alias of "ubfm arg0, arg1, arg2, #{31/63}". 313 kA64Lsr3rrr, // lsr [s0011010110] rm[20-16] [001001] rn[9-5] rd[4-0]. 314 kA64Movk3rdM, // mov [010100101] hw[22-21] imm_16[20-5] rd[4-0]. 315 kA64Movn3rdM, // mov [000100101] hw[22-21] imm_16[20-5] rd[4-0]. 316 kA64Movz3rdM, // mov [011100101] hw[22-21] imm_16[20-5] rd[4-0]. 317 kA64Mov2rr, // mov [00101010000] rm[20-16] [000000] [11111] rd[4-0]. 318 kA64Mvn2rr, // mov [00101010001] rm[20-16] [000000] [11111] rd[4-0]. 319 kA64Mul3rrr, // mul [00011011000] rm[20-16] [011111] rn[9-5] rd[4-0]. 320 kA64Msub4rrrr, // msub[s0011011000] rm[20-16] [1] ra[14-10] rn[9-5] rd[4-0]. 321 kA64Neg3rro, // neg alias of "sub arg0, rzr, arg1, arg2". 322 kA64Orr3Rrl, // orr [s01100100] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 323 kA64Orr4rrro, // orr [s0101010] shift[23-22] [0] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 324 kA64Ret, // ret [11010110010111110000001111000000]. 325 kA64Rbit2rr, // rbit [s101101011000000000000] rn[9-5] rd[4-0]. 326 kA64Rev2rr, // rev [s10110101100000000001x] rn[9-5] rd[4-0]. 327 kA64Rev162rr, // rev16[s101101011000000000001] rn[9-5] rd[4-0]. 328 kA64Ror3rrr, // ror [s0011010110] rm[20-16] [001011] rn[9-5] rd[4-0]. 329 kA64Sbc3rrr, // sbc [s0011010000] rm[20-16] [000000] rn[9-5] rd[4-0]. 330 kA64Sbfm4rrdd, // sbfm[0001001100] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 331 kA64Scvtf2fw, // scvtf [000111100s100010000000] rn[9-5] rd[4-0]. 332 kA64Scvtf2fx, // scvtf [100111100s100010000000] rn[9-5] rd[4-0]. 333 kA64Sdiv3rrr, // sdiv[s0011010110] rm[20-16] [000011] rn[9-5] rd[4-0]. 334 kA64Smaddl4xwwx, // smaddl [10011011001] rm[20-16] [0] ra[14-10] rn[9-5] rd[4-0]. 335 kA64Smulh3xxx, // smulh [10011011010] rm[20-16] [011111] rn[9-5] rd[4-0]. 336 kA64Stp4ffXD, // stp [0s10110100] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 337 kA64Stp4rrXD, // stp [s010100100] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 338 kA64StpPost4rrXD, // stp [s010100010] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 339 kA64StpPre4ffXD, // stp [0s10110110] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 340 kA64StpPre4rrXD, // stp [s010100110] imm_7[21-15] rt2[14-10] rn[9-5] rt[4-0]. 341 kA64Str3fXD, // str [1s11110100] imm_12[21-10] rn[9-5] rt[4-0]. 342 kA64Str4fXxG, // str [1s111100001] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 343 kA64Str3rXD, // str [1s11100100] imm_12[21-10] rn[9-5] rt[4-0]. 344 kA64Str4rXxG, // str [1s111000001] rm[20-16] option[15-13] S[12-12] [10] rn[9-5] rt[4-0]. 345 kA64Strb3wXd, // strb[0011100100] imm_12[21-10] rn[9-5] rt[4-0]. 346 kA64Strb3wXx, // strb[00111000001] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 347 kA64Strh3wXF, // strh[0111100100] imm_12[21-10] rn[9-5] rt[4-0]. 348 kA64Strh4wXxd, // strh[01111000001] rm[20-16] [011] S[12] [10] rn[9-5] rt[4-0]. 349 kA64StrPost3rXd, // str [1s111000000] imm_9[20-12] [01] rn[9-5] rt[4-0]. 350 kA64Stur3fXd, // stur[1s111100000] imm_9[20-12] [00] rn[9-5] rt[4-0]. 351 kA64Stur3rXd, // stur[1s111000000] imm_9[20-12] [00] rn[9-5] rt[4-0]. 352 kA64Stxr3wrX, // stxr[11001000000] rs[20-16] [011111] rn[9-5] rt[4-0]. 353 kA64Stlxr3wrX, // stlxr[11001000000] rs[20-16] [111111] rn[9-5] rt[4-0]. 354 kA64Sub4RRdT, // sub [s101000100] imm_12[21-10] rn[9-5] rd[4-0]. 355 kA64Sub4rrro, // sub [s1001011000] rm[20-16] imm_6[15-10] rn[9-5] rd[4-0]. 356 kA64Sub4RRre, // sub [s1001011001] rm[20-16] option[15-13] imm_3[12-10] rn[9-5] rd[4-0]. 357 kA64Subs3rRd, // subs[s111000100] imm_12[21-10] rn[9-5] rd[4-0]. 358 kA64Tst3rro, // tst alias of "ands rzr, arg1, arg2, arg3". 359 kA64Ubfm4rrdd, // ubfm[s10100110] N[22] imm_r[21-16] imm_s[15-10] rn[9-5] rd[4-0]. 360 kA64Last, 361 kA64NotWide = 0, // Flag used to select the first instruction variant. 362 kA64Wide = 0x1000 // Flag used to select the second instruction variant. 363}; 364 365/* 366 * The A64 instruction set provides two variants for many instructions. For example, "mov wN, wM" 367 * and "mov xN, xM" or - for floating point instructions - "mov sN, sM" and "mov dN, dM". 368 * It definitely makes sense to exploit this symmetries of the instruction set. We do this via the 369 * WIDE, UNWIDE macros. For opcodes that allow it, the wide variant can be obtained by applying the 370 * WIDE macro to the non-wide opcode. E.g. WIDE(kA64Sub4RRdT). 371 */ 372 373// Return the wide and no-wide variants of the given opcode. 374#define WIDE(op) ((ArmOpcode)((op) | kA64Wide)) 375#define UNWIDE(op) ((ArmOpcode)((op) & ~kA64Wide)) 376 377// Whether the given opcode is wide. 378#define IS_WIDE(op) (((op) & kA64Wide) != 0) 379 380/* 381 * Floating point variants. These are just aliases of the macros above which we use for floating 382 * point instructions, just for readibility reasons. 383 * TODO(Arm64): should we remove these and use the original macros? 384 */ 385#define FWIDE WIDE 386#define FUNWIDE UNWIDE 387#define IS_FWIDE IS_WIDE 388 389enum ArmOpDmbOptions { 390 kSY = 0xf, 391 kST = 0xe, 392 kISH = 0xb, 393 kISHST = 0xa, 394 kISHLD = 0x9, 395 kNSH = 0x7, 396 kNSHST = 0x6 397}; 398 399// Instruction assembly field_loc kind. 400enum ArmEncodingKind { 401 // All the formats below are encoded in the same way (as a kFmtBitBlt). 402 // These are grouped together, for fast handling (e.g. "if (LIKELY(fmt <= kFmtBitBlt)) ..."). 403 kFmtRegW = 0, // Word register (w) or wzr. 404 kFmtRegX, // Extended word register (x) or xzr. 405 kFmtRegR, // Register with same width as the instruction or zr. 406 kFmtRegWOrSp, // Word register (w) or wsp. 407 kFmtRegXOrSp, // Extended word register (x) or sp. 408 kFmtRegROrSp, // Register with same width as the instruction or sp. 409 kFmtRegS, // Single FP reg. 410 kFmtRegD, // Double FP reg. 411 kFmtRegF, // Single/double FP reg depending on the instruction width. 412 kFmtBitBlt, // Bit string using end/start. 413 414 // Less likely formats. 415 kFmtUnused, // Unused field and marks end of formats. 416 kFmtImm21, // Sign-extended immediate using [23..5,30..29]. 417 kFmtShift, // Register shift, 9-bit at [23..21, 15..10].. 418 kFmtExtend, // Register extend, 9-bit at [23..21, 15..10]. 419 kFmtSkip, // Unused field, but continue to next. 420}; 421 422// Struct used to define the snippet positions for each A64 opcode. 423struct ArmEncodingMap { 424 uint32_t wskeleton; 425 uint32_t xskeleton; 426 struct { 427 ArmEncodingKind kind; 428 int end; // end for kFmtBitBlt, 1-bit slice end for FP regs. 429 int start; // start for kFmtBitBlt, 4-bit slice end for FP regs. 430 } field_loc[4]; 431 ArmOpcode opcode; // can be WIDE()-ned to indicate it has a wide variant. 432 uint64_t flags; 433 const char* name; 434 const char* fmt; 435 int size; // Note: size is in bytes. 436 FixupKind fixup; 437}; 438 439#if 0 440// TODO(Arm64): try the following alternative, which fits exactly in one cache line (64 bytes). 441struct ArmEncodingMap { 442 uint32_t wskeleton; 443 uint32_t xskeleton; 444 uint64_t flags; 445 const char* name; 446 const char* fmt; 447 struct { 448 uint8_t kind; 449 int8_t end; // end for kFmtBitBlt, 1-bit slice end for FP regs. 450 int8_t start; // start for kFmtBitBlt, 4-bit slice end for FP regs. 451 } field_loc[4]; 452 uint32_t fixup; 453 uint32_t opcode; // can be WIDE()-ned to indicate it has a wide variant. 454 uint32_t padding[3]; 455}; 456#endif 457 458} // namespace art 459 460#endif // ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ 461