assemble_arm64.cc revision f29ecd69af2743a425314baa4abd6c44d8d88649
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "arm64_lir.h" 18#include "codegen_arm64.h" 19#include "dex/quick/mir_to_lir-inl.h" 20 21namespace art { 22 23// The macros below are exclusively used in the encoding map. 24 25// Most generic way of providing two variants for one instructions. 26#define CUSTOM_VARIANTS(variant1, variant2) variant1, variant2 27 28// Used for instructions which do not have a wide variant. 29#define NO_VARIANTS(variant) \ 30 CUSTOM_VARIANTS(variant, 0) 31 32// Used for instructions which have a wide variant with the sf bit set to 1. 33#define SF_VARIANTS(sf0_skeleton) \ 34 CUSTOM_VARIANTS(sf0_skeleton, (sf0_skeleton | 0x80000000)) 35 36// Used for instructions which have a wide variant with the size bits set to either x0 or x1. 37#define SIZE_VARIANTS(sizex0_skeleton) \ 38 CUSTOM_VARIANTS(sizex0_skeleton, (sizex0_skeleton | 0x40000000)) 39 40// Used for instructions which have a wide variant with the sf and n bits set to 1. 41#define SF_N_VARIANTS(sf0_n0_skeleton) \ 42 CUSTOM_VARIANTS(sf0_n0_skeleton, (sf0_n0_skeleton | 0x80400000)) 43 44// Used for FP instructions which have a single and double precision variants, with he type bits set 45// to either 00 or 01. 46#define FLOAT_VARIANTS(type00_skeleton) \ 47 CUSTOM_VARIANTS(type00_skeleton, (type00_skeleton | 0x00400000)) 48 49/* 50 * opcode: ArmOpcode enum 51 * variants: instruction skeletons supplied via CUSTOM_VARIANTS or derived macros. 52 * a{n}k: key to applying argument {n} \ 53 * a{n}s: argument {n} start bit position | n = 0, 1, 2, 3 54 * a{n}e: argument {n} end bit position / 55 * flags: instruction attributes (used in optimization) 56 * name: mnemonic name 57 * fmt: for pretty-printing 58 * fixup: used for second-pass fixes (e.g. adresses fixups in branch instructions). 59 */ 60#define ENCODING_MAP(opcode, variants, a0k, a0s, a0e, a1k, a1s, a1e, a2k, a2s, a2e, \ 61 a3k, a3s, a3e, flags, name, fmt, fixup) \ 62 {variants, {{a0k, a0s, a0e}, {a1k, a1s, a1e}, {a2k, a2s, a2e}, \ 63 {a3k, a3s, a3e}}, opcode, flags, name, fmt, 4, fixup} 64 65/* Instruction dump string format keys: !pf, where "!" is the start 66 * of the key, "p" is which numeric operand to use and "f" is the 67 * print format. 68 * 69 * [p]ositions: 70 * 0 -> operands[0] (dest) 71 * 1 -> operands[1] (src1) 72 * 2 -> operands[2] (src2) 73 * 3 -> operands[3] (extra) 74 * 75 * [f]ormats: 76 * d -> decimal 77 * D -> decimal*4 or decimal*8 depending on the instruction width 78 * E -> decimal*4 79 * F -> decimal*2 80 * G -> ", lsl #2" or ", lsl #3" depending on the instruction width 81 * c -> branch condition (eq, ne, etc.) 82 * t -> pc-relative target 83 * p -> pc-relative address 84 * s -> single precision floating point register 85 * S -> double precision floating point register 86 * f -> single or double precision register (depending on instruction width) 87 * I -> 8-bit immediate floating point number 88 * l -> logical immediate 89 * M -> 16-bit shift expression ("" or ", lsl #16" or ", lsl #32"...) 90 * B -> dmb option string (sy, st, ish, ishst, nsh, hshst) 91 * H -> operand shift 92 * T -> register shift (either ", lsl #0" or ", lsl #12") 93 * e -> register extend (e.g. uxtb #1) 94 * o -> register shift (e.g. lsl #1) for Word registers 95 * w -> word (32-bit) register wn, or wzr 96 * W -> word (32-bit) register wn, or wsp 97 * x -> extended (64-bit) register xn, or xzr 98 * X -> extended (64-bit) register xn, or sp 99 * r -> register with same width as instruction, r31 -> wzr, xzr 100 * R -> register with same width as instruction, r31 -> wsp, sp 101 * 102 * [!] escape. To insert "!", use "!!" 103 */ 104/* NOTE: must be kept in sync with enum ArmOpcode from arm64_lir.h */ 105const ArmEncodingMap Arm64Mir2Lir::EncodingMap[kA64Last] = { 106 ENCODING_MAP(WIDE(kA64Adc3rrr), SF_VARIANTS(0x1a000000), 107 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 108 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 109 "adc", "!0r, !1r, !2r", kFixupNone), 110 ENCODING_MAP(WIDE(kA64Add4RRdT), SF_VARIANTS(0x11000000), 111 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, 112 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1, 113 "add", "!0R, !1R, #!2d!3T", kFixupNone), 114 ENCODING_MAP(WIDE(kA64Add4rrro), SF_VARIANTS(0x0b000000), 115 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 116 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 117 "add", "!0r, !1r, !2r!3o", kFixupNone), 118 ENCODING_MAP(WIDE(kA64Add4RRre), SF_VARIANTS(0x0b200000), 119 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, 120 kFmtExtend, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 121 "add", "!0r, !1r, !2r!3e", kFixupNone), 122 // Note: adr is binary, but declared as tertiary. The third argument is used while doing the 123 // fixups and contains information to identify the adr label. 124 ENCODING_MAP(kA64Adr2xd, NO_VARIANTS(0x10000000), 125 kFmtRegX, 4, 0, kFmtImm21, -1, -1, kFmtUnused, -1, -1, 126 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | NEEDS_FIXUP, 127 "adr", "!0x, #!1d", kFixupAdr), 128 ENCODING_MAP(WIDE(kA64And3Rrl), SF_VARIANTS(0x12000000), 129 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10, 130 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 131 "and", "!0R, !1r, #!2l", kFixupNone), 132 ENCODING_MAP(WIDE(kA64And4rrro), SF_VARIANTS(0x0a000000), 133 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 134 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 135 "and", "!0r, !1r, !2r!3o", kFixupNone), 136 ENCODING_MAP(WIDE(kA64Asr3rrd), CUSTOM_VARIANTS(0x13007c00, 0x9340fc00), 137 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 138 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 139 "asr", "!0r, !1r, #!2d", kFixupNone), 140 ENCODING_MAP(WIDE(kA64Asr3rrr), SF_VARIANTS(0x1ac02800), 141 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 142 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 143 "asr", "!0r, !1r, !2r", kFixupNone), 144 ENCODING_MAP(kA64B2ct, NO_VARIANTS(0x54000000), 145 kFmtBitBlt, 3, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 146 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | USES_CCODES | 147 NEEDS_FIXUP, "b.!0c", "!1t", kFixupCondBranch), 148 ENCODING_MAP(kA64Blr1x, NO_VARIANTS(0xd63f0000), 149 kFmtRegX, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 150 kFmtUnused, -1, -1, 151 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR, 152 "blr", "!0x", kFixupNone), 153 ENCODING_MAP(kA64Br1x, NO_VARIANTS(0xd61f0000), 154 kFmtRegX, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 155 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE0 | IS_BRANCH, 156 "br", "!0x", kFixupNone), 157 ENCODING_MAP(kA64Brk1d, NO_VARIANTS(0xd4200000), 158 kFmtBitBlt, 20, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 159 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH, 160 "brk", "!0d", kFixupNone), 161 ENCODING_MAP(kA64B1t, NO_VARIANTS(0x14000000), 162 kFmtBitBlt, 25, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 163 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, 164 "b", "!0t", kFixupT1Branch), 165 ENCODING_MAP(WIDE(kA64Cbnz2rt), SF_VARIANTS(0x35000000), 166 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 167 kFmtUnused, -1, -1, 168 IS_BINARY_OP | REG_USE0 | IS_BRANCH | NEEDS_FIXUP, 169 "cbnz", "!0r, !1t", kFixupCBxZ), 170 ENCODING_MAP(WIDE(kA64Cbz2rt), SF_VARIANTS(0x34000000), 171 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 172 kFmtUnused, -1, -1, 173 IS_BINARY_OP | REG_USE0 | IS_BRANCH | NEEDS_FIXUP, 174 "cbz", "!0r, !1t", kFixupCBxZ), 175 ENCODING_MAP(WIDE(kA64Cmn3rro), SF_VARIANTS(0x2b00001f), 176 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1, 177 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 178 "cmn", "!0r, !1r!2o", kFixupNone), 179 ENCODING_MAP(WIDE(kA64Cmn3Rre), SF_VARIANTS(0x2b20001f), 180 kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, kFmtExtend, -1, -1, 181 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 182 "cmn", "!0R, !1r!2e", kFixupNone), 183 ENCODING_MAP(WIDE(kA64Cmn3RdT), SF_VARIANTS(0x3100001f), 184 kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, kFmtBitBlt, 23, 22, 185 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, 186 "cmn", "!0R, #!1d!2T", kFixupNone), 187 ENCODING_MAP(WIDE(kA64Cmp3rro), SF_VARIANTS(0x6b00001f), 188 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1, 189 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 190 "cmp", "!0r, !1r!2o", kFixupNone), 191 ENCODING_MAP(WIDE(kA64Cmp3Rre), SF_VARIANTS(0x6b20001f), 192 kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, kFmtExtend, -1, -1, 193 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 194 "cmp", "!0R, !1r!2e", kFixupNone), 195 ENCODING_MAP(WIDE(kA64Cmp3RdT), SF_VARIANTS(0x7100001f), 196 kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, kFmtBitBlt, 23, 22, 197 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, 198 "cmp", "!0R, #!1d!2T", kFixupNone), 199 ENCODING_MAP(WIDE(kA64Csel4rrrc), SF_VARIANTS(0x1a800000), 200 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 201 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 202 "csel", "!0r, !1r, !2r, !3c", kFixupNone), 203 ENCODING_MAP(WIDE(kA64Csinc4rrrc), SF_VARIANTS(0x1a800400), 204 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 205 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 206 "csinc", "!0r, !1r, !2r, !3c", kFixupNone), 207 ENCODING_MAP(WIDE(kA64Csinv4rrrc), SF_VARIANTS(0x5a800000), 208 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 209 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 210 "csinv", "!0r, !1r, !2r, !3c", kFixupNone), 211 ENCODING_MAP(WIDE(kA64Csneg4rrrc), SF_VARIANTS(0x5a800400), 212 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 213 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 214 "csneg", "!0r, !1r, !2r, !3c", kFixupNone), 215 ENCODING_MAP(kA64Dmb1B, NO_VARIANTS(0xd50330bf), 216 kFmtBitBlt, 11, 8, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 217 kFmtUnused, -1, -1, IS_UNARY_OP, 218 "dmb", "#!0B", kFixupNone), 219 ENCODING_MAP(WIDE(kA64Eor3Rrl), SF_VARIANTS(0x52000000), 220 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10, 221 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 222 "eor", "!0R, !1r, #!2l", kFixupNone), 223 ENCODING_MAP(WIDE(kA64Eor4rrro), SF_VARIANTS(0x4a000000), 224 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 225 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 226 "eor", "!0r, !1r, !2r!3o", kFixupNone), 227 ENCODING_MAP(WIDE(kA64Extr4rrrd), SF_N_VARIANTS(0x13800000), 228 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 229 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE12, 230 "extr", "!0r, !1r, !2r, #!3d", kFixupNone), 231 ENCODING_MAP(FWIDE(kA64Fabs2ff), FLOAT_VARIANTS(0x1e20c000), 232 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 233 kFmtUnused, -1, -1, IS_BINARY_OP| REG_DEF0_USE1, 234 "fabs", "!0f, !1f", kFixupNone), 235 ENCODING_MAP(FWIDE(kA64Fadd3fff), FLOAT_VARIANTS(0x1e202800), 236 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 237 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 238 "fadd", "!0f, !1f, !2f", kFixupNone), 239 ENCODING_MAP(FWIDE(kA64Fcmp1f), FLOAT_VARIANTS(0x1e202008), 240 kFmtRegF, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 241 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE0 | SETS_CCODES, 242 "fcmp", "!0f, #0", kFixupNone), 243 ENCODING_MAP(FWIDE(kA64Fcmp2ff), FLOAT_VARIANTS(0x1e202000), 244 kFmtRegF, 9, 5, kFmtRegF, 20, 16, kFmtUnused, -1, -1, 245 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES, 246 "fcmp", "!0f, !1f", kFixupNone), 247 ENCODING_MAP(FWIDE(kA64Fcvtzs2wf), FLOAT_VARIANTS(0x1e380000), 248 kFmtRegW, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 249 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 250 "fcvtzs", "!0w, !1f", kFixupNone), 251 ENCODING_MAP(FWIDE(kA64Fcvtzs2xf), FLOAT_VARIANTS(0x9e380000), 252 kFmtRegX, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 253 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 254 "fcvtzs", "!0x, !1f", kFixupNone), 255 ENCODING_MAP(kA64Fcvt2Ss, NO_VARIANTS(0x1e22C000), 256 kFmtRegD, 4, 0, kFmtRegS, 9, 5, kFmtUnused, -1, -1, 257 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 258 "fcvt", "!0S, !1s", kFixupNone), 259 ENCODING_MAP(kA64Fcvt2sS, NO_VARIANTS(0x1e624000), 260 kFmtRegS, 4, 0, kFmtRegD, 9, 5, kFmtUnused, -1, -1, 261 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 262 "fcvt", "!0s, !1S", kFixupNone), 263 ENCODING_MAP(FWIDE(kA64Fdiv3fff), FLOAT_VARIANTS(0x1e201800), 264 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 265 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 266 "fdiv", "!0f, !1f, !2f", kFixupNone), 267 ENCODING_MAP(FWIDE(kA64Fmax3fff), FLOAT_VARIANTS(0x1e204800), 268 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 269 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 270 "fmax", "!0f, !1f, !2f", kFixupNone), 271 ENCODING_MAP(FWIDE(kA64Fmin3fff), FLOAT_VARIANTS(0x1e205800), 272 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 273 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 274 "fmin", "!0f, !1f, !2f", kFixupNone), 275 ENCODING_MAP(FWIDE(kA64Fmov2ff), FLOAT_VARIANTS(0x1e204000), 276 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 277 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 278 "fmov", "!0f, !1f", kFixupNone), 279 ENCODING_MAP(FWIDE(kA64Fmov2fI), FLOAT_VARIANTS(0x1e201000), 280 kFmtRegF, 4, 0, kFmtBitBlt, 20, 13, kFmtUnused, -1, -1, 281 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0, 282 "fmov", "!0f, #!1I", kFixupNone), 283 ENCODING_MAP(kA64Fmov2sw, NO_VARIANTS(0x1e270000), 284 kFmtRegS, 4, 0, kFmtRegW, 9, 5, kFmtUnused, -1, -1, 285 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 286 "fmov", "!0s, !1w", kFixupNone), 287 ENCODING_MAP(kA64Fmov2Sx, NO_VARIANTS(0x9e670000), 288 kFmtRegD, 4, 0, kFmtRegX, 9, 5, kFmtUnused, -1, -1, 289 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 290 "fmov", "!0S, !1x", kFixupNone), 291 ENCODING_MAP(kA64Fmov2ws, NO_VARIANTS(0x1e260000), 292 kFmtRegW, 4, 0, kFmtRegS, 9, 5, kFmtUnused, -1, -1, 293 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 294 "fmov", "!0w, !1s", kFixupNone), 295 ENCODING_MAP(kA64Fmov2xS, NO_VARIANTS(0x9e660000), 296 kFmtRegX, 4, 0, kFmtRegD, 9, 5, kFmtUnused, -1, -1, 297 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 298 "fmov", "!0x, !1S", kFixupNone), 299 ENCODING_MAP(FWIDE(kA64Fmul3fff), FLOAT_VARIANTS(0x1e200800), 300 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 301 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 302 "fmul", "!0f, !1f, !2f", kFixupNone), 303 ENCODING_MAP(FWIDE(kA64Fneg2ff), FLOAT_VARIANTS(0x1e214000), 304 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 305 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 306 "fneg", "!0f, !1f", kFixupNone), 307 ENCODING_MAP(FWIDE(kA64Frintz2ff), FLOAT_VARIANTS(0x1e25c000), 308 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 309 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 310 "frintz", "!0f, !1f", kFixupNone), 311 ENCODING_MAP(FWIDE(kA64Fsqrt2ff), FLOAT_VARIANTS(0x1e61c000), 312 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 313 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 314 "fsqrt", "!0f, !1f", kFixupNone), 315 ENCODING_MAP(FWIDE(kA64Fsub3fff), FLOAT_VARIANTS(0x1e203800), 316 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 317 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 318 "fsub", "!0f, !1f, !2f", kFixupNone), 319 ENCODING_MAP(kA64Ldrb3wXd, NO_VARIANTS(0x39400000), 320 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 321 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 322 "ldrb", "!0w, [!1X, #!2d]", kFixupNone), 323 ENCODING_MAP(kA64Ldrb3wXx, NO_VARIANTS(0x38606800), 324 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 325 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD, 326 "ldrb", "!0w, [!1X, !2x]", kFixupNone), 327 ENCODING_MAP(WIDE(kA64Ldrsb3rXd), CUSTOM_VARIANTS(0x39c00000, 0x39800000), 328 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 329 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 330 "ldrsb", "!0r, [!1X, #!2d]", kFixupNone), 331 ENCODING_MAP(WIDE(kA64Ldrsb3rXx), CUSTOM_VARIANTS(0x38e06800, 0x38a06800), 332 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 333 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD, 334 "ldrsb", "!0r, [!1X, !2x]", kFixupNone), 335 ENCODING_MAP(kA64Ldrh3wXF, NO_VARIANTS(0x79400000), 336 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 337 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 338 "ldrh", "!0w, [!1X, #!2F]", kFixupNone), 339 ENCODING_MAP(kA64Ldrh4wXxd, NO_VARIANTS(0x78606800), 340 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 341 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD, 342 "ldrh", "!0w, [!1X, !2x, lsl #!3d]", kFixupNone), 343 ENCODING_MAP(WIDE(kA64Ldrsh3rXF), CUSTOM_VARIANTS(0x79c00000, 0x79800000), 344 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 345 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 346 "ldrsh", "!0r, [!1X, #!2F]", kFixupNone), 347 ENCODING_MAP(WIDE(kA64Ldrsh4rXxd), CUSTOM_VARIANTS(0x78e06800, 0x78906800), 348 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 349 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD, 350 "ldrsh", "!0r, [!1X, !2x, lsl #!3d]", kFixupNone), 351 ENCODING_MAP(FWIDE(kA64Ldr2fp), SIZE_VARIANTS(0x1c000000), 352 kFmtRegF, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 353 kFmtUnused, -1, -1, 354 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP, 355 "ldr", "!0f, !1p", kFixupLoad), 356 ENCODING_MAP(WIDE(kA64Ldr2rp), SIZE_VARIANTS(0x18000000), 357 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 358 kFmtUnused, -1, -1, 359 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP, 360 "ldr", "!0r, !1p", kFixupLoad), 361 ENCODING_MAP(FWIDE(kA64Ldr3fXD), SIZE_VARIANTS(0xbd400000), 362 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 363 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 364 "ldr", "!0f, [!1X, #!2D]", kFixupNone), 365 ENCODING_MAP(WIDE(kA64Ldr3rXD), SIZE_VARIANTS(0xb9400000), 366 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 367 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 368 "ldr", "!0r, [!1X, #!2D]", kFixupNone), 369 ENCODING_MAP(FWIDE(kA64Ldr4fXxG), SIZE_VARIANTS(0xbc606800), 370 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 371 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD, 372 "ldr", "!0f, [!1X, !2x!3G]", kFixupNone), 373 ENCODING_MAP(WIDE(kA64Ldr4rXxG), SIZE_VARIANTS(0xb8606800), 374 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 375 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD, 376 "ldr", "!0r, [!1X, !2x!3G]", kFixupNone), 377 ENCODING_MAP(WIDE(kA64LdrPost3rXd), SIZE_VARIANTS(0xb8400400), 378 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 379 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF01 | REG_USE1 | IS_LOAD, 380 "ldr", "!0r, [!1X], #!2d", kFixupNone), 381 ENCODING_MAP(WIDE(kA64Ldp4ffXD), CUSTOM_VARIANTS(0x2d400000, 0x6d400000), 382 kFmtRegF, 4, 0, kFmtRegF, 14, 10, kFmtRegXOrSp, 9, 5, 383 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF01 | IS_LOAD, 384 "ldp", "!0f, !1f, [!2X, #!3D]", kFixupNone), 385 ENCODING_MAP(WIDE(kA64Ldp4rrXD), SF_VARIANTS(0x29400000), 386 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 387 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF01 | IS_LOAD, 388 "ldp", "!0r, !1r, [!2X, #!3D]", kFixupNone), 389 ENCODING_MAP(WIDE(kA64LdpPost4rrXD), CUSTOM_VARIANTS(0x28c00000, 0xa8c00000), 390 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 391 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF012 | IS_LOAD, 392 "ldp", "!0r, !1r, [!2X], #!3D", kFixupNone), 393 ENCODING_MAP(FWIDE(kA64Ldur3fXd), CUSTOM_VARIANTS(0xbc400000, 0xfc400000), 394 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 395 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 396 "ldur", "!0f, [!1X, #!2d]", kFixupNone), 397 ENCODING_MAP(WIDE(kA64Ldur3rXd), SIZE_VARIANTS(0xb8400000), 398 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 399 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 400 "ldur", "!0r, [!1X, #!2d]", kFixupNone), 401 ENCODING_MAP(WIDE(kA64Ldxr2rX), SIZE_VARIANTS(0x885f7c00), 402 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtUnused, -1, -1, 403 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1 | IS_LOAD, 404 "ldxr", "!0r, [!1X]", kFixupNone), 405 ENCODING_MAP(WIDE(kA64Ldaxr2rX), SIZE_VARIANTS(0x885ffc00), 406 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtUnused, -1, -1, 407 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1 | IS_LOAD, 408 "ldaxr", "!0r, [!1X]", kFixupNone), 409 ENCODING_MAP(WIDE(kA64Lsl3rrr), SF_VARIANTS(0x1ac02000), 410 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 411 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 412 "lsl", "!0r, !1r, !2r", kFixupNone), 413 ENCODING_MAP(WIDE(kA64Lsr3rrd), CUSTOM_VARIANTS(0x53007c00, 0xd340fc00), 414 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 415 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 416 "lsr", "!0r, !1r, #!2d", kFixupNone), 417 ENCODING_MAP(WIDE(kA64Lsr3rrr), SF_VARIANTS(0x1ac02400), 418 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 419 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 420 "lsr", "!0r, !1r, !2r", kFixupNone), 421 ENCODING_MAP(WIDE(kA64Movk3rdM), SF_VARIANTS(0x72800000), 422 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21, 423 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE0, 424 "movk", "!0r, #!1d!2M", kFixupNone), 425 ENCODING_MAP(WIDE(kA64Movn3rdM), SF_VARIANTS(0x12800000), 426 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21, 427 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0, 428 "movn", "!0r, #!1d!2M", kFixupNone), 429 ENCODING_MAP(WIDE(kA64Movz3rdM), SF_VARIANTS(0x52800000), 430 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21, 431 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0, 432 "movz", "!0r, #!1d!2M", kFixupNone), 433 ENCODING_MAP(WIDE(kA64Mov2rr), SF_VARIANTS(0x2a0003e0), 434 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtUnused, -1, -1, 435 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 436 "mov", "!0r, !1r", kFixupNone), 437 ENCODING_MAP(WIDE(kA64Mvn2rr), SF_VARIANTS(0x2a2003e0), 438 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtUnused, -1, -1, 439 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 440 "mvn", "!0r, !1r", kFixupNone), 441 ENCODING_MAP(WIDE(kA64Mul3rrr), SF_VARIANTS(0x1b007c00), 442 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 443 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 444 "mul", "!0r, !1r, !2r", kFixupNone), 445 ENCODING_MAP(WIDE(kA64Msub4rrrr), SF_VARIANTS(0x1b008000), 446 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 14, 10, 447 kFmtRegR, 20, 16, IS_QUAD_OP | REG_DEF0_USE123, 448 "msub", "!0r, !1r, !3r, !2r", kFixupNone), 449 ENCODING_MAP(WIDE(kA64Neg3rro), SF_VARIANTS(0x4b0003e0), 450 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtShift, -1, -1, 451 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 452 "neg", "!0r, !1r!2o", kFixupNone), 453 ENCODING_MAP(WIDE(kA64Orr3Rrl), SF_VARIANTS(0x32000000), 454 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10, 455 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 456 "orr", "!0R, !1r, #!2l", kFixupNone), 457 ENCODING_MAP(WIDE(kA64Orr4rrro), SF_VARIANTS(0x2a000000), 458 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 459 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 460 "orr", "!0r, !1r, !2r!3o", kFixupNone), 461 ENCODING_MAP(kA64Ret, NO_VARIANTS(0xd65f03c0), 462 kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 463 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH, 464 "ret", "", kFixupNone), 465 ENCODING_MAP(WIDE(kA64Rbit2rr), SF_VARIANTS(0x5ac00000), 466 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtUnused, -1, -1, 467 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 468 "rbit", "!0r, !1r", kFixupNone), 469 ENCODING_MAP(WIDE(kA64Rev2rr), CUSTOM_VARIANTS(0x5ac00800, 0xdac00c00), 470 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtUnused, -1, -1, 471 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 472 "rev", "!0r, !1r", kFixupNone), 473 ENCODING_MAP(WIDE(kA64Rev162rr), SF_VARIANTS(0x5ac00400), 474 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtUnused, -1, -1, 475 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 476 "rev16", "!0r, !1r", kFixupNone), 477 ENCODING_MAP(WIDE(kA64Ror3rrr), SF_VARIANTS(0x1ac02c00), 478 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 479 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 480 "ror", "!0r, !1r, !2r", kFixupNone), 481 ENCODING_MAP(WIDE(kA64Sbc3rrr), SF_VARIANTS(0x5a000000), 482 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 483 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 484 "sbc", "!0r, !1r, !2r", kFixupNone), 485 ENCODING_MAP(WIDE(kA64Sbfm4rrdd), SF_N_VARIANTS(0x13000000), 486 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 487 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE1, 488 "sbfm", "!0r, !1r, #!2d, #!3d", kFixupNone), 489 ENCODING_MAP(FWIDE(kA64Scvtf2fw), FLOAT_VARIANTS(0x1e220000), 490 kFmtRegF, 4, 0, kFmtRegW, 9, 5, kFmtUnused, -1, -1, 491 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 492 "scvtf", "!0f, !1w", kFixupNone), 493 ENCODING_MAP(FWIDE(kA64Scvtf2fx), FLOAT_VARIANTS(0x9e220000), 494 kFmtRegF, 4, 0, kFmtRegX, 9, 5, kFmtUnused, -1, -1, 495 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 496 "scvtf", "!0f, !1x", kFixupNone), 497 ENCODING_MAP(WIDE(kA64Sdiv3rrr), SF_VARIANTS(0x1ac00c00), 498 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 499 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 500 "sdiv", "!0r, !1r, !2r", kFixupNone), 501 ENCODING_MAP(WIDE(kA64Smaddl4xwwx), NO_VARIANTS(0x9b200000), 502 kFmtRegX, 4, 0, kFmtRegW, 9, 5, kFmtRegW, 20, 16, 503 kFmtRegX, 14, 10, IS_QUAD_OP | REG_DEF0_USE123, 504 "smaddl", "!0x, !1w, !2w, !3x", kFixupNone), 505 ENCODING_MAP(kA64Smulh3xxx, NO_VARIANTS(0x9b407c00), 506 kFmtRegX, 4, 0, kFmtRegX, 9, 5, kFmtRegX, 20, 16, 507 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 508 "smulh", "!0x, !1x, !2x", kFixupNone), 509 ENCODING_MAP(WIDE(kA64Stp4ffXD), CUSTOM_VARIANTS(0x2d000000, 0x6d000000), 510 kFmtRegF, 4, 0, kFmtRegF, 14, 10, kFmtRegXOrSp, 9, 5, 511 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE012 | IS_STORE, 512 "stp", "!0f, !1f, [!2X, #!3D]", kFixupNone), 513 ENCODING_MAP(WIDE(kA64Stp4rrXD), SF_VARIANTS(0x29000000), 514 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 515 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE012 | IS_STORE, 516 "stp", "!0r, !1r, [!2X, #!3D]", kFixupNone), 517 ENCODING_MAP(WIDE(kA64StpPost4rrXD), CUSTOM_VARIANTS(0x28800000, 0xa8800000), 518 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 519 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE, 520 "stp", "!0r, !1r, [!2X], #!3D", kFixupNone), 521 ENCODING_MAP(WIDE(kA64StpPre4ffXD), CUSTOM_VARIANTS(0x2d800000, 0x6d800000), 522 kFmtRegF, 4, 0, kFmtRegF, 14, 10, kFmtRegXOrSp, 9, 5, 523 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE, 524 "stp", "!0r, !1f, [!2X, #!3D]!!", kFixupNone), 525 ENCODING_MAP(WIDE(kA64StpPre4rrXD), CUSTOM_VARIANTS(0x29800000, 0xa9800000), 526 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 527 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE, 528 "stp", "!0r, !1r, [!2X, #!3D]!!", kFixupNone), 529 ENCODING_MAP(FWIDE(kA64Str3fXD), CUSTOM_VARIANTS(0xbd000000, 0xfd000000), 530 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 531 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 532 "str", "!0f, [!1X, #!2D]", kFixupNone), 533 ENCODING_MAP(FWIDE(kA64Str4fXxG), CUSTOM_VARIANTS(0xbc206800, 0xfc206800), 534 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 535 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE, 536 "str", "!0f, [!1X, !2x!3G]", kFixupNone), 537 ENCODING_MAP(WIDE(kA64Str3rXD), SIZE_VARIANTS(0xb9000000), 538 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 539 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 540 "str", "!0r, [!1X, #!2D]", kFixupNone), 541 ENCODING_MAP(WIDE(kA64Str4rXxG), SIZE_VARIANTS(0xb8206800), 542 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 543 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE, 544 "str", "!0r, [!1X, !2x!3G]", kFixupNone), 545 ENCODING_MAP(kA64Strb3wXd, NO_VARIANTS(0x39000000), 546 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 547 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 548 "strb", "!0w, [!1X, #!2d]", kFixupNone), 549 ENCODING_MAP(kA64Strb3wXx, NO_VARIANTS(0x38206800), 550 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 551 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012 | IS_STORE, 552 "strb", "!0w, [!1X, !2x]", kFixupNone), 553 ENCODING_MAP(kA64Strh3wXF, NO_VARIANTS(0x79000000), 554 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 555 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 556 "strh", "!0w, [!1X, #!2F]", kFixupNone), 557 ENCODING_MAP(kA64Strh4wXxd, NO_VARIANTS(0x78206800), 558 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 559 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE, 560 "strh", "!0w, [!1X, !2x, lsl #!3d]", kFixupNone), 561 ENCODING_MAP(WIDE(kA64StrPost3rXd), SIZE_VARIANTS(0xb8000400), 562 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 563 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | REG_DEF1 | IS_STORE, 564 "str", "!0r, [!1X], #!2d", kFixupNone), 565 ENCODING_MAP(FWIDE(kA64Stur3fXd), CUSTOM_VARIANTS(0xbc000000, 0xfc000000), 566 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 567 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 568 "stur", "!0f, [!1X, #!2d]", kFixupNone), 569 ENCODING_MAP(WIDE(kA64Stur3rXd), SIZE_VARIANTS(0xb8000000), 570 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 571 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 572 "stur", "!0r, [!1X, #!2d]", kFixupNone), 573 ENCODING_MAP(WIDE(kA64Stxr3wrX), SIZE_VARIANTS(0x88007c00), 574 kFmtRegW, 20, 16, kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, 575 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_STORE, 576 "stxr", "!0w, !1r, [!2X]", kFixupNone), 577 ENCODING_MAP(WIDE(kA64Stlxr3wrX), SIZE_VARIANTS(0x8800fc00), 578 kFmtRegW, 20, 16, kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, 579 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_STORE, 580 "stlxr", "!0w, !1r, [!2X]", kFixupNone), 581 ENCODING_MAP(WIDE(kA64Sub4RRdT), SF_VARIANTS(0x51000000), 582 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, 583 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1, 584 "sub", "!0R, !1R, #!2d!3T", kFixupNone), 585 ENCODING_MAP(WIDE(kA64Sub4rrro), SF_VARIANTS(0x4b000000), 586 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 587 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 588 "sub", "!0r, !1r, !2r!3o", kFixupNone), 589 ENCODING_MAP(WIDE(kA64Sub4RRre), SF_VARIANTS(0x4b200000), 590 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, 591 kFmtExtend, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 592 "sub", "!0r, !1r, !2r!3e", kFixupNone), 593 ENCODING_MAP(WIDE(kA64Subs3rRd), SF_VARIANTS(0x71000000), 594 kFmtRegR, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, 595 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, 596 "subs", "!0r, !1R, #!2d", kFixupNone), 597 ENCODING_MAP(WIDE(kA64Tst3rro), SF_VARIANTS(0x6a000000), 598 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1, 599 kFmtUnused, -1, -1, IS_QUAD_OP | REG_USE01 | SETS_CCODES, 600 "tst", "!0r, !1r!2o", kFixupNone), 601 ENCODING_MAP(WIDE(kA64Ubfm4rrdd), SF_N_VARIANTS(0x53000000), 602 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 603 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE1, 604 "ubfm", "!0r, !1r, !2d, !3d", kFixupNone), 605}; 606 607// new_lir replaces orig_lir in the pcrel_fixup list. 608void Arm64Mir2Lir::ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { 609 new_lir->u.a.pcrel_next = orig_lir->u.a.pcrel_next; 610 if (UNLIKELY(prev_lir == NULL)) { 611 first_fixup_ = new_lir; 612 } else { 613 prev_lir->u.a.pcrel_next = new_lir; 614 } 615 orig_lir->flags.fixup = kFixupNone; 616} 617 618// new_lir is inserted before orig_lir in the pcrel_fixup list. 619void Arm64Mir2Lir::InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { 620 new_lir->u.a.pcrel_next = orig_lir; 621 if (UNLIKELY(prev_lir == NULL)) { 622 first_fixup_ = new_lir; 623 } else { 624 DCHECK(prev_lir->u.a.pcrel_next == orig_lir); 625 prev_lir->u.a.pcrel_next = new_lir; 626 } 627} 628 629/* Nop, used for aligning code. Nop is an alias for hint #0. */ 630#define PADDING_NOP (UINT32_C(0xd503201f)) 631 632uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { 633 for (; lir != nullptr; lir = NEXT_LIR(lir)) { 634 bool opcode_is_wide = IS_WIDE(lir->opcode); 635 ArmOpcode opcode = UNWIDE(lir->opcode); 636 637 if (UNLIKELY(IsPseudoLirOp(opcode))) { 638 continue; 639 } 640 641 if (LIKELY(!lir->flags.is_nop)) { 642 const ArmEncodingMap *encoder = &EncodingMap[opcode]; 643 644 // Select the right variant of the skeleton. 645 uint32_t bits = opcode_is_wide ? encoder->xskeleton : encoder->wskeleton; 646 DCHECK(!opcode_is_wide || IS_WIDE(encoder->opcode)); 647 648 for (int i = 0; i < 4; i++) { 649 ArmEncodingKind kind = encoder->field_loc[i].kind; 650 uint32_t operand = lir->operands[i]; 651 uint32_t value; 652 653 if (LIKELY(static_cast<unsigned>(kind) <= kFmtBitBlt)) { 654 // Note: this will handle kFmtReg* and kFmtBitBlt. 655 656 if (static_cast<unsigned>(kind) < kFmtBitBlt) { 657 bool is_zero = A64_REG_IS_ZR(operand); 658 659 if (kIsDebugBuild && (kFailOnSizeError || kReportSizeError)) { 660 // Register usage checks: First establish register usage requirements based on the 661 // format in `kind'. 662 bool want_float = false; // Want a float (rather than core) register. 663 bool want_64_bit = false; // Want a 64-bit (rather than 32-bit) register. 664 bool want_var_size = true; // Want register with variable size (kFmtReg{R,F}). 665 bool want_zero = false; // Want the zero (rather than sp) register. 666 switch (kind) { 667 case kFmtRegX: 668 want_64_bit = true; 669 // Intentional fall-through. 670 case kFmtRegW: 671 want_var_size = false; 672 // Intentional fall-through. 673 case kFmtRegR: 674 want_zero = true; 675 break; 676 case kFmtRegXOrSp: 677 want_64_bit = true; 678 // Intentional fall-through. 679 case kFmtRegWOrSp: 680 want_var_size = false; 681 break; 682 case kFmtRegROrSp: 683 break; 684 case kFmtRegD: 685 want_64_bit = true; 686 // Intentional fall-through. 687 case kFmtRegS: 688 want_var_size = false; 689 // Intentional fall-through. 690 case kFmtRegF: 691 want_float = true; 692 break; 693 default: 694 LOG(FATAL) << "Bad fmt for arg n. " << i << " of " << encoder->name 695 << " (" << kind << ")"; 696 break; 697 } 698 699 // want_var_size == true means kind == kFmtReg{R,F}. In these two cases, we want 700 // the register size to be coherent with the instruction width. 701 if (want_var_size) { 702 want_64_bit = opcode_is_wide; 703 } 704 705 // Now check that the requirements are satisfied. 706 RegStorage reg(operand | RegStorage::kValid); 707 const char *expected = nullptr; 708 if (want_float) { 709 if (!reg.IsFloat()) { 710 expected = "float register"; 711 } else if (reg.IsDouble() != want_64_bit) { 712 expected = (want_64_bit) ? "double register" : "single register"; 713 } 714 } else { 715 if (reg.IsFloat()) { 716 expected = "core register"; 717 } else if (reg.Is64Bit() != want_64_bit) { 718 expected = (want_64_bit) ? "x-register" : "w-register"; 719 } else if (A64_REGSTORAGE_IS_SP_OR_ZR(reg) && is_zero != want_zero) { 720 expected = (want_zero) ? "zero-register" : "sp-register"; 721 } 722 } 723 724 // Fail, if `expected' contains an unsatisfied requirement. 725 if (expected != nullptr) { 726 LOG(WARNING) << "Method: " << PrettyMethod(cu_->method_idx, *cu_->dex_file) 727 << " @ 0x" << std::hex << lir->dalvik_offset; 728 if (kFailOnSizeError) { 729 LOG(FATAL) << "Bad argument n. " << i << " of " << encoder->name 730 << "(" << UNWIDE(encoder->opcode) << ", " << encoder->fmt << ")" 731 << ". Expected " << expected << ", got 0x" << std::hex << operand; 732 } else { 733 LOG(WARNING) << "Bad argument n. " << i << " of " << encoder->name 734 << ". Expected " << expected << ", got 0x" << std::hex << operand; 735 } 736 } 737 } 738 739 // In the lines below, we rely on (operand & 0x1f) == 31 to be true for register sp 740 // and zr. This means that these two registers do not need any special treatment, as 741 // their bottom 5 bits are correctly set to 31 == 0b11111, which is the right 742 // value for encoding both sp and zr. 743 COMPILE_ASSERT((rxzr & 0x1f) == 0x1f, rzr_register_number_must_be_31); 744 COMPILE_ASSERT((rsp & 0x1f) == 0x1f, rsp_register_number_must_be_31); 745 } 746 747 value = (operand << encoder->field_loc[i].start) & 748 ((1 << (encoder->field_loc[i].end + 1)) - 1); 749 bits |= value; 750 } else { 751 switch (kind) { 752 case kFmtSkip: 753 break; // Nothing to do, but continue to next. 754 case kFmtUnused: 755 i = 4; // Done, break out of the enclosing loop. 756 break; 757 case kFmtShift: 758 // Intentional fallthrough. 759 case kFmtExtend: 760 DCHECK_EQ((operand & (1 << 6)) == 0, kind == kFmtShift); 761 value = (operand & 0x3f) << 10; 762 value |= ((operand & 0x1c0) >> 6) << 21; 763 bits |= value; 764 break; 765 case kFmtImm21: 766 value = (operand & 0x3) << 29; 767 value |= ((operand & 0x1ffffc) >> 2) << 5; 768 bits |= value; 769 break; 770 default: 771 LOG(FATAL) << "Bad fmt for arg. " << i << " in " << encoder->name 772 << " (" << kind << ")"; 773 } 774 } 775 } 776 777 DCHECK_EQ(encoder->size, 4); 778 write_pos[0] = (bits & 0xff); 779 write_pos[1] = ((bits >> 8) & 0xff); 780 write_pos[2] = ((bits >> 16) & 0xff); 781 write_pos[3] = ((bits >> 24) & 0xff); 782 write_pos += 4; 783 } 784 } 785 786 return write_pos; 787} 788 789// Align data offset on 8 byte boundary: it will only contain double-word items, as word immediates 790// are better set directly from the code (they will require no more than 2 instructions). 791#define ALIGNED_DATA_OFFSET(offset) (((offset) + 0x7) & ~0x7) 792 793// Assemble the LIR into binary instruction format. 794void Arm64Mir2Lir::AssembleLIR() { 795 LIR* lir; 796 LIR* prev_lir; 797 cu_->NewTimingSplit("Assemble"); 798 int assembler_retries = 0; 799 CodeOffset starting_offset = LinkFixupInsns(first_lir_insn_, last_lir_insn_, 0); 800 data_offset_ = ALIGNED_DATA_OFFSET(starting_offset); 801 int32_t offset_adjustment; 802 AssignDataOffsets(); 803 804 /* 805 * Note: generation must be 1 on first pass (to distinguish from initialized state of 0 806 * for non-visited nodes). Start at zero here, and bit will be flipped to 1 on entry to the loop. 807 */ 808 int generation = 0; 809 while (true) { 810 // TODO(Arm64): check whether passes and offset adjustments are really necessary. 811 // Currently they aren't, as - in the fixups below - LIR are never inserted. 812 // Things can be different if jump ranges above 1 MB need to be supported. 813 // If they are not, then we can get rid of the assembler retry logic. 814 815 offset_adjustment = 0; 816 AssemblerStatus res = kSuccess; // Assume success 817 generation ^= 1; 818 // Note: nodes requiring possible fixup linked in ascending order. 819 lir = first_fixup_; 820 prev_lir = NULL; 821 while (lir != NULL) { 822 /* 823 * NOTE: the lir being considered here will be encoded following the switch (so long as 824 * we're not in a retry situation). However, any new non-pc_rel instructions inserted 825 * due to retry must be explicitly encoded at the time of insertion. Note that 826 * inserted instructions don't need use/def flags, but do need size and pc-rel status 827 * properly updated. 828 */ 829 lir->offset += offset_adjustment; 830 // During pass, allows us to tell whether a node has been updated with offset_adjustment yet. 831 lir->flags.generation = generation; 832 switch (static_cast<FixupKind>(lir->flags.fixup)) { 833 case kFixupLabel: 834 case kFixupNone: 835 case kFixupVLoad: 836 break; 837 case kFixupT1Branch: { 838 LIR *target_lir = lir->target; 839 DCHECK(target_lir); 840 CodeOffset pc = lir->offset; 841 CodeOffset target = target_lir->offset + 842 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment); 843 int32_t delta = target - pc; 844 if (!((delta & 0x3) == 0 && IS_SIGNED_IMM19(delta >> 2))) { 845 LOG(FATAL) << "Invalid jump range in kFixupT1Branch"; 846 } 847 lir->operands[0] = delta >> 2; 848 break; 849 } 850 case kFixupLoad: 851 case kFixupCBxZ: 852 case kFixupCondBranch: { 853 LIR *target_lir = lir->target; 854 DCHECK(target_lir); 855 CodeOffset pc = lir->offset; 856 CodeOffset target = target_lir->offset + 857 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment); 858 int32_t delta = target - pc; 859 if (!((delta & 0x3) == 0 && IS_SIGNED_IMM19(delta >> 2))) { 860 LOG(FATAL) << "Invalid jump range in kFixupLoad"; 861 } 862 lir->operands[1] = delta >> 2; 863 break; 864 } 865 case kFixupAdr: { 866 LIR* target_lir = lir->target; 867 int32_t delta; 868 if (target_lir) { 869 CodeOffset target_offs = ((target_lir->flags.generation == lir->flags.generation) ? 870 0 : offset_adjustment) + target_lir->offset; 871 delta = target_offs - lir->offset; 872 } else if (lir->operands[2] >= 0) { 873 EmbeddedData* tab = reinterpret_cast<EmbeddedData*>(UnwrapPointer(lir->operands[2])); 874 delta = tab->offset + offset_adjustment - lir->offset; 875 } else { 876 // No fixup: this usage allows to retrieve the current PC. 877 delta = lir->operands[1]; 878 } 879 if (!IS_SIGNED_IMM21(delta)) { 880 LOG(FATAL) << "Jump range above 1MB in kFixupAdr"; 881 } 882 lir->operands[1] = delta; 883 break; 884 } 885 default: 886 LOG(FATAL) << "Unexpected case " << lir->flags.fixup; 887 } 888 prev_lir = lir; 889 lir = lir->u.a.pcrel_next; 890 } 891 892 if (res == kSuccess) { 893 break; 894 } else { 895 assembler_retries++; 896 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 897 CodegenDump(); 898 LOG(FATAL) << "Assembler error - too many retries"; 899 } 900 starting_offset += offset_adjustment; 901 data_offset_ = ALIGNED_DATA_OFFSET(starting_offset); 902 AssignDataOffsets(); 903 } 904 } 905 906 // Build the CodeBuffer. 907 DCHECK_LE(data_offset_, total_size_); 908 code_buffer_.reserve(total_size_); 909 code_buffer_.resize(starting_offset); 910 uint8_t* write_pos = &code_buffer_[0]; 911 write_pos = EncodeLIRs(write_pos, first_lir_insn_); 912 DCHECK_EQ(static_cast<CodeOffset>(write_pos - &code_buffer_[0]), starting_offset); 913 914 DCHECK_EQ(data_offset_, ALIGNED_DATA_OFFSET(code_buffer_.size())); 915 916 // Install literals 917 InstallLiteralPools(); 918 919 // Install switch tables 920 InstallSwitchTables(); 921 922 // Install fill array data 923 InstallFillArrayData(); 924 925 // Create the mapping table and native offset to reference map. 926 cu_->NewTimingSplit("PcMappingTable"); 927 CreateMappingTables(); 928 929 cu_->NewTimingSplit("GcMap"); 930 CreateNativeGcMap(); 931} 932 933size_t Arm64Mir2Lir::GetInsnSize(LIR* lir) { 934 ArmOpcode opcode = UNWIDE(lir->opcode); 935 DCHECK(!IsPseudoLirOp(opcode)); 936 return EncodingMap[opcode].size; 937} 938 939// Encode instruction bit pattern and assign offsets. 940uint32_t Arm64Mir2Lir::LinkFixupInsns(LIR* head_lir, LIR* tail_lir, uint32_t offset) { 941 LIR* end_lir = tail_lir->next; 942 943 LIR* last_fixup = NULL; 944 for (LIR* lir = head_lir; lir != end_lir; lir = NEXT_LIR(lir)) { 945 ArmOpcode opcode = UNWIDE(lir->opcode); 946 if (!lir->flags.is_nop) { 947 if (lir->flags.fixup != kFixupNone) { 948 if (!IsPseudoLirOp(opcode)) { 949 lir->flags.size = EncodingMap[opcode].size; 950 lir->flags.fixup = EncodingMap[opcode].fixup; 951 } else { 952 DCHECK_NE(static_cast<int>(opcode), kPseudoPseudoAlign4); 953 lir->flags.size = 0; 954 lir->flags.fixup = kFixupLabel; 955 } 956 // Link into the fixup chain. 957 lir->flags.use_def_invalid = true; 958 lir->u.a.pcrel_next = NULL; 959 if (first_fixup_ == NULL) { 960 first_fixup_ = lir; 961 } else { 962 last_fixup->u.a.pcrel_next = lir; 963 } 964 last_fixup = lir; 965 lir->offset = offset; 966 } 967 offset += lir->flags.size; 968 } 969 } 970 return offset; 971} 972 973void Arm64Mir2Lir::AssignDataOffsets() { 974 /* Set up offsets for literals */ 975 CodeOffset offset = data_offset_; 976 977 offset = AssignLiteralOffset(offset); 978 979 offset = AssignSwitchTablesOffset(offset); 980 981 total_size_ = AssignFillArrayDataOffset(offset); 982} 983 984} // namespace art 985