codegen_arm64.h revision 147eb41b53729ec8d5c188d1cac90964a51afb8a
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 18#define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 19 20#include "arm64_lir.h" 21#include "dex/compiler_internals.h" 22 23#include <map> 24 25namespace art { 26 27class Arm64Mir2Lir FINAL : public Mir2Lir { 28 protected: 29 // TODO: consolidate 64-bit target support. 30 class InToRegStorageMapper { 31 public: 32 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 33 virtual ~InToRegStorageMapper() {} 34 }; 35 36 class InToRegStorageArm64Mapper : public InToRegStorageMapper { 37 public: 38 InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} 39 virtual ~InToRegStorageArm64Mapper() {} 40 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 41 private: 42 int cur_core_reg_; 43 int cur_fp_reg_; 44 }; 45 46 class InToRegStorageMapping { 47 public: 48 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 49 initialized_(false) {} 50 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 51 int GetMaxMappedIn() { return max_mapped_in_; } 52 bool IsThereStackMapped() { return is_there_stack_mapped_; } 53 RegStorage Get(int in_position); 54 bool IsInitialized() { return initialized_; } 55 private: 56 std::map<int, RegStorage> mapping_; 57 int max_mapped_in_; 58 bool is_there_stack_mapped_; 59 bool initialized_; 60 }; 61 62 public: 63 Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 64 65 // Required for target - codegen helpers. 66 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 67 RegLocation rl_dest, int lit) OVERRIDE; 68 bool SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 69 RegLocation rl_dest, int64_t lit); 70 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 71 RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 72 bool HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div, 73 RegLocation rl_src, RegLocation rl_dest, int64_t lit); 74 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 75 LIR* CheckSuspendUsingLoad() OVERRIDE; 76 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 77 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 78 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 79 OpSize size, VolatileKind is_volatile) OVERRIDE; 80 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, 81 VolatileKind is_volatile) 82 OVERRIDE; 83 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 84 OpSize size) OVERRIDE; 85 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) 86 OVERRIDE; 87 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 88 RegStorage r_dest, OpSize size) OVERRIDE; 89 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 90 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 91 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 92 OpSize size, VolatileKind is_volatile) OVERRIDE; 93 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, 94 VolatileKind is_volatile) OVERRIDE; 95 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 96 OpSize size) OVERRIDE; 97 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) 98 OVERRIDE; 99 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 100 RegStorage r_src, OpSize size) OVERRIDE; 101 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; 102 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 103 int offset, int check_value, LIR* target, LIR** compare) OVERRIDE; 104 105 // Required for target - register utilities. 106 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 107 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 108 RegStorage reg = TargetReg(symbolic_reg); 109 if (wide_kind == kWide || wide_kind == kRef) { 110 return (reg.Is64Bit()) ? reg : As64BitReg(reg); 111 } else { 112 return (reg.Is32Bit()) ? reg : As32BitReg(reg); 113 } 114 } 115 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 116 RegStorage reg = TargetReg(symbolic_reg); 117 return (reg.Is64Bit() ? reg : As64BitReg(reg)); 118 } 119 RegStorage GetArgMappingToPhysicalReg(int arg_num); 120 RegLocation GetReturnAlt(); 121 RegLocation GetReturnWideAlt(); 122 RegLocation LocCReturn(); 123 RegLocation LocCReturnRef(); 124 RegLocation LocCReturnDouble(); 125 RegLocation LocCReturnFloat(); 126 RegLocation LocCReturnWide(); 127 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 128 void AdjustSpillMask(); 129 void ClobberCallerSave(); 130 void FreeCallTemps(); 131 void LockCallTemps(); 132 void CompilerInitializeRegAlloc(); 133 134 // Required for target - miscellaneous. 135 void AssembleLIR(); 136 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); 137 int AssignInsnOffsets(); 138 void AssignOffsets(); 139 uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); 140 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 141 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 142 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 143 const char* GetTargetInstFmt(int opcode); 144 const char* GetTargetInstName(int opcode); 145 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 146 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 147 uint64_t GetTargetInstFlags(int opcode); 148 size_t GetInsnSize(LIR* lir) OVERRIDE; 149 bool IsUnconditionalBranch(LIR* lir); 150 151 // Check support for volatile load/store of a given size. 152 bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; 153 // Get the register class for load/store of a field. 154 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 155 156 // Required for target - Dalvik-level generators. 157 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 158 RegLocation lr_shift); 159 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 160 RegLocation rl_src1, RegLocation rl_src2); 161 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 162 RegLocation rl_index, RegLocation rl_dest, int scale); 163 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 164 RegLocation rl_src, int scale, bool card_mark); 165 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 166 RegLocation rl_src1, RegLocation rl_shift); 167 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 168 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 169 RegLocation rl_src2); 170 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 171 RegLocation rl_src2); 172 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 173 RegLocation rl_src2); 174 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 175 RegLocation rl_src2); 176 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 177 RegLocation rl_src2); 178 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 179 RegLocation rl_src2); 180 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 181 bool GenInlinedReverseBits(CallInfo* info, OpSize size); 182 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 183 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 184 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 185 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double); 186 bool GenInlinedSqrt(CallInfo* info); 187 bool GenInlinedPeek(CallInfo* info, OpSize size); 188 bool GenInlinedPoke(CallInfo* info, OpSize size); 189 bool GenInlinedAbsLong(CallInfo* info); 190 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 191 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 192 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 193 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 194 RegLocation rl_src2); 195 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 196 RegLocation rl_src2); 197 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 198 RegLocation rl_src2); 199 void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 200 RegLocation rl_src2, bool is_div); 201 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 202 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 203 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 204 void GenDivZeroCheckWide(RegStorage reg); 205 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 206 void GenExitSequence(); 207 void GenSpecialExitSequence(); 208 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 209 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 210 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 211 void GenSelect(BasicBlock* bb, MIR* mir); 212 bool GenMemBarrier(MemBarrierKind barrier_kind); 213 void GenMonitorEnter(int opt_flags, RegLocation rl_src); 214 void GenMonitorExit(int opt_flags, RegLocation rl_src); 215 void GenMoveException(RegLocation rl_dest); 216 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 217 int first_bit, int second_bit); 218 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 219 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 220 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 221 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 222 223 uint32_t GenPairWise(uint32_t reg_mask, int* reg1, int* reg2); 224 void UnSpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); 225 void SpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); 226 void UnSpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); 227 void SpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); 228 229 // Required for target - single operation generators. 230 LIR* OpUnconditionalBranch(LIR* target); 231 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 232 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 233 LIR* OpCondBranch(ConditionCode cc, LIR* target); 234 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 235 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 236 LIR* OpIT(ConditionCode cond, const char* guide); 237 void OpEndIT(LIR* it); 238 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 239 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 240 LIR* OpReg(OpKind op, RegStorage r_dest_src); 241 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 242 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 243 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value); 244 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 245 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 246 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 247 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 248 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 249 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 250 LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value); 251 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 252 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 253 LIR* OpTestSuspend(LIR* target); 254 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 255 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 256 LIR* OpVldm(RegStorage r_base, int count); 257 LIR* OpVstm(RegStorage r_base, int count); 258 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 259 void OpRegCopyWide(RegStorage dest, RegStorage src); 260 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 261 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 262 263 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); 264 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 265 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 266 int shift); 267 LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 268 A64RegExtEncodings ext, uint8_t amount); 269 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 270 LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 271 static const ArmEncodingMap EncodingMap[kA64Last]; 272 int EncodeShift(int code, int amount); 273 int EncodeExtend(int extend_type, int amount); 274 bool IsExtendEncoding(int encoded_value); 275 int EncodeLogicalImmediate(bool is_wide, uint64_t value); 276 uint64_t DecodeLogicalImmediate(bool is_wide, int value); 277 278 ArmConditionCode ArmConditionEncoding(ConditionCode code); 279 bool InexpensiveConstantInt(int32_t value); 280 bool InexpensiveConstantFloat(int32_t value); 281 bool InexpensiveConstantLong(int64_t value); 282 bool InexpensiveConstantDouble(int64_t value); 283 284 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 285 286 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 287 NextCallInsn next_call_insn, 288 const MethodReference& target_method, 289 uint32_t vtable_idx, 290 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 291 bool skip_this); 292 293 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 294 NextCallInsn next_call_insn, 295 const MethodReference& target_method, 296 uint32_t vtable_idx, 297 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 298 bool skip_this); 299 InToRegStorageMapping in_to_reg_storage_mapping_; 300 301 bool WideGPRsAreAliases() OVERRIDE { 302 return true; // 64b architecture. 303 } 304 bool WideFPRsAreAliases() OVERRIDE { 305 return true; // 64b architecture. 306 } 307 308 private: 309 /** 310 * @brief Given register xNN (dNN), returns register wNN (sNN). 311 * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2). 312 * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2). 313 * @see As64BitReg 314 */ 315 RegStorage As32BitReg(RegStorage reg) { 316 DCHECK(!reg.IsPair()); 317 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 318 if (kFailOnSizeError) { 319 LOG(FATAL) << "Expected 64b register"; 320 } else { 321 LOG(WARNING) << "Expected 64b register"; 322 return reg; 323 } 324 } 325 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 326 reg.GetRawBits() & RegStorage::kRegTypeMask); 327 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 328 ->GetReg().GetReg(), 329 ret_val.GetReg()); 330 return ret_val; 331 } 332 333 RegStorage Check32BitReg(RegStorage reg) { 334 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 335 if (kFailOnSizeError) { 336 LOG(FATAL) << "Checked for 32b register"; 337 } else { 338 LOG(WARNING) << "Checked for 32b register"; 339 return As32BitReg(reg); 340 } 341 } 342 return reg; 343 } 344 345 /** 346 * @brief Given register wNN (sNN), returns register xNN (dNN). 347 * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2). 348 * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2). 349 * @see As32BitReg 350 */ 351 RegStorage As64BitReg(RegStorage reg) { 352 DCHECK(!reg.IsPair()); 353 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 354 if (kFailOnSizeError) { 355 LOG(FATAL) << "Expected 32b register"; 356 } else { 357 LOG(WARNING) << "Expected 32b register"; 358 return reg; 359 } 360 } 361 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 362 reg.GetRawBits() & RegStorage::kRegTypeMask); 363 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 364 ->GetReg().GetReg(), 365 ret_val.GetReg()); 366 return ret_val; 367 } 368 369 RegStorage Check64BitReg(RegStorage reg) { 370 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 371 if (kFailOnSizeError) { 372 LOG(FATAL) << "Checked for 64b register"; 373 } else { 374 LOG(WARNING) << "Checked for 64b register"; 375 return As64BitReg(reg); 376 } 377 } 378 return reg; 379 } 380 381 LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value); 382 LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value); 383 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 384 void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 385 void AssignDataOffsets(); 386 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 387 bool is_div, bool check_zero); 388 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); 389}; 390 391} // namespace art 392 393#endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 394