codegen_arm64.h revision 2eba1fa7e9e5f91e18ae3778d529520bd2c78d55
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 18#define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 19 20#include "arm64_lir.h" 21#include "dex/compiler_internals.h" 22 23#include <map> 24 25namespace art { 26 27class Arm64Mir2Lir FINAL : public Mir2Lir { 28 protected: 29 // TODO: consolidate 64-bit target support. 30 class InToRegStorageMapper { 31 public: 32 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 33 virtual ~InToRegStorageMapper() {} 34 }; 35 36 class InToRegStorageArm64Mapper : public InToRegStorageMapper { 37 public: 38 InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} 39 virtual ~InToRegStorageArm64Mapper() {} 40 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 41 private: 42 int cur_core_reg_; 43 int cur_fp_reg_; 44 }; 45 46 class InToRegStorageMapping { 47 public: 48 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 49 initialized_(false) {} 50 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 51 int GetMaxMappedIn() { return max_mapped_in_; } 52 bool IsThereStackMapped() { return is_there_stack_mapped_; } 53 RegStorage Get(int in_position); 54 bool IsInitialized() { return initialized_; } 55 private: 56 std::map<int, RegStorage> mapping_; 57 int max_mapped_in_; 58 bool is_there_stack_mapped_; 59 bool initialized_; 60 }; 61 62 public: 63 Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 64 65 // Required for target - codegen helpers. 66 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 67 RegLocation rl_dest, int lit) OVERRIDE; 68 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 69 RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 70 bool HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div, 71 RegLocation rl_src, RegLocation rl_dest, int64_t lit); 72 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 73 LIR* CheckSuspendUsingLoad() OVERRIDE; 74 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; 75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 76 OpSize size, VolatileKind is_volatile) OVERRIDE; 77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, 78 VolatileKind is_volatile) OVERRIDE; 79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 80 OpSize size) OVERRIDE; 81 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) 82 OVERRIDE; 83 LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE; 84 LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE; 85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, 86 VolatileKind is_volatile) OVERRIDE; 87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile) 88 OVERRIDE; 89 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 90 OpSize size) OVERRIDE; 91 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE; 92 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; 93 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 94 int offset, int check_value, LIR* target, LIR** compare) OVERRIDE; 95 96 // Required for target - register utilities. 97 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 98 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 99 if (wide_kind == kWide || wide_kind == kRef) { 100 return As64BitReg(TargetReg(symbolic_reg)); 101 } else { 102 return Check32BitReg(TargetReg(symbolic_reg)); 103 } 104 } 105 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 106 return As64BitReg(TargetReg(symbolic_reg)); 107 } 108 RegStorage GetArgMappingToPhysicalReg(int arg_num) OVERRIDE; 109 RegLocation GetReturnAlt() OVERRIDE; 110 RegLocation GetReturnWideAlt() OVERRIDE; 111 RegLocation LocCReturn() OVERRIDE; 112 RegLocation LocCReturnRef() OVERRIDE; 113 RegLocation LocCReturnDouble() OVERRIDE; 114 RegLocation LocCReturnFloat() OVERRIDE; 115 RegLocation LocCReturnWide() OVERRIDE; 116 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 117 void AdjustSpillMask() OVERRIDE; 118 void ClobberCallerSave() OVERRIDE; 119 void FreeCallTemps() OVERRIDE; 120 void LockCallTemps() OVERRIDE; 121 void CompilerInitializeRegAlloc() OVERRIDE; 122 123 // Required for target - miscellaneous. 124 void AssembleLIR() OVERRIDE; 125 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 126 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 127 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 128 const char* GetTargetInstFmt(int opcode) OVERRIDE; 129 const char* GetTargetInstName(int opcode) OVERRIDE; 130 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE; 131 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 132 uint64_t GetTargetInstFlags(int opcode) OVERRIDE; 133 size_t GetInsnSize(LIR* lir) OVERRIDE; 134 bool IsUnconditionalBranch(LIR* lir) OVERRIDE; 135 136 // Get the register class for load/store of a field. 137 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 138 139 // Required for target - Dalvik-level generators. 140 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 141 RegLocation lr_shift) OVERRIDE; 142 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 143 RegLocation rl_src2) OVERRIDE; 144 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 145 RegLocation rl_dest, int scale) OVERRIDE; 146 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 147 RegLocation rl_src, int scale, bool card_mark) OVERRIDE; 148 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 149 RegLocation rl_shift) OVERRIDE; 150 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 151 RegLocation rl_src2) OVERRIDE; 152 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 153 RegLocation rl_src2) OVERRIDE; 154 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 155 RegLocation rl_src2) OVERRIDE; 156 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 157 RegLocation rl_src2) OVERRIDE; 158 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 159 RegLocation rl_src2) OVERRIDE; 160 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 161 RegLocation rl_src2) OVERRIDE; 162 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 163 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE; 164 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 165 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 166 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE; 167 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE; 168 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE; 169 bool GenInlinedSqrt(CallInfo* info) OVERRIDE; 170 bool GenInlinedCeil(CallInfo* info) OVERRIDE; 171 bool GenInlinedFloor(CallInfo* info) OVERRIDE; 172 bool GenInlinedRint(CallInfo* info) OVERRIDE; 173 bool GenInlinedRound(CallInfo* info, bool is_double) OVERRIDE; 174 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE; 175 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE; 176 bool GenInlinedAbsLong(CallInfo* info) OVERRIDE; 177 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 178 void GenNotLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 179 void GenNegLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 180 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 181 RegLocation rl_src2) OVERRIDE; 182 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 183 RegLocation rl_src2) OVERRIDE; 184 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 185 RegLocation rl_src2) OVERRIDE; 186 void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 187 RegLocation rl_src2, bool is_div) OVERRIDE; 188 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div) 189 OVERRIDE; 190 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) 191 OVERRIDE; 192 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE; 193 void GenDivZeroCheckWide(RegStorage reg) OVERRIDE; 194 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; 195 void GenExitSequence() OVERRIDE; 196 void GenSpecialExitSequence() OVERRIDE; 197 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) OVERRIDE; 198 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; 199 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; 200 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; 201 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 202 int32_t true_val, int32_t false_val, RegStorage rs_dest, 203 int dest_reg_class) OVERRIDE; 204 205 bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE; 206 void GenMonitorEnter(int opt_flags, RegLocation rl_src) OVERRIDE; 207 void GenMonitorExit(int opt_flags, RegLocation rl_src) OVERRIDE; 208 void GenMoveException(RegLocation rl_dest) OVERRIDE; 209 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 210 int first_bit, int second_bit) OVERRIDE; 211 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 212 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 213 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 214 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 215 216 // Required for target - single operation generators. 217 LIR* OpUnconditionalBranch(LIR* target) OVERRIDE; 218 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE; 219 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE; 220 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE; 221 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE; 222 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 223 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE; 224 void OpEndIT(LIR* it) OVERRIDE; 225 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; 226 LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE; 227 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE; 228 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 229 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; 230 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE; 231 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE; 232 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; 233 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; 234 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; 235 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE; 236 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE; 237 LIR* OpTestSuspend(LIR* target) OVERRIDE; 238 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; 239 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; 240 void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE; 241 242 bool InexpensiveConstantInt(int32_t value) OVERRIDE; 243 bool InexpensiveConstantFloat(int32_t value) OVERRIDE; 244 bool InexpensiveConstantLong(int64_t value) OVERRIDE; 245 bool InexpensiveConstantDouble(int64_t value) OVERRIDE; 246 247 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; 248 249 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 250 NextCallInsn next_call_insn, 251 const MethodReference& target_method, 252 uint32_t vtable_idx, 253 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 254 bool skip_this) OVERRIDE; 255 256 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 257 NextCallInsn next_call_insn, 258 const MethodReference& target_method, 259 uint32_t vtable_idx, 260 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 261 bool skip_this) OVERRIDE; 262 263 bool WideGPRsAreAliases() OVERRIDE { 264 return true; // 64b architecture. 265 } 266 bool WideFPRsAreAliases() OVERRIDE { 267 return true; // 64b architecture. 268 } 269 270 size_t GetInstructionOffset(LIR* lir) OVERRIDE; 271 272 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; 273 274 private: 275 /** 276 * @brief Given register xNN (dNN), returns register wNN (sNN). 277 * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2). 278 * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2). 279 * @see As64BitReg 280 */ 281 RegStorage As32BitReg(RegStorage reg) { 282 DCHECK(!reg.IsPair()); 283 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 284 if (kFailOnSizeError) { 285 LOG(FATAL) << "Expected 64b register"; 286 } else { 287 LOG(WARNING) << "Expected 64b register"; 288 return reg; 289 } 290 } 291 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 292 reg.GetRawBits() & RegStorage::kRegTypeMask); 293 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 294 ->GetReg().GetReg(), 295 ret_val.GetReg()); 296 return ret_val; 297 } 298 299 RegStorage Check32BitReg(RegStorage reg) { 300 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 301 if (kFailOnSizeError) { 302 LOG(FATAL) << "Checked for 32b register"; 303 } else { 304 LOG(WARNING) << "Checked for 32b register"; 305 return As32BitReg(reg); 306 } 307 } 308 return reg; 309 } 310 311 /** 312 * @brief Given register wNN (sNN), returns register xNN (dNN). 313 * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2). 314 * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2). 315 * @see As32BitReg 316 */ 317 RegStorage As64BitReg(RegStorage reg) { 318 DCHECK(!reg.IsPair()); 319 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 320 if (kFailOnSizeError) { 321 LOG(FATAL) << "Expected 32b register"; 322 } else { 323 LOG(WARNING) << "Expected 32b register"; 324 return reg; 325 } 326 } 327 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 328 reg.GetRawBits() & RegStorage::kRegTypeMask); 329 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 330 ->GetReg().GetReg(), 331 ret_val.GetReg()); 332 return ret_val; 333 } 334 335 RegStorage Check64BitReg(RegStorage reg) { 336 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 337 if (kFailOnSizeError) { 338 LOG(FATAL) << "Checked for 64b register"; 339 } else { 340 LOG(WARNING) << "Checked for 64b register"; 341 return As64BitReg(reg); 342 } 343 } 344 return reg; 345 } 346 347 int32_t EncodeImmSingle(uint32_t bits); 348 int32_t EncodeImmDouble(uint64_t bits); 349 LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value); 350 LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value); 351 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 352 void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 353 void AssignDataOffsets(); 354 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 355 bool is_div, bool check_zero); 356 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); 357 size_t GetLoadStoreSize(LIR* lir); 358 359 bool SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 360 RegLocation rl_dest, int64_t lit); 361 362 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); 363 int AssignInsnOffsets(); 364 void AssignOffsets(); 365 uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); 366 367 // Spill core and FP registers. Returns the SP difference: either spill size, or whole 368 // frame size. 369 int SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size); 370 371 // Unspill core and FP registers. 372 void UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size); 373 374 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 375 376 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value); 377 LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value); 378 379 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 380 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 381 int shift); 382 int EncodeShift(int code, int amount); 383 384 LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, 385 A64RegExtEncodings ext, uint8_t amount); 386 LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 387 A64RegExtEncodings ext, uint8_t amount); 388 int EncodeExtend(int extend_type, int amount); 389 bool IsExtendEncoding(int encoded_value); 390 391 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); 392 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 393 394 int EncodeLogicalImmediate(bool is_wide, uint64_t value); 395 uint64_t DecodeLogicalImmediate(bool is_wide, int value); 396 ArmConditionCode ArmConditionEncoding(ConditionCode code); 397 398 // Helper used in the two GenSelect variants. 399 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest, 400 int result_reg_class); 401 402 InToRegStorageMapping in_to_reg_storage_mapping_; 403 static const ArmEncodingMap EncodingMap[kA64Last]; 404}; 405 406} // namespace art 407 408#endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 409