codegen_arm64.h revision c32447bcc8c36ee8ff265ed678c7df86936a9ebe
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 18#define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 19 20#include "arm64_lir.h" 21#include "dex/compiler_internals.h" 22 23#include <map> 24 25namespace art { 26 27class Arm64Mir2Lir FINAL : public Mir2Lir { 28 protected: 29 // TODO: consolidate 64-bit target support. 30 class InToRegStorageMapper { 31 public: 32 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 33 virtual ~InToRegStorageMapper() {} 34 }; 35 36 class InToRegStorageArm64Mapper : public InToRegStorageMapper { 37 public: 38 InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} 39 virtual ~InToRegStorageArm64Mapper() {} 40 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 41 private: 42 int cur_core_reg_; 43 int cur_fp_reg_; 44 }; 45 46 class InToRegStorageMapping { 47 public: 48 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 49 initialized_(false) {} 50 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 51 int GetMaxMappedIn() { return max_mapped_in_; } 52 bool IsThereStackMapped() { return is_there_stack_mapped_; } 53 RegStorage Get(int in_position); 54 bool IsInitialized() { return initialized_; } 55 private: 56 std::map<int, RegStorage> mapping_; 57 int max_mapped_in_; 58 bool is_there_stack_mapped_; 59 bool initialized_; 60 }; 61 62 public: 63 Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 64 65 // Required for target - codegen helpers. 66 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 67 RegLocation rl_dest, int lit) OVERRIDE; 68 bool SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 69 RegLocation rl_dest, int64_t lit); 70 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 71 RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 72 bool HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div, 73 RegLocation rl_src, RegLocation rl_dest, int64_t lit); 74 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 75 LIR* CheckSuspendUsingLoad() OVERRIDE; 76 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 77 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 78 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 79 OpSize size, VolatileKind is_volatile) OVERRIDE; 80 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, 81 VolatileKind is_volatile) 82 OVERRIDE; 83 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 84 OpSize size) OVERRIDE; 85 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) 86 OVERRIDE; 87 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 88 RegStorage r_dest, OpSize size) OVERRIDE; 89 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 90 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 91 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 92 OpSize size, VolatileKind is_volatile) OVERRIDE; 93 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, 94 VolatileKind is_volatile) OVERRIDE; 95 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 96 OpSize size) OVERRIDE; 97 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) 98 OVERRIDE; 99 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 100 RegStorage r_src, OpSize size) OVERRIDE; 101 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; 102 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 103 int offset, int check_value, LIR* target, LIR** compare) OVERRIDE; 104 105 // Required for target - register utilities. 106 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 107 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 108 if (wide_kind == kWide || wide_kind == kRef) { 109 return As64BitReg(TargetReg(symbolic_reg)); 110 } else { 111 return Check32BitReg(TargetReg(symbolic_reg)); 112 } 113 } 114 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 115 return As64BitReg(TargetReg(symbolic_reg)); 116 } 117 RegStorage GetArgMappingToPhysicalReg(int arg_num); 118 RegLocation GetReturnAlt(); 119 RegLocation GetReturnWideAlt(); 120 RegLocation LocCReturn(); 121 RegLocation LocCReturnRef(); 122 RegLocation LocCReturnDouble(); 123 RegLocation LocCReturnFloat(); 124 RegLocation LocCReturnWide(); 125 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 126 void AdjustSpillMask(); 127 void ClobberCallerSave(); 128 void FreeCallTemps(); 129 void LockCallTemps(); 130 void CompilerInitializeRegAlloc(); 131 132 // Required for target - miscellaneous. 133 void AssembleLIR(); 134 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); 135 int AssignInsnOffsets(); 136 void AssignOffsets(); 137 uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); 138 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 139 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 140 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 141 const char* GetTargetInstFmt(int opcode); 142 const char* GetTargetInstName(int opcode); 143 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 144 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 145 uint64_t GetTargetInstFlags(int opcode); 146 size_t GetInsnSize(LIR* lir) OVERRIDE; 147 bool IsUnconditionalBranch(LIR* lir); 148 149 // Get the register class for load/store of a field. 150 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 151 152 // Required for target - Dalvik-level generators. 153 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 154 RegLocation lr_shift); 155 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 156 RegLocation rl_src1, RegLocation rl_src2); 157 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 158 RegLocation rl_index, RegLocation rl_dest, int scale); 159 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 160 RegLocation rl_src, int scale, bool card_mark); 161 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 162 RegLocation rl_src1, RegLocation rl_shift); 163 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 164 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 165 RegLocation rl_src2); 166 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 167 RegLocation rl_src2); 168 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 169 RegLocation rl_src2); 170 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 171 RegLocation rl_src2); 172 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 173 RegLocation rl_src2); 174 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 175 RegLocation rl_src2); 176 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 177 bool GenInlinedReverseBits(CallInfo* info, OpSize size); 178 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 179 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 180 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 181 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 182 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double); 183 bool GenInlinedSqrt(CallInfo* info); 184 bool GenInlinedPeek(CallInfo* info, OpSize size); 185 bool GenInlinedPoke(CallInfo* info, OpSize size); 186 bool GenInlinedAbsLong(CallInfo* info); 187 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 188 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 189 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 190 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 191 RegLocation rl_src2); 192 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 193 RegLocation rl_src2); 194 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 195 RegLocation rl_src2); 196 void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 197 RegLocation rl_src2, bool is_div); 198 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 199 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 200 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 201 void GenDivZeroCheckWide(RegStorage reg); 202 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 203 void GenExitSequence(); 204 void GenSpecialExitSequence(); 205 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 206 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 207 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 208 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; 209 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 210 int32_t true_val, int32_t false_val, RegStorage rs_dest, 211 int dest_reg_class) OVERRIDE; 212 // Helper used in the above two. 213 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest, 214 int result_reg_class); 215 216 bool GenMemBarrier(MemBarrierKind barrier_kind); 217 void GenMonitorEnter(int opt_flags, RegLocation rl_src); 218 void GenMonitorExit(int opt_flags, RegLocation rl_src); 219 void GenMoveException(RegLocation rl_dest); 220 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 221 int first_bit, int second_bit); 222 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 223 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 224 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 225 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 226 227 uint32_t GenPairWise(uint32_t reg_mask, int* reg1, int* reg2); 228 void UnSpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); 229 void SpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); 230 void UnSpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); 231 void SpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); 232 233 // Required for target - single operation generators. 234 LIR* OpUnconditionalBranch(LIR* target); 235 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 236 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 237 LIR* OpCondBranch(ConditionCode cc, LIR* target); 238 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 239 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 240 LIR* OpIT(ConditionCode cond, const char* guide); 241 void OpEndIT(LIR* it); 242 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 243 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 244 LIR* OpReg(OpKind op, RegStorage r_dest_src); 245 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 246 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 247 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value); 248 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 249 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 250 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 251 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 252 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 253 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 254 LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value); 255 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 256 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 257 LIR* OpTestSuspend(LIR* target); 258 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 259 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 260 LIR* OpVldm(RegStorage r_base, int count); 261 LIR* OpVstm(RegStorage r_base, int count); 262 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 263 void OpRegCopyWide(RegStorage dest, RegStorage src); 264 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 265 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 266 267 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); 268 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 269 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 270 int shift); 271 LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 272 A64RegExtEncodings ext, uint8_t amount); 273 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 274 LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 275 static const ArmEncodingMap EncodingMap[kA64Last]; 276 int EncodeShift(int code, int amount); 277 int EncodeExtend(int extend_type, int amount); 278 bool IsExtendEncoding(int encoded_value); 279 int EncodeLogicalImmediate(bool is_wide, uint64_t value); 280 uint64_t DecodeLogicalImmediate(bool is_wide, int value); 281 282 ArmConditionCode ArmConditionEncoding(ConditionCode code); 283 bool InexpensiveConstantInt(int32_t value); 284 bool InexpensiveConstantFloat(int32_t value); 285 bool InexpensiveConstantLong(int64_t value); 286 bool InexpensiveConstantDouble(int64_t value); 287 288 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 289 290 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 291 NextCallInsn next_call_insn, 292 const MethodReference& target_method, 293 uint32_t vtable_idx, 294 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 295 bool skip_this); 296 297 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 298 NextCallInsn next_call_insn, 299 const MethodReference& target_method, 300 uint32_t vtable_idx, 301 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 302 bool skip_this); 303 InToRegStorageMapping in_to_reg_storage_mapping_; 304 305 bool WideGPRsAreAliases() OVERRIDE { 306 return true; // 64b architecture. 307 } 308 bool WideFPRsAreAliases() OVERRIDE { 309 return true; // 64b architecture. 310 } 311 312 private: 313 /** 314 * @brief Given register xNN (dNN), returns register wNN (sNN). 315 * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2). 316 * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2). 317 * @see As64BitReg 318 */ 319 RegStorage As32BitReg(RegStorage reg) { 320 DCHECK(!reg.IsPair()); 321 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 322 if (kFailOnSizeError) { 323 LOG(FATAL) << "Expected 64b register"; 324 } else { 325 LOG(WARNING) << "Expected 64b register"; 326 return reg; 327 } 328 } 329 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 330 reg.GetRawBits() & RegStorage::kRegTypeMask); 331 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 332 ->GetReg().GetReg(), 333 ret_val.GetReg()); 334 return ret_val; 335 } 336 337 RegStorage Check32BitReg(RegStorage reg) { 338 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 339 if (kFailOnSizeError) { 340 LOG(FATAL) << "Checked for 32b register"; 341 } else { 342 LOG(WARNING) << "Checked for 32b register"; 343 return As32BitReg(reg); 344 } 345 } 346 return reg; 347 } 348 349 /** 350 * @brief Given register wNN (sNN), returns register xNN (dNN). 351 * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2). 352 * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2). 353 * @see As32BitReg 354 */ 355 RegStorage As64BitReg(RegStorage reg) { 356 DCHECK(!reg.IsPair()); 357 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 358 if (kFailOnSizeError) { 359 LOG(FATAL) << "Expected 32b register"; 360 } else { 361 LOG(WARNING) << "Expected 32b register"; 362 return reg; 363 } 364 } 365 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 366 reg.GetRawBits() & RegStorage::kRegTypeMask); 367 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 368 ->GetReg().GetReg(), 369 ret_val.GetReg()); 370 return ret_val; 371 } 372 373 RegStorage Check64BitReg(RegStorage reg) { 374 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 375 if (kFailOnSizeError) { 376 LOG(FATAL) << "Checked for 64b register"; 377 } else { 378 LOG(WARNING) << "Checked for 64b register"; 379 return As64BitReg(reg); 380 } 381 } 382 return reg; 383 } 384 385 LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value); 386 LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value); 387 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 388 void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 389 void AssignDataOffsets(); 390 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 391 bool is_div, bool check_zero); 392 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); 393}; 394 395} // namespace art 396 397#endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 398