codegen_arm64.h revision c76c614d681d187d815760eb909e5faf488a3c35
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 18#define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 19 20#include "arm64_lir.h" 21#include "dex/compiler_internals.h" 22 23#include <map> 24 25namespace art { 26 27class Arm64Mir2Lir FINAL : public Mir2Lir { 28 protected: 29 // TODO: consolidate 64-bit target support. 30 class InToRegStorageMapper { 31 public: 32 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 33 virtual ~InToRegStorageMapper() {} 34 }; 35 36 class InToRegStorageArm64Mapper : public InToRegStorageMapper { 37 public: 38 InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} 39 virtual ~InToRegStorageArm64Mapper() {} 40 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 41 private: 42 int cur_core_reg_; 43 int cur_fp_reg_; 44 }; 45 46 class InToRegStorageMapping { 47 public: 48 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 49 initialized_(false) {} 50 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 51 int GetMaxMappedIn() { return max_mapped_in_; } 52 bool IsThereStackMapped() { return is_there_stack_mapped_; } 53 RegStorage Get(int in_position); 54 bool IsInitialized() { return initialized_; } 55 private: 56 std::map<int, RegStorage> mapping_; 57 int max_mapped_in_; 58 bool is_there_stack_mapped_; 59 bool initialized_; 60 }; 61 62 public: 63 Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 64 65 // Required for target - codegen helpers. 66 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 67 RegLocation rl_dest, int lit) OVERRIDE; 68 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 69 RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 70 bool HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div, 71 RegLocation rl_src, RegLocation rl_dest, int64_t lit); 72 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 73 LIR* CheckSuspendUsingLoad() OVERRIDE; 74 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; 75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 76 OpSize size, VolatileKind is_volatile) OVERRIDE; 77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, 78 VolatileKind is_volatile) OVERRIDE; 79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 80 OpSize size) OVERRIDE; 81 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) 82 OVERRIDE; 83 LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE; 84 LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE; 85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, 86 VolatileKind is_volatile) OVERRIDE; 87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile) 88 OVERRIDE; 89 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 90 OpSize size) OVERRIDE; 91 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE; 92 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; 93 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 94 int offset, int check_value, LIR* target, LIR** compare) OVERRIDE; 95 96 // Required for target - register utilities. 97 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 98 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 99 if (wide_kind == kWide || wide_kind == kRef) { 100 return As64BitReg(TargetReg(symbolic_reg)); 101 } else { 102 return Check32BitReg(TargetReg(symbolic_reg)); 103 } 104 } 105 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 106 return As64BitReg(TargetReg(symbolic_reg)); 107 } 108 RegStorage GetArgMappingToPhysicalReg(int arg_num) OVERRIDE; 109 RegLocation GetReturnAlt() OVERRIDE; 110 RegLocation GetReturnWideAlt() OVERRIDE; 111 RegLocation LocCReturn() OVERRIDE; 112 RegLocation LocCReturnRef() OVERRIDE; 113 RegLocation LocCReturnDouble() OVERRIDE; 114 RegLocation LocCReturnFloat() OVERRIDE; 115 RegLocation LocCReturnWide() OVERRIDE; 116 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 117 void AdjustSpillMask() OVERRIDE; 118 void ClobberCallerSave() OVERRIDE; 119 void FreeCallTemps() OVERRIDE; 120 void LockCallTemps() OVERRIDE; 121 void CompilerInitializeRegAlloc() OVERRIDE; 122 123 // Required for target - miscellaneous. 124 void AssembleLIR() OVERRIDE; 125 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 126 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 127 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 128 const char* GetTargetInstFmt(int opcode) OVERRIDE; 129 const char* GetTargetInstName(int opcode) OVERRIDE; 130 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE; 131 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 132 uint64_t GetTargetInstFlags(int opcode) OVERRIDE; 133 size_t GetInsnSize(LIR* lir) OVERRIDE; 134 bool IsUnconditionalBranch(LIR* lir) OVERRIDE; 135 136 // Get the register class for load/store of a field. 137 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 138 139 // Required for target - Dalvik-level generators. 140 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 141 RegLocation lr_shift) OVERRIDE; 142 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 143 RegLocation rl_src2) OVERRIDE; 144 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 145 RegLocation rl_dest, int scale) OVERRIDE; 146 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 147 RegLocation rl_src, int scale, bool card_mark) OVERRIDE; 148 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 149 RegLocation rl_shift) OVERRIDE; 150 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 151 RegLocation rl_src2) OVERRIDE; 152 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 153 RegLocation rl_src2) OVERRIDE; 154 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 155 RegLocation rl_src2) OVERRIDE; 156 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 157 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE; 158 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 159 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 160 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE; 161 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE; 162 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE; 163 bool GenInlinedSqrt(CallInfo* info) OVERRIDE; 164 bool GenInlinedCeil(CallInfo* info) OVERRIDE; 165 bool GenInlinedFloor(CallInfo* info) OVERRIDE; 166 bool GenInlinedRint(CallInfo* info) OVERRIDE; 167 bool GenInlinedRound(CallInfo* info, bool is_double) OVERRIDE; 168 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE; 169 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE; 170 bool GenInlinedAbsLong(CallInfo* info) OVERRIDE; 171 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 172 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 173 RegLocation rl_src2) OVERRIDE; 174 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div) 175 OVERRIDE; 176 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) 177 OVERRIDE; 178 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE; 179 void GenDivZeroCheckWide(RegStorage reg) OVERRIDE; 180 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; 181 void GenExitSequence() OVERRIDE; 182 void GenSpecialExitSequence() OVERRIDE; 183 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) OVERRIDE; 184 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; 185 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; 186 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; 187 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 188 int32_t true_val, int32_t false_val, RegStorage rs_dest, 189 int dest_reg_class) OVERRIDE; 190 191 bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE; 192 void GenMonitorEnter(int opt_flags, RegLocation rl_src) OVERRIDE; 193 void GenMonitorExit(int opt_flags, RegLocation rl_src) OVERRIDE; 194 void GenMoveException(RegLocation rl_dest) OVERRIDE; 195 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 196 int first_bit, int second_bit) OVERRIDE; 197 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 198 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 199 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 200 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 201 202 // Required for target - single operation generators. 203 LIR* OpUnconditionalBranch(LIR* target) OVERRIDE; 204 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE; 205 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE; 206 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE; 207 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE; 208 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 209 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE; 210 void OpEndIT(LIR* it) OVERRIDE; 211 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; 212 LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE; 213 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE; 214 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 215 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; 216 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE; 217 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE; 218 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; 219 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; 220 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; 221 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE; 222 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE; 223 LIR* OpTestSuspend(LIR* target) OVERRIDE; 224 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; 225 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; 226 void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE; 227 228 bool InexpensiveConstantInt(int32_t value) OVERRIDE; 229 bool InexpensiveConstantInt(int32_t value, Instruction::Code opcode) OVERRIDE; 230 bool InexpensiveConstantFloat(int32_t value) OVERRIDE; 231 bool InexpensiveConstantLong(int64_t value) OVERRIDE; 232 bool InexpensiveConstantDouble(int64_t value) OVERRIDE; 233 234 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; 235 236 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 237 NextCallInsn next_call_insn, 238 const MethodReference& target_method, 239 uint32_t vtable_idx, 240 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 241 bool skip_this) OVERRIDE; 242 243 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 244 NextCallInsn next_call_insn, 245 const MethodReference& target_method, 246 uint32_t vtable_idx, 247 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 248 bool skip_this) OVERRIDE; 249 250 bool WideGPRsAreAliases() OVERRIDE { 251 return true; // 64b architecture. 252 } 253 bool WideFPRsAreAliases() OVERRIDE { 254 return true; // 64b architecture. 255 } 256 257 size_t GetInstructionOffset(LIR* lir) OVERRIDE; 258 259 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; 260 261 private: 262 /** 263 * @brief Given register xNN (dNN), returns register wNN (sNN). 264 * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2). 265 * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2). 266 * @see As64BitReg 267 */ 268 RegStorage As32BitReg(RegStorage reg) { 269 DCHECK(!reg.IsPair()); 270 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 271 if (kFailOnSizeError) { 272 LOG(FATAL) << "Expected 64b register"; 273 } else { 274 LOG(WARNING) << "Expected 64b register"; 275 return reg; 276 } 277 } 278 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 279 reg.GetRawBits() & RegStorage::kRegTypeMask); 280 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 281 ->GetReg().GetReg(), 282 ret_val.GetReg()); 283 return ret_val; 284 } 285 286 RegStorage Check32BitReg(RegStorage reg) { 287 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 288 if (kFailOnSizeError) { 289 LOG(FATAL) << "Checked for 32b register"; 290 } else { 291 LOG(WARNING) << "Checked for 32b register"; 292 return As32BitReg(reg); 293 } 294 } 295 return reg; 296 } 297 298 /** 299 * @brief Given register wNN (sNN), returns register xNN (dNN). 300 * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2). 301 * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2). 302 * @see As32BitReg 303 */ 304 RegStorage As64BitReg(RegStorage reg) { 305 DCHECK(!reg.IsPair()); 306 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 307 if (kFailOnSizeError) { 308 LOG(FATAL) << "Expected 32b register"; 309 } else { 310 LOG(WARNING) << "Expected 32b register"; 311 return reg; 312 } 313 } 314 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 315 reg.GetRawBits() & RegStorage::kRegTypeMask); 316 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 317 ->GetReg().GetReg(), 318 ret_val.GetReg()); 319 return ret_val; 320 } 321 322 RegStorage Check64BitReg(RegStorage reg) { 323 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 324 if (kFailOnSizeError) { 325 LOG(FATAL) << "Checked for 64b register"; 326 } else { 327 LOG(WARNING) << "Checked for 64b register"; 328 return As64BitReg(reg); 329 } 330 } 331 return reg; 332 } 333 334 int32_t EncodeImmSingle(uint32_t bits); 335 int32_t EncodeImmDouble(uint64_t bits); 336 LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value); 337 LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value); 338 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 339 void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 340 void AssignDataOffsets(); 341 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 342 bool is_div, bool check_zero); 343 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); 344 size_t GetLoadStoreSize(LIR* lir); 345 346 bool SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 347 RegLocation rl_dest, int64_t lit); 348 349 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); 350 int AssignInsnOffsets(); 351 void AssignOffsets(); 352 uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); 353 354 // Spill core and FP registers. Returns the SP difference: either spill size, or whole 355 // frame size. 356 int SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size); 357 358 // Unspill core and FP registers. 359 void UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size); 360 361 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 362 363 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value); 364 LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value); 365 366 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 367 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 368 int shift); 369 int EncodeShift(int code, int amount); 370 371 LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, 372 A64RegExtEncodings ext, uint8_t amount); 373 LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 374 A64RegExtEncodings ext, uint8_t amount); 375 int EncodeExtend(int extend_type, int amount); 376 bool IsExtendEncoding(int encoded_value); 377 378 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); 379 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 380 381 int EncodeLogicalImmediate(bool is_wide, uint64_t value); 382 uint64_t DecodeLogicalImmediate(bool is_wide, int value); 383 ArmConditionCode ArmConditionEncoding(ConditionCode code); 384 385 // Helper used in the two GenSelect variants. 386 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest, 387 int result_reg_class); 388 389 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 390 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 391 void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 392 RegLocation rl_src2, bool is_div); 393 394 InToRegStorageMapping in_to_reg_storage_mapping_; 395 static const ArmEncodingMap EncodingMap[kA64Last]; 396}; 397 398} // namespace art 399 400#endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 401