gen_common.cc revision 0237ac84b1459cb1718dce23f3572ae2fe1bd77e
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include "dex/compiler_ir.h" 17#include "dex/compiler_internals.h" 18#include "dex/quick/arm/arm_lir.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object_array-inl.h" 23#include "mirror/object-inl.h" 24#include "verifier/method_verifier.h" 25#include <functional> 26 27namespace art { 28 29// Shortcuts to repeatedly used long types. 30typedef mirror::ObjectArray<mirror::Object> ObjArray; 31typedef mirror::ObjectArray<mirror::Class> ClassArray; 32 33/* 34 * This source files contains "gen" codegen routines that should 35 * be applicable to most targets. Only mid-level support utilities 36 * and "op" calls may be used here. 37 */ 38 39/* 40 * Generate a kPseudoBarrier marker to indicate the boundary of special 41 * blocks. 42 */ 43void Mir2Lir::GenBarrier() { 44 LIR* barrier = NewLIR0(kPseudoBarrier); 45 /* Mark all resources as being clobbered */ 46 DCHECK(!barrier->flags.use_def_invalid); 47 barrier->u.m.def_mask = &kEncodeAll; 48} 49 50void Mir2Lir::GenDivZeroException() { 51 LIR* branch = OpUnconditionalBranch(nullptr); 52 AddDivZeroCheckSlowPath(branch); 53} 54 55void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { 56 LIR* branch = OpCondBranch(c_code, nullptr); 57 AddDivZeroCheckSlowPath(branch); 58} 59 60void Mir2Lir::GenDivZeroCheck(RegStorage reg) { 61 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 62 AddDivZeroCheckSlowPath(branch); 63} 64 65void Mir2Lir::AddDivZeroCheckSlowPath(LIR* branch) { 66 class DivZeroCheckSlowPath : public Mir2Lir::LIRSlowPath { 67 public: 68 DivZeroCheckSlowPath(Mir2Lir* m2l, LIR* branch) 69 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 70 } 71 72 void Compile() OVERRIDE { 73 m2l_->ResetRegPool(); 74 m2l_->ResetDefTracking(); 75 GenerateTargetLabel(kPseudoThrowTarget); 76 if (m2l_->cu_->target64) { 77 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowDivZero), true); 78 } else { 79 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowDivZero), true); 80 } 81 } 82 }; 83 84 AddSlowPath(new (arena_) DivZeroCheckSlowPath(this, branch)); 85} 86 87void Mir2Lir::GenArrayBoundsCheck(RegStorage index, RegStorage length) { 88 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 89 public: 90 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, RegStorage index, RegStorage length) 91 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 92 index_(index), length_(length) { 93 } 94 95 void Compile() OVERRIDE { 96 m2l_->ResetRegPool(); 97 m2l_->ResetDefTracking(); 98 GenerateTargetLabel(kPseudoThrowTarget); 99 if (m2l_->cu_->target64) { 100 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 101 index_, length_, true); 102 } else { 103 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 104 index_, length_, true); 105 } 106 } 107 108 private: 109 const RegStorage index_; 110 const RegStorage length_; 111 }; 112 113 LIR* branch = OpCmpBranch(kCondUge, index, length, nullptr); 114 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 115} 116 117void Mir2Lir::GenArrayBoundsCheck(int index, RegStorage length) { 118 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 119 public: 120 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, int index, RegStorage length) 121 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 122 index_(index), length_(length) { 123 } 124 125 void Compile() OVERRIDE { 126 m2l_->ResetRegPool(); 127 m2l_->ResetDefTracking(); 128 GenerateTargetLabel(kPseudoThrowTarget); 129 130 RegStorage arg1_32 = m2l_->TargetReg(kArg1, kNotWide); 131 RegStorage arg0_32 = m2l_->TargetReg(kArg0, kNotWide); 132 133 m2l_->OpRegCopy(arg1_32, length_); 134 m2l_->LoadConstant(arg0_32, index_); 135 if (m2l_->cu_->target64) { 136 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 137 arg0_32, arg1_32, true); 138 } else { 139 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 140 arg0_32, arg1_32, true); 141 } 142 } 143 144 private: 145 const int32_t index_; 146 const RegStorage length_; 147 }; 148 149 LIR* branch = OpCmpImmBranch(kCondLs, length, index, nullptr); 150 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 151} 152 153LIR* Mir2Lir::GenNullCheck(RegStorage reg) { 154 class NullCheckSlowPath : public Mir2Lir::LIRSlowPath { 155 public: 156 NullCheckSlowPath(Mir2Lir* m2l, LIR* branch) 157 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 158 } 159 160 void Compile() OVERRIDE { 161 m2l_->ResetRegPool(); 162 m2l_->ResetDefTracking(); 163 GenerateTargetLabel(kPseudoThrowTarget); 164 if (m2l_->cu_->target64) { 165 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowNullPointer), true); 166 } else { 167 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowNullPointer), true); 168 } 169 } 170 }; 171 172 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 173 AddSlowPath(new (arena_) NullCheckSlowPath(this, branch)); 174 return branch; 175} 176 177/* Perform null-check on a register. */ 178LIR* Mir2Lir::GenNullCheck(RegStorage m_reg, int opt_flags) { 179 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 180 return GenExplicitNullCheck(m_reg, opt_flags); 181 } 182 return nullptr; 183} 184 185/* Perform an explicit null-check on a register. */ 186LIR* Mir2Lir::GenExplicitNullCheck(RegStorage m_reg, int opt_flags) { 187 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 188 return NULL; 189 } 190 return GenNullCheck(m_reg); 191} 192 193void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 194 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 195 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 196 return; 197 } 198 // Insert after last instruction. 199 MarkSafepointPC(last_lir_insn_); 200 } 201} 202 203void Mir2Lir::MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after) { 204 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 205 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 206 return; 207 } 208 MarkSafepointPCAfter(after); 209 } 210} 211 212void Mir2Lir::MarkPossibleStackOverflowException() { 213 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitStackOverflowChecks()) { 214 MarkSafepointPC(last_lir_insn_); 215 } 216} 217 218void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { 219 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 220 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 221 return; 222 } 223 // Force an implicit null check by performing a memory operation (load) from the given 224 // register with offset 0. This will cause a signal if the register contains 0 (null). 225 RegStorage tmp = AllocTemp(); 226 // TODO: for Mips, would be best to use rZERO as the bogus register target. 227 LIR* load = Load32Disp(reg, 0, tmp); 228 FreeTemp(tmp); 229 MarkSafepointPC(load); 230 } 231} 232 233void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 234 RegLocation rl_src2, LIR* taken, 235 LIR* fall_through) { 236 DCHECK(!rl_src1.fp); 237 DCHECK(!rl_src2.fp); 238 ConditionCode cond; 239 switch (opcode) { 240 case Instruction::IF_EQ: 241 cond = kCondEq; 242 break; 243 case Instruction::IF_NE: 244 cond = kCondNe; 245 break; 246 case Instruction::IF_LT: 247 cond = kCondLt; 248 break; 249 case Instruction::IF_GE: 250 cond = kCondGe; 251 break; 252 case Instruction::IF_GT: 253 cond = kCondGt; 254 break; 255 case Instruction::IF_LE: 256 cond = kCondLe; 257 break; 258 default: 259 cond = static_cast<ConditionCode>(0); 260 LOG(FATAL) << "Unexpected opcode " << opcode; 261 } 262 263 // Normalize such that if either operand is constant, src2 will be constant 264 if (rl_src1.is_const) { 265 RegLocation rl_temp = rl_src1; 266 rl_src1 = rl_src2; 267 rl_src2 = rl_temp; 268 cond = FlipComparisonOrder(cond); 269 } 270 271 rl_src1 = LoadValue(rl_src1); 272 // Is this really an immediate comparison? 273 if (rl_src2.is_const) { 274 // If it's already live in a register or not easily materialized, just keep going 275 RegLocation rl_temp = UpdateLoc(rl_src2); 276 int32_t constant_value = mir_graph_->ConstantValue(rl_src2); 277 if ((rl_temp.location == kLocDalvikFrame) && 278 InexpensiveConstantInt(constant_value)) { 279 // OK - convert this to a compare immediate and branch 280 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); 281 return; 282 } 283 284 // It's also commonly more efficient to have a test against zero with Eq/Ne. This is not worse 285 // for x86, and allows a cbz/cbnz for Arm and Mips. At the same time, it works around a register 286 // mismatch for 64b systems, where a reference is compared against null, as dex bytecode uses 287 // the 32b literal 0 for null. 288 if (constant_value == 0 && (cond == kCondEq || cond == kCondNe)) { 289 // Use the OpCmpImmBranch and ignore the value in the register. 290 OpCmpImmBranch(cond, rl_src1.reg, 0, taken); 291 return; 292 } 293 } 294 295 rl_src2 = LoadValue(rl_src2); 296 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken); 297} 298 299void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 300 LIR* fall_through) { 301 ConditionCode cond; 302 DCHECK(!rl_src.fp); 303 rl_src = LoadValue(rl_src); 304 switch (opcode) { 305 case Instruction::IF_EQZ: 306 cond = kCondEq; 307 break; 308 case Instruction::IF_NEZ: 309 cond = kCondNe; 310 break; 311 case Instruction::IF_LTZ: 312 cond = kCondLt; 313 break; 314 case Instruction::IF_GEZ: 315 cond = kCondGe; 316 break; 317 case Instruction::IF_GTZ: 318 cond = kCondGt; 319 break; 320 case Instruction::IF_LEZ: 321 cond = kCondLe; 322 break; 323 default: 324 cond = static_cast<ConditionCode>(0); 325 LOG(FATAL) << "Unexpected opcode " << opcode; 326 } 327 OpCmpImmBranch(cond, rl_src.reg, 0, taken); 328} 329 330void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 331 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 332 if (rl_src.location == kLocPhysReg) { 333 OpRegCopy(rl_result.reg, rl_src.reg); 334 } else { 335 LoadValueDirect(rl_src, rl_result.reg.GetLow()); 336 } 337 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_result.reg.GetLow(), 31); 338 StoreValueWide(rl_dest, rl_result); 339} 340 341void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 342 RegLocation rl_src) { 343 rl_src = LoadValue(rl_src, kCoreReg); 344 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 345 OpKind op = kOpInvalid; 346 switch (opcode) { 347 case Instruction::INT_TO_BYTE: 348 op = kOp2Byte; 349 break; 350 case Instruction::INT_TO_SHORT: 351 op = kOp2Short; 352 break; 353 case Instruction::INT_TO_CHAR: 354 op = kOp2Char; 355 break; 356 default: 357 LOG(ERROR) << "Bad int conversion type"; 358 } 359 OpRegReg(op, rl_result.reg, rl_src.reg); 360 StoreValue(rl_dest, rl_result); 361} 362 363template <size_t pointer_size> 364static void GenNewArrayImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, 365 uint32_t type_idx, RegLocation rl_dest, 366 RegLocation rl_src) { 367 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 368 ThreadOffset<pointer_size> func_offset(-1); 369 const DexFile* dex_file = cu->dex_file; 370 CompilerDriver* driver = cu->compiler_driver; 371 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *dex_file, 372 type_idx)) { 373 bool is_type_initialized; // Ignored as an array does not have an initializer. 374 bool use_direct_type_ptr; 375 uintptr_t direct_type_ptr; 376 bool is_finalizable; 377 if (kEmbedClassInCode && 378 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 379 &direct_type_ptr, &is_finalizable)) { 380 // The fast path. 381 if (!use_direct_type_ptr) { 382 mir_to_lir->LoadClassType(type_idx, kArg0); 383 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 384 mir_to_lir->CallRuntimeHelperRegMethodRegLocation(func_offset, 385 mir_to_lir->TargetReg(kArg0, kNotWide), 386 rl_src, true); 387 } else { 388 // Use the direct pointer. 389 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 390 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, 391 true); 392 } 393 } else { 394 // The slow path. 395 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArray); 396 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 397 } 398 DCHECK_NE(func_offset.Int32Value(), -1); 399 } else { 400 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayWithAccessCheck); 401 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 402 } 403 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 404 mir_to_lir->StoreValue(rl_dest, rl_result); 405} 406 407/* 408 * Let helper function take care of everything. Will call 409 * Array::AllocFromCode(type_idx, method, count); 410 * Note: AllocFromCode will handle checks for errNegativeArraySize. 411 */ 412void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 413 RegLocation rl_src) { 414 if (cu_->target64) { 415 GenNewArrayImpl<8>(this, cu_, type_idx, rl_dest, rl_src); 416 } else { 417 GenNewArrayImpl<4>(this, cu_, type_idx, rl_dest, rl_src); 418 } 419} 420 421template <size_t pointer_size> 422static void GenFilledNewArrayCall(Mir2Lir* mir_to_lir, CompilationUnit* cu, int elems, int type_idx) { 423 ThreadOffset<pointer_size> func_offset(-1); 424 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *cu->dex_file, 425 type_idx)) { 426 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArray); 427 } else { 428 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArrayWithAccessCheck); 429 } 430 mir_to_lir->CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 431} 432 433/* 434 * Similar to GenNewArray, but with post-allocation initialization. 435 * Verifier guarantees we're dealing with an array class. Current 436 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 437 * Current code also throws internal unimp if not 'L', '[' or 'I'. 438 */ 439void Mir2Lir::GenFilledNewArray(CallInfo* info) { 440 int elems = info->num_arg_words; 441 int type_idx = info->index; 442 FlushAllRegs(); /* Everything to home location */ 443 if (cu_->target64) { 444 GenFilledNewArrayCall<8>(this, cu_, elems, type_idx); 445 } else { 446 GenFilledNewArrayCall<4>(this, cu_, elems, type_idx); 447 } 448 FreeTemp(TargetReg(kArg2, kNotWide)); 449 FreeTemp(TargetReg(kArg1, kNotWide)); 450 /* 451 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 452 * return region. Because AllocFromCode placed the new array 453 * in kRet0, we'll just lock it into place. When debugger support is 454 * added, it may be necessary to additionally copy all return 455 * values to a home location in thread-local storage 456 */ 457 RegStorage ref_reg = TargetReg(kRet0, kRef); 458 LockTemp(ref_reg); 459 460 // TODO: use the correct component size, currently all supported types 461 // share array alignment with ints (see comment at head of function) 462 size_t component_size = sizeof(int32_t); 463 464 // Having a range of 0 is legal 465 if (info->is_range && (elems > 0)) { 466 /* 467 * Bit of ugliness here. We're going generate a mem copy loop 468 * on the register range, but it is possible that some regs 469 * in the range have been promoted. This is unlikely, but 470 * before generating the copy, we'll just force a flush 471 * of any regs in the source range that have been promoted to 472 * home location. 473 */ 474 for (int i = 0; i < elems; i++) { 475 RegLocation loc = UpdateLoc(info->args[i]); 476 if (loc.location == kLocPhysReg) { 477 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 478 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 479 } 480 } 481 /* 482 * TUNING note: generated code here could be much improved, but 483 * this is an uncommon operation and isn't especially performance 484 * critical. 485 */ 486 // This is addressing the stack, which may be out of the 4G area. 487 RegStorage r_src = AllocTempRef(); 488 RegStorage r_dst = AllocTempRef(); 489 RegStorage r_idx = AllocTempRef(); // Not really a reference, but match src/dst. 490 RegStorage r_val; 491 switch (cu_->instruction_set) { 492 case kThumb2: 493 case kArm64: 494 r_val = TargetReg(kLr, kNotWide); 495 break; 496 case kX86: 497 case kX86_64: 498 FreeTemp(ref_reg); 499 r_val = AllocTemp(); 500 break; 501 case kMips: 502 r_val = AllocTemp(); 503 break; 504 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 505 } 506 // Set up source pointer 507 RegLocation rl_first = info->args[0]; 508 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); 509 // Set up the target pointer 510 OpRegRegImm(kOpAdd, r_dst, ref_reg, 511 mirror::Array::DataOffset(component_size).Int32Value()); 512 // Set up the loop counter (known to be > 0) 513 LoadConstant(r_idx, elems - 1); 514 // Generate the copy loop. Going backwards for convenience 515 LIR* target = NewLIR0(kPseudoTargetLabel); 516 // Copy next element 517 { 518 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 519 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32); 520 // NOTE: No dalvik register annotation, local optimizations will be stopped 521 // by the loop boundaries. 522 } 523 StoreBaseIndexed(r_dst, r_idx, r_val, 2, k32); 524 FreeTemp(r_val); 525 OpDecAndBranch(kCondGe, r_idx, target); 526 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 527 // Restore the target pointer 528 OpRegRegImm(kOpAdd, ref_reg, r_dst, 529 -mirror::Array::DataOffset(component_size).Int32Value()); 530 } 531 } else if (!info->is_range) { 532 // TUNING: interleave 533 for (int i = 0; i < elems; i++) { 534 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 535 Store32Disp(ref_reg, 536 mirror::Array::DataOffset(component_size).Int32Value() + i * 4, rl_arg.reg); 537 // If the LoadValue caused a temp to be allocated, free it 538 if (IsTemp(rl_arg.reg)) { 539 FreeTemp(rl_arg.reg); 540 } 541 } 542 } 543 if (info->result.location != kLocInvalid) { 544 StoreValue(info->result, GetReturn(kRefReg)); 545 } 546} 547 548// 549// Slow path to ensure a class is initialized for sget/sput. 550// 551class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 552 public: 553 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, int storage_index, 554 RegStorage r_base) : 555 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), 556 storage_index_(storage_index), r_base_(r_base) { 557 } 558 559 void Compile() { 560 LIR* unresolved_target = GenerateTargetLabel(); 561 uninit_->target = unresolved_target; 562 if (cu_->target64) { 563 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeStaticStorage), 564 storage_index_, true); 565 } else { 566 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeStaticStorage), 567 storage_index_, true); 568 } 569 // Copy helper's result into r_base, a no-op on all but MIPS. 570 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0, kRef)); 571 572 m2l_->OpUnconditionalBranch(cont_); 573 } 574 575 private: 576 LIR* const uninit_; 577 const int storage_index_; 578 const RegStorage r_base_; 579}; 580 581template <size_t pointer_size> 582static void GenSputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 583 const MirSFieldLoweringInfo* field_info, RegLocation rl_src) { 584 ThreadOffset<pointer_size> setter_offset = 585 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Static) 586 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjStatic) 587 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Static)); 588 mir_to_lir->CallRuntimeHelperImmRegLocation(setter_offset, field_info->FieldIndex(), rl_src, 589 true); 590} 591 592void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 593 bool is_object) { 594 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 595 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 596 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 597 if (!SLOW_FIELD_PATH && field_info.FastPut() && 598 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 599 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 600 RegStorage r_base; 601 if (field_info.IsReferrersClass()) { 602 // Fast path, static storage base is this method's class 603 RegLocation rl_method = LoadCurrMethod(); 604 r_base = AllocTempRef(); 605 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 606 kNotVolatile); 607 if (IsTemp(rl_method.reg)) { 608 FreeTemp(rl_method.reg); 609 } 610 } else { 611 // Medium path, static storage base in a different class which requires checks that the other 612 // class is initialized. 613 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 614 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 615 // May do runtime call so everything to home locations. 616 FlushAllRegs(); 617 // Using fixed register to sync with possible call to runtime support. 618 RegStorage r_method = TargetReg(kArg1, kRef); 619 LockTemp(r_method); 620 LoadCurrMethodDirect(r_method); 621 r_base = TargetReg(kArg0, kRef); 622 LockTemp(r_base); 623 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 624 kNotVolatile); 625 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 626 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 627 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 628 if (!field_info.IsInitialized() && 629 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 630 // Check if r_base is NULL or a not yet initialized class. 631 632 // The slow path is invoked if the r_base is NULL or the class pointed 633 // to by it is not initialized. 634 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 635 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 636 LockTemp(r_tmp); 637 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 638 mirror::Class::StatusOffset().Int32Value(), 639 mirror::Class::kStatusInitialized, nullptr, nullptr); 640 LIR* cont = NewLIR0(kPseudoTargetLabel); 641 642 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 643 field_info.StorageIndex(), r_base)); 644 645 FreeTemp(r_tmp); 646 // Ensure load of status and store of value don't re-order. 647 // TODO: Presumably the actual value store is control-dependent on the status load, 648 // and will thus not be reordered in any case, since stores are never speculated. 649 // Does later code "know" that the class is now initialized? If so, we still 650 // need the barrier to guard later static loads. 651 GenMemBarrier(kLoadAny); 652 } 653 FreeTemp(r_method); 654 } 655 // rBase now holds static storage base 656 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 657 if (is_long_or_double) { 658 rl_src = LoadValueWide(rl_src, reg_class); 659 } else { 660 rl_src = LoadValue(rl_src, reg_class); 661 } 662 if (is_object) { 663 StoreRefDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, 664 field_info.IsVolatile() ? kVolatile : kNotVolatile); 665 } else { 666 StoreBaseDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, store_size, 667 field_info.IsVolatile() ? kVolatile : kNotVolatile); 668 } 669 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 670 MarkGCCard(rl_src.reg, r_base); 671 } 672 FreeTemp(r_base); 673 } else { 674 FlushAllRegs(); // Everything to home locations 675 if (cu_->target64) { 676 GenSputCall<8>(this, is_long_or_double, is_object, &field_info, rl_src); 677 } else { 678 GenSputCall<4>(this, is_long_or_double, is_object, &field_info, rl_src); 679 } 680 } 681} 682 683template <size_t pointer_size> 684static void GenSgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 685 const MirSFieldLoweringInfo* field_info) { 686 ThreadOffset<pointer_size> getter_offset = 687 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Static) 688 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjStatic) 689 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Static)); 690 mir_to_lir->CallRuntimeHelperImm(getter_offset, field_info->FieldIndex(), true); 691} 692 693void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 694 bool is_long_or_double, bool is_object) { 695 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 696 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 697 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 698 if (!SLOW_FIELD_PATH && field_info.FastGet() && 699 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 700 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 701 RegStorage r_base; 702 if (field_info.IsReferrersClass()) { 703 // Fast path, static storage base is this method's class 704 RegLocation rl_method = LoadCurrMethod(); 705 r_base = AllocTempRef(); 706 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 707 kNotVolatile); 708 } else { 709 // Medium path, static storage base in a different class which requires checks that the other 710 // class is initialized 711 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 712 // May do runtime call so everything to home locations. 713 FlushAllRegs(); 714 // Using fixed register to sync with possible call to runtime support. 715 RegStorage r_method = TargetReg(kArg1, kRef); 716 LockTemp(r_method); 717 LoadCurrMethodDirect(r_method); 718 r_base = TargetReg(kArg0, kRef); 719 LockTemp(r_base); 720 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 721 kNotVolatile); 722 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 723 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 724 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 725 if (!field_info.IsInitialized() && 726 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 727 // Check if r_base is NULL or a not yet initialized class. 728 729 // The slow path is invoked if the r_base is NULL or the class pointed 730 // to by it is not initialized. 731 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 732 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 733 LockTemp(r_tmp); 734 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 735 mirror::Class::StatusOffset().Int32Value(), 736 mirror::Class::kStatusInitialized, nullptr, nullptr); 737 LIR* cont = NewLIR0(kPseudoTargetLabel); 738 739 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 740 field_info.StorageIndex(), r_base)); 741 742 FreeTemp(r_tmp); 743 // Ensure load of status and load of value don't re-order. 744 GenMemBarrier(kLoadAny); 745 } 746 FreeTemp(r_method); 747 } 748 // r_base now holds static storage base 749 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 750 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 751 752 int field_offset = field_info.FieldOffset().Int32Value(); 753 if (is_object) { 754 LoadRefDisp(r_base, field_offset, rl_result.reg, field_info.IsVolatile() ? kVolatile : 755 kNotVolatile); 756 } else { 757 LoadBaseDisp(r_base, field_offset, rl_result.reg, load_size, field_info.IsVolatile() ? 758 kVolatile : kNotVolatile); 759 } 760 FreeTemp(r_base); 761 762 if (is_long_or_double) { 763 StoreValueWide(rl_dest, rl_result); 764 } else { 765 StoreValue(rl_dest, rl_result); 766 } 767 } else { 768 FlushAllRegs(); // Everything to home locations 769 if (cu_->target64) { 770 GenSgetCall<8>(this, is_long_or_double, is_object, &field_info); 771 } else { 772 GenSgetCall<4>(this, is_long_or_double, is_object, &field_info); 773 } 774 // FIXME: pGetXXStatic always return an int or int64 regardless of rl_dest.fp. 775 if (is_long_or_double) { 776 RegLocation rl_result = GetReturnWide(kCoreReg); 777 StoreValueWide(rl_dest, rl_result); 778 } else { 779 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 780 StoreValue(rl_dest, rl_result); 781 } 782 } 783} 784 785// Generate code for all slow paths. 786void Mir2Lir::HandleSlowPaths() { 787 // We should check slow_paths_.Size() every time, because a new slow path 788 // may be created during slowpath->Compile(). 789 for (size_t i = 0; i < slow_paths_.Size(); ++i) { 790 LIRSlowPath* slowpath = slow_paths_.Get(i); 791 slowpath->Compile(); 792 } 793 slow_paths_.Reset(); 794} 795 796template <size_t pointer_size> 797static void GenIgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 798 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj) { 799 ThreadOffset<pointer_size> getter_offset = 800 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Instance) 801 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjInstance) 802 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Instance)); 803 mir_to_lir->CallRuntimeHelperImmRegLocation(getter_offset, field_info->FieldIndex(), rl_obj, 804 true); 805} 806 807void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 808 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 809 bool is_object) { 810 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 811 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 812 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 813 if (!SLOW_FIELD_PATH && field_info.FastGet() && 814 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 815 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 816 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 817 rl_obj = LoadValue(rl_obj, kRefReg); 818 GenNullCheck(rl_obj.reg, opt_flags); 819 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 820 int field_offset = field_info.FieldOffset().Int32Value(); 821 LIR* load_lir; 822 if (is_object) { 823 load_lir = LoadRefDisp(rl_obj.reg, field_offset, rl_result.reg, field_info.IsVolatile() ? 824 kVolatile : kNotVolatile); 825 } else { 826 load_lir = LoadBaseDisp(rl_obj.reg, field_offset, rl_result.reg, load_size, 827 field_info.IsVolatile() ? kVolatile : kNotVolatile); 828 } 829 MarkPossibleNullPointerExceptionAfter(opt_flags, load_lir); 830 if (is_long_or_double) { 831 StoreValueWide(rl_dest, rl_result); 832 } else { 833 StoreValue(rl_dest, rl_result); 834 } 835 } else { 836 if (cu_->target64) { 837 GenIgetCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj); 838 } else { 839 GenIgetCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj); 840 } 841 // FIXME: pGetXXInstance always return an int or int64 regardless of rl_dest.fp. 842 if (is_long_or_double) { 843 RegLocation rl_result = GetReturnWide(kCoreReg); 844 StoreValueWide(rl_dest, rl_result); 845 } else { 846 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 847 StoreValue(rl_dest, rl_result); 848 } 849 } 850} 851 852template <size_t pointer_size> 853static void GenIputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 854 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj, 855 RegLocation rl_src) { 856 ThreadOffset<pointer_size> setter_offset = 857 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Instance) 858 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjInstance) 859 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Instance)); 860 mir_to_lir->CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info->FieldIndex(), 861 rl_obj, rl_src, true); 862} 863 864void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 865 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 866 bool is_object) { 867 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 868 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 869 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 870 if (!SLOW_FIELD_PATH && field_info.FastPut() && 871 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 872 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 873 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 874 rl_obj = LoadValue(rl_obj, kRefReg); 875 if (is_long_or_double) { 876 rl_src = LoadValueWide(rl_src, reg_class); 877 } else { 878 rl_src = LoadValue(rl_src, reg_class); 879 } 880 GenNullCheck(rl_obj.reg, opt_flags); 881 int field_offset = field_info.FieldOffset().Int32Value(); 882 LIR* store; 883 if (is_object) { 884 store = StoreRefDisp(rl_obj.reg, field_offset, rl_src.reg, field_info.IsVolatile() ? 885 kVolatile : kNotVolatile); 886 } else { 887 store = StoreBaseDisp(rl_obj.reg, field_offset, rl_src.reg, store_size, 888 field_info.IsVolatile() ? kVolatile : kNotVolatile); 889 } 890 MarkPossibleNullPointerExceptionAfter(opt_flags, store); 891 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 892 MarkGCCard(rl_src.reg, rl_obj.reg); 893 } 894 } else { 895 if (cu_->target64) { 896 GenIputCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 897 } else { 898 GenIputCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 899 } 900 } 901} 902 903template <size_t pointer_size> 904static void GenArrayObjPutCall(Mir2Lir* mir_to_lir, bool needs_range_check, bool needs_null_check, 905 RegLocation rl_array, RegLocation rl_index, RegLocation rl_src) { 906 ThreadOffset<pointer_size> helper = needs_range_check 907 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithNullAndBoundCheck) 908 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithBoundCheck)) 909 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObject); 910 mir_to_lir->CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, 911 true); 912} 913 914void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 915 RegLocation rl_src) { 916 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 917 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 918 (opt_flags & MIR_IGNORE_NULL_CHECK)); 919 if (cu_->target64) { 920 GenArrayObjPutCall<8>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 921 } else { 922 GenArrayObjPutCall<4>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 923 } 924} 925 926void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 927 RegLocation rl_method = LoadCurrMethod(); 928 CheckRegLocation(rl_method); 929 RegStorage res_reg = AllocTempRef(); 930 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 931 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 932 *cu_->dex_file, 933 type_idx)) { 934 // Call out to helper which resolves type and verifies access. 935 // Resolved type returned in kRet0. 936 if (cu_->target64) { 937 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 938 type_idx, rl_method.reg, true); 939 } else { 940 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 941 type_idx, rl_method.reg, true); 942 } 943 RegLocation rl_result = GetReturn(kRefReg); 944 StoreValue(rl_dest, rl_result); 945 } else { 946 // We're don't need access checks, load type from dex cache 947 int32_t dex_cache_offset = 948 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 949 LoadRefDisp(rl_method.reg, dex_cache_offset, res_reg, kNotVolatile); 950 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 951 LoadRefDisp(res_reg, offset_of_type, rl_result.reg, kNotVolatile); 952 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 953 type_idx) || SLOW_TYPE_PATH) { 954 // Slow path, at runtime test if type is null and if so initialize 955 FlushAllRegs(); 956 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg, 0, NULL); 957 LIR* cont = NewLIR0(kPseudoTargetLabel); 958 959 // Object to generate the slow path for class resolution. 960 class SlowPath : public LIRSlowPath { 961 public: 962 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 963 const RegLocation& rl_method, const RegLocation& rl_result) : 964 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 965 rl_method_(rl_method), rl_result_(rl_result) { 966 } 967 968 void Compile() { 969 GenerateTargetLabel(); 970 971 if (cu_->target64) { 972 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 973 rl_method_.reg, true); 974 } else { 975 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 976 rl_method_.reg, true); 977 } 978 m2l_->OpRegCopy(rl_result_.reg, m2l_->TargetReg(kRet0, kRef)); 979 980 m2l_->OpUnconditionalBranch(cont_); 981 } 982 983 private: 984 const int type_idx_; 985 const RegLocation rl_method_; 986 const RegLocation rl_result_; 987 }; 988 989 // Add to list for future. 990 AddSlowPath(new (arena_) SlowPath(this, branch, cont, type_idx, rl_method, rl_result)); 991 992 StoreValue(rl_dest, rl_result); 993 } else { 994 // Fast path, we're done - just store result 995 StoreValue(rl_dest, rl_result); 996 } 997 } 998} 999 1000void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 1001 /* NOTE: Most strings should be available at compile time */ 1002 int32_t offset_of_string = mirror::ObjectArray<mirror::String>::OffsetOfElement(string_idx). 1003 Int32Value(); 1004 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 1005 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 1006 // slow path, resolve string if not in dex cache 1007 FlushAllRegs(); 1008 LockCallTemps(); // Using explicit registers 1009 1010 // If the Method* is already in a register, we can save a copy. 1011 RegLocation rl_method = mir_graph_->GetMethodLoc(); 1012 RegStorage r_method; 1013 if (rl_method.location == kLocPhysReg) { 1014 // A temp would conflict with register use below. 1015 DCHECK(!IsTemp(rl_method.reg)); 1016 r_method = rl_method.reg; 1017 } else { 1018 r_method = TargetReg(kArg2, kRef); 1019 LoadCurrMethodDirect(r_method); 1020 } 1021 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 1022 TargetReg(kArg0, kRef), kNotVolatile); 1023 1024 // Might call out to helper, which will return resolved string in kRet0 1025 LoadRefDisp(TargetReg(kArg0, kRef), offset_of_string, TargetReg(kRet0, kRef), kNotVolatile); 1026 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0, kRef), 0, NULL); 1027 LIR* cont = NewLIR0(kPseudoTargetLabel); 1028 1029 { 1030 // Object to generate the slow path for string resolution. 1031 class SlowPath : public LIRSlowPath { 1032 public: 1033 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, RegStorage r_method, int32_t string_idx) : 1034 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), 1035 r_method_(r_method), string_idx_(string_idx) { 1036 } 1037 1038 void Compile() { 1039 GenerateTargetLabel(); 1040 if (cu_->target64) { 1041 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pResolveString), 1042 r_method_, string_idx_, true); 1043 } else { 1044 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pResolveString), 1045 r_method_, string_idx_, true); 1046 } 1047 m2l_->OpUnconditionalBranch(cont_); 1048 } 1049 1050 private: 1051 const RegStorage r_method_; 1052 const int32_t string_idx_; 1053 }; 1054 1055 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method, string_idx)); 1056 } 1057 1058 GenBarrier(); 1059 StoreValue(rl_dest, GetReturn(kRefReg)); 1060 } else { 1061 RegLocation rl_method = LoadCurrMethod(); 1062 RegStorage res_reg = AllocTempRef(); 1063 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1064 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg, 1065 kNotVolatile); 1066 LoadRefDisp(res_reg, offset_of_string, rl_result.reg, kNotVolatile); 1067 StoreValue(rl_dest, rl_result); 1068 } 1069} 1070 1071template <size_t pointer_size> 1072static void GenNewInstanceImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, uint32_t type_idx, 1073 RegLocation rl_dest) { 1074 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 1075 // alloc will always check for resolution, do we also need to verify 1076 // access because the verifier was unable to? 1077 ThreadOffset<pointer_size> func_offset(-1); 1078 const DexFile* dex_file = cu->dex_file; 1079 CompilerDriver* driver = cu->compiler_driver; 1080 if (driver->CanAccessInstantiableTypeWithoutChecks( 1081 cu->method_idx, *dex_file, type_idx)) { 1082 bool is_type_initialized; 1083 bool use_direct_type_ptr; 1084 uintptr_t direct_type_ptr; 1085 bool is_finalizable; 1086 if (kEmbedClassInCode && 1087 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 1088 &direct_type_ptr, &is_finalizable) && 1089 !is_finalizable) { 1090 // The fast path. 1091 if (!use_direct_type_ptr) { 1092 mir_to_lir->LoadClassType(type_idx, kArg0); 1093 if (!is_type_initialized) { 1094 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1095 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1096 true); 1097 } else { 1098 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1099 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1100 true); 1101 } 1102 } else { 1103 // Use the direct pointer. 1104 if (!is_type_initialized) { 1105 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1106 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1107 } else { 1108 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1109 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1110 } 1111 } 1112 } else { 1113 // The slow path. 1114 DCHECK_EQ(func_offset.Int32Value(), -1); 1115 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObject); 1116 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1117 } 1118 DCHECK_NE(func_offset.Int32Value(), -1); 1119 } else { 1120 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectWithAccessCheck); 1121 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1122 } 1123 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 1124 mir_to_lir->StoreValue(rl_dest, rl_result); 1125} 1126 1127/* 1128 * Let helper function take care of everything. Will 1129 * call Class::NewInstanceFromCode(type_idx, method); 1130 */ 1131void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 1132 if (cu_->target64) { 1133 GenNewInstanceImpl<8>(this, cu_, type_idx, rl_dest); 1134 } else { 1135 GenNewInstanceImpl<4>(this, cu_, type_idx, rl_dest); 1136 } 1137} 1138 1139void Mir2Lir::GenThrow(RegLocation rl_src) { 1140 FlushAllRegs(); 1141 if (cu_->target64) { 1142 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), rl_src, true); 1143 } else { 1144 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException), rl_src, true); 1145 } 1146} 1147 1148// For final classes there are no sub-classes to check and so we can answer the instance-of 1149// question with simple comparisons. 1150void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1151 RegLocation rl_src) { 1152 // X86 has its own implementation. 1153 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1154 1155 RegLocation object = LoadValue(rl_src, kRefReg); 1156 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1157 RegStorage result_reg = rl_result.reg; 1158 if (IsSameReg(result_reg, object.reg)) { 1159 result_reg = AllocTypedTemp(false, kCoreReg); 1160 DCHECK(!IsSameReg(result_reg, object.reg)); 1161 } 1162 LoadConstant(result_reg, 0); // assume false 1163 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 1164 1165 RegStorage check_class = AllocTypedTemp(false, kRefReg); 1166 RegStorage object_class = AllocTypedTemp(false, kRefReg); 1167 1168 LoadCurrMethodDirect(check_class); 1169 if (use_declaring_class) { 1170 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), check_class, 1171 kNotVolatile); 1172 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1173 kNotVolatile); 1174 } else { 1175 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1176 check_class, kNotVolatile); 1177 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1178 kNotVolatile); 1179 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1180 LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); 1181 } 1182 1183 // FIXME: what should we be comparing here? compressed or decompressed references? 1184 if (cu_->instruction_set == kThumb2) { 1185 OpRegReg(kOpCmp, check_class, object_class); // Same? 1186 LIR* it = OpIT(kCondEq, ""); // if-convert the test 1187 LoadConstant(result_reg, 1); // .eq case - load true 1188 OpEndIT(it); 1189 } else { 1190 GenSelectConst32(check_class, object_class, kCondEq, 1, 0, result_reg, kCoreReg); 1191 } 1192 LIR* target = NewLIR0(kPseudoTargetLabel); 1193 null_branchover->target = target; 1194 FreeTemp(object_class); 1195 FreeTemp(check_class); 1196 if (IsTemp(result_reg)) { 1197 OpRegCopy(rl_result.reg, result_reg); 1198 FreeTemp(result_reg); 1199 } 1200 StoreValue(rl_dest, rl_result); 1201} 1202 1203void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1204 bool type_known_abstract, bool use_declaring_class, 1205 bool can_assume_type_is_in_dex_cache, 1206 uint32_t type_idx, RegLocation rl_dest, 1207 RegLocation rl_src) { 1208 // X86 has its own implementation. 1209 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1210 1211 FlushAllRegs(); 1212 // May generate a call - use explicit registers 1213 LockCallTemps(); 1214 RegStorage method_reg = TargetReg(kArg1, kRef); 1215 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1216 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1217 if (needs_access_check) { 1218 // Check we have access to type_idx and if not throw IllegalAccessError, 1219 // returns Class* in kArg0 1220 if (cu_->target64) { 1221 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1222 type_idx, true); 1223 } else { 1224 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1225 type_idx, true); 1226 } 1227 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1228 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1229 } else if (use_declaring_class) { 1230 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1231 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1232 class_reg, kNotVolatile); 1233 } else { 1234 if (can_assume_type_is_in_dex_cache) { 1235 // Conditionally, as in the other case we will also load it. 1236 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1237 } 1238 1239 // Load dex cache entry into class_reg (kArg2) 1240 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1241 class_reg, kNotVolatile); 1242 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1243 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1244 if (!can_assume_type_is_in_dex_cache) { 1245 LIR* slow_path_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1246 LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); 1247 1248 // Should load value here. 1249 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1250 1251 class InitTypeSlowPath : public Mir2Lir::LIRSlowPath { 1252 public: 1253 InitTypeSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont, uint32_t type_idx, 1254 RegLocation rl_src) 1255 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont), type_idx_(type_idx), 1256 rl_src_(rl_src) { 1257 } 1258 1259 void Compile() OVERRIDE { 1260 GenerateTargetLabel(); 1261 1262 if (cu_->target64) { 1263 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1264 true); 1265 } else { 1266 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1267 true); 1268 } 1269 m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kRef), 1270 m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1271 1272 m2l_->OpUnconditionalBranch(cont_); 1273 } 1274 1275 private: 1276 uint32_t type_idx_; 1277 RegLocation rl_src_; 1278 }; 1279 1280 AddSlowPath(new (arena_) InitTypeSlowPath(this, slow_path_branch, slow_path_target, 1281 type_idx, rl_src)); 1282 } 1283 } 1284 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1285 RegLocation rl_result = GetReturn(kCoreReg); 1286 if (cu_->instruction_set == kMips) { 1287 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1288 LoadConstant(rl_result.reg, 0); 1289 } 1290 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, NULL); 1291 1292 /* load object->klass_ */ 1293 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1294 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1295 TargetReg(kArg1, kRef), kNotVolatile); 1296 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1297 LIR* branchover = NULL; 1298 if (type_known_final) { 1299 // rl_result == ref == null == 0. 1300 GenSelectConst32(TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), kCondEq, 1, 0, rl_result.reg, 1301 kCoreReg); 1302 } else { 1303 if (cu_->instruction_set == kThumb2) { 1304 RegStorage r_tgt = cu_->target64 ? 1305 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1306 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1307 LIR* it = nullptr; 1308 if (!type_known_abstract) { 1309 /* Uses conditional nullification */ 1310 OpRegReg(kOpCmp, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef)); // Same? 1311 it = OpIT(kCondEq, "EE"); // if-convert the test 1312 LoadConstant(TargetReg(kArg0, kNotWide), 1); // .eq case - load true 1313 } 1314 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1315 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1316 if (it != nullptr) { 1317 OpEndIT(it); 1318 } 1319 FreeTemp(r_tgt); 1320 } else { 1321 if (!type_known_abstract) { 1322 /* Uses branchovers */ 1323 LoadConstant(rl_result.reg, 1); // assume true 1324 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1325 } 1326 1327 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1328 if (cu_->target64) { 1329 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial), false); 1330 } else { 1331 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial), false); 1332 } 1333 } 1334 } 1335 // TODO: only clobber when type isn't final? 1336 ClobberCallerSave(); 1337 /* branch targets here */ 1338 LIR* target = NewLIR0(kPseudoTargetLabel); 1339 StoreValue(rl_dest, rl_result); 1340 branch1->target = target; 1341 if (branchover != NULL) { 1342 branchover->target = target; 1343 } 1344} 1345 1346void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1347 bool type_known_final, type_known_abstract, use_declaring_class; 1348 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1349 *cu_->dex_file, 1350 type_idx, 1351 &type_known_final, 1352 &type_known_abstract, 1353 &use_declaring_class); 1354 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1355 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1356 1357 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1358 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1359 } else { 1360 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1361 use_declaring_class, can_assume_type_is_in_dex_cache, 1362 type_idx, rl_dest, rl_src); 1363 } 1364} 1365 1366void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1367 bool type_known_final, type_known_abstract, use_declaring_class; 1368 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1369 *cu_->dex_file, 1370 type_idx, 1371 &type_known_final, 1372 &type_known_abstract, 1373 &use_declaring_class); 1374 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1375 // of the exception throw path. 1376 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1377 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1378 // Verifier type analysis proved this check cast would never cause an exception. 1379 return; 1380 } 1381 FlushAllRegs(); 1382 // May generate a call - use explicit registers 1383 LockCallTemps(); 1384 RegStorage method_reg = TargetReg(kArg1, kRef); 1385 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1386 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1387 if (needs_access_check) { 1388 // Check we have access to type_idx and if not throw IllegalAccessError, 1389 // returns Class* in kRet0 1390 // InitializeTypeAndVerifyAccess(idx, method) 1391 if (cu_->target64) { 1392 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1393 type_idx, true); 1394 } else { 1395 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1396 type_idx, true); 1397 } 1398 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1399 } else if (use_declaring_class) { 1400 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1401 class_reg, kNotVolatile); 1402 } else { 1403 // Load dex cache entry into class_reg (kArg2) 1404 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1405 class_reg, kNotVolatile); 1406 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1407 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1408 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1409 // Need to test presence of type in dex cache at runtime 1410 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1411 LIR* cont = NewLIR0(kPseudoTargetLabel); 1412 1413 // Slow path to initialize the type. Executed if the type is NULL. 1414 class SlowPath : public LIRSlowPath { 1415 public: 1416 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1417 const RegStorage class_reg) : 1418 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1419 class_reg_(class_reg) { 1420 } 1421 1422 void Compile() { 1423 GenerateTargetLabel(); 1424 1425 // Call out to helper, which will return resolved type in kArg0 1426 // InitializeTypeFromCode(idx, method) 1427 if (m2l_->cu_->target64) { 1428 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1429 m2l_->TargetReg(kArg1, kRef), true); 1430 } else { 1431 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1432 m2l_->TargetReg(kArg1, kRef), true); 1433 } 1434 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1435 m2l_->OpUnconditionalBranch(cont_); 1436 } 1437 1438 public: 1439 const int type_idx_; 1440 const RegStorage class_reg_; 1441 }; 1442 1443 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, type_idx, class_reg)); 1444 } 1445 } 1446 // At this point, class_reg (kArg2) has class 1447 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1448 1449 // Slow path for the case where the classes are not equal. In this case we need 1450 // to call a helper function to do the check. 1451 class SlowPath : public LIRSlowPath { 1452 public: 1453 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1454 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1455 } 1456 1457 void Compile() { 1458 GenerateTargetLabel(); 1459 1460 if (load_) { 1461 m2l_->LoadRefDisp(m2l_->TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1462 m2l_->TargetReg(kArg1, kRef), kNotVolatile); 1463 } 1464 if (m2l_->cu_->target64) { 1465 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pCheckCast), 1466 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1467 true); 1468 } else { 1469 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pCheckCast), 1470 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1471 true); 1472 } 1473 1474 m2l_->OpUnconditionalBranch(cont_); 1475 } 1476 1477 private: 1478 const bool load_; 1479 }; 1480 1481 if (type_known_abstract) { 1482 // Easier case, run slow path if target is non-null (slow path will load from target) 1483 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0, kRef), 0, nullptr); 1484 LIR* cont = NewLIR0(kPseudoTargetLabel); 1485 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1486 } else { 1487 // Harder, more common case. We need to generate a forward branch over the load 1488 // if the target is null. If it's non-null we perform the load and branch to the 1489 // slow path if the classes are not equal. 1490 1491 /* Null is OK - continue */ 1492 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, nullptr); 1493 /* load object->klass_ */ 1494 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1495 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1496 TargetReg(kArg1, kRef), kNotVolatile); 1497 1498 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), class_reg, nullptr); 1499 LIR* cont = NewLIR0(kPseudoTargetLabel); 1500 1501 // Add the slow path that will not perform load since this is already done. 1502 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1503 1504 // Set the null check to branch to the continuation. 1505 branch1->target = cont; 1506 } 1507} 1508 1509void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1510 RegLocation rl_src1, RegLocation rl_src2) { 1511 RegLocation rl_result; 1512 if (cu_->instruction_set == kThumb2) { 1513 /* 1514 * NOTE: This is the one place in the code in which we might have 1515 * as many as six live temporary registers. There are 5 in the normal 1516 * set for Arm. Until we have spill capabilities, temporarily add 1517 * lr to the temp set. It is safe to do this locally, but note that 1518 * lr is used explicitly elsewhere in the code generator and cannot 1519 * normally be used as a general temp register. 1520 */ 1521 MarkTemp(TargetReg(kLr, kNotWide)); // Add lr to the temp pool 1522 FreeTemp(TargetReg(kLr, kNotWide)); // and make it available 1523 } 1524 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1525 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1526 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1527 // The longs may overlap - use intermediate temp if so 1528 if ((rl_result.reg.GetLowReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg())) { 1529 RegStorage t_reg = AllocTemp(); 1530 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1531 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1532 OpRegCopy(rl_result.reg.GetLow(), t_reg); 1533 FreeTemp(t_reg); 1534 } else { 1535 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1536 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1537 } 1538 /* 1539 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1540 * following StoreValueWide might need to allocate a temp register. 1541 * To further work around the lack of a spill capability, explicitly 1542 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1543 * Remove when spill is functional. 1544 */ 1545 FreeRegLocTemps(rl_result, rl_src1); 1546 FreeRegLocTemps(rl_result, rl_src2); 1547 StoreValueWide(rl_dest, rl_result); 1548 if (cu_->instruction_set == kThumb2) { 1549 Clobber(TargetReg(kLr, kNotWide)); 1550 UnmarkTemp(TargetReg(kLr, kNotWide)); // Remove lr from the temp pool 1551 } 1552} 1553 1554 1555template <size_t pointer_size> 1556static void GenShiftOpLongCall(Mir2Lir* mir_to_lir, Instruction::Code opcode, RegLocation rl_src1, 1557 RegLocation rl_shift) { 1558 ThreadOffset<pointer_size> func_offset(-1); 1559 1560 switch (opcode) { 1561 case Instruction::SHL_LONG: 1562 case Instruction::SHL_LONG_2ADDR: 1563 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShlLong); 1564 break; 1565 case Instruction::SHR_LONG: 1566 case Instruction::SHR_LONG_2ADDR: 1567 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShrLong); 1568 break; 1569 case Instruction::USHR_LONG: 1570 case Instruction::USHR_LONG_2ADDR: 1571 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pUshrLong); 1572 break; 1573 default: 1574 LOG(FATAL) << "Unexpected case"; 1575 } 1576 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 1577 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1578} 1579 1580void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1581 RegLocation rl_src1, RegLocation rl_shift) { 1582 if (cu_->target64) { 1583 GenShiftOpLongCall<8>(this, opcode, rl_src1, rl_shift); 1584 } else { 1585 GenShiftOpLongCall<4>(this, opcode, rl_src1, rl_shift); 1586 } 1587 RegLocation rl_result = GetReturnWide(kCoreReg); 1588 StoreValueWide(rl_dest, rl_result); 1589} 1590 1591 1592void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1593 RegLocation rl_src1, RegLocation rl_src2) { 1594 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1595 OpKind op = kOpBkpt; 1596 bool is_div_rem = false; 1597 bool check_zero = false; 1598 bool unary = false; 1599 RegLocation rl_result; 1600 bool shift_op = false; 1601 switch (opcode) { 1602 case Instruction::NEG_INT: 1603 op = kOpNeg; 1604 unary = true; 1605 break; 1606 case Instruction::NOT_INT: 1607 op = kOpMvn; 1608 unary = true; 1609 break; 1610 case Instruction::ADD_INT: 1611 case Instruction::ADD_INT_2ADDR: 1612 op = kOpAdd; 1613 break; 1614 case Instruction::SUB_INT: 1615 case Instruction::SUB_INT_2ADDR: 1616 op = kOpSub; 1617 break; 1618 case Instruction::MUL_INT: 1619 case Instruction::MUL_INT_2ADDR: 1620 op = kOpMul; 1621 break; 1622 case Instruction::DIV_INT: 1623 case Instruction::DIV_INT_2ADDR: 1624 check_zero = true; 1625 op = kOpDiv; 1626 is_div_rem = true; 1627 break; 1628 /* NOTE: returns in kArg1 */ 1629 case Instruction::REM_INT: 1630 case Instruction::REM_INT_2ADDR: 1631 check_zero = true; 1632 op = kOpRem; 1633 is_div_rem = true; 1634 break; 1635 case Instruction::AND_INT: 1636 case Instruction::AND_INT_2ADDR: 1637 op = kOpAnd; 1638 break; 1639 case Instruction::OR_INT: 1640 case Instruction::OR_INT_2ADDR: 1641 op = kOpOr; 1642 break; 1643 case Instruction::XOR_INT: 1644 case Instruction::XOR_INT_2ADDR: 1645 op = kOpXor; 1646 break; 1647 case Instruction::SHL_INT: 1648 case Instruction::SHL_INT_2ADDR: 1649 shift_op = true; 1650 op = kOpLsl; 1651 break; 1652 case Instruction::SHR_INT: 1653 case Instruction::SHR_INT_2ADDR: 1654 shift_op = true; 1655 op = kOpAsr; 1656 break; 1657 case Instruction::USHR_INT: 1658 case Instruction::USHR_INT_2ADDR: 1659 shift_op = true; 1660 op = kOpLsr; 1661 break; 1662 default: 1663 LOG(FATAL) << "Invalid word arith op: " << opcode; 1664 } 1665 if (!is_div_rem) { 1666 if (unary) { 1667 rl_src1 = LoadValue(rl_src1, kCoreReg); 1668 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1669 OpRegReg(op, rl_result.reg, rl_src1.reg); 1670 } else { 1671 if ((shift_op) && (cu_->instruction_set != kArm64)) { 1672 rl_src2 = LoadValue(rl_src2, kCoreReg); 1673 RegStorage t_reg = AllocTemp(); 1674 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg, 31); 1675 rl_src1 = LoadValue(rl_src1, kCoreReg); 1676 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1677 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 1678 FreeTemp(t_reg); 1679 } else { 1680 rl_src1 = LoadValue(rl_src1, kCoreReg); 1681 rl_src2 = LoadValue(rl_src2, kCoreReg); 1682 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1683 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); 1684 } 1685 } 1686 StoreValue(rl_dest, rl_result); 1687 } else { 1688 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1689 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1690 rl_src1 = LoadValue(rl_src1, kCoreReg); 1691 rl_src2 = LoadValue(rl_src2, kCoreReg); 1692 if (check_zero) { 1693 GenDivZeroCheck(rl_src2.reg); 1694 } 1695 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1696 done = true; 1697 } else if (cu_->instruction_set == kThumb2) { 1698 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1699 // Use ARM SDIV instruction for division. For remainder we also need to 1700 // calculate using a MUL and subtract. 1701 rl_src1 = LoadValue(rl_src1, kCoreReg); 1702 rl_src2 = LoadValue(rl_src2, kCoreReg); 1703 if (check_zero) { 1704 GenDivZeroCheck(rl_src2.reg); 1705 } 1706 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1707 done = true; 1708 } 1709 } 1710 1711 // If we haven't already generated the code use the callout function. 1712 if (!done) { 1713 FlushAllRegs(); /* Send everything to home location */ 1714 LoadValueDirectFixed(rl_src2, TargetReg(kArg1, kNotWide)); 1715 RegStorage r_tgt = cu_->target64 ? 1716 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod)) : 1717 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod)); 1718 LoadValueDirectFixed(rl_src1, TargetReg(kArg0, kNotWide)); 1719 if (check_zero) { 1720 GenDivZeroCheck(TargetReg(kArg1, kNotWide)); 1721 } 1722 // NOTE: callout here is not a safepoint. 1723 if (cu_->target64) { 1724 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), false /* not a safepoint */); 1725 } else { 1726 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), false /* not a safepoint */); 1727 } 1728 if (op == kOpDiv) 1729 rl_result = GetReturn(kCoreReg); 1730 else 1731 rl_result = GetReturnAlt(); 1732 } 1733 StoreValue(rl_dest, rl_result); 1734 } 1735} 1736 1737/* 1738 * The following are the first-level codegen routines that analyze the format 1739 * of each bytecode then either dispatch special purpose codegen routines 1740 * or produce corresponding Thumb instructions directly. 1741 */ 1742 1743// Returns true if no more than two bits are set in 'x'. 1744static bool IsPopCountLE2(unsigned int x) { 1745 x &= x - 1; 1746 return (x & (x - 1)) == 0; 1747} 1748 1749// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1750// and store the result in 'rl_dest'. 1751bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1752 RegLocation rl_src, RegLocation rl_dest, int lit) { 1753 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1754 return false; 1755 } 1756 // No divide instruction for Arm, so check for more special cases 1757 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1758 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1759 } 1760 int k = LowestSetBit(lit); 1761 if (k >= 30) { 1762 // Avoid special cases. 1763 return false; 1764 } 1765 rl_src = LoadValue(rl_src, kCoreReg); 1766 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1767 if (is_div) { 1768 RegStorage t_reg = AllocTemp(); 1769 if (lit == 2) { 1770 // Division by 2 is by far the most common division by constant. 1771 OpRegRegImm(kOpLsr, t_reg, rl_src.reg, 32 - k); 1772 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1773 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1774 } else { 1775 OpRegRegImm(kOpAsr, t_reg, rl_src.reg, 31); 1776 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1777 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1778 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1779 } 1780 } else { 1781 RegStorage t_reg1 = AllocTemp(); 1782 RegStorage t_reg2 = AllocTemp(); 1783 if (lit == 2) { 1784 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg, 32 - k); 1785 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1786 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1787 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1788 } else { 1789 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg, 31); 1790 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1791 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1792 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1793 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1794 } 1795 } 1796 StoreValue(rl_dest, rl_result); 1797 return true; 1798} 1799 1800// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1801// and store the result in 'rl_dest'. 1802bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1803 if (lit < 0) { 1804 return false; 1805 } 1806 if (lit == 0) { 1807 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1808 LoadConstant(rl_result.reg, 0); 1809 StoreValue(rl_dest, rl_result); 1810 return true; 1811 } 1812 if (lit == 1) { 1813 rl_src = LoadValue(rl_src, kCoreReg); 1814 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1815 OpRegCopy(rl_result.reg, rl_src.reg); 1816 StoreValue(rl_dest, rl_result); 1817 return true; 1818 } 1819 // There is RegRegRegShift on Arm, so check for more special cases 1820 if (cu_->instruction_set == kThumb2) { 1821 return EasyMultiply(rl_src, rl_dest, lit); 1822 } 1823 // Can we simplify this multiplication? 1824 bool power_of_two = false; 1825 bool pop_count_le2 = false; 1826 bool power_of_two_minus_one = false; 1827 if (IsPowerOfTwo(lit)) { 1828 power_of_two = true; 1829 } else if (IsPopCountLE2(lit)) { 1830 pop_count_le2 = true; 1831 } else if (IsPowerOfTwo(lit + 1)) { 1832 power_of_two_minus_one = true; 1833 } else { 1834 return false; 1835 } 1836 rl_src = LoadValue(rl_src, kCoreReg); 1837 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1838 if (power_of_two) { 1839 // Shift. 1840 OpRegRegImm(kOpLsl, rl_result.reg, rl_src.reg, LowestSetBit(lit)); 1841 } else if (pop_count_le2) { 1842 // Shift and add and shift. 1843 int first_bit = LowestSetBit(lit); 1844 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1845 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1846 } else { 1847 // Reverse subtract: (src << (shift + 1)) - src. 1848 DCHECK(power_of_two_minus_one); 1849 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1850 RegStorage t_reg = AllocTemp(); 1851 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, LowestSetBit(lit + 1)); 1852 OpRegRegReg(kOpSub, rl_result.reg, t_reg, rl_src.reg); 1853 } 1854 StoreValue(rl_dest, rl_result); 1855 return true; 1856} 1857 1858void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1859 int lit) { 1860 RegLocation rl_result; 1861 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1862 int shift_op = false; 1863 bool is_div = false; 1864 1865 switch (opcode) { 1866 case Instruction::RSUB_INT_LIT8: 1867 case Instruction::RSUB_INT: { 1868 rl_src = LoadValue(rl_src, kCoreReg); 1869 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1870 if (cu_->instruction_set == kThumb2) { 1871 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, lit); 1872 } else { 1873 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1874 OpRegImm(kOpAdd, rl_result.reg, lit); 1875 } 1876 StoreValue(rl_dest, rl_result); 1877 return; 1878 } 1879 1880 case Instruction::SUB_INT: 1881 case Instruction::SUB_INT_2ADDR: 1882 lit = -lit; 1883 // Intended fallthrough 1884 case Instruction::ADD_INT: 1885 case Instruction::ADD_INT_2ADDR: 1886 case Instruction::ADD_INT_LIT8: 1887 case Instruction::ADD_INT_LIT16: 1888 op = kOpAdd; 1889 break; 1890 case Instruction::MUL_INT: 1891 case Instruction::MUL_INT_2ADDR: 1892 case Instruction::MUL_INT_LIT8: 1893 case Instruction::MUL_INT_LIT16: { 1894 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1895 return; 1896 } 1897 op = kOpMul; 1898 break; 1899 } 1900 case Instruction::AND_INT: 1901 case Instruction::AND_INT_2ADDR: 1902 case Instruction::AND_INT_LIT8: 1903 case Instruction::AND_INT_LIT16: 1904 op = kOpAnd; 1905 break; 1906 case Instruction::OR_INT: 1907 case Instruction::OR_INT_2ADDR: 1908 case Instruction::OR_INT_LIT8: 1909 case Instruction::OR_INT_LIT16: 1910 op = kOpOr; 1911 break; 1912 case Instruction::XOR_INT: 1913 case Instruction::XOR_INT_2ADDR: 1914 case Instruction::XOR_INT_LIT8: 1915 case Instruction::XOR_INT_LIT16: 1916 op = kOpXor; 1917 break; 1918 case Instruction::SHL_INT_LIT8: 1919 case Instruction::SHL_INT: 1920 case Instruction::SHL_INT_2ADDR: 1921 lit &= 31; 1922 shift_op = true; 1923 op = kOpLsl; 1924 break; 1925 case Instruction::SHR_INT_LIT8: 1926 case Instruction::SHR_INT: 1927 case Instruction::SHR_INT_2ADDR: 1928 lit &= 31; 1929 shift_op = true; 1930 op = kOpAsr; 1931 break; 1932 case Instruction::USHR_INT_LIT8: 1933 case Instruction::USHR_INT: 1934 case Instruction::USHR_INT_2ADDR: 1935 lit &= 31; 1936 shift_op = true; 1937 op = kOpLsr; 1938 break; 1939 1940 case Instruction::DIV_INT: 1941 case Instruction::DIV_INT_2ADDR: 1942 case Instruction::DIV_INT_LIT8: 1943 case Instruction::DIV_INT_LIT16: 1944 case Instruction::REM_INT: 1945 case Instruction::REM_INT_2ADDR: 1946 case Instruction::REM_INT_LIT8: 1947 case Instruction::REM_INT_LIT16: { 1948 if (lit == 0) { 1949 GenDivZeroException(); 1950 return; 1951 } 1952 if ((opcode == Instruction::DIV_INT) || 1953 (opcode == Instruction::DIV_INT_2ADDR) || 1954 (opcode == Instruction::DIV_INT_LIT8) || 1955 (opcode == Instruction::DIV_INT_LIT16)) { 1956 is_div = true; 1957 } else { 1958 is_div = false; 1959 } 1960 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1961 return; 1962 } 1963 1964 bool done = false; 1965 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1966 rl_src = LoadValue(rl_src, kCoreReg); 1967 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1968 done = true; 1969 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1970 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1971 done = true; 1972 } else if (cu_->instruction_set == kThumb2) { 1973 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1974 // Use ARM SDIV instruction for division. For remainder we also need to 1975 // calculate using a MUL and subtract. 1976 rl_src = LoadValue(rl_src, kCoreReg); 1977 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1978 done = true; 1979 } 1980 } 1981 1982 if (!done) { 1983 FlushAllRegs(); /* Everything to home location. */ 1984 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kNotWide)); 1985 Clobber(TargetReg(kArg0, kNotWide)); 1986 if (cu_->target64) { 1987 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), TargetReg(kArg0, kNotWide), 1988 lit, false); 1989 } else { 1990 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), TargetReg(kArg0, kNotWide), 1991 lit, false); 1992 } 1993 if (is_div) 1994 rl_result = GetReturn(kCoreReg); 1995 else 1996 rl_result = GetReturnAlt(); 1997 } 1998 StoreValue(rl_dest, rl_result); 1999 return; 2000 } 2001 default: 2002 LOG(FATAL) << "Unexpected opcode " << opcode; 2003 } 2004 rl_src = LoadValue(rl_src, kCoreReg); 2005 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2006 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 2007 if (shift_op && (lit == 0)) { 2008 OpRegCopy(rl_result.reg, rl_src.reg); 2009 } else { 2010 OpRegRegImm(op, rl_result.reg, rl_src.reg, lit); 2011 } 2012 StoreValue(rl_dest, rl_result); 2013} 2014 2015template <size_t pointer_size> 2016static void GenArithOpLongImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, Instruction::Code opcode, 2017 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 2018 RegLocation rl_result; 2019 OpKind first_op = kOpBkpt; 2020 OpKind second_op = kOpBkpt; 2021 bool call_out = false; 2022 bool check_zero = false; 2023 ThreadOffset<pointer_size> func_offset(-1); 2024 int ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2025 2026 switch (opcode) { 2027 case Instruction::NOT_LONG: 2028 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2029 mir_to_lir->GenNotLong(rl_dest, rl_src2); 2030 return; 2031 } 2032 rl_src2 = mir_to_lir->LoadValueWide(rl_src2, kCoreReg); 2033 rl_result = mir_to_lir->EvalLoc(rl_dest, kCoreReg, true); 2034 // Check for destructive overlap 2035 if (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg()) { 2036 RegStorage t_reg = mir_to_lir->AllocTemp(); 2037 mir_to_lir->OpRegCopy(t_reg, rl_src2.reg.GetHigh()); 2038 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2039 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), t_reg); 2040 mir_to_lir->FreeTemp(t_reg); 2041 } else { 2042 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2043 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); 2044 } 2045 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2046 return; 2047 case Instruction::ADD_LONG: 2048 case Instruction::ADD_LONG_2ADDR: 2049 if (cu->instruction_set != kThumb2) { 2050 mir_to_lir->GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 2051 return; 2052 } 2053 first_op = kOpAdd; 2054 second_op = kOpAdc; 2055 break; 2056 case Instruction::SUB_LONG: 2057 case Instruction::SUB_LONG_2ADDR: 2058 if (cu->instruction_set != kThumb2) { 2059 mir_to_lir->GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 2060 return; 2061 } 2062 first_op = kOpSub; 2063 second_op = kOpSbc; 2064 break; 2065 case Instruction::MUL_LONG: 2066 case Instruction::MUL_LONG_2ADDR: 2067 if (cu->instruction_set != kMips) { 2068 mir_to_lir->GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 2069 return; 2070 } else { 2071 call_out = true; 2072 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2073 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmul); 2074 } 2075 break; 2076 case Instruction::DIV_LONG: 2077 case Instruction::DIV_LONG_2ADDR: 2078 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2079 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); 2080 return; 2081 } 2082 call_out = true; 2083 check_zero = true; 2084 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2085 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLdiv); 2086 break; 2087 case Instruction::REM_LONG: 2088 case Instruction::REM_LONG_2ADDR: 2089 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2090 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); 2091 return; 2092 } 2093 call_out = true; 2094 check_zero = true; 2095 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmod); 2096 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 2097 ret_reg = (cu->instruction_set == kThumb2) ? mir_to_lir->TargetReg(kArg2, kNotWide).GetReg() : 2098 mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2099 break; 2100 case Instruction::AND_LONG_2ADDR: 2101 case Instruction::AND_LONG: 2102 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2103 cu->instruction_set == kArm64) { 2104 return mir_to_lir->GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 2105 } 2106 first_op = kOpAnd; 2107 second_op = kOpAnd; 2108 break; 2109 case Instruction::OR_LONG: 2110 case Instruction::OR_LONG_2ADDR: 2111 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2112 cu->instruction_set == kArm64) { 2113 mir_to_lir->GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 2114 return; 2115 } 2116 first_op = kOpOr; 2117 second_op = kOpOr; 2118 break; 2119 case Instruction::XOR_LONG: 2120 case Instruction::XOR_LONG_2ADDR: 2121 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2122 cu->instruction_set == kArm64) { 2123 mir_to_lir->GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 2124 return; 2125 } 2126 first_op = kOpXor; 2127 second_op = kOpXor; 2128 break; 2129 case Instruction::NEG_LONG: { 2130 mir_to_lir->GenNegLong(rl_dest, rl_src2); 2131 return; 2132 } 2133 default: 2134 LOG(FATAL) << "Invalid long arith op"; 2135 } 2136 if (!call_out) { 2137 mir_to_lir->GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 2138 } else { 2139 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 2140 if (check_zero) { 2141 RegStorage r_tmp1 = mir_to_lir->TargetReg(kArg0, kWide); 2142 RegStorage r_tmp2 = mir_to_lir->TargetReg(kArg2, kWide); 2143 mir_to_lir->LoadValueDirectWideFixed(rl_src2, r_tmp2); 2144 RegStorage r_tgt = mir_to_lir->CallHelperSetup(func_offset); 2145 mir_to_lir->GenDivZeroCheckWide(r_tmp2); 2146 mir_to_lir->LoadValueDirectWideFixed(rl_src1, r_tmp1); 2147 // NOTE: callout here is not a safepoint 2148 mir_to_lir->CallHelper(r_tgt, func_offset, false /* not safepoint */); 2149 } else { 2150 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 2151 } 2152 // Adjust return regs in to handle case of rem returning kArg2/kArg3 2153 if (ret_reg == mir_to_lir->TargetReg(kRet0, kNotWide).GetReg()) 2154 rl_result = mir_to_lir->GetReturnWide(kCoreReg); 2155 else 2156 rl_result = mir_to_lir->GetReturnWideAlt(); 2157 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2158 } 2159} 2160 2161void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 2162 RegLocation rl_src1, RegLocation rl_src2) { 2163 if (cu_->target64) { 2164 GenArithOpLongImpl<8>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2165 } else { 2166 GenArithOpLongImpl<4>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2167 } 2168} 2169 2170void Mir2Lir::GenConst(RegLocation rl_dest, int value) { 2171 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2172 LoadConstantNoClobber(rl_result.reg, value); 2173 StoreValue(rl_dest, rl_result); 2174 if (value == 0) { 2175 Workaround7250540(rl_dest, rl_result.reg); 2176 } 2177} 2178 2179template <size_t pointer_size> 2180void Mir2Lir::GenConversionCall(ThreadOffset<pointer_size> func_offset, 2181 RegLocation rl_dest, RegLocation rl_src) { 2182 /* 2183 * Don't optimize the register usage since it calls out to support 2184 * functions 2185 */ 2186 DCHECK_EQ(pointer_size, GetInstructionSetPointerSize(cu_->instruction_set)); 2187 2188 FlushAllRegs(); /* Send everything to home location */ 2189 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 2190 if (rl_dest.wide) { 2191 RegLocation rl_result; 2192 rl_result = GetReturnWide(LocToRegClass(rl_dest)); 2193 StoreValueWide(rl_dest, rl_result); 2194 } else { 2195 RegLocation rl_result; 2196 rl_result = GetReturn(LocToRegClass(rl_dest)); 2197 StoreValue(rl_dest, rl_result); 2198 } 2199} 2200template void Mir2Lir::GenConversionCall(ThreadOffset<4> func_offset, 2201 RegLocation rl_dest, RegLocation rl_src); 2202template void Mir2Lir::GenConversionCall(ThreadOffset<8> func_offset, 2203 RegLocation rl_dest, RegLocation rl_src); 2204 2205class SuspendCheckSlowPath : public Mir2Lir::LIRSlowPath { 2206 public: 2207 SuspendCheckSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont) 2208 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont) { 2209 } 2210 2211 void Compile() OVERRIDE { 2212 m2l_->ResetRegPool(); 2213 m2l_->ResetDefTracking(); 2214 GenerateTargetLabel(kPseudoSuspendTarget); 2215 if (cu_->target64) { 2216 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pTestSuspend), true); 2217 } else { 2218 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pTestSuspend), true); 2219 } 2220 if (cont_ != nullptr) { 2221 m2l_->OpUnconditionalBranch(cont_); 2222 } 2223 } 2224}; 2225 2226/* Check if we need to check for pending suspend request */ 2227void Mir2Lir::GenSuspendTest(int opt_flags) { 2228 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2229 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2230 return; 2231 } 2232 FlushAllRegs(); 2233 LIR* branch = OpTestSuspend(NULL); 2234 LIR* cont = NewLIR0(kPseudoTargetLabel); 2235 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, cont)); 2236 } else { 2237 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2238 return; 2239 } 2240 FlushAllRegs(); // TODO: needed? 2241 LIR* inst = CheckSuspendUsingLoad(); 2242 MarkSafepointPC(inst); 2243 } 2244} 2245 2246/* Check if we need to check for pending suspend request */ 2247void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 2248 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2249 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2250 OpUnconditionalBranch(target); 2251 return; 2252 } 2253 OpTestSuspend(target); 2254 FlushAllRegs(); 2255 LIR* branch = OpUnconditionalBranch(nullptr); 2256 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, target)); 2257 } else { 2258 // For the implicit suspend check, just perform the trigger 2259 // load and branch to the target. 2260 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2261 OpUnconditionalBranch(target); 2262 return; 2263 } 2264 FlushAllRegs(); 2265 LIR* inst = CheckSuspendUsingLoad(); 2266 MarkSafepointPC(inst); 2267 OpUnconditionalBranch(target); 2268 } 2269} 2270 2271/* Call out to helper assembly routine that will null check obj and then lock it. */ 2272void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2273 FlushAllRegs(); 2274 if (cu_->target64) { 2275 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pLockObject), rl_src, true); 2276 } else { 2277 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pLockObject), rl_src, true); 2278 } 2279} 2280 2281/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2282void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2283 FlushAllRegs(); 2284 if (cu_->target64) { 2285 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject), rl_src, true); 2286 } else { 2287 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject), rl_src, true); 2288 } 2289} 2290 2291/* Generic code for generating a wide constant into a VR. */ 2292void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2293 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2294 LoadConstantWide(rl_result.reg, value); 2295 StoreValueWide(rl_dest, rl_result); 2296} 2297 2298} // namespace art 2299