gen_common.cc revision 0d507d1e0441e6bd6f3affca3a60774ea920f317
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "dex/compiler_ir.h" 18#include "dex/compiler_internals.h" 19#include "dex/quick/arm/arm_lir.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "entrypoints/quick/quick_entrypoints.h" 22#include "mirror/array.h" 23#include "mirror/object-inl.h" 24#include "verifier/method_verifier.h" 25#include <functional> 26 27namespace art { 28 29/* 30 * This source files contains "gen" codegen routines that should 31 * be applicable to most targets. Only mid-level support utilities 32 * and "op" calls may be used here. 33 */ 34 35/* 36 * Generate a kPseudoBarrier marker to indicate the boundary of special 37 * blocks. 38 */ 39void Mir2Lir::GenBarrier() { 40 LIR* barrier = NewLIR0(kPseudoBarrier); 41 /* Mark all resources as being clobbered */ 42 DCHECK(!barrier->flags.use_def_invalid); 43 barrier->u.m.def_mask = ENCODE_ALL; 44} 45 46// TODO: need to do some work to split out targets with 47// condition codes and those without 48LIR* Mir2Lir::GenCheck(ConditionCode c_code, ThrowKind kind) { 49 DCHECK_NE(cu_->instruction_set, kMips); 50 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_); 51 LIR* branch = OpCondBranch(c_code, tgt); 52 // Remember branch target - will process later 53 throw_launchpads_.Insert(tgt); 54 return branch; 55} 56 57LIR* Mir2Lir::GenImmedCheck(ConditionCode c_code, int reg, int imm_val, ThrowKind kind) { 58 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg, imm_val); 59 LIR* branch; 60 if (c_code == kCondAl) { 61 branch = OpUnconditionalBranch(tgt); 62 } else { 63 branch = OpCmpImmBranch(c_code, reg, imm_val, tgt); 64 } 65 // Remember branch target - will process later 66 throw_launchpads_.Insert(tgt); 67 return branch; 68} 69 70 71/* Perform null-check on a register. */ 72LIR* Mir2Lir::GenNullCheck(int m_reg, int opt_flags) { 73 if (Runtime::Current()->ExplicitNullChecks()) { 74 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 75 return NULL; 76 } 77 return GenImmedCheck(kCondEq, m_reg, 0, kThrowNullPointer); 78 } 79 return nullptr; 80} 81 82void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 83 if (!Runtime::Current()->ExplicitNullChecks()) { 84 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 85 return; 86 } 87 MarkSafepointPC(last_lir_insn_); 88 } 89} 90 91void Mir2Lir::MarkPossibleStackOverflowException() { 92 if (!Runtime::Current()->ExplicitStackOverflowChecks()) { 93 MarkSafepointPC(last_lir_insn_); 94 } 95} 96 97void Mir2Lir::ForceImplicitNullCheck(int reg, int opt_flags) { 98 if (!Runtime::Current()->ExplicitNullChecks()) { 99 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 100 return; 101 } 102 // Force an implicit null check by performing a memory operation (load) from the given 103 // register with offset 0. This will cause a signal if the register contains 0 (null). 104 int tmp = AllocTemp(); 105 LIR* load = LoadWordDisp(reg, 0, tmp); 106 FreeTemp(tmp); 107 MarkSafepointPC(load); 108 } 109} 110 111/* Perform check on two registers */ 112LIR* Mir2Lir::GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 113 ThrowKind kind) { 114 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg1, reg2); 115 LIR* branch = OpCmpBranch(c_code, reg1, reg2, tgt); 116 // Remember branch target - will process later 117 throw_launchpads_.Insert(tgt); 118 return branch; 119} 120 121void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 122 RegLocation rl_src2, LIR* taken, 123 LIR* fall_through) { 124 ConditionCode cond; 125 switch (opcode) { 126 case Instruction::IF_EQ: 127 cond = kCondEq; 128 break; 129 case Instruction::IF_NE: 130 cond = kCondNe; 131 break; 132 case Instruction::IF_LT: 133 cond = kCondLt; 134 break; 135 case Instruction::IF_GE: 136 cond = kCondGe; 137 break; 138 case Instruction::IF_GT: 139 cond = kCondGt; 140 break; 141 case Instruction::IF_LE: 142 cond = kCondLe; 143 break; 144 default: 145 cond = static_cast<ConditionCode>(0); 146 LOG(FATAL) << "Unexpected opcode " << opcode; 147 } 148 149 // Normalize such that if either operand is constant, src2 will be constant 150 if (rl_src1.is_const) { 151 RegLocation rl_temp = rl_src1; 152 rl_src1 = rl_src2; 153 rl_src2 = rl_temp; 154 cond = FlipComparisonOrder(cond); 155 } 156 157 rl_src1 = LoadValue(rl_src1, kCoreReg); 158 // Is this really an immediate comparison? 159 if (rl_src2.is_const) { 160 // If it's already live in a register or not easily materialized, just keep going 161 RegLocation rl_temp = UpdateLoc(rl_src2); 162 if ((rl_temp.location == kLocDalvikFrame) && 163 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 164 // OK - convert this to a compare immediate and branch 165 OpCmpImmBranch(cond, rl_src1.reg.GetReg(), mir_graph_->ConstantValue(rl_src2), taken); 166 return; 167 } 168 } 169 rl_src2 = LoadValue(rl_src2, kCoreReg); 170 OpCmpBranch(cond, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), taken); 171} 172 173void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 174 LIR* fall_through) { 175 ConditionCode cond; 176 rl_src = LoadValue(rl_src, kCoreReg); 177 switch (opcode) { 178 case Instruction::IF_EQZ: 179 cond = kCondEq; 180 break; 181 case Instruction::IF_NEZ: 182 cond = kCondNe; 183 break; 184 case Instruction::IF_LTZ: 185 cond = kCondLt; 186 break; 187 case Instruction::IF_GEZ: 188 cond = kCondGe; 189 break; 190 case Instruction::IF_GTZ: 191 cond = kCondGt; 192 break; 193 case Instruction::IF_LEZ: 194 cond = kCondLe; 195 break; 196 default: 197 cond = static_cast<ConditionCode>(0); 198 LOG(FATAL) << "Unexpected opcode " << opcode; 199 } 200 OpCmpImmBranch(cond, rl_src.reg.GetReg(), 0, taken); 201} 202 203void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 204 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 205 if (rl_src.location == kLocPhysReg) { 206 OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg()); 207 } else { 208 LoadValueDirect(rl_src, rl_result.reg.GetReg()); 209 } 210 OpRegRegImm(kOpAsr, rl_result.reg.GetHighReg(), rl_result.reg.GetReg(), 31); 211 StoreValueWide(rl_dest, rl_result); 212} 213 214void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 215 RegLocation rl_src) { 216 rl_src = LoadValue(rl_src, kCoreReg); 217 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 218 OpKind op = kOpInvalid; 219 switch (opcode) { 220 case Instruction::INT_TO_BYTE: 221 op = kOp2Byte; 222 break; 223 case Instruction::INT_TO_SHORT: 224 op = kOp2Short; 225 break; 226 case Instruction::INT_TO_CHAR: 227 op = kOp2Char; 228 break; 229 default: 230 LOG(ERROR) << "Bad int conversion type"; 231 } 232 OpRegReg(op, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 233 StoreValue(rl_dest, rl_result); 234} 235 236/* 237 * Let helper function take care of everything. Will call 238 * Array::AllocFromCode(type_idx, method, count); 239 * Note: AllocFromCode will handle checks for errNegativeArraySize. 240 */ 241void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 242 RegLocation rl_src) { 243 FlushAllRegs(); /* Everything to home location */ 244 ThreadOffset func_offset(-1); 245 const DexFile* dex_file = cu_->dex_file; 246 CompilerDriver* driver = cu_->compiler_driver; 247 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *dex_file, 248 type_idx)) { 249 bool is_type_initialized; // Ignored as an array does not have an initializer. 250 bool use_direct_type_ptr; 251 uintptr_t direct_type_ptr; 252 if (kEmbedClassInCode && 253 driver->CanEmbedTypeInCode(*dex_file, type_idx, 254 &is_type_initialized, &use_direct_type_ptr, &direct_type_ptr)) { 255 // The fast path. 256 if (!use_direct_type_ptr) { 257 LoadClassType(type_idx, kArg0); 258 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved); 259 CallRuntimeHelperRegMethodRegLocation(func_offset, TargetReg(kArg0), rl_src, true); 260 } else { 261 // Use the direct pointer. 262 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved); 263 CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, true); 264 } 265 } else { 266 // The slow path. 267 DCHECK_EQ(func_offset.Int32Value(), -1); 268 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArray); 269 CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 270 } 271 DCHECK_NE(func_offset.Int32Value(), -1); 272 } else { 273 func_offset= QUICK_ENTRYPOINT_OFFSET(pAllocArrayWithAccessCheck); 274 CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 275 } 276 RegLocation rl_result = GetReturn(false); 277 StoreValue(rl_dest, rl_result); 278} 279 280/* 281 * Similar to GenNewArray, but with post-allocation initialization. 282 * Verifier guarantees we're dealing with an array class. Current 283 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 284 * Current code also throws internal unimp if not 'L', '[' or 'I'. 285 */ 286void Mir2Lir::GenFilledNewArray(CallInfo* info) { 287 int elems = info->num_arg_words; 288 int type_idx = info->index; 289 FlushAllRegs(); /* Everything to home location */ 290 ThreadOffset func_offset(-1); 291 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *cu_->dex_file, 292 type_idx)) { 293 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArray); 294 } else { 295 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArrayWithAccessCheck); 296 } 297 CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 298 FreeTemp(TargetReg(kArg2)); 299 FreeTemp(TargetReg(kArg1)); 300 /* 301 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 302 * return region. Because AllocFromCode placed the new array 303 * in kRet0, we'll just lock it into place. When debugger support is 304 * added, it may be necessary to additionally copy all return 305 * values to a home location in thread-local storage 306 */ 307 LockTemp(TargetReg(kRet0)); 308 309 // TODO: use the correct component size, currently all supported types 310 // share array alignment with ints (see comment at head of function) 311 size_t component_size = sizeof(int32_t); 312 313 // Having a range of 0 is legal 314 if (info->is_range && (elems > 0)) { 315 /* 316 * Bit of ugliness here. We're going generate a mem copy loop 317 * on the register range, but it is possible that some regs 318 * in the range have been promoted. This is unlikely, but 319 * before generating the copy, we'll just force a flush 320 * of any regs in the source range that have been promoted to 321 * home location. 322 */ 323 for (int i = 0; i < elems; i++) { 324 RegLocation loc = UpdateLoc(info->args[i]); 325 if (loc.location == kLocPhysReg) { 326 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), 327 loc.reg.GetReg(), kWord); 328 } 329 } 330 /* 331 * TUNING note: generated code here could be much improved, but 332 * this is an uncommon operation and isn't especially performance 333 * critical. 334 */ 335 int r_src = AllocTemp(); 336 int r_dst = AllocTemp(); 337 int r_idx = AllocTemp(); 338 int r_val = INVALID_REG; 339 switch (cu_->instruction_set) { 340 case kThumb2: 341 r_val = TargetReg(kLr); 342 break; 343 case kX86: 344 FreeTemp(TargetReg(kRet0)); 345 r_val = AllocTemp(); 346 break; 347 case kMips: 348 r_val = AllocTemp(); 349 break; 350 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 351 } 352 // Set up source pointer 353 RegLocation rl_first = info->args[0]; 354 OpRegRegImm(kOpAdd, r_src, TargetReg(kSp), SRegOffset(rl_first.s_reg_low)); 355 // Set up the target pointer 356 OpRegRegImm(kOpAdd, r_dst, TargetReg(kRet0), 357 mirror::Array::DataOffset(component_size).Int32Value()); 358 // Set up the loop counter (known to be > 0) 359 LoadConstant(r_idx, elems - 1); 360 // Generate the copy loop. Going backwards for convenience 361 LIR* target = NewLIR0(kPseudoTargetLabel); 362 // Copy next element 363 LoadBaseIndexed(r_src, r_idx, r_val, 2, kWord); 364 StoreBaseIndexed(r_dst, r_idx, r_val, 2, kWord); 365 FreeTemp(r_val); 366 OpDecAndBranch(kCondGe, r_idx, target); 367 if (cu_->instruction_set == kX86) { 368 // Restore the target pointer 369 OpRegRegImm(kOpAdd, TargetReg(kRet0), r_dst, 370 -mirror::Array::DataOffset(component_size).Int32Value()); 371 } 372 } else if (!info->is_range) { 373 // TUNING: interleave 374 for (int i = 0; i < elems; i++) { 375 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 376 StoreBaseDisp(TargetReg(kRet0), 377 mirror::Array::DataOffset(component_size).Int32Value() + 378 i * 4, rl_arg.reg.GetReg(), kWord); 379 // If the LoadValue caused a temp to be allocated, free it 380 if (IsTemp(rl_arg.reg.GetReg())) { 381 FreeTemp(rl_arg.reg.GetReg()); 382 } 383 } 384 } 385 if (info->result.location != kLocInvalid) { 386 StoreValue(info->result, GetReturn(false /* not fp */)); 387 } 388} 389 390// 391// Slow path to ensure a class is initialized for sget/sput. 392// 393class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 394 public: 395 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, 396 int storage_index, int r_base) : 397 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), storage_index_(storage_index), 398 r_base_(r_base) { 399 } 400 401 void Compile() { 402 LIR* unresolved_target = GenerateTargetLabel(); 403 uninit_->target = unresolved_target; 404 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeStaticStorage), 405 storage_index_, true); 406 // Copy helper's result into r_base, a no-op on all but MIPS. 407 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0)); 408 409 m2l_->OpUnconditionalBranch(cont_); 410 } 411 412 private: 413 LIR* const uninit_; 414 const int storage_index_; 415 const int r_base_; 416}; 417 418void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 419 bool is_object) { 420 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 421 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 422 if (field_info.FastPut() && !SLOW_FIELD_PATH) { 423 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 424 int r_base; 425 if (field_info.IsReferrersClass()) { 426 // Fast path, static storage base is this method's class 427 RegLocation rl_method = LoadCurrMethod(); 428 r_base = AllocTemp(); 429 LoadWordDisp(rl_method.reg.GetReg(), 430 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base); 431 if (IsTemp(rl_method.reg.GetReg())) { 432 FreeTemp(rl_method.reg.GetReg()); 433 } 434 } else { 435 // Medium path, static storage base in a different class which requires checks that the other 436 // class is initialized. 437 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 438 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 439 // May do runtime call so everything to home locations. 440 FlushAllRegs(); 441 // Using fixed register to sync with possible call to runtime support. 442 int r_method = TargetReg(kArg1); 443 LockTemp(r_method); 444 LoadCurrMethodDirect(r_method); 445 r_base = TargetReg(kArg0); 446 LockTemp(r_base); 447 LoadWordDisp(r_method, 448 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 449 r_base); 450 LoadWordDisp(r_base, mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 451 sizeof(int32_t*) * field_info.StorageIndex(), r_base); 452 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 453 if (!field_info.IsInitialized() && 454 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 455 // Check if r_base is NULL or a not yet initialized class. 456 457 // The slow path is invoked if the r_base is NULL or the class pointed 458 // to by it is not initialized. 459 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 460 int r_tmp = TargetReg(kArg2); 461 LockTemp(r_tmp); 462 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 463 mirror::Class::StatusOffset().Int32Value(), 464 mirror::Class::kStatusInitialized, NULL); 465 LIR* cont = NewLIR0(kPseudoTargetLabel); 466 467 AddSlowPath(new (arena_) StaticFieldSlowPath(this, 468 unresolved_branch, uninit_branch, cont, 469 field_info.StorageIndex(), r_base)); 470 471 FreeTemp(r_tmp); 472 } 473 FreeTemp(r_method); 474 } 475 // rBase now holds static storage base 476 if (is_long_or_double) { 477 rl_src = LoadValueWide(rl_src, kAnyReg); 478 } else { 479 rl_src = LoadValue(rl_src, kAnyReg); 480 } 481 if (field_info.IsVolatile()) { 482 GenMemBarrier(kStoreStore); 483 } 484 if (is_long_or_double) { 485 StoreBaseDispWide(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg.GetReg(), 486 rl_src.reg.GetHighReg()); 487 } else { 488 StoreWordDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg.GetReg()); 489 } 490 if (field_info.IsVolatile()) { 491 GenMemBarrier(kStoreLoad); 492 } 493 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 494 MarkGCCard(rl_src.reg.GetReg(), r_base); 495 } 496 FreeTemp(r_base); 497 } else { 498 FlushAllRegs(); // Everything to home locations 499 ThreadOffset setter_offset = 500 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Static) 501 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjStatic) 502 : QUICK_ENTRYPOINT_OFFSET(pSet32Static)); 503 CallRuntimeHelperImmRegLocation(setter_offset, field_info.FieldIndex(), rl_src, true); 504 } 505} 506 507void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 508 bool is_long_or_double, bool is_object) { 509 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 510 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 511 if (field_info.FastGet() && !SLOW_FIELD_PATH) { 512 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 513 int r_base; 514 if (field_info.IsReferrersClass()) { 515 // Fast path, static storage base is this method's class 516 RegLocation rl_method = LoadCurrMethod(); 517 r_base = AllocTemp(); 518 LoadWordDisp(rl_method.reg.GetReg(), 519 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base); 520 } else { 521 // Medium path, static storage base in a different class which requires checks that the other 522 // class is initialized 523 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 524 // May do runtime call so everything to home locations. 525 FlushAllRegs(); 526 // Using fixed register to sync with possible call to runtime support. 527 int r_method = TargetReg(kArg1); 528 LockTemp(r_method); 529 LoadCurrMethodDirect(r_method); 530 r_base = TargetReg(kArg0); 531 LockTemp(r_base); 532 LoadWordDisp(r_method, 533 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 534 r_base); 535 LoadWordDisp(r_base, mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 536 sizeof(int32_t*) * field_info.StorageIndex(), r_base); 537 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 538 if (!field_info.IsInitialized() && 539 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 540 // Check if r_base is NULL or a not yet initialized class. 541 542 // The slow path is invoked if the r_base is NULL or the class pointed 543 // to by it is not initialized. 544 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 545 int r_tmp = TargetReg(kArg2); 546 LockTemp(r_tmp); 547 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 548 mirror::Class::StatusOffset().Int32Value(), 549 mirror::Class::kStatusInitialized, NULL); 550 LIR* cont = NewLIR0(kPseudoTargetLabel); 551 552 AddSlowPath(new (arena_) StaticFieldSlowPath(this, 553 unresolved_branch, uninit_branch, cont, 554 field_info.StorageIndex(), r_base)); 555 556 FreeTemp(r_tmp); 557 } 558 FreeTemp(r_method); 559 } 560 // r_base now holds static storage base 561 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 562 if (field_info.IsVolatile()) { 563 GenMemBarrier(kLoadLoad); 564 } 565 if (is_long_or_double) { 566 LoadBaseDispWide(r_base, field_info.FieldOffset().Int32Value(), rl_result.reg.GetReg(), 567 rl_result.reg.GetHighReg(), INVALID_SREG); 568 } else { 569 LoadWordDisp(r_base, field_info.FieldOffset().Int32Value(), rl_result.reg.GetReg()); 570 } 571 FreeTemp(r_base); 572 if (is_long_or_double) { 573 StoreValueWide(rl_dest, rl_result); 574 } else { 575 StoreValue(rl_dest, rl_result); 576 } 577 } else { 578 FlushAllRegs(); // Everything to home locations 579 ThreadOffset getterOffset = 580 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Static) 581 :(is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjStatic) 582 : QUICK_ENTRYPOINT_OFFSET(pGet32Static)); 583 CallRuntimeHelperImm(getterOffset, field_info.FieldIndex(), true); 584 if (is_long_or_double) { 585 RegLocation rl_result = GetReturnWide(rl_dest.fp); 586 StoreValueWide(rl_dest, rl_result); 587 } else { 588 RegLocation rl_result = GetReturn(rl_dest.fp); 589 StoreValue(rl_dest, rl_result); 590 } 591 } 592} 593 594// Generate code for all slow paths. 595void Mir2Lir::HandleSlowPaths() { 596 int n = slow_paths_.Size(); 597 for (int i = 0; i < n; ++i) { 598 LIRSlowPath* slowpath = slow_paths_.Get(i); 599 slowpath->Compile(); 600 } 601 slow_paths_.Reset(); 602} 603 604void Mir2Lir::HandleSuspendLaunchPads() { 605 int num_elems = suspend_launchpads_.Size(); 606 ThreadOffset helper_offset = QUICK_ENTRYPOINT_OFFSET(pTestSuspend); 607 for (int i = 0; i < num_elems; i++) { 608 ResetRegPool(); 609 ResetDefTracking(); 610 LIR* lab = suspend_launchpads_.Get(i); 611 LIR* resume_lab = reinterpret_cast<LIR*>(UnwrapPointer(lab->operands[0])); 612 current_dalvik_offset_ = lab->operands[1]; 613 AppendLIR(lab); 614 int r_tgt = CallHelperSetup(helper_offset); 615 CallHelper(r_tgt, helper_offset, true /* MarkSafepointPC */); 616 OpUnconditionalBranch(resume_lab); 617 } 618} 619 620void Mir2Lir::HandleThrowLaunchPads() { 621 int num_elems = throw_launchpads_.Size(); 622 for (int i = 0; i < num_elems; i++) { 623 ResetRegPool(); 624 ResetDefTracking(); 625 LIR* lab = throw_launchpads_.Get(i); 626 current_dalvik_offset_ = lab->operands[1]; 627 AppendLIR(lab); 628 ThreadOffset func_offset(-1); 629 int v1 = lab->operands[2]; 630 int v2 = lab->operands[3]; 631 const bool target_x86 = cu_->instruction_set == kX86; 632 switch (lab->operands[0]) { 633 case kThrowNullPointer: 634 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowNullPointer); 635 break; 636 case kThrowConstantArrayBounds: // v1 is length reg (for Arm/Mips), v2 constant index 637 // v1 holds the constant array index. Mips/Arm uses v2 for length, x86 reloads. 638 if (target_x86) { 639 OpRegMem(kOpMov, TargetReg(kArg1), v1, mirror::Array::LengthOffset().Int32Value()); 640 } else { 641 OpRegCopy(TargetReg(kArg1), v1); 642 } 643 // Make sure the following LoadConstant doesn't mess with kArg1. 644 LockTemp(TargetReg(kArg1)); 645 LoadConstant(TargetReg(kArg0), v2); 646 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 647 break; 648 case kThrowArrayBounds: 649 // Move v1 (array index) to kArg0 and v2 (array length) to kArg1 650 if (v2 != TargetReg(kArg0)) { 651 OpRegCopy(TargetReg(kArg0), v1); 652 if (target_x86) { 653 // x86 leaves the array pointer in v2, so load the array length that the handler expects 654 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 655 } else { 656 OpRegCopy(TargetReg(kArg1), v2); 657 } 658 } else { 659 if (v1 == TargetReg(kArg1)) { 660 // Swap v1 and v2, using kArg2 as a temp 661 OpRegCopy(TargetReg(kArg2), v1); 662 if (target_x86) { 663 // x86 leaves the array pointer in v2; load the array length that the handler expects 664 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 665 } else { 666 OpRegCopy(TargetReg(kArg1), v2); 667 } 668 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 669 } else { 670 if (target_x86) { 671 // x86 leaves the array pointer in v2; load the array length that the handler expects 672 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 673 } else { 674 OpRegCopy(TargetReg(kArg1), v2); 675 } 676 OpRegCopy(TargetReg(kArg0), v1); 677 } 678 } 679 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 680 break; 681 case kThrowDivZero: 682 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowDivZero); 683 break; 684 case kThrowNoSuchMethod: 685 OpRegCopy(TargetReg(kArg0), v1); 686 func_offset = 687 QUICK_ENTRYPOINT_OFFSET(pThrowNoSuchMethod); 688 break; 689 default: 690 LOG(FATAL) << "Unexpected throw kind: " << lab->operands[0]; 691 } 692 ClobberCallerSave(); 693 int r_tgt = CallHelperSetup(func_offset); 694 CallHelper(r_tgt, func_offset, true /* MarkSafepointPC */, true /* UseLink */); 695 } 696} 697 698void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 699 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 700 bool is_object) { 701 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 702 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 703 if (field_info.FastGet() && !SLOW_FIELD_PATH) { 704 RegLocation rl_result; 705 RegisterClass reg_class = oat_reg_class_by_size(size); 706 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 707 rl_obj = LoadValue(rl_obj, kCoreReg); 708 if (is_long_or_double) { 709 DCHECK(rl_dest.wide); 710 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 711 if (cu_->instruction_set == kX86) { 712 rl_result = EvalLoc(rl_dest, reg_class, true); 713 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 714 LoadBaseDispWide(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 715 rl_result.reg.GetReg(), 716 rl_result.reg.GetHighReg(), rl_obj.s_reg_low); 717 MarkPossibleNullPointerException(opt_flags); 718 if (field_info.IsVolatile()) { 719 GenMemBarrier(kLoadLoad); 720 } 721 } else { 722 int reg_ptr = AllocTemp(); 723 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value()); 724 rl_result = EvalLoc(rl_dest, reg_class, true); 725 LoadBaseDispWide(reg_ptr, 0, rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), 726 INVALID_SREG); 727 if (field_info.IsVolatile()) { 728 GenMemBarrier(kLoadLoad); 729 } 730 FreeTemp(reg_ptr); 731 } 732 StoreValueWide(rl_dest, rl_result); 733 } else { 734 rl_result = EvalLoc(rl_dest, reg_class, true); 735 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 736 LoadBaseDisp(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 737 rl_result.reg.GetReg(), kWord, rl_obj.s_reg_low); 738 MarkPossibleNullPointerException(opt_flags); 739 if (field_info.IsVolatile()) { 740 GenMemBarrier(kLoadLoad); 741 } 742 StoreValue(rl_dest, rl_result); 743 } 744 } else { 745 ThreadOffset getterOffset = 746 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Instance) 747 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjInstance) 748 : QUICK_ENTRYPOINT_OFFSET(pGet32Instance)); 749 CallRuntimeHelperImmRegLocation(getterOffset, field_info.FieldIndex(), rl_obj, true); 750 if (is_long_or_double) { 751 RegLocation rl_result = GetReturnWide(rl_dest.fp); 752 StoreValueWide(rl_dest, rl_result); 753 } else { 754 RegLocation rl_result = GetReturn(rl_dest.fp); 755 StoreValue(rl_dest, rl_result); 756 } 757 } 758} 759 760void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 761 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 762 bool is_object) { 763 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 764 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 765 if (field_info.FastPut() && !SLOW_FIELD_PATH) { 766 RegisterClass reg_class = oat_reg_class_by_size(size); 767 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 768 rl_obj = LoadValue(rl_obj, kCoreReg); 769 if (is_long_or_double) { 770 int reg_ptr; 771 rl_src = LoadValueWide(rl_src, kAnyReg); 772 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 773 reg_ptr = AllocTemp(); 774 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value()); 775 if (field_info.IsVolatile()) { 776 GenMemBarrier(kStoreStore); 777 } 778 StoreBaseDispWide(reg_ptr, 0, rl_src.reg.GetReg(), rl_src.reg.GetHighReg()); 779 MarkPossibleNullPointerException(opt_flags); 780 if (field_info.IsVolatile()) { 781 GenMemBarrier(kLoadLoad); 782 } 783 FreeTemp(reg_ptr); 784 } else { 785 rl_src = LoadValue(rl_src, reg_class); 786 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 787 if (field_info.IsVolatile()) { 788 GenMemBarrier(kStoreStore); 789 } 790 StoreBaseDisp(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 791 rl_src.reg.GetReg(), kWord); 792 MarkPossibleNullPointerException(opt_flags); 793 if (field_info.IsVolatile()) { 794 GenMemBarrier(kLoadLoad); 795 } 796 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 797 MarkGCCard(rl_src.reg.GetReg(), rl_obj.reg.GetReg()); 798 } 799 } 800 } else { 801 ThreadOffset setter_offset = 802 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Instance) 803 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjInstance) 804 : QUICK_ENTRYPOINT_OFFSET(pSet32Instance)); 805 CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info.FieldIndex(), 806 rl_obj, rl_src, true); 807 } 808} 809 810void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 811 RegLocation rl_src) { 812 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 813 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 814 (opt_flags & MIR_IGNORE_NULL_CHECK)); 815 ThreadOffset helper = needs_range_check 816 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pAputObjectWithNullAndBoundCheck) 817 : QUICK_ENTRYPOINT_OFFSET(pAputObjectWithBoundCheck)) 818 : QUICK_ENTRYPOINT_OFFSET(pAputObject); 819 CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, true); 820} 821 822void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 823 RegLocation rl_method = LoadCurrMethod(); 824 int res_reg = AllocTemp(); 825 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 826 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 827 *cu_->dex_file, 828 type_idx)) { 829 // Call out to helper which resolves type and verifies access. 830 // Resolved type returned in kRet0. 831 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 832 type_idx, rl_method.reg.GetReg(), true); 833 RegLocation rl_result = GetReturn(false); 834 StoreValue(rl_dest, rl_result); 835 } else { 836 // We're don't need access checks, load type from dex cache 837 int32_t dex_cache_offset = 838 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 839 LoadWordDisp(rl_method.reg.GetReg(), dex_cache_offset, res_reg); 840 int32_t offset_of_type = 841 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 842 * type_idx); 843 LoadWordDisp(res_reg, offset_of_type, rl_result.reg.GetReg()); 844 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 845 type_idx) || SLOW_TYPE_PATH) { 846 // Slow path, at runtime test if type is null and if so initialize 847 FlushAllRegs(); 848 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg.GetReg(), 0, NULL); 849 LIR* cont = NewLIR0(kPseudoTargetLabel); 850 851 // Object to generate the slow path for class resolution. 852 class SlowPath : public LIRSlowPath { 853 public: 854 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 855 const RegLocation& rl_method, const RegLocation& rl_result) : 856 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 857 rl_method_(rl_method), rl_result_(rl_result) { 858 } 859 860 void Compile() { 861 GenerateTargetLabel(); 862 863 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_, 864 rl_method_.reg.GetReg(), true); 865 m2l_->OpRegCopy(rl_result_.reg.GetReg(), m2l_->TargetReg(kRet0)); 866 867 m2l_->OpUnconditionalBranch(cont_); 868 } 869 870 private: 871 const int type_idx_; 872 const RegLocation rl_method_; 873 const RegLocation rl_result_; 874 }; 875 876 // Add to list for future. 877 AddSlowPath(new (arena_) SlowPath(this, branch, cont, 878 type_idx, rl_method, rl_result)); 879 880 StoreValue(rl_dest, rl_result); 881 } else { 882 // Fast path, we're done - just store result 883 StoreValue(rl_dest, rl_result); 884 } 885 } 886} 887 888void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 889 /* NOTE: Most strings should be available at compile time */ 890 int32_t offset_of_string = mirror::Array::DataOffset(sizeof(mirror::String*)).Int32Value() + 891 (sizeof(mirror::String*) * string_idx); 892 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 893 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 894 // slow path, resolve string if not in dex cache 895 FlushAllRegs(); 896 LockCallTemps(); // Using explicit registers 897 898 // If the Method* is already in a register, we can save a copy. 899 RegLocation rl_method = mir_graph_->GetMethodLoc(); 900 int r_method; 901 if (rl_method.location == kLocPhysReg) { 902 // A temp would conflict with register use below. 903 DCHECK(!IsTemp(rl_method.reg.GetReg())); 904 r_method = rl_method.reg.GetReg(); 905 } else { 906 r_method = TargetReg(kArg2); 907 LoadCurrMethodDirect(r_method); 908 } 909 LoadWordDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 910 TargetReg(kArg0)); 911 912 // Might call out to helper, which will return resolved string in kRet0 913 LoadWordDisp(TargetReg(kArg0), offset_of_string, TargetReg(kRet0)); 914 if (cu_->instruction_set == kThumb2 || 915 cu_->instruction_set == kMips) { 916 // OpRegImm(kOpCmp, TargetReg(kRet0), 0); // Is resolved? 917 LoadConstant(TargetReg(kArg1), string_idx); 918 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0), 0, NULL); 919 LIR* cont = NewLIR0(kPseudoTargetLabel); 920 GenBarrier(); 921 922 // Object to generate the slow path for string resolution. 923 class SlowPath : public LIRSlowPath { 924 public: 925 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, int r_method) : 926 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), r_method_(r_method) { 927 } 928 929 void Compile() { 930 GenerateTargetLabel(); 931 932 int r_tgt = m2l_->CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(pResolveString)); 933 934 m2l_->OpRegCopy(m2l_->TargetReg(kArg0), r_method_); // .eq 935 LIR* call_inst = m2l_->OpReg(kOpBlx, r_tgt); 936 m2l_->MarkSafepointPC(call_inst); 937 m2l_->FreeTemp(r_tgt); 938 939 m2l_->OpUnconditionalBranch(cont_); 940 } 941 942 private: 943 int r_method_; 944 }; 945 946 // Add to list for future. 947 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method)); 948 } else { 949 DCHECK_EQ(cu_->instruction_set, kX86); 950 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kRet0), 0, NULL); 951 LoadConstant(TargetReg(kArg1), string_idx); 952 CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pResolveString), r_method, 953 TargetReg(kArg1), true); 954 LIR* target = NewLIR0(kPseudoTargetLabel); 955 branch->target = target; 956 } 957 GenBarrier(); 958 StoreValue(rl_dest, GetReturn(false)); 959 } else { 960 RegLocation rl_method = LoadCurrMethod(); 961 int res_reg = AllocTemp(); 962 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 963 LoadWordDisp(rl_method.reg.GetReg(), 964 mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg); 965 LoadWordDisp(res_reg, offset_of_string, rl_result.reg.GetReg()); 966 StoreValue(rl_dest, rl_result); 967 } 968} 969 970/* 971 * Let helper function take care of everything. Will 972 * call Class::NewInstanceFromCode(type_idx, method); 973 */ 974void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 975 FlushAllRegs(); /* Everything to home location */ 976 // alloc will always check for resolution, do we also need to verify 977 // access because the verifier was unable to? 978 ThreadOffset func_offset(-1); 979 const DexFile* dex_file = cu_->dex_file; 980 CompilerDriver* driver = cu_->compiler_driver; 981 if (driver->CanAccessInstantiableTypeWithoutChecks( 982 cu_->method_idx, *dex_file, type_idx)) { 983 bool is_type_initialized; 984 bool use_direct_type_ptr; 985 uintptr_t direct_type_ptr; 986 if (kEmbedClassInCode && 987 driver->CanEmbedTypeInCode(*dex_file, type_idx, 988 &is_type_initialized, &use_direct_type_ptr, &direct_type_ptr)) { 989 // The fast path. 990 if (!use_direct_type_ptr) { 991 LoadClassType(type_idx, kArg0); 992 if (!is_type_initialized) { 993 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved); 994 CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true); 995 } else { 996 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized); 997 CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true); 998 } 999 } else { 1000 // Use the direct pointer. 1001 if (!is_type_initialized) { 1002 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved); 1003 CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1004 } else { 1005 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized); 1006 CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1007 } 1008 } 1009 } else { 1010 // The slow path. 1011 DCHECK_EQ(func_offset.Int32Value(), -1); 1012 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObject); 1013 CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1014 } 1015 DCHECK_NE(func_offset.Int32Value(), -1); 1016 } else { 1017 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectWithAccessCheck); 1018 CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1019 } 1020 RegLocation rl_result = GetReturn(false); 1021 StoreValue(rl_dest, rl_result); 1022} 1023 1024void Mir2Lir::GenThrow(RegLocation rl_src) { 1025 FlushAllRegs(); 1026 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pDeliverException), rl_src, true); 1027} 1028 1029// For final classes there are no sub-classes to check and so we can answer the instance-of 1030// question with simple comparisons. 1031void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1032 RegLocation rl_src) { 1033 // X86 has its own implementation. 1034 DCHECK_NE(cu_->instruction_set, kX86); 1035 1036 RegLocation object = LoadValue(rl_src, kCoreReg); 1037 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1038 int result_reg = rl_result.reg.GetReg(); 1039 if (result_reg == object.reg.GetReg()) { 1040 result_reg = AllocTypedTemp(false, kCoreReg); 1041 } 1042 LoadConstant(result_reg, 0); // assume false 1043 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg.GetReg(), 0, NULL); 1044 1045 int check_class = AllocTypedTemp(false, kCoreReg); 1046 int object_class = AllocTypedTemp(false, kCoreReg); 1047 1048 LoadCurrMethodDirect(check_class); 1049 if (use_declaring_class) { 1050 LoadWordDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1051 check_class); 1052 LoadWordDisp(object.reg.GetReg(), mirror::Object::ClassOffset().Int32Value(), object_class); 1053 } else { 1054 LoadWordDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1055 check_class); 1056 LoadWordDisp(object.reg.GetReg(), mirror::Object::ClassOffset().Int32Value(), object_class); 1057 int32_t offset_of_type = 1058 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 1059 (sizeof(mirror::Class*) * type_idx); 1060 LoadWordDisp(check_class, offset_of_type, check_class); 1061 } 1062 1063 LIR* ne_branchover = NULL; 1064 if (cu_->instruction_set == kThumb2) { 1065 OpRegReg(kOpCmp, check_class, object_class); // Same? 1066 OpIT(kCondEq, ""); // if-convert the test 1067 LoadConstant(result_reg, 1); // .eq case - load true 1068 } else { 1069 ne_branchover = OpCmpBranch(kCondNe, check_class, object_class, NULL); 1070 LoadConstant(result_reg, 1); // eq case - load true 1071 } 1072 LIR* target = NewLIR0(kPseudoTargetLabel); 1073 null_branchover->target = target; 1074 if (ne_branchover != NULL) { 1075 ne_branchover->target = target; 1076 } 1077 FreeTemp(object_class); 1078 FreeTemp(check_class); 1079 if (IsTemp(result_reg)) { 1080 OpRegCopy(rl_result.reg.GetReg(), result_reg); 1081 FreeTemp(result_reg); 1082 } 1083 StoreValue(rl_dest, rl_result); 1084} 1085 1086void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1087 bool type_known_abstract, bool use_declaring_class, 1088 bool can_assume_type_is_in_dex_cache, 1089 uint32_t type_idx, RegLocation rl_dest, 1090 RegLocation rl_src) { 1091 // X86 has its own implementation. 1092 DCHECK_NE(cu_->instruction_set, kX86); 1093 1094 FlushAllRegs(); 1095 // May generate a call - use explicit registers 1096 LockCallTemps(); 1097 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 1098 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 1099 if (needs_access_check) { 1100 // Check we have access to type_idx and if not throw IllegalAccessError, 1101 // returns Class* in kArg0 1102 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 1103 type_idx, true); 1104 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1105 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1106 } else if (use_declaring_class) { 1107 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1108 LoadWordDisp(TargetReg(kArg1), 1109 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 1110 } else { 1111 // Load dex cache entry into class_reg (kArg2) 1112 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1113 LoadWordDisp(TargetReg(kArg1), 1114 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 1115 int32_t offset_of_type = 1116 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 1117 * type_idx); 1118 LoadWordDisp(class_reg, offset_of_type, class_reg); 1119 if (!can_assume_type_is_in_dex_cache) { 1120 // Need to test presence of type in dex cache at runtime 1121 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 1122 // Not resolved 1123 // Call out to helper, which will return resolved type in kRet0 1124 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, true); 1125 OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path 1126 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* reload Ref */ 1127 // Rejoin code paths 1128 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 1129 hop_branch->target = hop_target; 1130 } 1131 } 1132 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1133 RegLocation rl_result = GetReturn(false); 1134 if (cu_->instruction_set == kMips) { 1135 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1136 LoadConstant(rl_result.reg.GetReg(), 0); 1137 } 1138 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 1139 1140 /* load object->klass_ */ 1141 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1142 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 1143 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1144 LIR* branchover = NULL; 1145 if (type_known_final) { 1146 // rl_result == ref == null == 0. 1147 if (cu_->instruction_set == kThumb2) { 1148 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 1149 OpIT(kCondEq, "E"); // if-convert the test 1150 LoadConstant(rl_result.reg.GetReg(), 1); // .eq case - load true 1151 LoadConstant(rl_result.reg.GetReg(), 0); // .ne case - load false 1152 } else { 1153 LoadConstant(rl_result.reg.GetReg(), 0); // ne case - load false 1154 branchover = OpCmpBranch(kCondNe, TargetReg(kArg1), TargetReg(kArg2), NULL); 1155 LoadConstant(rl_result.reg.GetReg(), 1); // eq case - load true 1156 } 1157 } else { 1158 if (cu_->instruction_set == kThumb2) { 1159 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1160 if (!type_known_abstract) { 1161 /* Uses conditional nullification */ 1162 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 1163 OpIT(kCondEq, "EE"); // if-convert the test 1164 LoadConstant(TargetReg(kArg0), 1); // .eq case - load true 1165 } 1166 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 1167 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1168 FreeTemp(r_tgt); 1169 } else { 1170 if (!type_known_abstract) { 1171 /* Uses branchovers */ 1172 LoadConstant(rl_result.reg.GetReg(), 1); // assume true 1173 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); 1174 } 1175 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1176 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 1177 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1178 FreeTemp(r_tgt); 1179 } 1180 } 1181 // TODO: only clobber when type isn't final? 1182 ClobberCallerSave(); 1183 /* branch targets here */ 1184 LIR* target = NewLIR0(kPseudoTargetLabel); 1185 StoreValue(rl_dest, rl_result); 1186 branch1->target = target; 1187 if (branchover != NULL) { 1188 branchover->target = target; 1189 } 1190} 1191 1192void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1193 bool type_known_final, type_known_abstract, use_declaring_class; 1194 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1195 *cu_->dex_file, 1196 type_idx, 1197 &type_known_final, 1198 &type_known_abstract, 1199 &use_declaring_class); 1200 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1201 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1202 1203 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1204 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1205 } else { 1206 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1207 use_declaring_class, can_assume_type_is_in_dex_cache, 1208 type_idx, rl_dest, rl_src); 1209 } 1210} 1211 1212void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1213 bool type_known_final, type_known_abstract, use_declaring_class; 1214 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1215 *cu_->dex_file, 1216 type_idx, 1217 &type_known_final, 1218 &type_known_abstract, 1219 &use_declaring_class); 1220 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1221 // of the exception throw path. 1222 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1223 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1224 // Verifier type analysis proved this check cast would never cause an exception. 1225 return; 1226 } 1227 FlushAllRegs(); 1228 // May generate a call - use explicit registers 1229 LockCallTemps(); 1230 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 1231 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 1232 if (needs_access_check) { 1233 // Check we have access to type_idx and if not throw IllegalAccessError, 1234 // returns Class* in kRet0 1235 // InitializeTypeAndVerifyAccess(idx, method) 1236 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 1237 type_idx, TargetReg(kArg1), true); 1238 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1239 } else if (use_declaring_class) { 1240 LoadWordDisp(TargetReg(kArg1), 1241 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 1242 } else { 1243 // Load dex cache entry into class_reg (kArg2) 1244 LoadWordDisp(TargetReg(kArg1), 1245 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 1246 int32_t offset_of_type = 1247 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 1248 (sizeof(mirror::Class*) * type_idx); 1249 LoadWordDisp(class_reg, offset_of_type, class_reg); 1250 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1251 // Need to test presence of type in dex cache at runtime 1252 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1253 LIR* cont = NewLIR0(kPseudoTargetLabel); 1254 1255 // Slow path to initialize the type. Executed if the type is NULL. 1256 class SlowPath : public LIRSlowPath { 1257 public: 1258 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1259 const int class_reg) : 1260 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1261 class_reg_(class_reg) { 1262 } 1263 1264 void Compile() { 1265 GenerateTargetLabel(); 1266 1267 // Call out to helper, which will return resolved type in kArg0 1268 // InitializeTypeFromCode(idx, method) 1269 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_, 1270 m2l_->TargetReg(kArg1), true); 1271 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0)); // Align usage with fast path 1272 m2l_->OpUnconditionalBranch(cont_); 1273 } 1274 public: 1275 const int type_idx_; 1276 const int class_reg_; 1277 }; 1278 1279 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, 1280 type_idx, class_reg)); 1281 } 1282 } 1283 // At this point, class_reg (kArg2) has class 1284 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1285 1286 // Slow path for the case where the classes are not equal. In this case we need 1287 // to call a helper function to do the check. 1288 class SlowPath : public LIRSlowPath { 1289 public: 1290 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1291 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1292 } 1293 1294 void Compile() { 1295 GenerateTargetLabel(); 1296 1297 if (load_) { 1298 m2l_->LoadWordDisp(m2l_->TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), 1299 m2l_->TargetReg(kArg1)); 1300 } 1301 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pCheckCast), m2l_->TargetReg(kArg2), 1302 m2l_->TargetReg(kArg1), true); 1303 1304 m2l_->OpUnconditionalBranch(cont_); 1305 } 1306 1307 private: 1308 bool load_; 1309 }; 1310 1311 if (type_known_abstract) { 1312 // Easier case, run slow path if target is non-null (slow path will load from target) 1313 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0), 0, NULL); 1314 LIR* cont = NewLIR0(kPseudoTargetLabel); 1315 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1316 } else { 1317 // Harder, more common case. We need to generate a forward branch over the load 1318 // if the target is null. If it's non-null we perform the load and branch to the 1319 // slow path if the classes are not equal. 1320 1321 /* Null is OK - continue */ 1322 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 1323 /* load object->klass_ */ 1324 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1325 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), 1326 TargetReg(kArg1)); 1327 1328 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1), class_reg, NULL); 1329 LIR* cont = NewLIR0(kPseudoTargetLabel); 1330 1331 // Add the slow path that will not perform load since this is already done. 1332 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1333 1334 // Set the null check to branch to the continuation. 1335 branch1->target = cont; 1336 } 1337} 1338 1339void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1340 RegLocation rl_src1, RegLocation rl_src2) { 1341 RegLocation rl_result; 1342 if (cu_->instruction_set == kThumb2) { 1343 /* 1344 * NOTE: This is the one place in the code in which we might have 1345 * as many as six live temporary registers. There are 5 in the normal 1346 * set for Arm. Until we have spill capabilities, temporarily add 1347 * lr to the temp set. It is safe to do this locally, but note that 1348 * lr is used explicitly elsewhere in the code generator and cannot 1349 * normally be used as a general temp register. 1350 */ 1351 MarkTemp(TargetReg(kLr)); // Add lr to the temp pool 1352 FreeTemp(TargetReg(kLr)); // and make it available 1353 } 1354 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1355 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1356 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1357 // The longs may overlap - use intermediate temp if so 1358 if ((rl_result.reg.GetReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetReg() == rl_src2.reg.GetHighReg())) { 1359 int t_reg = AllocTemp(); 1360 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1361 OpRegRegReg(second_op, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1362 OpRegCopy(rl_result.reg.GetReg(), t_reg); 1363 FreeTemp(t_reg); 1364 } else { 1365 OpRegRegReg(first_op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1366 OpRegRegReg(second_op, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), 1367 rl_src2.reg.GetHighReg()); 1368 } 1369 /* 1370 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1371 * following StoreValueWide might need to allocate a temp register. 1372 * To further work around the lack of a spill capability, explicitly 1373 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1374 * Remove when spill is functional. 1375 */ 1376 FreeRegLocTemps(rl_result, rl_src1); 1377 FreeRegLocTemps(rl_result, rl_src2); 1378 StoreValueWide(rl_dest, rl_result); 1379 if (cu_->instruction_set == kThumb2) { 1380 Clobber(TargetReg(kLr)); 1381 UnmarkTemp(TargetReg(kLr)); // Remove lr from the temp pool 1382 } 1383} 1384 1385 1386void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1387 RegLocation rl_src1, RegLocation rl_shift) { 1388 ThreadOffset func_offset(-1); 1389 1390 switch (opcode) { 1391 case Instruction::SHL_LONG: 1392 case Instruction::SHL_LONG_2ADDR: 1393 func_offset = QUICK_ENTRYPOINT_OFFSET(pShlLong); 1394 break; 1395 case Instruction::SHR_LONG: 1396 case Instruction::SHR_LONG_2ADDR: 1397 func_offset = QUICK_ENTRYPOINT_OFFSET(pShrLong); 1398 break; 1399 case Instruction::USHR_LONG: 1400 case Instruction::USHR_LONG_2ADDR: 1401 func_offset = QUICK_ENTRYPOINT_OFFSET(pUshrLong); 1402 break; 1403 default: 1404 LOG(FATAL) << "Unexpected case"; 1405 } 1406 FlushAllRegs(); /* Send everything to home location */ 1407 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1408 RegLocation rl_result = GetReturnWide(false); 1409 StoreValueWide(rl_dest, rl_result); 1410} 1411 1412 1413void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1414 RegLocation rl_src1, RegLocation rl_src2) { 1415 DCHECK_NE(cu_->instruction_set, kX86); 1416 OpKind op = kOpBkpt; 1417 bool is_div_rem = false; 1418 bool check_zero = false; 1419 bool unary = false; 1420 RegLocation rl_result; 1421 bool shift_op = false; 1422 switch (opcode) { 1423 case Instruction::NEG_INT: 1424 op = kOpNeg; 1425 unary = true; 1426 break; 1427 case Instruction::NOT_INT: 1428 op = kOpMvn; 1429 unary = true; 1430 break; 1431 case Instruction::ADD_INT: 1432 case Instruction::ADD_INT_2ADDR: 1433 op = kOpAdd; 1434 break; 1435 case Instruction::SUB_INT: 1436 case Instruction::SUB_INT_2ADDR: 1437 op = kOpSub; 1438 break; 1439 case Instruction::MUL_INT: 1440 case Instruction::MUL_INT_2ADDR: 1441 op = kOpMul; 1442 break; 1443 case Instruction::DIV_INT: 1444 case Instruction::DIV_INT_2ADDR: 1445 check_zero = true; 1446 op = kOpDiv; 1447 is_div_rem = true; 1448 break; 1449 /* NOTE: returns in kArg1 */ 1450 case Instruction::REM_INT: 1451 case Instruction::REM_INT_2ADDR: 1452 check_zero = true; 1453 op = kOpRem; 1454 is_div_rem = true; 1455 break; 1456 case Instruction::AND_INT: 1457 case Instruction::AND_INT_2ADDR: 1458 op = kOpAnd; 1459 break; 1460 case Instruction::OR_INT: 1461 case Instruction::OR_INT_2ADDR: 1462 op = kOpOr; 1463 break; 1464 case Instruction::XOR_INT: 1465 case Instruction::XOR_INT_2ADDR: 1466 op = kOpXor; 1467 break; 1468 case Instruction::SHL_INT: 1469 case Instruction::SHL_INT_2ADDR: 1470 shift_op = true; 1471 op = kOpLsl; 1472 break; 1473 case Instruction::SHR_INT: 1474 case Instruction::SHR_INT_2ADDR: 1475 shift_op = true; 1476 op = kOpAsr; 1477 break; 1478 case Instruction::USHR_INT: 1479 case Instruction::USHR_INT_2ADDR: 1480 shift_op = true; 1481 op = kOpLsr; 1482 break; 1483 default: 1484 LOG(FATAL) << "Invalid word arith op: " << opcode; 1485 } 1486 if (!is_div_rem) { 1487 if (unary) { 1488 rl_src1 = LoadValue(rl_src1, kCoreReg); 1489 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1490 OpRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); 1491 } else { 1492 if (shift_op) { 1493 int t_reg = INVALID_REG; 1494 rl_src2 = LoadValue(rl_src2, kCoreReg); 1495 t_reg = AllocTemp(); 1496 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg.GetReg(), 31); 1497 rl_src1 = LoadValue(rl_src1, kCoreReg); 1498 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1499 OpRegRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), t_reg); 1500 FreeTemp(t_reg); 1501 } else { 1502 rl_src1 = LoadValue(rl_src1, kCoreReg); 1503 rl_src2 = LoadValue(rl_src2, kCoreReg); 1504 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1505 OpRegRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1506 } 1507 } 1508 StoreValue(rl_dest, rl_result); 1509 } else { 1510 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1511 if (cu_->instruction_set == kMips) { 1512 rl_src1 = LoadValue(rl_src1, kCoreReg); 1513 rl_src2 = LoadValue(rl_src2, kCoreReg); 1514 if (check_zero) { 1515 GenImmedCheck(kCondEq, rl_src2.reg.GetReg(), 0, kThrowDivZero); 1516 } 1517 rl_result = GenDivRem(rl_dest, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), op == kOpDiv); 1518 done = true; 1519 } else if (cu_->instruction_set == kThumb2) { 1520 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1521 // Use ARM SDIV instruction for division. For remainder we also need to 1522 // calculate using a MUL and subtract. 1523 rl_src1 = LoadValue(rl_src1, kCoreReg); 1524 rl_src2 = LoadValue(rl_src2, kCoreReg); 1525 if (check_zero) { 1526 GenImmedCheck(kCondEq, rl_src2.reg.GetReg(), 0, kThrowDivZero); 1527 } 1528 rl_result = GenDivRem(rl_dest, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), op == kOpDiv); 1529 done = true; 1530 } 1531 } 1532 1533 // If we haven't already generated the code use the callout function. 1534 if (!done) { 1535 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1536 FlushAllRegs(); /* Send everything to home location */ 1537 LoadValueDirectFixed(rl_src2, TargetReg(kArg1)); 1538 int r_tgt = CallHelperSetup(func_offset); 1539 LoadValueDirectFixed(rl_src1, TargetReg(kArg0)); 1540 if (check_zero) { 1541 GenImmedCheck(kCondEq, TargetReg(kArg1), 0, kThrowDivZero); 1542 } 1543 // NOTE: callout here is not a safepoint. 1544 CallHelper(r_tgt, func_offset, false /* not a safepoint */); 1545 if (op == kOpDiv) 1546 rl_result = GetReturn(false); 1547 else 1548 rl_result = GetReturnAlt(); 1549 } 1550 StoreValue(rl_dest, rl_result); 1551 } 1552} 1553 1554/* 1555 * The following are the first-level codegen routines that analyze the format 1556 * of each bytecode then either dispatch special purpose codegen routines 1557 * or produce corresponding Thumb instructions directly. 1558 */ 1559 1560// Returns true if no more than two bits are set in 'x'. 1561static bool IsPopCountLE2(unsigned int x) { 1562 x &= x - 1; 1563 return (x & (x - 1)) == 0; 1564} 1565 1566// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1567// and store the result in 'rl_dest'. 1568bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1569 RegLocation rl_src, RegLocation rl_dest, int lit) { 1570 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1571 return false; 1572 } 1573 // No divide instruction for Arm, so check for more special cases 1574 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1575 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1576 } 1577 int k = LowestSetBit(lit); 1578 if (k >= 30) { 1579 // Avoid special cases. 1580 return false; 1581 } 1582 rl_src = LoadValue(rl_src, kCoreReg); 1583 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1584 if (is_div) { 1585 int t_reg = AllocTemp(); 1586 if (lit == 2) { 1587 // Division by 2 is by far the most common division by constant. 1588 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetReg(), 32 - k); 1589 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg.GetReg()); 1590 OpRegRegImm(kOpAsr, rl_result.reg.GetReg(), t_reg, k); 1591 } else { 1592 OpRegRegImm(kOpAsr, t_reg, rl_src.reg.GetReg(), 31); 1593 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1594 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg.GetReg()); 1595 OpRegRegImm(kOpAsr, rl_result.reg.GetReg(), t_reg, k); 1596 } 1597 } else { 1598 int t_reg1 = AllocTemp(); 1599 int t_reg2 = AllocTemp(); 1600 if (lit == 2) { 1601 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg.GetReg(), 32 - k); 1602 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg.GetReg()); 1603 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1604 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg2, t_reg1); 1605 } else { 1606 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg.GetReg(), 31); 1607 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1608 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg.GetReg()); 1609 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1610 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg2, t_reg1); 1611 } 1612 } 1613 StoreValue(rl_dest, rl_result); 1614 return true; 1615} 1616 1617// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1618// and store the result in 'rl_dest'. 1619bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1620 // Can we simplify this multiplication? 1621 bool power_of_two = false; 1622 bool pop_count_le2 = false; 1623 bool power_of_two_minus_one = false; 1624 if (lit < 2) { 1625 // Avoid special cases. 1626 return false; 1627 } else if (IsPowerOfTwo(lit)) { 1628 power_of_two = true; 1629 } else if (IsPopCountLE2(lit)) { 1630 pop_count_le2 = true; 1631 } else if (IsPowerOfTwo(lit + 1)) { 1632 power_of_two_minus_one = true; 1633 } else { 1634 return false; 1635 } 1636 rl_src = LoadValue(rl_src, kCoreReg); 1637 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1638 if (power_of_two) { 1639 // Shift. 1640 OpRegRegImm(kOpLsl, rl_result.reg.GetReg(), rl_src.reg.GetReg(), LowestSetBit(lit)); 1641 } else if (pop_count_le2) { 1642 // Shift and add and shift. 1643 int first_bit = LowestSetBit(lit); 1644 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1645 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1646 } else { 1647 // Reverse subtract: (src << (shift + 1)) - src. 1648 DCHECK(power_of_two_minus_one); 1649 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1650 int t_reg = AllocTemp(); 1651 OpRegRegImm(kOpLsl, t_reg, rl_src.reg.GetReg(), LowestSetBit(lit + 1)); 1652 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg, rl_src.reg.GetReg()); 1653 } 1654 StoreValue(rl_dest, rl_result); 1655 return true; 1656} 1657 1658void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1659 int lit) { 1660 RegLocation rl_result; 1661 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1662 int shift_op = false; 1663 bool is_div = false; 1664 1665 switch (opcode) { 1666 case Instruction::RSUB_INT_LIT8: 1667 case Instruction::RSUB_INT: { 1668 rl_src = LoadValue(rl_src, kCoreReg); 1669 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1670 if (cu_->instruction_set == kThumb2) { 1671 OpRegRegImm(kOpRsub, rl_result.reg.GetReg(), rl_src.reg.GetReg(), lit); 1672 } else { 1673 OpRegReg(kOpNeg, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 1674 OpRegImm(kOpAdd, rl_result.reg.GetReg(), lit); 1675 } 1676 StoreValue(rl_dest, rl_result); 1677 return; 1678 } 1679 1680 case Instruction::SUB_INT: 1681 case Instruction::SUB_INT_2ADDR: 1682 lit = -lit; 1683 // Intended fallthrough 1684 case Instruction::ADD_INT: 1685 case Instruction::ADD_INT_2ADDR: 1686 case Instruction::ADD_INT_LIT8: 1687 case Instruction::ADD_INT_LIT16: 1688 op = kOpAdd; 1689 break; 1690 case Instruction::MUL_INT: 1691 case Instruction::MUL_INT_2ADDR: 1692 case Instruction::MUL_INT_LIT8: 1693 case Instruction::MUL_INT_LIT16: { 1694 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1695 return; 1696 } 1697 op = kOpMul; 1698 break; 1699 } 1700 case Instruction::AND_INT: 1701 case Instruction::AND_INT_2ADDR: 1702 case Instruction::AND_INT_LIT8: 1703 case Instruction::AND_INT_LIT16: 1704 op = kOpAnd; 1705 break; 1706 case Instruction::OR_INT: 1707 case Instruction::OR_INT_2ADDR: 1708 case Instruction::OR_INT_LIT8: 1709 case Instruction::OR_INT_LIT16: 1710 op = kOpOr; 1711 break; 1712 case Instruction::XOR_INT: 1713 case Instruction::XOR_INT_2ADDR: 1714 case Instruction::XOR_INT_LIT8: 1715 case Instruction::XOR_INT_LIT16: 1716 op = kOpXor; 1717 break; 1718 case Instruction::SHL_INT_LIT8: 1719 case Instruction::SHL_INT: 1720 case Instruction::SHL_INT_2ADDR: 1721 lit &= 31; 1722 shift_op = true; 1723 op = kOpLsl; 1724 break; 1725 case Instruction::SHR_INT_LIT8: 1726 case Instruction::SHR_INT: 1727 case Instruction::SHR_INT_2ADDR: 1728 lit &= 31; 1729 shift_op = true; 1730 op = kOpAsr; 1731 break; 1732 case Instruction::USHR_INT_LIT8: 1733 case Instruction::USHR_INT: 1734 case Instruction::USHR_INT_2ADDR: 1735 lit &= 31; 1736 shift_op = true; 1737 op = kOpLsr; 1738 break; 1739 1740 case Instruction::DIV_INT: 1741 case Instruction::DIV_INT_2ADDR: 1742 case Instruction::DIV_INT_LIT8: 1743 case Instruction::DIV_INT_LIT16: 1744 case Instruction::REM_INT: 1745 case Instruction::REM_INT_2ADDR: 1746 case Instruction::REM_INT_LIT8: 1747 case Instruction::REM_INT_LIT16: { 1748 if (lit == 0) { 1749 GenImmedCheck(kCondAl, 0, 0, kThrowDivZero); 1750 return; 1751 } 1752 if ((opcode == Instruction::DIV_INT) || 1753 (opcode == Instruction::DIV_INT_2ADDR) || 1754 (opcode == Instruction::DIV_INT_LIT8) || 1755 (opcode == Instruction::DIV_INT_LIT16)) { 1756 is_div = true; 1757 } else { 1758 is_div = false; 1759 } 1760 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1761 return; 1762 } 1763 1764 bool done = false; 1765 if (cu_->instruction_set == kMips) { 1766 rl_src = LoadValue(rl_src, kCoreReg); 1767 rl_result = GenDivRemLit(rl_dest, rl_src.reg.GetReg(), lit, is_div); 1768 done = true; 1769 } else if (cu_->instruction_set == kX86) { 1770 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1771 done = true; 1772 } else if (cu_->instruction_set == kThumb2) { 1773 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1774 // Use ARM SDIV instruction for division. For remainder we also need to 1775 // calculate using a MUL and subtract. 1776 rl_src = LoadValue(rl_src, kCoreReg); 1777 rl_result = GenDivRemLit(rl_dest, rl_src.reg.GetReg(), lit, is_div); 1778 done = true; 1779 } 1780 } 1781 1782 if (!done) { 1783 FlushAllRegs(); /* Everything to home location. */ 1784 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 1785 Clobber(TargetReg(kArg0)); 1786 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1787 CallRuntimeHelperRegImm(func_offset, TargetReg(kArg0), lit, false); 1788 if (is_div) 1789 rl_result = GetReturn(false); 1790 else 1791 rl_result = GetReturnAlt(); 1792 } 1793 StoreValue(rl_dest, rl_result); 1794 return; 1795 } 1796 default: 1797 LOG(FATAL) << "Unexpected opcode " << opcode; 1798 } 1799 rl_src = LoadValue(rl_src, kCoreReg); 1800 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1801 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 1802 if (shift_op && (lit == 0)) { 1803 OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg()); 1804 } else { 1805 OpRegRegImm(op, rl_result.reg.GetReg(), rl_src.reg.GetReg(), lit); 1806 } 1807 StoreValue(rl_dest, rl_result); 1808} 1809 1810void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 1811 RegLocation rl_src1, RegLocation rl_src2) { 1812 RegLocation rl_result; 1813 OpKind first_op = kOpBkpt; 1814 OpKind second_op = kOpBkpt; 1815 bool call_out = false; 1816 bool check_zero = false; 1817 ThreadOffset func_offset(-1); 1818 int ret_reg = TargetReg(kRet0); 1819 1820 switch (opcode) { 1821 case Instruction::NOT_LONG: 1822 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1823 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1824 // Check for destructive overlap 1825 if (rl_result.reg.GetReg() == rl_src2.reg.GetHighReg()) { 1826 int t_reg = AllocTemp(); 1827 OpRegCopy(t_reg, rl_src2.reg.GetHighReg()); 1828 OpRegReg(kOpMvn, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1829 OpRegReg(kOpMvn, rl_result.reg.GetHighReg(), t_reg); 1830 FreeTemp(t_reg); 1831 } else { 1832 OpRegReg(kOpMvn, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1833 OpRegReg(kOpMvn, rl_result.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1834 } 1835 StoreValueWide(rl_dest, rl_result); 1836 return; 1837 case Instruction::ADD_LONG: 1838 case Instruction::ADD_LONG_2ADDR: 1839 if (cu_->instruction_set != kThumb2) { 1840 GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 1841 return; 1842 } 1843 first_op = kOpAdd; 1844 second_op = kOpAdc; 1845 break; 1846 case Instruction::SUB_LONG: 1847 case Instruction::SUB_LONG_2ADDR: 1848 if (cu_->instruction_set != kThumb2) { 1849 GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 1850 return; 1851 } 1852 first_op = kOpSub; 1853 second_op = kOpSbc; 1854 break; 1855 case Instruction::MUL_LONG: 1856 case Instruction::MUL_LONG_2ADDR: 1857 if (cu_->instruction_set != kMips) { 1858 GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 1859 return; 1860 } else { 1861 call_out = true; 1862 ret_reg = TargetReg(kRet0); 1863 func_offset = QUICK_ENTRYPOINT_OFFSET(pLmul); 1864 } 1865 break; 1866 case Instruction::DIV_LONG: 1867 case Instruction::DIV_LONG_2ADDR: 1868 call_out = true; 1869 check_zero = true; 1870 ret_reg = TargetReg(kRet0); 1871 func_offset = QUICK_ENTRYPOINT_OFFSET(pLdiv); 1872 break; 1873 case Instruction::REM_LONG: 1874 case Instruction::REM_LONG_2ADDR: 1875 call_out = true; 1876 check_zero = true; 1877 func_offset = QUICK_ENTRYPOINT_OFFSET(pLmod); 1878 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 1879 ret_reg = (cu_->instruction_set == kThumb2) ? TargetReg(kArg2) : TargetReg(kRet0); 1880 break; 1881 case Instruction::AND_LONG_2ADDR: 1882 case Instruction::AND_LONG: 1883 if (cu_->instruction_set == kX86) { 1884 return GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 1885 } 1886 first_op = kOpAnd; 1887 second_op = kOpAnd; 1888 break; 1889 case Instruction::OR_LONG: 1890 case Instruction::OR_LONG_2ADDR: 1891 if (cu_->instruction_set == kX86) { 1892 GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 1893 return; 1894 } 1895 first_op = kOpOr; 1896 second_op = kOpOr; 1897 break; 1898 case Instruction::XOR_LONG: 1899 case Instruction::XOR_LONG_2ADDR: 1900 if (cu_->instruction_set == kX86) { 1901 GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 1902 return; 1903 } 1904 first_op = kOpXor; 1905 second_op = kOpXor; 1906 break; 1907 case Instruction::NEG_LONG: { 1908 GenNegLong(rl_dest, rl_src2); 1909 return; 1910 } 1911 default: 1912 LOG(FATAL) << "Invalid long arith op"; 1913 } 1914 if (!call_out) { 1915 GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 1916 } else { 1917 FlushAllRegs(); /* Send everything to home location */ 1918 if (check_zero) { 1919 LoadValueDirectWideFixed(rl_src2, TargetReg(kArg2), TargetReg(kArg3)); 1920 int r_tgt = CallHelperSetup(func_offset); 1921 GenDivZeroCheck(TargetReg(kArg2), TargetReg(kArg3)); 1922 LoadValueDirectWideFixed(rl_src1, TargetReg(kArg0), TargetReg(kArg1)); 1923 // NOTE: callout here is not a safepoint 1924 CallHelper(r_tgt, func_offset, false /* not safepoint */); 1925 } else { 1926 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 1927 } 1928 // Adjust return regs in to handle case of rem returning kArg2/kArg3 1929 if (ret_reg == TargetReg(kRet0)) 1930 rl_result = GetReturnWide(false); 1931 else 1932 rl_result = GetReturnWideAlt(); 1933 StoreValueWide(rl_dest, rl_result); 1934 } 1935} 1936 1937void Mir2Lir::GenConversionCall(ThreadOffset func_offset, 1938 RegLocation rl_dest, RegLocation rl_src) { 1939 /* 1940 * Don't optimize the register usage since it calls out to support 1941 * functions 1942 */ 1943 FlushAllRegs(); /* Send everything to home location */ 1944 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 1945 if (rl_dest.wide) { 1946 RegLocation rl_result; 1947 rl_result = GetReturnWide(rl_dest.fp); 1948 StoreValueWide(rl_dest, rl_result); 1949 } else { 1950 RegLocation rl_result; 1951 rl_result = GetReturn(rl_dest.fp); 1952 StoreValue(rl_dest, rl_result); 1953 } 1954} 1955 1956/* Check if we need to check for pending suspend request */ 1957void Mir2Lir::GenSuspendTest(int opt_flags) { 1958 if (Runtime::Current()->ExplicitSuspendChecks()) { 1959 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1960 return; 1961 } 1962 FlushAllRegs(); 1963 LIR* branch = OpTestSuspend(NULL); 1964 LIR* ret_lab = NewLIR0(kPseudoTargetLabel); 1965 LIR* target = RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, WrapPointer(ret_lab), 1966 current_dalvik_offset_); 1967 branch->target = target; 1968 suspend_launchpads_.Insert(target); 1969 } else { 1970 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1971 return; 1972 } 1973 FlushAllRegs(); // TODO: needed? 1974 LIR* inst = CheckSuspendUsingLoad(); 1975 MarkSafepointPC(inst); 1976 } 1977} 1978 1979/* Check if we need to check for pending suspend request */ 1980void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 1981 if (Runtime::Current()->ExplicitSuspendChecks()) { 1982 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1983 OpUnconditionalBranch(target); 1984 return; 1985 } 1986 OpTestSuspend(target); 1987 LIR* launch_pad = 1988 RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, WrapPointer(target), 1989 current_dalvik_offset_); 1990 FlushAllRegs(); 1991 OpUnconditionalBranch(launch_pad); 1992 suspend_launchpads_.Insert(launch_pad); 1993 } else { 1994 // For the implicit suspend check, just perform the trigger 1995 // load and branch to the target. 1996 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1997 OpUnconditionalBranch(target); 1998 return; 1999 } 2000 FlushAllRegs(); 2001 LIR* inst = CheckSuspendUsingLoad(); 2002 MarkSafepointPC(inst); 2003 OpUnconditionalBranch(target); 2004 } 2005} 2006 2007/* Call out to helper assembly routine that will null check obj and then lock it. */ 2008void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2009 FlushAllRegs(); 2010 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pLockObject), rl_src, true); 2011} 2012 2013/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2014void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2015 FlushAllRegs(); 2016 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pUnlockObject), rl_src, true); 2017} 2018 2019/* Generic code for generating a wide constant into a VR. */ 2020void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2021 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2022 LoadConstantWide(rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), value); 2023 StoreValueWide(rl_dest, rl_result); 2024} 2025 2026} // namespace art 2027