gen_common.cc revision 69dfe51b684dd9d510dbcb63295fe180f998efde
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include "dex/compiler_ir.h" 17#include "dex/compiler_internals.h" 18#include "dex/quick/arm/arm_lir.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object_array-inl.h" 23#include "mirror/object-inl.h" 24#include "verifier/method_verifier.h" 25#include <functional> 26 27namespace art { 28 29// Shortcuts to repeatedly used long types. 30typedef mirror::ObjectArray<mirror::Object> ObjArray; 31typedef mirror::ObjectArray<mirror::Class> ClassArray; 32 33/* 34 * This source files contains "gen" codegen routines that should 35 * be applicable to most targets. Only mid-level support utilities 36 * and "op" calls may be used here. 37 */ 38 39/* 40 * Generate a kPseudoBarrier marker to indicate the boundary of special 41 * blocks. 42 */ 43void Mir2Lir::GenBarrier() { 44 LIR* barrier = NewLIR0(kPseudoBarrier); 45 /* Mark all resources as being clobbered */ 46 DCHECK(!barrier->flags.use_def_invalid); 47 barrier->u.m.def_mask = &kEncodeAll; 48} 49 50void Mir2Lir::GenDivZeroException() { 51 LIR* branch = OpUnconditionalBranch(nullptr); 52 AddDivZeroCheckSlowPath(branch); 53} 54 55void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { 56 LIR* branch = OpCondBranch(c_code, nullptr); 57 AddDivZeroCheckSlowPath(branch); 58} 59 60void Mir2Lir::GenDivZeroCheck(RegStorage reg) { 61 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 62 AddDivZeroCheckSlowPath(branch); 63} 64 65void Mir2Lir::AddDivZeroCheckSlowPath(LIR* branch) { 66 class DivZeroCheckSlowPath : public Mir2Lir::LIRSlowPath { 67 public: 68 DivZeroCheckSlowPath(Mir2Lir* m2l, LIR* branch) 69 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 70 } 71 72 void Compile() OVERRIDE { 73 m2l_->ResetRegPool(); 74 m2l_->ResetDefTracking(); 75 GenerateTargetLabel(kPseudoThrowTarget); 76 if (m2l_->cu_->target64) { 77 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowDivZero), true); 78 } else { 79 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowDivZero), true); 80 } 81 } 82 }; 83 84 AddSlowPath(new (arena_) DivZeroCheckSlowPath(this, branch)); 85} 86 87void Mir2Lir::GenArrayBoundsCheck(RegStorage index, RegStorage length) { 88 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 89 public: 90 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, RegStorage index, RegStorage length) 91 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 92 index_(index), length_(length) { 93 } 94 95 void Compile() OVERRIDE { 96 m2l_->ResetRegPool(); 97 m2l_->ResetDefTracking(); 98 GenerateTargetLabel(kPseudoThrowTarget); 99 if (m2l_->cu_->target64) { 100 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 101 index_, length_, true); 102 } else { 103 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 104 index_, length_, true); 105 } 106 } 107 108 private: 109 const RegStorage index_; 110 const RegStorage length_; 111 }; 112 113 LIR* branch = OpCmpBranch(kCondUge, index, length, nullptr); 114 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 115} 116 117void Mir2Lir::GenArrayBoundsCheck(int index, RegStorage length) { 118 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 119 public: 120 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, int index, RegStorage length) 121 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 122 index_(index), length_(length) { 123 } 124 125 void Compile() OVERRIDE { 126 m2l_->ResetRegPool(); 127 m2l_->ResetDefTracking(); 128 GenerateTargetLabel(kPseudoThrowTarget); 129 130 RegStorage arg1_32 = m2l_->TargetReg(kArg1, kNotWide); 131 RegStorage arg0_32 = m2l_->TargetReg(kArg0, kNotWide); 132 133 m2l_->OpRegCopy(arg1_32, length_); 134 m2l_->LoadConstant(arg0_32, index_); 135 if (m2l_->cu_->target64) { 136 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 137 arg0_32, arg1_32, true); 138 } else { 139 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 140 arg0_32, arg1_32, true); 141 } 142 } 143 144 private: 145 const int32_t index_; 146 const RegStorage length_; 147 }; 148 149 LIR* branch = OpCmpImmBranch(kCondLs, length, index, nullptr); 150 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 151} 152 153LIR* Mir2Lir::GenNullCheck(RegStorage reg) { 154 class NullCheckSlowPath : public Mir2Lir::LIRSlowPath { 155 public: 156 NullCheckSlowPath(Mir2Lir* m2l, LIR* branch) 157 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 158 } 159 160 void Compile() OVERRIDE { 161 m2l_->ResetRegPool(); 162 m2l_->ResetDefTracking(); 163 GenerateTargetLabel(kPseudoThrowTarget); 164 if (m2l_->cu_->target64) { 165 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowNullPointer), true); 166 } else { 167 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowNullPointer), true); 168 } 169 } 170 }; 171 172 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 173 AddSlowPath(new (arena_) NullCheckSlowPath(this, branch)); 174 return branch; 175} 176 177/* Perform null-check on a register. */ 178LIR* Mir2Lir::GenNullCheck(RegStorage m_reg, int opt_flags) { 179 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 180 return GenExplicitNullCheck(m_reg, opt_flags); 181 } 182 return nullptr; 183} 184 185/* Perform an explicit null-check on a register. */ 186LIR* Mir2Lir::GenExplicitNullCheck(RegStorage m_reg, int opt_flags) { 187 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 188 return NULL; 189 } 190 return GenNullCheck(m_reg); 191} 192 193void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 194 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 195 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 196 return; 197 } 198 // Insert after last instruction. 199 MarkSafepointPC(last_lir_insn_); 200 } 201} 202 203void Mir2Lir::MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after) { 204 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 205 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 206 return; 207 } 208 MarkSafepointPCAfter(after); 209 } 210} 211 212void Mir2Lir::MarkPossibleStackOverflowException() { 213 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitStackOverflowChecks()) { 214 MarkSafepointPC(last_lir_insn_); 215 } 216} 217 218void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { 219 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 220 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 221 return; 222 } 223 // Force an implicit null check by performing a memory operation (load) from the given 224 // register with offset 0. This will cause a signal if the register contains 0 (null). 225 RegStorage tmp = AllocTemp(); 226 // TODO: for Mips, would be best to use rZERO as the bogus register target. 227 LIR* load = Load32Disp(reg, 0, tmp); 228 FreeTemp(tmp); 229 MarkSafepointPC(load); 230 } 231} 232 233void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 234 RegLocation rl_src2, LIR* taken, 235 LIR* fall_through) { 236 DCHECK(!rl_src1.fp); 237 DCHECK(!rl_src2.fp); 238 ConditionCode cond; 239 switch (opcode) { 240 case Instruction::IF_EQ: 241 cond = kCondEq; 242 break; 243 case Instruction::IF_NE: 244 cond = kCondNe; 245 break; 246 case Instruction::IF_LT: 247 cond = kCondLt; 248 break; 249 case Instruction::IF_GE: 250 cond = kCondGe; 251 break; 252 case Instruction::IF_GT: 253 cond = kCondGt; 254 break; 255 case Instruction::IF_LE: 256 cond = kCondLe; 257 break; 258 default: 259 cond = static_cast<ConditionCode>(0); 260 LOG(FATAL) << "Unexpected opcode " << opcode; 261 } 262 263 // Normalize such that if either operand is constant, src2 will be constant 264 if (rl_src1.is_const) { 265 RegLocation rl_temp = rl_src1; 266 rl_src1 = rl_src2; 267 rl_src2 = rl_temp; 268 cond = FlipComparisonOrder(cond); 269 } 270 271 rl_src1 = LoadValue(rl_src1); 272 // Is this really an immediate comparison? 273 if (rl_src2.is_const) { 274 // If it's already live in a register or not easily materialized, just keep going 275 RegLocation rl_temp = UpdateLoc(rl_src2); 276 if ((rl_temp.location == kLocDalvikFrame) && 277 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 278 // OK - convert this to a compare immediate and branch 279 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); 280 return; 281 } 282 } 283 rl_src2 = LoadValue(rl_src2); 284 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken); 285} 286 287void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 288 LIR* fall_through) { 289 ConditionCode cond; 290 DCHECK(!rl_src.fp); 291 rl_src = LoadValue(rl_src); 292 switch (opcode) { 293 case Instruction::IF_EQZ: 294 cond = kCondEq; 295 break; 296 case Instruction::IF_NEZ: 297 cond = kCondNe; 298 break; 299 case Instruction::IF_LTZ: 300 cond = kCondLt; 301 break; 302 case Instruction::IF_GEZ: 303 cond = kCondGe; 304 break; 305 case Instruction::IF_GTZ: 306 cond = kCondGt; 307 break; 308 case Instruction::IF_LEZ: 309 cond = kCondLe; 310 break; 311 default: 312 cond = static_cast<ConditionCode>(0); 313 LOG(FATAL) << "Unexpected opcode " << opcode; 314 } 315 OpCmpImmBranch(cond, rl_src.reg, 0, taken); 316} 317 318void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 319 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 320 if (rl_src.location == kLocPhysReg) { 321 OpRegCopy(rl_result.reg, rl_src.reg); 322 } else { 323 LoadValueDirect(rl_src, rl_result.reg.GetLow()); 324 } 325 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_result.reg.GetLow(), 31); 326 StoreValueWide(rl_dest, rl_result); 327} 328 329void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 330 RegLocation rl_src) { 331 rl_src = LoadValue(rl_src, kCoreReg); 332 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 333 OpKind op = kOpInvalid; 334 switch (opcode) { 335 case Instruction::INT_TO_BYTE: 336 op = kOp2Byte; 337 break; 338 case Instruction::INT_TO_SHORT: 339 op = kOp2Short; 340 break; 341 case Instruction::INT_TO_CHAR: 342 op = kOp2Char; 343 break; 344 default: 345 LOG(ERROR) << "Bad int conversion type"; 346 } 347 OpRegReg(op, rl_result.reg, rl_src.reg); 348 StoreValue(rl_dest, rl_result); 349} 350 351template <size_t pointer_size> 352static void GenNewArrayImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, 353 uint32_t type_idx, RegLocation rl_dest, 354 RegLocation rl_src) { 355 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 356 ThreadOffset<pointer_size> func_offset(-1); 357 const DexFile* dex_file = cu->dex_file; 358 CompilerDriver* driver = cu->compiler_driver; 359 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *dex_file, 360 type_idx)) { 361 bool is_type_initialized; // Ignored as an array does not have an initializer. 362 bool use_direct_type_ptr; 363 uintptr_t direct_type_ptr; 364 bool is_finalizable; 365 if (kEmbedClassInCode && 366 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 367 &direct_type_ptr, &is_finalizable)) { 368 // The fast path. 369 if (!use_direct_type_ptr) { 370 mir_to_lir->LoadClassType(type_idx, kArg0); 371 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 372 mir_to_lir->CallRuntimeHelperRegMethodRegLocation(func_offset, 373 mir_to_lir->TargetReg(kArg0, kNotWide), 374 rl_src, true); 375 } else { 376 // Use the direct pointer. 377 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 378 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, 379 true); 380 } 381 } else { 382 // The slow path. 383 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArray); 384 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 385 } 386 DCHECK_NE(func_offset.Int32Value(), -1); 387 } else { 388 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayWithAccessCheck); 389 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 390 } 391 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 392 mir_to_lir->StoreValue(rl_dest, rl_result); 393} 394 395/* 396 * Let helper function take care of everything. Will call 397 * Array::AllocFromCode(type_idx, method, count); 398 * Note: AllocFromCode will handle checks for errNegativeArraySize. 399 */ 400void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 401 RegLocation rl_src) { 402 if (cu_->target64) { 403 GenNewArrayImpl<8>(this, cu_, type_idx, rl_dest, rl_src); 404 } else { 405 GenNewArrayImpl<4>(this, cu_, type_idx, rl_dest, rl_src); 406 } 407} 408 409template <size_t pointer_size> 410static void GenFilledNewArrayCall(Mir2Lir* mir_to_lir, CompilationUnit* cu, int elems, int type_idx) { 411 ThreadOffset<pointer_size> func_offset(-1); 412 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *cu->dex_file, 413 type_idx)) { 414 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArray); 415 } else { 416 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArrayWithAccessCheck); 417 } 418 mir_to_lir->CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 419} 420 421/* 422 * Similar to GenNewArray, but with post-allocation initialization. 423 * Verifier guarantees we're dealing with an array class. Current 424 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 425 * Current code also throws internal unimp if not 'L', '[' or 'I'. 426 */ 427void Mir2Lir::GenFilledNewArray(CallInfo* info) { 428 int elems = info->num_arg_words; 429 int type_idx = info->index; 430 FlushAllRegs(); /* Everything to home location */ 431 if (cu_->target64) { 432 GenFilledNewArrayCall<8>(this, cu_, elems, type_idx); 433 } else { 434 GenFilledNewArrayCall<4>(this, cu_, elems, type_idx); 435 } 436 FreeTemp(TargetReg(kArg2, kNotWide)); 437 FreeTemp(TargetReg(kArg1, kNotWide)); 438 /* 439 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 440 * return region. Because AllocFromCode placed the new array 441 * in kRet0, we'll just lock it into place. When debugger support is 442 * added, it may be necessary to additionally copy all return 443 * values to a home location in thread-local storage 444 */ 445 RegStorage ref_reg = TargetReg(kRet0, kRef); 446 LockTemp(ref_reg); 447 448 // TODO: use the correct component size, currently all supported types 449 // share array alignment with ints (see comment at head of function) 450 size_t component_size = sizeof(int32_t); 451 452 // Having a range of 0 is legal 453 if (info->is_range && (elems > 0)) { 454 /* 455 * Bit of ugliness here. We're going generate a mem copy loop 456 * on the register range, but it is possible that some regs 457 * in the range have been promoted. This is unlikely, but 458 * before generating the copy, we'll just force a flush 459 * of any regs in the source range that have been promoted to 460 * home location. 461 */ 462 for (int i = 0; i < elems; i++) { 463 RegLocation loc = UpdateLoc(info->args[i]); 464 if (loc.location == kLocPhysReg) { 465 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 466 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 467 } 468 } 469 /* 470 * TUNING note: generated code here could be much improved, but 471 * this is an uncommon operation and isn't especially performance 472 * critical. 473 */ 474 // This is addressing the stack, which may be out of the 4G area. 475 RegStorage r_src = AllocTempRef(); 476 RegStorage r_dst = AllocTempRef(); 477 RegStorage r_idx = AllocTempRef(); // Not really a reference, but match src/dst. 478 RegStorage r_val; 479 switch (cu_->instruction_set) { 480 case kThumb2: 481 case kArm64: 482 r_val = TargetReg(kLr, kNotWide); 483 break; 484 case kX86: 485 case kX86_64: 486 FreeTemp(ref_reg); 487 r_val = AllocTemp(); 488 break; 489 case kMips: 490 r_val = AllocTemp(); 491 break; 492 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 493 } 494 // Set up source pointer 495 RegLocation rl_first = info->args[0]; 496 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); 497 // Set up the target pointer 498 OpRegRegImm(kOpAdd, r_dst, ref_reg, 499 mirror::Array::DataOffset(component_size).Int32Value()); 500 // Set up the loop counter (known to be > 0) 501 LoadConstant(r_idx, elems - 1); 502 // Generate the copy loop. Going backwards for convenience 503 LIR* target = NewLIR0(kPseudoTargetLabel); 504 // Copy next element 505 { 506 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 507 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32); 508 // NOTE: No dalvik register annotation, local optimizations will be stopped 509 // by the loop boundaries. 510 } 511 StoreBaseIndexed(r_dst, r_idx, r_val, 2, k32); 512 FreeTemp(r_val); 513 OpDecAndBranch(kCondGe, r_idx, target); 514 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 515 // Restore the target pointer 516 OpRegRegImm(kOpAdd, ref_reg, r_dst, 517 -mirror::Array::DataOffset(component_size).Int32Value()); 518 } 519 } else if (!info->is_range) { 520 // TUNING: interleave 521 for (int i = 0; i < elems; i++) { 522 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 523 Store32Disp(ref_reg, 524 mirror::Array::DataOffset(component_size).Int32Value() + i * 4, rl_arg.reg); 525 // If the LoadValue caused a temp to be allocated, free it 526 if (IsTemp(rl_arg.reg)) { 527 FreeTemp(rl_arg.reg); 528 } 529 } 530 } 531 if (info->result.location != kLocInvalid) { 532 StoreValue(info->result, GetReturn(kRefReg)); 533 } 534} 535 536// 537// Slow path to ensure a class is initialized for sget/sput. 538// 539class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 540 public: 541 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, int storage_index, 542 RegStorage r_base) : 543 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), 544 storage_index_(storage_index), r_base_(r_base) { 545 } 546 547 void Compile() { 548 LIR* unresolved_target = GenerateTargetLabel(); 549 uninit_->target = unresolved_target; 550 if (cu_->target64) { 551 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeStaticStorage), 552 storage_index_, true); 553 } else { 554 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeStaticStorage), 555 storage_index_, true); 556 } 557 // Copy helper's result into r_base, a no-op on all but MIPS. 558 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0, kRef)); 559 560 m2l_->OpUnconditionalBranch(cont_); 561 } 562 563 private: 564 LIR* const uninit_; 565 const int storage_index_; 566 const RegStorage r_base_; 567}; 568 569template <size_t pointer_size> 570static void GenSputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 571 const MirSFieldLoweringInfo* field_info, RegLocation rl_src) { 572 ThreadOffset<pointer_size> setter_offset = 573 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Static) 574 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjStatic) 575 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Static)); 576 mir_to_lir->CallRuntimeHelperImmRegLocation(setter_offset, field_info->FieldIndex(), rl_src, 577 true); 578} 579 580void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 581 bool is_object) { 582 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 583 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 584 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 585 if (!SLOW_FIELD_PATH && field_info.FastPut() && 586 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 587 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 588 RegStorage r_base; 589 if (field_info.IsReferrersClass()) { 590 // Fast path, static storage base is this method's class 591 RegLocation rl_method = LoadCurrMethod(); 592 r_base = AllocTempRef(); 593 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 594 kNotVolatile); 595 if (IsTemp(rl_method.reg)) { 596 FreeTemp(rl_method.reg); 597 } 598 } else { 599 // Medium path, static storage base in a different class which requires checks that the other 600 // class is initialized. 601 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 602 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 603 // May do runtime call so everything to home locations. 604 FlushAllRegs(); 605 // Using fixed register to sync with possible call to runtime support. 606 RegStorage r_method = TargetReg(kArg1, kRef); 607 LockTemp(r_method); 608 LoadCurrMethodDirect(r_method); 609 r_base = TargetReg(kArg0, kRef); 610 LockTemp(r_base); 611 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 612 kNotVolatile); 613 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 614 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 615 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 616 if (!field_info.IsInitialized() && 617 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 618 // Check if r_base is NULL or a not yet initialized class. 619 620 // The slow path is invoked if the r_base is NULL or the class pointed 621 // to by it is not initialized. 622 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 623 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 624 LockTemp(r_tmp); 625 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 626 mirror::Class::StatusOffset().Int32Value(), 627 mirror::Class::kStatusInitialized, nullptr, nullptr); 628 LIR* cont = NewLIR0(kPseudoTargetLabel); 629 630 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 631 field_info.StorageIndex(), r_base)); 632 633 FreeTemp(r_tmp); 634 // Ensure load of status and store of value don't re-order. 635 // TODO: Presumably the actual value store is control-dependent on the status load, 636 // and will thus not be reordered in any case, since stores are never speculated. 637 // Does later code "know" that the class is now initialized? If so, we still 638 // need the barrier to guard later static loads. 639 GenMemBarrier(kLoadAny); 640 } 641 FreeTemp(r_method); 642 } 643 // rBase now holds static storage base 644 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 645 if (is_long_or_double) { 646 rl_src = LoadValueWide(rl_src, reg_class); 647 } else { 648 rl_src = LoadValue(rl_src, reg_class); 649 } 650 if (is_object) { 651 StoreRefDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, 652 field_info.IsVolatile() ? kVolatile : kNotVolatile); 653 } else { 654 StoreBaseDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, store_size, 655 field_info.IsVolatile() ? kVolatile : kNotVolatile); 656 } 657 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 658 MarkGCCard(rl_src.reg, r_base); 659 } 660 FreeTemp(r_base); 661 } else { 662 FlushAllRegs(); // Everything to home locations 663 if (cu_->target64) { 664 GenSputCall<8>(this, is_long_or_double, is_object, &field_info, rl_src); 665 } else { 666 GenSputCall<4>(this, is_long_or_double, is_object, &field_info, rl_src); 667 } 668 } 669} 670 671template <size_t pointer_size> 672static void GenSgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 673 const MirSFieldLoweringInfo* field_info) { 674 ThreadOffset<pointer_size> getter_offset = 675 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Static) 676 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjStatic) 677 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Static)); 678 mir_to_lir->CallRuntimeHelperImm(getter_offset, field_info->FieldIndex(), true); 679} 680 681void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 682 bool is_long_or_double, bool is_object) { 683 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 684 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 685 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 686 if (!SLOW_FIELD_PATH && field_info.FastGet() && 687 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 688 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 689 RegStorage r_base; 690 if (field_info.IsReferrersClass()) { 691 // Fast path, static storage base is this method's class 692 RegLocation rl_method = LoadCurrMethod(); 693 r_base = AllocTempRef(); 694 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 695 kNotVolatile); 696 } else { 697 // Medium path, static storage base in a different class which requires checks that the other 698 // class is initialized 699 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 700 // May do runtime call so everything to home locations. 701 FlushAllRegs(); 702 // Using fixed register to sync with possible call to runtime support. 703 RegStorage r_method = TargetReg(kArg1, kRef); 704 LockTemp(r_method); 705 LoadCurrMethodDirect(r_method); 706 r_base = TargetReg(kArg0, kRef); 707 LockTemp(r_base); 708 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 709 kNotVolatile); 710 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 711 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 712 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 713 if (!field_info.IsInitialized() && 714 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 715 // Check if r_base is NULL or a not yet initialized class. 716 717 // The slow path is invoked if the r_base is NULL or the class pointed 718 // to by it is not initialized. 719 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 720 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 721 LockTemp(r_tmp); 722 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 723 mirror::Class::StatusOffset().Int32Value(), 724 mirror::Class::kStatusInitialized, nullptr, nullptr); 725 LIR* cont = NewLIR0(kPseudoTargetLabel); 726 727 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 728 field_info.StorageIndex(), r_base)); 729 730 FreeTemp(r_tmp); 731 // Ensure load of status and load of value don't re-order. 732 GenMemBarrier(kLoadAny); 733 } 734 FreeTemp(r_method); 735 } 736 // r_base now holds static storage base 737 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 738 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 739 740 int field_offset = field_info.FieldOffset().Int32Value(); 741 if (is_object) { 742 LoadRefDisp(r_base, field_offset, rl_result.reg, field_info.IsVolatile() ? kVolatile : 743 kNotVolatile); 744 } else { 745 LoadBaseDisp(r_base, field_offset, rl_result.reg, load_size, field_info.IsVolatile() ? 746 kVolatile : kNotVolatile); 747 } 748 FreeTemp(r_base); 749 750 if (is_long_or_double) { 751 StoreValueWide(rl_dest, rl_result); 752 } else { 753 StoreValue(rl_dest, rl_result); 754 } 755 } else { 756 FlushAllRegs(); // Everything to home locations 757 if (cu_->target64) { 758 GenSgetCall<8>(this, is_long_or_double, is_object, &field_info); 759 } else { 760 GenSgetCall<4>(this, is_long_or_double, is_object, &field_info); 761 } 762 // FIXME: pGetXXStatic always return an int or int64 regardless of rl_dest.fp. 763 if (is_long_or_double) { 764 RegLocation rl_result = GetReturnWide(kCoreReg); 765 StoreValueWide(rl_dest, rl_result); 766 } else { 767 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 768 StoreValue(rl_dest, rl_result); 769 } 770 } 771} 772 773// Generate code for all slow paths. 774void Mir2Lir::HandleSlowPaths() { 775 // We should check slow_paths_.Size() every time, because a new slow path 776 // may be created during slowpath->Compile(). 777 for (size_t i = 0; i < slow_paths_.Size(); ++i) { 778 LIRSlowPath* slowpath = slow_paths_.Get(i); 779 slowpath->Compile(); 780 } 781 slow_paths_.Reset(); 782} 783 784template <size_t pointer_size> 785static void GenIgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 786 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj) { 787 ThreadOffset<pointer_size> getter_offset = 788 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Instance) 789 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjInstance) 790 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Instance)); 791 mir_to_lir->CallRuntimeHelperImmRegLocation(getter_offset, field_info->FieldIndex(), rl_obj, 792 true); 793} 794 795void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 796 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 797 bool is_object) { 798 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 799 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 800 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 801 if (!SLOW_FIELD_PATH && field_info.FastGet() && 802 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 803 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 804 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 805 rl_obj = LoadValue(rl_obj, kRefReg); 806 GenNullCheck(rl_obj.reg, opt_flags); 807 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 808 int field_offset = field_info.FieldOffset().Int32Value(); 809 LIR* load_lir; 810 if (is_object) { 811 load_lir = LoadRefDisp(rl_obj.reg, field_offset, rl_result.reg, field_info.IsVolatile() ? 812 kVolatile : kNotVolatile); 813 } else { 814 load_lir = LoadBaseDisp(rl_obj.reg, field_offset, rl_result.reg, load_size, 815 field_info.IsVolatile() ? kVolatile : kNotVolatile); 816 } 817 MarkPossibleNullPointerExceptionAfter(opt_flags, load_lir); 818 if (is_long_or_double) { 819 StoreValueWide(rl_dest, rl_result); 820 } else { 821 StoreValue(rl_dest, rl_result); 822 } 823 } else { 824 if (cu_->target64) { 825 GenIgetCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj); 826 } else { 827 GenIgetCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj); 828 } 829 // FIXME: pGetXXInstance always return an int or int64 regardless of rl_dest.fp. 830 if (is_long_or_double) { 831 RegLocation rl_result = GetReturnWide(kCoreReg); 832 StoreValueWide(rl_dest, rl_result); 833 } else { 834 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 835 StoreValue(rl_dest, rl_result); 836 } 837 } 838} 839 840template <size_t pointer_size> 841static void GenIputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 842 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj, 843 RegLocation rl_src) { 844 ThreadOffset<pointer_size> setter_offset = 845 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Instance) 846 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjInstance) 847 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Instance)); 848 mir_to_lir->CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info->FieldIndex(), 849 rl_obj, rl_src, true); 850} 851 852void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 853 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 854 bool is_object) { 855 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 856 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 857 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 858 if (!SLOW_FIELD_PATH && field_info.FastPut() && 859 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 860 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 861 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 862 rl_obj = LoadValue(rl_obj, kRefReg); 863 if (is_long_or_double) { 864 rl_src = LoadValueWide(rl_src, reg_class); 865 } else { 866 rl_src = LoadValue(rl_src, reg_class); 867 } 868 GenNullCheck(rl_obj.reg, opt_flags); 869 int field_offset = field_info.FieldOffset().Int32Value(); 870 LIR* store; 871 if (is_object) { 872 store = StoreRefDisp(rl_obj.reg, field_offset, rl_src.reg, field_info.IsVolatile() ? 873 kVolatile : kNotVolatile); 874 } else { 875 store = StoreBaseDisp(rl_obj.reg, field_offset, rl_src.reg, store_size, 876 field_info.IsVolatile() ? kVolatile : kNotVolatile); 877 } 878 MarkPossibleNullPointerExceptionAfter(opt_flags, store); 879 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 880 MarkGCCard(rl_src.reg, rl_obj.reg); 881 } 882 } else { 883 if (cu_->target64) { 884 GenIputCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 885 } else { 886 GenIputCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 887 } 888 } 889} 890 891template <size_t pointer_size> 892static void GenArrayObjPutCall(Mir2Lir* mir_to_lir, bool needs_range_check, bool needs_null_check, 893 RegLocation rl_array, RegLocation rl_index, RegLocation rl_src) { 894 ThreadOffset<pointer_size> helper = needs_range_check 895 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithNullAndBoundCheck) 896 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithBoundCheck)) 897 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObject); 898 mir_to_lir->CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, 899 true); 900} 901 902void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 903 RegLocation rl_src) { 904 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 905 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 906 (opt_flags & MIR_IGNORE_NULL_CHECK)); 907 if (cu_->target64) { 908 GenArrayObjPutCall<8>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 909 } else { 910 GenArrayObjPutCall<4>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 911 } 912} 913 914void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 915 RegLocation rl_method = LoadCurrMethod(); 916 CheckRegLocation(rl_method); 917 RegStorage res_reg = AllocTempRef(); 918 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 919 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 920 *cu_->dex_file, 921 type_idx)) { 922 // Call out to helper which resolves type and verifies access. 923 // Resolved type returned in kRet0. 924 if (cu_->target64) { 925 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 926 type_idx, rl_method.reg, true); 927 } else { 928 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 929 type_idx, rl_method.reg, true); 930 } 931 RegLocation rl_result = GetReturn(kRefReg); 932 StoreValue(rl_dest, rl_result); 933 } else { 934 // We're don't need access checks, load type from dex cache 935 int32_t dex_cache_offset = 936 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 937 LoadRefDisp(rl_method.reg, dex_cache_offset, res_reg, kNotVolatile); 938 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 939 LoadRefDisp(res_reg, offset_of_type, rl_result.reg, kNotVolatile); 940 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 941 type_idx) || SLOW_TYPE_PATH) { 942 // Slow path, at runtime test if type is null and if so initialize 943 FlushAllRegs(); 944 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg, 0, NULL); 945 LIR* cont = NewLIR0(kPseudoTargetLabel); 946 947 // Object to generate the slow path for class resolution. 948 class SlowPath : public LIRSlowPath { 949 public: 950 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 951 const RegLocation& rl_method, const RegLocation& rl_result) : 952 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 953 rl_method_(rl_method), rl_result_(rl_result) { 954 } 955 956 void Compile() { 957 GenerateTargetLabel(); 958 959 if (cu_->target64) { 960 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 961 rl_method_.reg, true); 962 } else { 963 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 964 rl_method_.reg, true); 965 } 966 m2l_->OpRegCopy(rl_result_.reg, m2l_->TargetReg(kRet0, kRef)); 967 968 m2l_->OpUnconditionalBranch(cont_); 969 } 970 971 private: 972 const int type_idx_; 973 const RegLocation rl_method_; 974 const RegLocation rl_result_; 975 }; 976 977 // Add to list for future. 978 AddSlowPath(new (arena_) SlowPath(this, branch, cont, type_idx, rl_method, rl_result)); 979 980 StoreValue(rl_dest, rl_result); 981 } else { 982 // Fast path, we're done - just store result 983 StoreValue(rl_dest, rl_result); 984 } 985 } 986} 987 988void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 989 /* NOTE: Most strings should be available at compile time */ 990 int32_t offset_of_string = mirror::ObjectArray<mirror::String>::OffsetOfElement(string_idx). 991 Int32Value(); 992 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 993 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 994 // slow path, resolve string if not in dex cache 995 FlushAllRegs(); 996 LockCallTemps(); // Using explicit registers 997 998 // If the Method* is already in a register, we can save a copy. 999 RegLocation rl_method = mir_graph_->GetMethodLoc(); 1000 RegStorage r_method; 1001 if (rl_method.location == kLocPhysReg) { 1002 // A temp would conflict with register use below. 1003 DCHECK(!IsTemp(rl_method.reg)); 1004 r_method = rl_method.reg; 1005 } else { 1006 r_method = TargetReg(kArg2, kRef); 1007 LoadCurrMethodDirect(r_method); 1008 } 1009 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 1010 TargetReg(kArg0, kRef), kNotVolatile); 1011 1012 // Might call out to helper, which will return resolved string in kRet0 1013 LoadRefDisp(TargetReg(kArg0, kRef), offset_of_string, TargetReg(kRet0, kRef), kNotVolatile); 1014 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0, kRef), 0, NULL); 1015 LIR* cont = NewLIR0(kPseudoTargetLabel); 1016 1017 { 1018 // Object to generate the slow path for string resolution. 1019 class SlowPath : public LIRSlowPath { 1020 public: 1021 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, RegStorage r_method, int32_t string_idx) : 1022 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), 1023 r_method_(r_method), string_idx_(string_idx) { 1024 } 1025 1026 void Compile() { 1027 GenerateTargetLabel(); 1028 if (cu_->target64) { 1029 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pResolveString), 1030 r_method_, string_idx_, true); 1031 } else { 1032 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pResolveString), 1033 r_method_, string_idx_, true); 1034 } 1035 m2l_->OpUnconditionalBranch(cont_); 1036 } 1037 1038 private: 1039 const RegStorage r_method_; 1040 const int32_t string_idx_; 1041 }; 1042 1043 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method, string_idx)); 1044 } 1045 1046 GenBarrier(); 1047 StoreValue(rl_dest, GetReturn(kRefReg)); 1048 } else { 1049 RegLocation rl_method = LoadCurrMethod(); 1050 RegStorage res_reg = AllocTempRef(); 1051 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1052 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg, 1053 kNotVolatile); 1054 LoadRefDisp(res_reg, offset_of_string, rl_result.reg, kNotVolatile); 1055 StoreValue(rl_dest, rl_result); 1056 } 1057} 1058 1059template <size_t pointer_size> 1060static void GenNewInstanceImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, uint32_t type_idx, 1061 RegLocation rl_dest) { 1062 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 1063 // alloc will always check for resolution, do we also need to verify 1064 // access because the verifier was unable to? 1065 ThreadOffset<pointer_size> func_offset(-1); 1066 const DexFile* dex_file = cu->dex_file; 1067 CompilerDriver* driver = cu->compiler_driver; 1068 if (driver->CanAccessInstantiableTypeWithoutChecks( 1069 cu->method_idx, *dex_file, type_idx)) { 1070 bool is_type_initialized; 1071 bool use_direct_type_ptr; 1072 uintptr_t direct_type_ptr; 1073 bool is_finalizable; 1074 if (kEmbedClassInCode && 1075 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 1076 &direct_type_ptr, &is_finalizable) && 1077 !is_finalizable) { 1078 // The fast path. 1079 if (!use_direct_type_ptr) { 1080 mir_to_lir->LoadClassType(type_idx, kArg0); 1081 if (!is_type_initialized) { 1082 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1083 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1084 true); 1085 } else { 1086 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1087 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1088 true); 1089 } 1090 } else { 1091 // Use the direct pointer. 1092 if (!is_type_initialized) { 1093 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1094 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1095 } else { 1096 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1097 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1098 } 1099 } 1100 } else { 1101 // The slow path. 1102 DCHECK_EQ(func_offset.Int32Value(), -1); 1103 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObject); 1104 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1105 } 1106 DCHECK_NE(func_offset.Int32Value(), -1); 1107 } else { 1108 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectWithAccessCheck); 1109 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1110 } 1111 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 1112 mir_to_lir->StoreValue(rl_dest, rl_result); 1113} 1114 1115/* 1116 * Let helper function take care of everything. Will 1117 * call Class::NewInstanceFromCode(type_idx, method); 1118 */ 1119void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 1120 if (cu_->target64) { 1121 GenNewInstanceImpl<8>(this, cu_, type_idx, rl_dest); 1122 } else { 1123 GenNewInstanceImpl<4>(this, cu_, type_idx, rl_dest); 1124 } 1125} 1126 1127void Mir2Lir::GenThrow(RegLocation rl_src) { 1128 FlushAllRegs(); 1129 if (cu_->target64) { 1130 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), rl_src, true); 1131 } else { 1132 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException), rl_src, true); 1133 } 1134} 1135 1136// For final classes there are no sub-classes to check and so we can answer the instance-of 1137// question with simple comparisons. 1138void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1139 RegLocation rl_src) { 1140 // X86 has its own implementation. 1141 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1142 1143 RegLocation object = LoadValue(rl_src, kRefReg); 1144 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1145 RegStorage result_reg = rl_result.reg; 1146 if (IsSameReg(result_reg, object.reg)) { 1147 result_reg = AllocTypedTemp(false, kCoreReg); 1148 DCHECK(!IsSameReg(result_reg, object.reg)); 1149 } 1150 LoadConstant(result_reg, 0); // assume false 1151 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 1152 1153 RegStorage check_class = AllocTypedTemp(false, kRefReg); 1154 RegStorage object_class = AllocTypedTemp(false, kRefReg); 1155 1156 LoadCurrMethodDirect(check_class); 1157 if (use_declaring_class) { 1158 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), check_class, 1159 kNotVolatile); 1160 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1161 kNotVolatile); 1162 } else { 1163 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1164 check_class, kNotVolatile); 1165 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1166 kNotVolatile); 1167 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1168 LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); 1169 } 1170 1171 LIR* ne_branchover = NULL; 1172 // FIXME: what should we be comparing here? compressed or decompressed references? 1173 if (cu_->instruction_set == kThumb2) { 1174 OpRegReg(kOpCmp, check_class, object_class); // Same? 1175 LIR* it = OpIT(kCondEq, ""); // if-convert the test 1176 LoadConstant(result_reg, 1); // .eq case - load true 1177 OpEndIT(it); 1178 } else { 1179 ne_branchover = OpCmpBranch(kCondNe, check_class, object_class, NULL); 1180 LoadConstant(result_reg, 1); // eq case - load true 1181 } 1182 LIR* target = NewLIR0(kPseudoTargetLabel); 1183 null_branchover->target = target; 1184 if (ne_branchover != NULL) { 1185 ne_branchover->target = target; 1186 } 1187 FreeTemp(object_class); 1188 FreeTemp(check_class); 1189 if (IsTemp(result_reg)) { 1190 OpRegCopy(rl_result.reg, result_reg); 1191 FreeTemp(result_reg); 1192 } 1193 StoreValue(rl_dest, rl_result); 1194} 1195 1196void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1197 bool type_known_abstract, bool use_declaring_class, 1198 bool can_assume_type_is_in_dex_cache, 1199 uint32_t type_idx, RegLocation rl_dest, 1200 RegLocation rl_src) { 1201 // X86 has its own implementation. 1202 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1203 1204 FlushAllRegs(); 1205 // May generate a call - use explicit registers 1206 LockCallTemps(); 1207 RegStorage method_reg = TargetReg(kArg1, kRef); 1208 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1209 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1210 if (needs_access_check) { 1211 // Check we have access to type_idx and if not throw IllegalAccessError, 1212 // returns Class* in kArg0 1213 if (cu_->target64) { 1214 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1215 type_idx, true); 1216 } else { 1217 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1218 type_idx, true); 1219 } 1220 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1221 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1222 } else if (use_declaring_class) { 1223 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1224 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1225 class_reg, kNotVolatile); 1226 } else { 1227 // Load dex cache entry into class_reg (kArg2) 1228 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1229 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1230 class_reg, kNotVolatile); 1231 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1232 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1233 if (!can_assume_type_is_in_dex_cache) { 1234 // Need to test presence of type in dex cache at runtime 1235 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 1236 // Not resolved 1237 // Call out to helper, which will return resolved type in kRet0 1238 if (cu_->target64) { 1239 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx, true); 1240 } else { 1241 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true); 1242 } 1243 OpRegCopy(TargetReg(kArg2, kRef), TargetReg(kRet0, kRef)); // Align usage with fast path 1244 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); /* reload Ref */ 1245 // Rejoin code paths 1246 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 1247 hop_branch->target = hop_target; 1248 } 1249 } 1250 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1251 RegLocation rl_result = GetReturn(kCoreReg); 1252 if (cu_->instruction_set == kMips) { 1253 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1254 LoadConstant(rl_result.reg, 0); 1255 } 1256 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, NULL); 1257 1258 /* load object->klass_ */ 1259 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1260 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1261 TargetReg(kArg1, kRef), kNotVolatile); 1262 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1263 LIR* branchover = NULL; 1264 if (type_known_final) { 1265 // rl_result == ref == null == 0. 1266 if (cu_->instruction_set == kThumb2) { 1267 OpRegReg(kOpCmp, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef)); // Same? 1268 LIR* it = OpIT(kCondEq, "E"); // if-convert the test 1269 LoadConstant(rl_result.reg, 1); // .eq case - load true 1270 LoadConstant(rl_result.reg, 0); // .ne case - load false 1271 OpEndIT(it); 1272 } else { 1273 LoadConstant(rl_result.reg, 0); // ne case - load false 1274 branchover = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1275 LoadConstant(rl_result.reg, 1); // eq case - load true 1276 } 1277 } else { 1278 if (cu_->instruction_set == kThumb2) { 1279 RegStorage r_tgt = cu_->target64 ? 1280 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1281 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1282 LIR* it = nullptr; 1283 if (!type_known_abstract) { 1284 /* Uses conditional nullification */ 1285 OpRegReg(kOpCmp, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef)); // Same? 1286 it = OpIT(kCondEq, "EE"); // if-convert the test 1287 LoadConstant(TargetReg(kArg0, kNotWide), 1); // .eq case - load true 1288 } 1289 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1290 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1291 if (it != nullptr) { 1292 OpEndIT(it); 1293 } 1294 FreeTemp(r_tgt); 1295 } else { 1296 if (!type_known_abstract) { 1297 /* Uses branchovers */ 1298 LoadConstant(rl_result.reg, 1); // assume true 1299 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1300 } 1301 RegStorage r_tgt = cu_->target64 ? 1302 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1303 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1304 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1305 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1306 FreeTemp(r_tgt); 1307 } 1308 } 1309 // TODO: only clobber when type isn't final? 1310 ClobberCallerSave(); 1311 /* branch targets here */ 1312 LIR* target = NewLIR0(kPseudoTargetLabel); 1313 StoreValue(rl_dest, rl_result); 1314 branch1->target = target; 1315 if (branchover != NULL) { 1316 branchover->target = target; 1317 } 1318} 1319 1320void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1321 bool type_known_final, type_known_abstract, use_declaring_class; 1322 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1323 *cu_->dex_file, 1324 type_idx, 1325 &type_known_final, 1326 &type_known_abstract, 1327 &use_declaring_class); 1328 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1329 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1330 1331 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1332 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1333 } else { 1334 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1335 use_declaring_class, can_assume_type_is_in_dex_cache, 1336 type_idx, rl_dest, rl_src); 1337 } 1338} 1339 1340void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1341 bool type_known_final, type_known_abstract, use_declaring_class; 1342 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1343 *cu_->dex_file, 1344 type_idx, 1345 &type_known_final, 1346 &type_known_abstract, 1347 &use_declaring_class); 1348 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1349 // of the exception throw path. 1350 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1351 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1352 // Verifier type analysis proved this check cast would never cause an exception. 1353 return; 1354 } 1355 FlushAllRegs(); 1356 // May generate a call - use explicit registers 1357 LockCallTemps(); 1358 RegStorage method_reg = TargetReg(kArg1, kRef); 1359 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1360 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1361 if (needs_access_check) { 1362 // Check we have access to type_idx and if not throw IllegalAccessError, 1363 // returns Class* in kRet0 1364 // InitializeTypeAndVerifyAccess(idx, method) 1365 if (cu_->target64) { 1366 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1367 type_idx, true); 1368 } else { 1369 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1370 type_idx, true); 1371 } 1372 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1373 } else if (use_declaring_class) { 1374 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1375 class_reg, kNotVolatile); 1376 } else { 1377 // Load dex cache entry into class_reg (kArg2) 1378 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1379 class_reg, kNotVolatile); 1380 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1381 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1382 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1383 // Need to test presence of type in dex cache at runtime 1384 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1385 LIR* cont = NewLIR0(kPseudoTargetLabel); 1386 1387 // Slow path to initialize the type. Executed if the type is NULL. 1388 class SlowPath : public LIRSlowPath { 1389 public: 1390 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1391 const RegStorage class_reg) : 1392 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1393 class_reg_(class_reg) { 1394 } 1395 1396 void Compile() { 1397 GenerateTargetLabel(); 1398 1399 // Call out to helper, which will return resolved type in kArg0 1400 // InitializeTypeFromCode(idx, method) 1401 if (m2l_->cu_->target64) { 1402 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1403 m2l_->TargetReg(kArg1, kRef), true); 1404 } else { 1405 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1406 m2l_->TargetReg(kArg1, kRef), true); 1407 } 1408 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1409 m2l_->OpUnconditionalBranch(cont_); 1410 } 1411 1412 public: 1413 const int type_idx_; 1414 const RegStorage class_reg_; 1415 }; 1416 1417 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, type_idx, class_reg)); 1418 } 1419 } 1420 // At this point, class_reg (kArg2) has class 1421 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1422 1423 // Slow path for the case where the classes are not equal. In this case we need 1424 // to call a helper function to do the check. 1425 class SlowPath : public LIRSlowPath { 1426 public: 1427 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1428 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1429 } 1430 1431 void Compile() { 1432 GenerateTargetLabel(); 1433 1434 if (load_) { 1435 m2l_->LoadRefDisp(m2l_->TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1436 m2l_->TargetReg(kArg1, kRef), kNotVolatile); 1437 } 1438 if (m2l_->cu_->target64) { 1439 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pCheckCast), 1440 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1441 true); 1442 } else { 1443 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pCheckCast), 1444 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1445 true); 1446 } 1447 1448 m2l_->OpUnconditionalBranch(cont_); 1449 } 1450 1451 private: 1452 const bool load_; 1453 }; 1454 1455 if (type_known_abstract) { 1456 // Easier case, run slow path if target is non-null (slow path will load from target) 1457 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0, kRef), 0, nullptr); 1458 LIR* cont = NewLIR0(kPseudoTargetLabel); 1459 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1460 } else { 1461 // Harder, more common case. We need to generate a forward branch over the load 1462 // if the target is null. If it's non-null we perform the load and branch to the 1463 // slow path if the classes are not equal. 1464 1465 /* Null is OK - continue */ 1466 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, nullptr); 1467 /* load object->klass_ */ 1468 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1469 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1470 TargetReg(kArg1, kRef), kNotVolatile); 1471 1472 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), class_reg, nullptr); 1473 LIR* cont = NewLIR0(kPseudoTargetLabel); 1474 1475 // Add the slow path that will not perform load since this is already done. 1476 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1477 1478 // Set the null check to branch to the continuation. 1479 branch1->target = cont; 1480 } 1481} 1482 1483void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1484 RegLocation rl_src1, RegLocation rl_src2) { 1485 RegLocation rl_result; 1486 if (cu_->instruction_set == kThumb2) { 1487 /* 1488 * NOTE: This is the one place in the code in which we might have 1489 * as many as six live temporary registers. There are 5 in the normal 1490 * set for Arm. Until we have spill capabilities, temporarily add 1491 * lr to the temp set. It is safe to do this locally, but note that 1492 * lr is used explicitly elsewhere in the code generator and cannot 1493 * normally be used as a general temp register. 1494 */ 1495 MarkTemp(TargetReg(kLr, kNotWide)); // Add lr to the temp pool 1496 FreeTemp(TargetReg(kLr, kNotWide)); // and make it available 1497 } 1498 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1499 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1500 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1501 // The longs may overlap - use intermediate temp if so 1502 if ((rl_result.reg.GetLowReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg())) { 1503 RegStorage t_reg = AllocTemp(); 1504 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1505 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1506 OpRegCopy(rl_result.reg.GetLow(), t_reg); 1507 FreeTemp(t_reg); 1508 } else { 1509 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1510 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1511 } 1512 /* 1513 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1514 * following StoreValueWide might need to allocate a temp register. 1515 * To further work around the lack of a spill capability, explicitly 1516 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1517 * Remove when spill is functional. 1518 */ 1519 FreeRegLocTemps(rl_result, rl_src1); 1520 FreeRegLocTemps(rl_result, rl_src2); 1521 StoreValueWide(rl_dest, rl_result); 1522 if (cu_->instruction_set == kThumb2) { 1523 Clobber(TargetReg(kLr, kNotWide)); 1524 UnmarkTemp(TargetReg(kLr, kNotWide)); // Remove lr from the temp pool 1525 } 1526} 1527 1528 1529template <size_t pointer_size> 1530static void GenShiftOpLongCall(Mir2Lir* mir_to_lir, Instruction::Code opcode, RegLocation rl_src1, 1531 RegLocation rl_shift) { 1532 ThreadOffset<pointer_size> func_offset(-1); 1533 1534 switch (opcode) { 1535 case Instruction::SHL_LONG: 1536 case Instruction::SHL_LONG_2ADDR: 1537 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShlLong); 1538 break; 1539 case Instruction::SHR_LONG: 1540 case Instruction::SHR_LONG_2ADDR: 1541 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShrLong); 1542 break; 1543 case Instruction::USHR_LONG: 1544 case Instruction::USHR_LONG_2ADDR: 1545 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pUshrLong); 1546 break; 1547 default: 1548 LOG(FATAL) << "Unexpected case"; 1549 } 1550 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 1551 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1552} 1553 1554void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1555 RegLocation rl_src1, RegLocation rl_shift) { 1556 if (cu_->target64) { 1557 GenShiftOpLongCall<8>(this, opcode, rl_src1, rl_shift); 1558 } else { 1559 GenShiftOpLongCall<4>(this, opcode, rl_src1, rl_shift); 1560 } 1561 RegLocation rl_result = GetReturnWide(kCoreReg); 1562 StoreValueWide(rl_dest, rl_result); 1563} 1564 1565 1566void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1567 RegLocation rl_src1, RegLocation rl_src2) { 1568 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1569 OpKind op = kOpBkpt; 1570 bool is_div_rem = false; 1571 bool check_zero = false; 1572 bool unary = false; 1573 RegLocation rl_result; 1574 bool shift_op = false; 1575 switch (opcode) { 1576 case Instruction::NEG_INT: 1577 op = kOpNeg; 1578 unary = true; 1579 break; 1580 case Instruction::NOT_INT: 1581 op = kOpMvn; 1582 unary = true; 1583 break; 1584 case Instruction::ADD_INT: 1585 case Instruction::ADD_INT_2ADDR: 1586 op = kOpAdd; 1587 break; 1588 case Instruction::SUB_INT: 1589 case Instruction::SUB_INT_2ADDR: 1590 op = kOpSub; 1591 break; 1592 case Instruction::MUL_INT: 1593 case Instruction::MUL_INT_2ADDR: 1594 op = kOpMul; 1595 break; 1596 case Instruction::DIV_INT: 1597 case Instruction::DIV_INT_2ADDR: 1598 check_zero = true; 1599 op = kOpDiv; 1600 is_div_rem = true; 1601 break; 1602 /* NOTE: returns in kArg1 */ 1603 case Instruction::REM_INT: 1604 case Instruction::REM_INT_2ADDR: 1605 check_zero = true; 1606 op = kOpRem; 1607 is_div_rem = true; 1608 break; 1609 case Instruction::AND_INT: 1610 case Instruction::AND_INT_2ADDR: 1611 op = kOpAnd; 1612 break; 1613 case Instruction::OR_INT: 1614 case Instruction::OR_INT_2ADDR: 1615 op = kOpOr; 1616 break; 1617 case Instruction::XOR_INT: 1618 case Instruction::XOR_INT_2ADDR: 1619 op = kOpXor; 1620 break; 1621 case Instruction::SHL_INT: 1622 case Instruction::SHL_INT_2ADDR: 1623 shift_op = true; 1624 op = kOpLsl; 1625 break; 1626 case Instruction::SHR_INT: 1627 case Instruction::SHR_INT_2ADDR: 1628 shift_op = true; 1629 op = kOpAsr; 1630 break; 1631 case Instruction::USHR_INT: 1632 case Instruction::USHR_INT_2ADDR: 1633 shift_op = true; 1634 op = kOpLsr; 1635 break; 1636 default: 1637 LOG(FATAL) << "Invalid word arith op: " << opcode; 1638 } 1639 if (!is_div_rem) { 1640 if (unary) { 1641 rl_src1 = LoadValue(rl_src1, kCoreReg); 1642 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1643 OpRegReg(op, rl_result.reg, rl_src1.reg); 1644 } else { 1645 if ((shift_op) && (cu_->instruction_set != kArm64)) { 1646 rl_src2 = LoadValue(rl_src2, kCoreReg); 1647 RegStorage t_reg = AllocTemp(); 1648 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg, 31); 1649 rl_src1 = LoadValue(rl_src1, kCoreReg); 1650 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1651 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 1652 FreeTemp(t_reg); 1653 } else { 1654 rl_src1 = LoadValue(rl_src1, kCoreReg); 1655 rl_src2 = LoadValue(rl_src2, kCoreReg); 1656 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1657 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); 1658 } 1659 } 1660 StoreValue(rl_dest, rl_result); 1661 } else { 1662 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1663 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1664 rl_src1 = LoadValue(rl_src1, kCoreReg); 1665 rl_src2 = LoadValue(rl_src2, kCoreReg); 1666 if (check_zero) { 1667 GenDivZeroCheck(rl_src2.reg); 1668 } 1669 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1670 done = true; 1671 } else if (cu_->instruction_set == kThumb2) { 1672 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1673 // Use ARM SDIV instruction for division. For remainder we also need to 1674 // calculate using a MUL and subtract. 1675 rl_src1 = LoadValue(rl_src1, kCoreReg); 1676 rl_src2 = LoadValue(rl_src2, kCoreReg); 1677 if (check_zero) { 1678 GenDivZeroCheck(rl_src2.reg); 1679 } 1680 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1681 done = true; 1682 } 1683 } 1684 1685 // If we haven't already generated the code use the callout function. 1686 if (!done) { 1687 FlushAllRegs(); /* Send everything to home location */ 1688 LoadValueDirectFixed(rl_src2, TargetReg(kArg1, kNotWide)); 1689 RegStorage r_tgt = cu_->target64 ? 1690 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod)) : 1691 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod)); 1692 LoadValueDirectFixed(rl_src1, TargetReg(kArg0, kNotWide)); 1693 if (check_zero) { 1694 GenDivZeroCheck(TargetReg(kArg1, kNotWide)); 1695 } 1696 // NOTE: callout here is not a safepoint. 1697 if (cu_->target64) { 1698 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), false /* not a safepoint */); 1699 } else { 1700 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), false /* not a safepoint */); 1701 } 1702 if (op == kOpDiv) 1703 rl_result = GetReturn(kCoreReg); 1704 else 1705 rl_result = GetReturnAlt(); 1706 } 1707 StoreValue(rl_dest, rl_result); 1708 } 1709} 1710 1711/* 1712 * The following are the first-level codegen routines that analyze the format 1713 * of each bytecode then either dispatch special purpose codegen routines 1714 * or produce corresponding Thumb instructions directly. 1715 */ 1716 1717// Returns true if no more than two bits are set in 'x'. 1718static bool IsPopCountLE2(unsigned int x) { 1719 x &= x - 1; 1720 return (x & (x - 1)) == 0; 1721} 1722 1723// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1724// and store the result in 'rl_dest'. 1725bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1726 RegLocation rl_src, RegLocation rl_dest, int lit) { 1727 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1728 return false; 1729 } 1730 // No divide instruction for Arm, so check for more special cases 1731 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1732 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1733 } 1734 int k = LowestSetBit(lit); 1735 if (k >= 30) { 1736 // Avoid special cases. 1737 return false; 1738 } 1739 rl_src = LoadValue(rl_src, kCoreReg); 1740 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1741 if (is_div) { 1742 RegStorage t_reg = AllocTemp(); 1743 if (lit == 2) { 1744 // Division by 2 is by far the most common division by constant. 1745 OpRegRegImm(kOpLsr, t_reg, rl_src.reg, 32 - k); 1746 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1747 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1748 } else { 1749 OpRegRegImm(kOpAsr, t_reg, rl_src.reg, 31); 1750 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1751 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1752 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1753 } 1754 } else { 1755 RegStorage t_reg1 = AllocTemp(); 1756 RegStorage t_reg2 = AllocTemp(); 1757 if (lit == 2) { 1758 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg, 32 - k); 1759 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1760 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1761 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1762 } else { 1763 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg, 31); 1764 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1765 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1766 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1767 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1768 } 1769 } 1770 StoreValue(rl_dest, rl_result); 1771 return true; 1772} 1773 1774// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1775// and store the result in 'rl_dest'. 1776bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1777 if (lit < 0) { 1778 return false; 1779 } 1780 if (lit == 0) { 1781 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1782 LoadConstant(rl_result.reg, 0); 1783 StoreValue(rl_dest, rl_result); 1784 return true; 1785 } 1786 if (lit == 1) { 1787 rl_src = LoadValue(rl_src, kCoreReg); 1788 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1789 OpRegCopy(rl_result.reg, rl_src.reg); 1790 StoreValue(rl_dest, rl_result); 1791 return true; 1792 } 1793 // There is RegRegRegShift on Arm, so check for more special cases 1794 if (cu_->instruction_set == kThumb2) { 1795 return EasyMultiply(rl_src, rl_dest, lit); 1796 } 1797 // Can we simplify this multiplication? 1798 bool power_of_two = false; 1799 bool pop_count_le2 = false; 1800 bool power_of_two_minus_one = false; 1801 if (IsPowerOfTwo(lit)) { 1802 power_of_two = true; 1803 } else if (IsPopCountLE2(lit)) { 1804 pop_count_le2 = true; 1805 } else if (IsPowerOfTwo(lit + 1)) { 1806 power_of_two_minus_one = true; 1807 } else { 1808 return false; 1809 } 1810 rl_src = LoadValue(rl_src, kCoreReg); 1811 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1812 if (power_of_two) { 1813 // Shift. 1814 OpRegRegImm(kOpLsl, rl_result.reg, rl_src.reg, LowestSetBit(lit)); 1815 } else if (pop_count_le2) { 1816 // Shift and add and shift. 1817 int first_bit = LowestSetBit(lit); 1818 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1819 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1820 } else { 1821 // Reverse subtract: (src << (shift + 1)) - src. 1822 DCHECK(power_of_two_minus_one); 1823 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1824 RegStorage t_reg = AllocTemp(); 1825 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, LowestSetBit(lit + 1)); 1826 OpRegRegReg(kOpSub, rl_result.reg, t_reg, rl_src.reg); 1827 } 1828 StoreValue(rl_dest, rl_result); 1829 return true; 1830} 1831 1832void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1833 int lit) { 1834 RegLocation rl_result; 1835 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1836 int shift_op = false; 1837 bool is_div = false; 1838 1839 switch (opcode) { 1840 case Instruction::RSUB_INT_LIT8: 1841 case Instruction::RSUB_INT: { 1842 rl_src = LoadValue(rl_src, kCoreReg); 1843 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1844 if (cu_->instruction_set == kThumb2) { 1845 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, lit); 1846 } else { 1847 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1848 OpRegImm(kOpAdd, rl_result.reg, lit); 1849 } 1850 StoreValue(rl_dest, rl_result); 1851 return; 1852 } 1853 1854 case Instruction::SUB_INT: 1855 case Instruction::SUB_INT_2ADDR: 1856 lit = -lit; 1857 // Intended fallthrough 1858 case Instruction::ADD_INT: 1859 case Instruction::ADD_INT_2ADDR: 1860 case Instruction::ADD_INT_LIT8: 1861 case Instruction::ADD_INT_LIT16: 1862 op = kOpAdd; 1863 break; 1864 case Instruction::MUL_INT: 1865 case Instruction::MUL_INT_2ADDR: 1866 case Instruction::MUL_INT_LIT8: 1867 case Instruction::MUL_INT_LIT16: { 1868 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1869 return; 1870 } 1871 op = kOpMul; 1872 break; 1873 } 1874 case Instruction::AND_INT: 1875 case Instruction::AND_INT_2ADDR: 1876 case Instruction::AND_INT_LIT8: 1877 case Instruction::AND_INT_LIT16: 1878 op = kOpAnd; 1879 break; 1880 case Instruction::OR_INT: 1881 case Instruction::OR_INT_2ADDR: 1882 case Instruction::OR_INT_LIT8: 1883 case Instruction::OR_INT_LIT16: 1884 op = kOpOr; 1885 break; 1886 case Instruction::XOR_INT: 1887 case Instruction::XOR_INT_2ADDR: 1888 case Instruction::XOR_INT_LIT8: 1889 case Instruction::XOR_INT_LIT16: 1890 op = kOpXor; 1891 break; 1892 case Instruction::SHL_INT_LIT8: 1893 case Instruction::SHL_INT: 1894 case Instruction::SHL_INT_2ADDR: 1895 lit &= 31; 1896 shift_op = true; 1897 op = kOpLsl; 1898 break; 1899 case Instruction::SHR_INT_LIT8: 1900 case Instruction::SHR_INT: 1901 case Instruction::SHR_INT_2ADDR: 1902 lit &= 31; 1903 shift_op = true; 1904 op = kOpAsr; 1905 break; 1906 case Instruction::USHR_INT_LIT8: 1907 case Instruction::USHR_INT: 1908 case Instruction::USHR_INT_2ADDR: 1909 lit &= 31; 1910 shift_op = true; 1911 op = kOpLsr; 1912 break; 1913 1914 case Instruction::DIV_INT: 1915 case Instruction::DIV_INT_2ADDR: 1916 case Instruction::DIV_INT_LIT8: 1917 case Instruction::DIV_INT_LIT16: 1918 case Instruction::REM_INT: 1919 case Instruction::REM_INT_2ADDR: 1920 case Instruction::REM_INT_LIT8: 1921 case Instruction::REM_INT_LIT16: { 1922 if (lit == 0) { 1923 GenDivZeroException(); 1924 return; 1925 } 1926 if ((opcode == Instruction::DIV_INT) || 1927 (opcode == Instruction::DIV_INT_2ADDR) || 1928 (opcode == Instruction::DIV_INT_LIT8) || 1929 (opcode == Instruction::DIV_INT_LIT16)) { 1930 is_div = true; 1931 } else { 1932 is_div = false; 1933 } 1934 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1935 return; 1936 } 1937 1938 bool done = false; 1939 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1940 rl_src = LoadValue(rl_src, kCoreReg); 1941 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1942 done = true; 1943 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1944 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1945 done = true; 1946 } else if (cu_->instruction_set == kThumb2) { 1947 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1948 // Use ARM SDIV instruction for division. For remainder we also need to 1949 // calculate using a MUL and subtract. 1950 rl_src = LoadValue(rl_src, kCoreReg); 1951 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1952 done = true; 1953 } 1954 } 1955 1956 if (!done) { 1957 FlushAllRegs(); /* Everything to home location. */ 1958 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kNotWide)); 1959 Clobber(TargetReg(kArg0, kNotWide)); 1960 if (cu_->target64) { 1961 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), TargetReg(kArg0, kNotWide), 1962 lit, false); 1963 } else { 1964 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), TargetReg(kArg0, kNotWide), 1965 lit, false); 1966 } 1967 if (is_div) 1968 rl_result = GetReturn(kCoreReg); 1969 else 1970 rl_result = GetReturnAlt(); 1971 } 1972 StoreValue(rl_dest, rl_result); 1973 return; 1974 } 1975 default: 1976 LOG(FATAL) << "Unexpected opcode " << opcode; 1977 } 1978 rl_src = LoadValue(rl_src, kCoreReg); 1979 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1980 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 1981 if (shift_op && (lit == 0)) { 1982 OpRegCopy(rl_result.reg, rl_src.reg); 1983 } else { 1984 OpRegRegImm(op, rl_result.reg, rl_src.reg, lit); 1985 } 1986 StoreValue(rl_dest, rl_result); 1987} 1988 1989template <size_t pointer_size> 1990static void GenArithOpLongImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, Instruction::Code opcode, 1991 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 1992 RegLocation rl_result; 1993 OpKind first_op = kOpBkpt; 1994 OpKind second_op = kOpBkpt; 1995 bool call_out = false; 1996 bool check_zero = false; 1997 ThreadOffset<pointer_size> func_offset(-1); 1998 int ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 1999 2000 switch (opcode) { 2001 case Instruction::NOT_LONG: 2002 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2003 mir_to_lir->GenNotLong(rl_dest, rl_src2); 2004 return; 2005 } 2006 rl_src2 = mir_to_lir->LoadValueWide(rl_src2, kCoreReg); 2007 rl_result = mir_to_lir->EvalLoc(rl_dest, kCoreReg, true); 2008 // Check for destructive overlap 2009 if (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg()) { 2010 RegStorage t_reg = mir_to_lir->AllocTemp(); 2011 mir_to_lir->OpRegCopy(t_reg, rl_src2.reg.GetHigh()); 2012 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2013 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), t_reg); 2014 mir_to_lir->FreeTemp(t_reg); 2015 } else { 2016 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2017 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); 2018 } 2019 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2020 return; 2021 case Instruction::ADD_LONG: 2022 case Instruction::ADD_LONG_2ADDR: 2023 if (cu->instruction_set != kThumb2) { 2024 mir_to_lir->GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 2025 return; 2026 } 2027 first_op = kOpAdd; 2028 second_op = kOpAdc; 2029 break; 2030 case Instruction::SUB_LONG: 2031 case Instruction::SUB_LONG_2ADDR: 2032 if (cu->instruction_set != kThumb2) { 2033 mir_to_lir->GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 2034 return; 2035 } 2036 first_op = kOpSub; 2037 second_op = kOpSbc; 2038 break; 2039 case Instruction::MUL_LONG: 2040 case Instruction::MUL_LONG_2ADDR: 2041 if (cu->instruction_set != kMips) { 2042 mir_to_lir->GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 2043 return; 2044 } else { 2045 call_out = true; 2046 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2047 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmul); 2048 } 2049 break; 2050 case Instruction::DIV_LONG: 2051 case Instruction::DIV_LONG_2ADDR: 2052 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2053 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); 2054 return; 2055 } 2056 call_out = true; 2057 check_zero = true; 2058 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2059 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLdiv); 2060 break; 2061 case Instruction::REM_LONG: 2062 case Instruction::REM_LONG_2ADDR: 2063 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2064 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); 2065 return; 2066 } 2067 call_out = true; 2068 check_zero = true; 2069 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmod); 2070 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 2071 ret_reg = (cu->instruction_set == kThumb2) ? mir_to_lir->TargetReg(kArg2, kNotWide).GetReg() : 2072 mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2073 break; 2074 case Instruction::AND_LONG_2ADDR: 2075 case Instruction::AND_LONG: 2076 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2077 cu->instruction_set == kArm64) { 2078 return mir_to_lir->GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 2079 } 2080 first_op = kOpAnd; 2081 second_op = kOpAnd; 2082 break; 2083 case Instruction::OR_LONG: 2084 case Instruction::OR_LONG_2ADDR: 2085 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2086 cu->instruction_set == kArm64) { 2087 mir_to_lir->GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 2088 return; 2089 } 2090 first_op = kOpOr; 2091 second_op = kOpOr; 2092 break; 2093 case Instruction::XOR_LONG: 2094 case Instruction::XOR_LONG_2ADDR: 2095 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2096 cu->instruction_set == kArm64) { 2097 mir_to_lir->GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 2098 return; 2099 } 2100 first_op = kOpXor; 2101 second_op = kOpXor; 2102 break; 2103 case Instruction::NEG_LONG: { 2104 mir_to_lir->GenNegLong(rl_dest, rl_src2); 2105 return; 2106 } 2107 default: 2108 LOG(FATAL) << "Invalid long arith op"; 2109 } 2110 if (!call_out) { 2111 mir_to_lir->GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 2112 } else { 2113 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 2114 if (check_zero) { 2115 RegStorage r_tmp1 = mir_to_lir->TargetReg(kArg0, kWide); 2116 RegStorage r_tmp2 = mir_to_lir->TargetReg(kArg2, kWide); 2117 mir_to_lir->LoadValueDirectWideFixed(rl_src2, r_tmp2); 2118 RegStorage r_tgt = mir_to_lir->CallHelperSetup(func_offset); 2119 mir_to_lir->GenDivZeroCheckWide(r_tmp2); 2120 mir_to_lir->LoadValueDirectWideFixed(rl_src1, r_tmp1); 2121 // NOTE: callout here is not a safepoint 2122 mir_to_lir->CallHelper(r_tgt, func_offset, false /* not safepoint */); 2123 } else { 2124 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 2125 } 2126 // Adjust return regs in to handle case of rem returning kArg2/kArg3 2127 if (ret_reg == mir_to_lir->TargetReg(kRet0, kNotWide).GetReg()) 2128 rl_result = mir_to_lir->GetReturnWide(kCoreReg); 2129 else 2130 rl_result = mir_to_lir->GetReturnWideAlt(); 2131 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2132 } 2133} 2134 2135void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 2136 RegLocation rl_src1, RegLocation rl_src2) { 2137 if (cu_->target64) { 2138 GenArithOpLongImpl<8>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2139 } else { 2140 GenArithOpLongImpl<4>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2141 } 2142} 2143 2144void Mir2Lir::GenConst(RegLocation rl_dest, int value) { 2145 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2146 LoadConstantNoClobber(rl_result.reg, value); 2147 StoreValue(rl_dest, rl_result); 2148 if (value == 0) { 2149 Workaround7250540(rl_dest, rl_result.reg); 2150 } 2151} 2152 2153template <size_t pointer_size> 2154void Mir2Lir::GenConversionCall(ThreadOffset<pointer_size> func_offset, 2155 RegLocation rl_dest, RegLocation rl_src) { 2156 /* 2157 * Don't optimize the register usage since it calls out to support 2158 * functions 2159 */ 2160 DCHECK_EQ(pointer_size, GetInstructionSetPointerSize(cu_->instruction_set)); 2161 2162 FlushAllRegs(); /* Send everything to home location */ 2163 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 2164 if (rl_dest.wide) { 2165 RegLocation rl_result; 2166 rl_result = GetReturnWide(LocToRegClass(rl_dest)); 2167 StoreValueWide(rl_dest, rl_result); 2168 } else { 2169 RegLocation rl_result; 2170 rl_result = GetReturn(LocToRegClass(rl_dest)); 2171 StoreValue(rl_dest, rl_result); 2172 } 2173} 2174template void Mir2Lir::GenConversionCall(ThreadOffset<4> func_offset, 2175 RegLocation rl_dest, RegLocation rl_src); 2176template void Mir2Lir::GenConversionCall(ThreadOffset<8> func_offset, 2177 RegLocation rl_dest, RegLocation rl_src); 2178 2179class SuspendCheckSlowPath : public Mir2Lir::LIRSlowPath { 2180 public: 2181 SuspendCheckSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont) 2182 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont) { 2183 } 2184 2185 void Compile() OVERRIDE { 2186 m2l_->ResetRegPool(); 2187 m2l_->ResetDefTracking(); 2188 GenerateTargetLabel(kPseudoSuspendTarget); 2189 if (cu_->target64) { 2190 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pTestSuspend), true); 2191 } else { 2192 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pTestSuspend), true); 2193 } 2194 if (cont_ != nullptr) { 2195 m2l_->OpUnconditionalBranch(cont_); 2196 } 2197 } 2198}; 2199 2200/* Check if we need to check for pending suspend request */ 2201void Mir2Lir::GenSuspendTest(int opt_flags) { 2202 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2203 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2204 return; 2205 } 2206 FlushAllRegs(); 2207 LIR* branch = OpTestSuspend(NULL); 2208 LIR* cont = NewLIR0(kPseudoTargetLabel); 2209 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, cont)); 2210 } else { 2211 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2212 return; 2213 } 2214 FlushAllRegs(); // TODO: needed? 2215 LIR* inst = CheckSuspendUsingLoad(); 2216 MarkSafepointPC(inst); 2217 } 2218} 2219 2220/* Check if we need to check for pending suspend request */ 2221void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 2222 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2223 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2224 OpUnconditionalBranch(target); 2225 return; 2226 } 2227 OpTestSuspend(target); 2228 FlushAllRegs(); 2229 LIR* branch = OpUnconditionalBranch(nullptr); 2230 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, target)); 2231 } else { 2232 // For the implicit suspend check, just perform the trigger 2233 // load and branch to the target. 2234 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2235 OpUnconditionalBranch(target); 2236 return; 2237 } 2238 FlushAllRegs(); 2239 LIR* inst = CheckSuspendUsingLoad(); 2240 MarkSafepointPC(inst); 2241 OpUnconditionalBranch(target); 2242 } 2243} 2244 2245/* Call out to helper assembly routine that will null check obj and then lock it. */ 2246void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2247 FlushAllRegs(); 2248 if (cu_->target64) { 2249 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pLockObject), rl_src, true); 2250 } else { 2251 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pLockObject), rl_src, true); 2252 } 2253} 2254 2255/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2256void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2257 FlushAllRegs(); 2258 if (cu_->target64) { 2259 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject), rl_src, true); 2260 } else { 2261 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject), rl_src, true); 2262 } 2263} 2264 2265/* Generic code for generating a wide constant into a VR. */ 2266void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2267 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2268 LoadConstantWide(rl_result.reg, value); 2269 StoreValueWide(rl_dest, rl_result); 2270} 2271 2272} // namespace art 2273