gen_common.cc revision 90969af6deb19b1dbe356d62fe68d8f5698d3d8f
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include "dex/compiler_ir.h" 17#include "dex/compiler_internals.h" 18#include "dex/quick/arm/arm_lir.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object_array-inl.h" 23#include "mirror/object-inl.h" 24#include "verifier/method_verifier.h" 25#include <functional> 26 27namespace art { 28 29// Shortcuts to repeatedly used long types. 30typedef mirror::ObjectArray<mirror::Object> ObjArray; 31typedef mirror::ObjectArray<mirror::Class> ClassArray; 32 33/* 34 * This source files contains "gen" codegen routines that should 35 * be applicable to most targets. Only mid-level support utilities 36 * and "op" calls may be used here. 37 */ 38 39/* 40 * Generate a kPseudoBarrier marker to indicate the boundary of special 41 * blocks. 42 */ 43void Mir2Lir::GenBarrier() { 44 LIR* barrier = NewLIR0(kPseudoBarrier); 45 /* Mark all resources as being clobbered */ 46 DCHECK(!barrier->flags.use_def_invalid); 47 barrier->u.m.def_mask = &kEncodeAll; 48} 49 50void Mir2Lir::GenDivZeroException() { 51 LIR* branch = OpUnconditionalBranch(nullptr); 52 AddDivZeroCheckSlowPath(branch); 53} 54 55void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { 56 LIR* branch = OpCondBranch(c_code, nullptr); 57 AddDivZeroCheckSlowPath(branch); 58} 59 60void Mir2Lir::GenDivZeroCheck(RegStorage reg) { 61 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 62 AddDivZeroCheckSlowPath(branch); 63} 64 65void Mir2Lir::AddDivZeroCheckSlowPath(LIR* branch) { 66 class DivZeroCheckSlowPath : public Mir2Lir::LIRSlowPath { 67 public: 68 DivZeroCheckSlowPath(Mir2Lir* m2l, LIR* branch) 69 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 70 } 71 72 void Compile() OVERRIDE { 73 m2l_->ResetRegPool(); 74 m2l_->ResetDefTracking(); 75 GenerateTargetLabel(kPseudoThrowTarget); 76 if (m2l_->cu_->target64) { 77 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowDivZero), true); 78 } else { 79 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowDivZero), true); 80 } 81 } 82 }; 83 84 AddSlowPath(new (arena_) DivZeroCheckSlowPath(this, branch)); 85} 86 87void Mir2Lir::GenArrayBoundsCheck(RegStorage index, RegStorage length) { 88 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 89 public: 90 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, RegStorage index, RegStorage length) 91 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 92 index_(index), length_(length) { 93 } 94 95 void Compile() OVERRIDE { 96 m2l_->ResetRegPool(); 97 m2l_->ResetDefTracking(); 98 GenerateTargetLabel(kPseudoThrowTarget); 99 if (m2l_->cu_->target64) { 100 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 101 index_, length_, true); 102 } else { 103 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 104 index_, length_, true); 105 } 106 } 107 108 private: 109 const RegStorage index_; 110 const RegStorage length_; 111 }; 112 113 LIR* branch = OpCmpBranch(kCondUge, index, length, nullptr); 114 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 115} 116 117void Mir2Lir::GenArrayBoundsCheck(int index, RegStorage length) { 118 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 119 public: 120 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, int index, RegStorage length) 121 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 122 index_(index), length_(length) { 123 } 124 125 void Compile() OVERRIDE { 126 m2l_->ResetRegPool(); 127 m2l_->ResetDefTracking(); 128 GenerateTargetLabel(kPseudoThrowTarget); 129 130 RegStorage arg1_32 = m2l_->TargetReg(kArg1, kNotWide); 131 RegStorage arg0_32 = m2l_->TargetReg(kArg0, kNotWide); 132 133 m2l_->OpRegCopy(arg1_32, length_); 134 m2l_->LoadConstant(arg0_32, index_); 135 if (m2l_->cu_->target64) { 136 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 137 arg0_32, arg1_32, true); 138 } else { 139 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 140 arg0_32, arg1_32, true); 141 } 142 } 143 144 private: 145 const int32_t index_; 146 const RegStorage length_; 147 }; 148 149 LIR* branch = OpCmpImmBranch(kCondLs, length, index, nullptr); 150 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 151} 152 153LIR* Mir2Lir::GenNullCheck(RegStorage reg) { 154 class NullCheckSlowPath : public Mir2Lir::LIRSlowPath { 155 public: 156 NullCheckSlowPath(Mir2Lir* m2l, LIR* branch) 157 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 158 } 159 160 void Compile() OVERRIDE { 161 m2l_->ResetRegPool(); 162 m2l_->ResetDefTracking(); 163 GenerateTargetLabel(kPseudoThrowTarget); 164 if (m2l_->cu_->target64) { 165 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowNullPointer), true); 166 } else { 167 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowNullPointer), true); 168 } 169 } 170 }; 171 172 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 173 AddSlowPath(new (arena_) NullCheckSlowPath(this, branch)); 174 return branch; 175} 176 177/* Perform null-check on a register. */ 178LIR* Mir2Lir::GenNullCheck(RegStorage m_reg, int opt_flags) { 179 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 180 return GenExplicitNullCheck(m_reg, opt_flags); 181 } 182 return nullptr; 183} 184 185/* Perform an explicit null-check on a register. */ 186LIR* Mir2Lir::GenExplicitNullCheck(RegStorage m_reg, int opt_flags) { 187 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 188 return NULL; 189 } 190 return GenNullCheck(m_reg); 191} 192 193void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 194 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 195 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 196 return; 197 } 198 MarkSafepointPC(last_lir_insn_); 199 } 200} 201 202void Mir2Lir::MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after) { 203 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 204 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 205 return; 206 } 207 MarkSafepointPCAfter(after); 208 } 209} 210 211void Mir2Lir::MarkPossibleStackOverflowException() { 212 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitStackOverflowChecks()) { 213 MarkSafepointPC(last_lir_insn_); 214 } 215} 216 217void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { 218 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 219 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 220 return; 221 } 222 // Force an implicit null check by performing a memory operation (load) from the given 223 // register with offset 0. This will cause a signal if the register contains 0 (null). 224 RegStorage tmp = AllocTemp(); 225 // TODO: for Mips, would be best to use rZERO as the bogus register target. 226 LIR* load = Load32Disp(reg, 0, tmp); 227 FreeTemp(tmp); 228 MarkSafepointPC(load); 229 } 230} 231 232void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 233 RegLocation rl_src2, LIR* taken, 234 LIR* fall_through) { 235 DCHECK(!rl_src1.fp); 236 DCHECK(!rl_src2.fp); 237 ConditionCode cond; 238 switch (opcode) { 239 case Instruction::IF_EQ: 240 cond = kCondEq; 241 break; 242 case Instruction::IF_NE: 243 cond = kCondNe; 244 break; 245 case Instruction::IF_LT: 246 cond = kCondLt; 247 break; 248 case Instruction::IF_GE: 249 cond = kCondGe; 250 break; 251 case Instruction::IF_GT: 252 cond = kCondGt; 253 break; 254 case Instruction::IF_LE: 255 cond = kCondLe; 256 break; 257 default: 258 cond = static_cast<ConditionCode>(0); 259 LOG(FATAL) << "Unexpected opcode " << opcode; 260 } 261 262 // Normalize such that if either operand is constant, src2 will be constant 263 if (rl_src1.is_const) { 264 RegLocation rl_temp = rl_src1; 265 rl_src1 = rl_src2; 266 rl_src2 = rl_temp; 267 cond = FlipComparisonOrder(cond); 268 } 269 270 rl_src1 = LoadValue(rl_src1); 271 // Is this really an immediate comparison? 272 if (rl_src2.is_const) { 273 // If it's already live in a register or not easily materialized, just keep going 274 RegLocation rl_temp = UpdateLoc(rl_src2); 275 if ((rl_temp.location == kLocDalvikFrame) && 276 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 277 // OK - convert this to a compare immediate and branch 278 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); 279 return; 280 } 281 } 282 rl_src2 = LoadValue(rl_src2); 283 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken); 284} 285 286void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 287 LIR* fall_through) { 288 ConditionCode cond; 289 DCHECK(!rl_src.fp); 290 rl_src = LoadValue(rl_src); 291 switch (opcode) { 292 case Instruction::IF_EQZ: 293 cond = kCondEq; 294 break; 295 case Instruction::IF_NEZ: 296 cond = kCondNe; 297 break; 298 case Instruction::IF_LTZ: 299 cond = kCondLt; 300 break; 301 case Instruction::IF_GEZ: 302 cond = kCondGe; 303 break; 304 case Instruction::IF_GTZ: 305 cond = kCondGt; 306 break; 307 case Instruction::IF_LEZ: 308 cond = kCondLe; 309 break; 310 default: 311 cond = static_cast<ConditionCode>(0); 312 LOG(FATAL) << "Unexpected opcode " << opcode; 313 } 314 OpCmpImmBranch(cond, rl_src.reg, 0, taken); 315} 316 317void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 318 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 319 if (rl_src.location == kLocPhysReg) { 320 OpRegCopy(rl_result.reg, rl_src.reg); 321 } else { 322 LoadValueDirect(rl_src, rl_result.reg.GetLow()); 323 } 324 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_result.reg.GetLow(), 31); 325 StoreValueWide(rl_dest, rl_result); 326} 327 328void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 329 RegLocation rl_src) { 330 rl_src = LoadValue(rl_src, kCoreReg); 331 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 332 OpKind op = kOpInvalid; 333 switch (opcode) { 334 case Instruction::INT_TO_BYTE: 335 op = kOp2Byte; 336 break; 337 case Instruction::INT_TO_SHORT: 338 op = kOp2Short; 339 break; 340 case Instruction::INT_TO_CHAR: 341 op = kOp2Char; 342 break; 343 default: 344 LOG(ERROR) << "Bad int conversion type"; 345 } 346 OpRegReg(op, rl_result.reg, rl_src.reg); 347 StoreValue(rl_dest, rl_result); 348} 349 350template <size_t pointer_size> 351static void GenNewArrayImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, 352 uint32_t type_idx, RegLocation rl_dest, 353 RegLocation rl_src) { 354 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 355 ThreadOffset<pointer_size> func_offset(-1); 356 const DexFile* dex_file = cu->dex_file; 357 CompilerDriver* driver = cu->compiler_driver; 358 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *dex_file, 359 type_idx)) { 360 bool is_type_initialized; // Ignored as an array does not have an initializer. 361 bool use_direct_type_ptr; 362 uintptr_t direct_type_ptr; 363 bool is_finalizable; 364 if (kEmbedClassInCode && 365 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 366 &direct_type_ptr, &is_finalizable)) { 367 // The fast path. 368 if (!use_direct_type_ptr) { 369 mir_to_lir->LoadClassType(type_idx, kArg0); 370 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 371 mir_to_lir->CallRuntimeHelperRegMethodRegLocation(func_offset, 372 mir_to_lir->TargetReg(kArg0, kNotWide), 373 rl_src, true); 374 } else { 375 // Use the direct pointer. 376 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 377 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, 378 true); 379 } 380 } else { 381 // The slow path. 382 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArray); 383 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 384 } 385 DCHECK_NE(func_offset.Int32Value(), -1); 386 } else { 387 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayWithAccessCheck); 388 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 389 } 390 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 391 mir_to_lir->StoreValue(rl_dest, rl_result); 392} 393 394/* 395 * Let helper function take care of everything. Will call 396 * Array::AllocFromCode(type_idx, method, count); 397 * Note: AllocFromCode will handle checks for errNegativeArraySize. 398 */ 399void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 400 RegLocation rl_src) { 401 if (cu_->target64) { 402 GenNewArrayImpl<8>(this, cu_, type_idx, rl_dest, rl_src); 403 } else { 404 GenNewArrayImpl<4>(this, cu_, type_idx, rl_dest, rl_src); 405 } 406} 407 408template <size_t pointer_size> 409static void GenFilledNewArrayCall(Mir2Lir* mir_to_lir, CompilationUnit* cu, int elems, int type_idx) { 410 ThreadOffset<pointer_size> func_offset(-1); 411 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *cu->dex_file, 412 type_idx)) { 413 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArray); 414 } else { 415 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArrayWithAccessCheck); 416 } 417 mir_to_lir->CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 418} 419 420/* 421 * Similar to GenNewArray, but with post-allocation initialization. 422 * Verifier guarantees we're dealing with an array class. Current 423 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 424 * Current code also throws internal unimp if not 'L', '[' or 'I'. 425 */ 426void Mir2Lir::GenFilledNewArray(CallInfo* info) { 427 int elems = info->num_arg_words; 428 int type_idx = info->index; 429 FlushAllRegs(); /* Everything to home location */ 430 if (cu_->target64) { 431 GenFilledNewArrayCall<8>(this, cu_, elems, type_idx); 432 } else { 433 GenFilledNewArrayCall<4>(this, cu_, elems, type_idx); 434 } 435 FreeTemp(TargetReg(kArg2, kNotWide)); 436 FreeTemp(TargetReg(kArg1, kNotWide)); 437 /* 438 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 439 * return region. Because AllocFromCode placed the new array 440 * in kRet0, we'll just lock it into place. When debugger support is 441 * added, it may be necessary to additionally copy all return 442 * values to a home location in thread-local storage 443 */ 444 RegStorage ref_reg = TargetReg(kRet0, kRef); 445 LockTemp(ref_reg); 446 447 // TODO: use the correct component size, currently all supported types 448 // share array alignment with ints (see comment at head of function) 449 size_t component_size = sizeof(int32_t); 450 451 // Having a range of 0 is legal 452 if (info->is_range && (elems > 0)) { 453 /* 454 * Bit of ugliness here. We're going generate a mem copy loop 455 * on the register range, but it is possible that some regs 456 * in the range have been promoted. This is unlikely, but 457 * before generating the copy, we'll just force a flush 458 * of any regs in the source range that have been promoted to 459 * home location. 460 */ 461 for (int i = 0; i < elems; i++) { 462 RegLocation loc = UpdateLoc(info->args[i]); 463 if (loc.location == kLocPhysReg) { 464 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 465 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 466 } 467 } 468 /* 469 * TUNING note: generated code here could be much improved, but 470 * this is an uncommon operation and isn't especially performance 471 * critical. 472 */ 473 // This is addressing the stack, which may be out of the 4G area. 474 RegStorage r_src = AllocTempRef(); 475 RegStorage r_dst = AllocTempRef(); 476 RegStorage r_idx = AllocTempRef(); // Not really a reference, but match src/dst. 477 RegStorage r_val; 478 switch (cu_->instruction_set) { 479 case kThumb2: 480 case kArm64: 481 r_val = TargetReg(kLr, kNotWide); 482 break; 483 case kX86: 484 case kX86_64: 485 FreeTemp(ref_reg); 486 r_val = AllocTemp(); 487 break; 488 case kMips: 489 r_val = AllocTemp(); 490 break; 491 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 492 } 493 // Set up source pointer 494 RegLocation rl_first = info->args[0]; 495 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); 496 // Set up the target pointer 497 OpRegRegImm(kOpAdd, r_dst, ref_reg, 498 mirror::Array::DataOffset(component_size).Int32Value()); 499 // Set up the loop counter (known to be > 0) 500 LoadConstant(r_idx, elems - 1); 501 // Generate the copy loop. Going backwards for convenience 502 LIR* target = NewLIR0(kPseudoTargetLabel); 503 // Copy next element 504 { 505 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 506 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32); 507 // NOTE: No dalvik register annotation, local optimizations will be stopped 508 // by the loop boundaries. 509 } 510 StoreBaseIndexed(r_dst, r_idx, r_val, 2, k32); 511 FreeTemp(r_val); 512 OpDecAndBranch(kCondGe, r_idx, target); 513 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 514 // Restore the target pointer 515 OpRegRegImm(kOpAdd, ref_reg, r_dst, 516 -mirror::Array::DataOffset(component_size).Int32Value()); 517 } 518 } else if (!info->is_range) { 519 // TUNING: interleave 520 for (int i = 0; i < elems; i++) { 521 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 522 Store32Disp(ref_reg, 523 mirror::Array::DataOffset(component_size).Int32Value() + i * 4, rl_arg.reg); 524 // If the LoadValue caused a temp to be allocated, free it 525 if (IsTemp(rl_arg.reg)) { 526 FreeTemp(rl_arg.reg); 527 } 528 } 529 } 530 if (info->result.location != kLocInvalid) { 531 StoreValue(info->result, GetReturn(kRefReg)); 532 } 533} 534 535// 536// Slow path to ensure a class is initialized for sget/sput. 537// 538class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 539 public: 540 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, int storage_index, 541 RegStorage r_base) : 542 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), 543 storage_index_(storage_index), r_base_(r_base) { 544 } 545 546 void Compile() { 547 LIR* unresolved_target = GenerateTargetLabel(); 548 uninit_->target = unresolved_target; 549 if (cu_->target64) { 550 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeStaticStorage), 551 storage_index_, true); 552 } else { 553 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeStaticStorage), 554 storage_index_, true); 555 } 556 // Copy helper's result into r_base, a no-op on all but MIPS. 557 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0, kRef)); 558 559 m2l_->OpUnconditionalBranch(cont_); 560 } 561 562 private: 563 LIR* const uninit_; 564 const int storage_index_; 565 const RegStorage r_base_; 566}; 567 568template <size_t pointer_size> 569static void GenSputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 570 const MirSFieldLoweringInfo* field_info, RegLocation rl_src) { 571 ThreadOffset<pointer_size> setter_offset = 572 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Static) 573 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjStatic) 574 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Static)); 575 mir_to_lir->CallRuntimeHelperImmRegLocation(setter_offset, field_info->FieldIndex(), rl_src, 576 true); 577} 578 579void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 580 bool is_object) { 581 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 582 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 583 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 584 if (!SLOW_FIELD_PATH && field_info.FastPut() && 585 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 586 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 587 RegStorage r_base; 588 if (field_info.IsReferrersClass()) { 589 // Fast path, static storage base is this method's class 590 RegLocation rl_method = LoadCurrMethod(); 591 r_base = AllocTempRef(); 592 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 593 kNotVolatile); 594 if (IsTemp(rl_method.reg)) { 595 FreeTemp(rl_method.reg); 596 } 597 } else { 598 // Medium path, static storage base in a different class which requires checks that the other 599 // class is initialized. 600 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 601 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 602 // May do runtime call so everything to home locations. 603 FlushAllRegs(); 604 // Using fixed register to sync with possible call to runtime support. 605 RegStorage r_method = TargetReg(kArg1, kRef); 606 LockTemp(r_method); 607 LoadCurrMethodDirect(r_method); 608 r_base = TargetReg(kArg0, kRef); 609 LockTemp(r_base); 610 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 611 kNotVolatile); 612 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 613 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 614 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 615 if (!field_info.IsInitialized() && 616 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 617 // Check if r_base is NULL or a not yet initialized class. 618 619 // The slow path is invoked if the r_base is NULL or the class pointed 620 // to by it is not initialized. 621 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 622 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 623 LockTemp(r_tmp); 624 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 625 mirror::Class::StatusOffset().Int32Value(), 626 mirror::Class::kStatusInitialized, NULL); 627 LIR* cont = NewLIR0(kPseudoTargetLabel); 628 629 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 630 field_info.StorageIndex(), r_base)); 631 632 FreeTemp(r_tmp); 633 // Ensure load of status and store of value don't re-order. 634 // TODO: Presumably the actual value store is control-dependent on the status load, 635 // and will thus not be reordered in any case, since stores are never speculated. 636 // Does later code "know" that the class is now initialized? If so, we still 637 // need the barrier to guard later static loads. 638 GenMemBarrier(kLoadAny); 639 } 640 FreeTemp(r_method); 641 } 642 // rBase now holds static storage base 643 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 644 if (is_long_or_double) { 645 rl_src = LoadValueWide(rl_src, reg_class); 646 } else { 647 rl_src = LoadValue(rl_src, reg_class); 648 } 649 if (is_object) { 650 StoreRefDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, 651 field_info.IsVolatile() ? kVolatile : kNotVolatile); 652 } else { 653 StoreBaseDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, store_size, 654 field_info.IsVolatile() ? kVolatile : kNotVolatile); 655 } 656 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 657 MarkGCCard(rl_src.reg, r_base); 658 } 659 FreeTemp(r_base); 660 } else { 661 FlushAllRegs(); // Everything to home locations 662 if (cu_->target64) { 663 GenSputCall<8>(this, is_long_or_double, is_object, &field_info, rl_src); 664 } else { 665 GenSputCall<4>(this, is_long_or_double, is_object, &field_info, rl_src); 666 } 667 } 668} 669 670template <size_t pointer_size> 671static void GenSgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 672 const MirSFieldLoweringInfo* field_info) { 673 ThreadOffset<pointer_size> getter_offset = 674 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Static) 675 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjStatic) 676 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Static)); 677 mir_to_lir->CallRuntimeHelperImm(getter_offset, field_info->FieldIndex(), true); 678} 679 680void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 681 bool is_long_or_double, bool is_object) { 682 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 683 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 684 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 685 if (!SLOW_FIELD_PATH && field_info.FastGet() && 686 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 687 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 688 RegStorage r_base; 689 if (field_info.IsReferrersClass()) { 690 // Fast path, static storage base is this method's class 691 RegLocation rl_method = LoadCurrMethod(); 692 r_base = AllocTempRef(); 693 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 694 kNotVolatile); 695 } else { 696 // Medium path, static storage base in a different class which requires checks that the other 697 // class is initialized 698 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 699 // May do runtime call so everything to home locations. 700 FlushAllRegs(); 701 // Using fixed register to sync with possible call to runtime support. 702 RegStorage r_method = TargetReg(kArg1, kRef); 703 LockTemp(r_method); 704 LoadCurrMethodDirect(r_method); 705 r_base = TargetReg(kArg0, kRef); 706 LockTemp(r_base); 707 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 708 kNotVolatile); 709 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 710 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 711 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 712 if (!field_info.IsInitialized() && 713 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 714 // Check if r_base is NULL or a not yet initialized class. 715 716 // The slow path is invoked if the r_base is NULL or the class pointed 717 // to by it is not initialized. 718 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 719 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 720 LockTemp(r_tmp); 721 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 722 mirror::Class::StatusOffset().Int32Value(), 723 mirror::Class::kStatusInitialized, NULL); 724 LIR* cont = NewLIR0(kPseudoTargetLabel); 725 726 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 727 field_info.StorageIndex(), r_base)); 728 729 FreeTemp(r_tmp); 730 // Ensure load of status and load of value don't re-order. 731 GenMemBarrier(kLoadAny); 732 } 733 FreeTemp(r_method); 734 } 735 // r_base now holds static storage base 736 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 737 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 738 739 int field_offset = field_info.FieldOffset().Int32Value(); 740 if (is_object) { 741 LoadRefDisp(r_base, field_offset, rl_result.reg, field_info.IsVolatile() ? kVolatile : 742 kNotVolatile); 743 } else { 744 LoadBaseDisp(r_base, field_offset, rl_result.reg, load_size, field_info.IsVolatile() ? 745 kVolatile : kNotVolatile); 746 } 747 FreeTemp(r_base); 748 749 if (is_long_or_double) { 750 StoreValueWide(rl_dest, rl_result); 751 } else { 752 StoreValue(rl_dest, rl_result); 753 } 754 } else { 755 FlushAllRegs(); // Everything to home locations 756 if (cu_->target64) { 757 GenSgetCall<8>(this, is_long_or_double, is_object, &field_info); 758 } else { 759 GenSgetCall<4>(this, is_long_or_double, is_object, &field_info); 760 } 761 // FIXME: pGetXXStatic always return an int or int64 regardless of rl_dest.fp. 762 if (is_long_or_double) { 763 RegLocation rl_result = GetReturnWide(kCoreReg); 764 StoreValueWide(rl_dest, rl_result); 765 } else { 766 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 767 StoreValue(rl_dest, rl_result); 768 } 769 } 770} 771 772// Generate code for all slow paths. 773void Mir2Lir::HandleSlowPaths() { 774 // We should check slow_paths_.Size() every time, because a new slow path 775 // may be created during slowpath->Compile(). 776 for (size_t i = 0; i < slow_paths_.Size(); ++i) { 777 LIRSlowPath* slowpath = slow_paths_.Get(i); 778 slowpath->Compile(); 779 } 780 slow_paths_.Reset(); 781} 782 783template <size_t pointer_size> 784static void GenIgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 785 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj) { 786 ThreadOffset<pointer_size> getter_offset = 787 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Instance) 788 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjInstance) 789 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Instance)); 790 mir_to_lir->CallRuntimeHelperImmRegLocation(getter_offset, field_info->FieldIndex(), rl_obj, 791 true); 792} 793 794void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 795 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 796 bool is_object) { 797 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 798 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 799 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 800 if (!SLOW_FIELD_PATH && field_info.FastGet() && 801 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 802 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 803 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 804 rl_obj = LoadValue(rl_obj, kRefReg); 805 GenNullCheck(rl_obj.reg, opt_flags); 806 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 807 int field_offset = field_info.FieldOffset().Int32Value(); 808 LIR* load_lir; 809 if (is_object) { 810 load_lir = LoadRefDisp(rl_obj.reg, field_offset, rl_result.reg, field_info.IsVolatile() ? 811 kVolatile : kNotVolatile); 812 } else { 813 load_lir = LoadBaseDisp(rl_obj.reg, field_offset, rl_result.reg, load_size, 814 field_info.IsVolatile() ? kVolatile : kNotVolatile); 815 } 816 MarkPossibleNullPointerExceptionAfter(opt_flags, load_lir); 817 if (is_long_or_double) { 818 StoreValueWide(rl_dest, rl_result); 819 } else { 820 StoreValue(rl_dest, rl_result); 821 } 822 } else { 823 if (cu_->target64) { 824 GenIgetCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj); 825 } else { 826 GenIgetCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj); 827 } 828 // FIXME: pGetXXInstance always return an int or int64 regardless of rl_dest.fp. 829 if (is_long_or_double) { 830 RegLocation rl_result = GetReturnWide(kCoreReg); 831 StoreValueWide(rl_dest, rl_result); 832 } else { 833 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 834 StoreValue(rl_dest, rl_result); 835 } 836 } 837} 838 839template <size_t pointer_size> 840static void GenIputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 841 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj, 842 RegLocation rl_src) { 843 ThreadOffset<pointer_size> setter_offset = 844 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Instance) 845 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjInstance) 846 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Instance)); 847 mir_to_lir->CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info->FieldIndex(), 848 rl_obj, rl_src, true); 849} 850 851void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 852 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 853 bool is_object) { 854 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 855 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 856 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 857 if (!SLOW_FIELD_PATH && field_info.FastPut() && 858 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 859 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 860 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 861 rl_obj = LoadValue(rl_obj, kRefReg); 862 if (is_long_or_double) { 863 rl_src = LoadValueWide(rl_src, reg_class); 864 } else { 865 rl_src = LoadValue(rl_src, reg_class); 866 } 867 GenNullCheck(rl_obj.reg, opt_flags); 868 int field_offset = field_info.FieldOffset().Int32Value(); 869 LIR* store; 870 if (is_object) { 871 store = StoreRefDisp(rl_obj.reg, field_offset, rl_src.reg, field_info.IsVolatile() ? 872 kVolatile : kNotVolatile); 873 } else { 874 store = StoreBaseDisp(rl_obj.reg, field_offset, rl_src.reg, store_size, 875 field_info.IsVolatile() ? kVolatile : kNotVolatile); 876 } 877 MarkPossibleNullPointerExceptionAfter(opt_flags, store); 878 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 879 MarkGCCard(rl_src.reg, rl_obj.reg); 880 } 881 } else { 882 if (cu_->target64) { 883 GenIputCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 884 } else { 885 GenIputCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 886 } 887 } 888} 889 890template <size_t pointer_size> 891static void GenArrayObjPutCall(Mir2Lir* mir_to_lir, bool needs_range_check, bool needs_null_check, 892 RegLocation rl_array, RegLocation rl_index, RegLocation rl_src) { 893 ThreadOffset<pointer_size> helper = needs_range_check 894 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithNullAndBoundCheck) 895 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithBoundCheck)) 896 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObject); 897 mir_to_lir->CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, 898 true); 899} 900 901void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 902 RegLocation rl_src) { 903 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 904 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 905 (opt_flags & MIR_IGNORE_NULL_CHECK)); 906 if (cu_->target64) { 907 GenArrayObjPutCall<8>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 908 } else { 909 GenArrayObjPutCall<4>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 910 } 911} 912 913void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 914 RegLocation rl_method = LoadCurrMethod(); 915 CheckRegLocation(rl_method); 916 RegStorage res_reg = AllocTempRef(); 917 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 918 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 919 *cu_->dex_file, 920 type_idx)) { 921 // Call out to helper which resolves type and verifies access. 922 // Resolved type returned in kRet0. 923 if (cu_->target64) { 924 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 925 type_idx, rl_method.reg, true); 926 } else { 927 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 928 type_idx, rl_method.reg, true); 929 } 930 RegLocation rl_result = GetReturn(kRefReg); 931 StoreValue(rl_dest, rl_result); 932 } else { 933 // We're don't need access checks, load type from dex cache 934 int32_t dex_cache_offset = 935 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 936 LoadRefDisp(rl_method.reg, dex_cache_offset, res_reg, kNotVolatile); 937 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 938 LoadRefDisp(res_reg, offset_of_type, rl_result.reg, kNotVolatile); 939 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 940 type_idx) || SLOW_TYPE_PATH) { 941 // Slow path, at runtime test if type is null and if so initialize 942 FlushAllRegs(); 943 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg, 0, NULL); 944 LIR* cont = NewLIR0(kPseudoTargetLabel); 945 946 // Object to generate the slow path for class resolution. 947 class SlowPath : public LIRSlowPath { 948 public: 949 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 950 const RegLocation& rl_method, const RegLocation& rl_result) : 951 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 952 rl_method_(rl_method), rl_result_(rl_result) { 953 } 954 955 void Compile() { 956 GenerateTargetLabel(); 957 958 if (cu_->target64) { 959 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 960 rl_method_.reg, true); 961 } else { 962 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 963 rl_method_.reg, true); 964 } 965 m2l_->OpRegCopy(rl_result_.reg, m2l_->TargetReg(kRet0, kRef)); 966 967 m2l_->OpUnconditionalBranch(cont_); 968 } 969 970 private: 971 const int type_idx_; 972 const RegLocation rl_method_; 973 const RegLocation rl_result_; 974 }; 975 976 // Add to list for future. 977 AddSlowPath(new (arena_) SlowPath(this, branch, cont, type_idx, rl_method, rl_result)); 978 979 StoreValue(rl_dest, rl_result); 980 } else { 981 // Fast path, we're done - just store result 982 StoreValue(rl_dest, rl_result); 983 } 984 } 985} 986 987void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 988 /* NOTE: Most strings should be available at compile time */ 989 int32_t offset_of_string = mirror::ObjectArray<mirror::String>::OffsetOfElement(string_idx). 990 Int32Value(); 991 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 992 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 993 // slow path, resolve string if not in dex cache 994 FlushAllRegs(); 995 LockCallTemps(); // Using explicit registers 996 997 // If the Method* is already in a register, we can save a copy. 998 RegLocation rl_method = mir_graph_->GetMethodLoc(); 999 RegStorage r_method; 1000 if (rl_method.location == kLocPhysReg) { 1001 // A temp would conflict with register use below. 1002 DCHECK(!IsTemp(rl_method.reg)); 1003 r_method = rl_method.reg; 1004 } else { 1005 r_method = TargetReg(kArg2, kRef); 1006 LoadCurrMethodDirect(r_method); 1007 } 1008 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 1009 TargetReg(kArg0, kRef), kNotVolatile); 1010 1011 // Might call out to helper, which will return resolved string in kRet0 1012 LoadRefDisp(TargetReg(kArg0, kRef), offset_of_string, TargetReg(kRet0, kRef), kNotVolatile); 1013 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0, kRef), 0, NULL); 1014 LIR* cont = NewLIR0(kPseudoTargetLabel); 1015 1016 { 1017 // Object to generate the slow path for string resolution. 1018 class SlowPath : public LIRSlowPath { 1019 public: 1020 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, RegStorage r_method, int32_t string_idx) : 1021 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), 1022 r_method_(r_method), string_idx_(string_idx) { 1023 } 1024 1025 void Compile() { 1026 GenerateTargetLabel(); 1027 if (cu_->target64) { 1028 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pResolveString), 1029 r_method_, string_idx_, true); 1030 } else { 1031 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pResolveString), 1032 r_method_, string_idx_, true); 1033 } 1034 m2l_->OpUnconditionalBranch(cont_); 1035 } 1036 1037 private: 1038 const RegStorage r_method_; 1039 const int32_t string_idx_; 1040 }; 1041 1042 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method, string_idx)); 1043 } 1044 1045 GenBarrier(); 1046 StoreValue(rl_dest, GetReturn(kRefReg)); 1047 } else { 1048 RegLocation rl_method = LoadCurrMethod(); 1049 RegStorage res_reg = AllocTempRef(); 1050 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1051 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg, 1052 kNotVolatile); 1053 LoadRefDisp(res_reg, offset_of_string, rl_result.reg, kNotVolatile); 1054 StoreValue(rl_dest, rl_result); 1055 } 1056} 1057 1058template <size_t pointer_size> 1059static void GenNewInstanceImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, uint32_t type_idx, 1060 RegLocation rl_dest) { 1061 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 1062 // alloc will always check for resolution, do we also need to verify 1063 // access because the verifier was unable to? 1064 ThreadOffset<pointer_size> func_offset(-1); 1065 const DexFile* dex_file = cu->dex_file; 1066 CompilerDriver* driver = cu->compiler_driver; 1067 if (driver->CanAccessInstantiableTypeWithoutChecks( 1068 cu->method_idx, *dex_file, type_idx)) { 1069 bool is_type_initialized; 1070 bool use_direct_type_ptr; 1071 uintptr_t direct_type_ptr; 1072 bool is_finalizable; 1073 if (kEmbedClassInCode && 1074 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 1075 &direct_type_ptr, &is_finalizable) && 1076 !is_finalizable) { 1077 // The fast path. 1078 if (!use_direct_type_ptr) { 1079 mir_to_lir->LoadClassType(type_idx, kArg0); 1080 if (!is_type_initialized) { 1081 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1082 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1083 true); 1084 } else { 1085 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1086 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1087 true); 1088 } 1089 } else { 1090 // Use the direct pointer. 1091 if (!is_type_initialized) { 1092 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1093 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1094 } else { 1095 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1096 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1097 } 1098 } 1099 } else { 1100 // The slow path. 1101 DCHECK_EQ(func_offset.Int32Value(), -1); 1102 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObject); 1103 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1104 } 1105 DCHECK_NE(func_offset.Int32Value(), -1); 1106 } else { 1107 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectWithAccessCheck); 1108 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1109 } 1110 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 1111 mir_to_lir->StoreValue(rl_dest, rl_result); 1112} 1113 1114/* 1115 * Let helper function take care of everything. Will 1116 * call Class::NewInstanceFromCode(type_idx, method); 1117 */ 1118void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 1119 if (cu_->target64) { 1120 GenNewInstanceImpl<8>(this, cu_, type_idx, rl_dest); 1121 } else { 1122 GenNewInstanceImpl<4>(this, cu_, type_idx, rl_dest); 1123 } 1124} 1125 1126void Mir2Lir::GenThrow(RegLocation rl_src) { 1127 FlushAllRegs(); 1128 if (cu_->target64) { 1129 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), rl_src, true); 1130 } else { 1131 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException), rl_src, true); 1132 } 1133} 1134 1135// For final classes there are no sub-classes to check and so we can answer the instance-of 1136// question with simple comparisons. 1137void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1138 RegLocation rl_src) { 1139 // X86 has its own implementation. 1140 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1141 1142 RegLocation object = LoadValue(rl_src, kRefReg); 1143 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1144 RegStorage result_reg = rl_result.reg; 1145 if (IsSameReg(result_reg, object.reg)) { 1146 result_reg = AllocTypedTemp(false, kCoreReg); 1147 DCHECK(!IsSameReg(result_reg, object.reg)); 1148 } 1149 LoadConstant(result_reg, 0); // assume false 1150 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 1151 1152 RegStorage check_class = AllocTypedTemp(false, kRefReg); 1153 RegStorage object_class = AllocTypedTemp(false, kRefReg); 1154 1155 LoadCurrMethodDirect(check_class); 1156 if (use_declaring_class) { 1157 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), check_class, 1158 kNotVolatile); 1159 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1160 kNotVolatile); 1161 } else { 1162 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1163 check_class, kNotVolatile); 1164 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1165 kNotVolatile); 1166 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1167 LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); 1168 } 1169 1170 // FIXME: what should we be comparing here? compressed or decompressed references? 1171 if (cu_->instruction_set == kThumb2) { 1172 OpRegReg(kOpCmp, check_class, object_class); // Same? 1173 LIR* it = OpIT(kCondEq, ""); // if-convert the test 1174 LoadConstant(result_reg, 1); // .eq case - load true 1175 OpEndIT(it); 1176 } else { 1177 GenSelectConst32(check_class, object_class, kCondEq, 1, 0, result_reg, kCoreReg); 1178 } 1179 LIR* target = NewLIR0(kPseudoTargetLabel); 1180 null_branchover->target = target; 1181 FreeTemp(object_class); 1182 FreeTemp(check_class); 1183 if (IsTemp(result_reg)) { 1184 OpRegCopy(rl_result.reg, result_reg); 1185 FreeTemp(result_reg); 1186 } 1187 StoreValue(rl_dest, rl_result); 1188} 1189 1190void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1191 bool type_known_abstract, bool use_declaring_class, 1192 bool can_assume_type_is_in_dex_cache, 1193 uint32_t type_idx, RegLocation rl_dest, 1194 RegLocation rl_src) { 1195 // X86 has its own implementation. 1196 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1197 1198 FlushAllRegs(); 1199 // May generate a call - use explicit registers 1200 LockCallTemps(); 1201 RegStorage method_reg = TargetReg(kArg1, kRef); 1202 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1203 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1204 if (needs_access_check) { 1205 // Check we have access to type_idx and if not throw IllegalAccessError, 1206 // returns Class* in kArg0 1207 if (cu_->target64) { 1208 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1209 type_idx, true); 1210 } else { 1211 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1212 type_idx, true); 1213 } 1214 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1215 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1216 } else if (use_declaring_class) { 1217 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1218 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1219 class_reg, kNotVolatile); 1220 } else { 1221 if (can_assume_type_is_in_dex_cache) { 1222 // Conditionally, as in the other case we will also load it. 1223 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1224 } 1225 1226 // Load dex cache entry into class_reg (kArg2) 1227 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1228 class_reg, kNotVolatile); 1229 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1230 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1231 if (!can_assume_type_is_in_dex_cache) { 1232 LIR* slow_path_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1233 LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); 1234 1235 // Should load value here. 1236 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1237 1238 class InitTypeSlowPath : public Mir2Lir::LIRSlowPath { 1239 public: 1240 InitTypeSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont, uint32_t type_idx, 1241 RegLocation rl_src) 1242 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont), type_idx_(type_idx), 1243 rl_src_(rl_src) { 1244 } 1245 1246 void Compile() OVERRIDE { 1247 GenerateTargetLabel(); 1248 1249 if (cu_->target64) { 1250 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1251 true); 1252 } else { 1253 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1254 true); 1255 } 1256 m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kRef), 1257 m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1258 1259 m2l_->OpUnconditionalBranch(cont_); 1260 } 1261 1262 private: 1263 uint32_t type_idx_; 1264 RegLocation rl_src_; 1265 }; 1266 1267 AddSlowPath(new (arena_) InitTypeSlowPath(this, slow_path_branch, slow_path_target, 1268 type_idx, rl_src)); 1269 } 1270 } 1271 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1272 RegLocation rl_result = GetReturn(kCoreReg); 1273 if (cu_->instruction_set == kMips) { 1274 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1275 LoadConstant(rl_result.reg, 0); 1276 } 1277 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, NULL); 1278 1279 /* load object->klass_ */ 1280 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1281 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1282 TargetReg(kArg1, kRef), kNotVolatile); 1283 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1284 LIR* branchover = NULL; 1285 if (type_known_final) { 1286 // rl_result == ref == null == 0. 1287 GenSelectConst32(TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), kCondEq, 1, 0, rl_result.reg, 1288 kCoreReg); 1289 } else { 1290 if (cu_->instruction_set == kThumb2) { 1291 RegStorage r_tgt = cu_->target64 ? 1292 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1293 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1294 LIR* it = nullptr; 1295 if (!type_known_abstract) { 1296 /* Uses conditional nullification */ 1297 OpRegReg(kOpCmp, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef)); // Same? 1298 it = OpIT(kCondEq, "EE"); // if-convert the test 1299 LoadConstant(TargetReg(kArg0, kNotWide), 1); // .eq case - load true 1300 } 1301 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1302 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1303 if (it != nullptr) { 1304 OpEndIT(it); 1305 } 1306 FreeTemp(r_tgt); 1307 } else { 1308 if (!type_known_abstract) { 1309 /* Uses branchovers */ 1310 LoadConstant(rl_result.reg, 1); // assume true 1311 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1312 } 1313 1314 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1315 if (cu_->target64) { 1316 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial), false); 1317 } else { 1318 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial), false); 1319 } 1320 } 1321 } 1322 // TODO: only clobber when type isn't final? 1323 ClobberCallerSave(); 1324 /* branch targets here */ 1325 LIR* target = NewLIR0(kPseudoTargetLabel); 1326 StoreValue(rl_dest, rl_result); 1327 branch1->target = target; 1328 if (branchover != NULL) { 1329 branchover->target = target; 1330 } 1331} 1332 1333void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1334 bool type_known_final, type_known_abstract, use_declaring_class; 1335 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1336 *cu_->dex_file, 1337 type_idx, 1338 &type_known_final, 1339 &type_known_abstract, 1340 &use_declaring_class); 1341 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1342 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1343 1344 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1345 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1346 } else { 1347 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1348 use_declaring_class, can_assume_type_is_in_dex_cache, 1349 type_idx, rl_dest, rl_src); 1350 } 1351} 1352 1353void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1354 bool type_known_final, type_known_abstract, use_declaring_class; 1355 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1356 *cu_->dex_file, 1357 type_idx, 1358 &type_known_final, 1359 &type_known_abstract, 1360 &use_declaring_class); 1361 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1362 // of the exception throw path. 1363 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1364 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1365 // Verifier type analysis proved this check cast would never cause an exception. 1366 return; 1367 } 1368 FlushAllRegs(); 1369 // May generate a call - use explicit registers 1370 LockCallTemps(); 1371 RegStorage method_reg = TargetReg(kArg1, kRef); 1372 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1373 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1374 if (needs_access_check) { 1375 // Check we have access to type_idx and if not throw IllegalAccessError, 1376 // returns Class* in kRet0 1377 // InitializeTypeAndVerifyAccess(idx, method) 1378 if (cu_->target64) { 1379 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1380 type_idx, true); 1381 } else { 1382 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1383 type_idx, true); 1384 } 1385 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1386 } else if (use_declaring_class) { 1387 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1388 class_reg, kNotVolatile); 1389 } else { 1390 // Load dex cache entry into class_reg (kArg2) 1391 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1392 class_reg, kNotVolatile); 1393 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1394 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1395 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1396 // Need to test presence of type in dex cache at runtime 1397 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1398 LIR* cont = NewLIR0(kPseudoTargetLabel); 1399 1400 // Slow path to initialize the type. Executed if the type is NULL. 1401 class SlowPath : public LIRSlowPath { 1402 public: 1403 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1404 const RegStorage class_reg) : 1405 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1406 class_reg_(class_reg) { 1407 } 1408 1409 void Compile() { 1410 GenerateTargetLabel(); 1411 1412 // Call out to helper, which will return resolved type in kArg0 1413 // InitializeTypeFromCode(idx, method) 1414 if (m2l_->cu_->target64) { 1415 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1416 m2l_->TargetReg(kArg1, kRef), true); 1417 } else { 1418 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1419 m2l_->TargetReg(kArg1, kRef), true); 1420 } 1421 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1422 m2l_->OpUnconditionalBranch(cont_); 1423 } 1424 1425 public: 1426 const int type_idx_; 1427 const RegStorage class_reg_; 1428 }; 1429 1430 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, type_idx, class_reg)); 1431 } 1432 } 1433 // At this point, class_reg (kArg2) has class 1434 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1435 1436 // Slow path for the case where the classes are not equal. In this case we need 1437 // to call a helper function to do the check. 1438 class SlowPath : public LIRSlowPath { 1439 public: 1440 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1441 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1442 } 1443 1444 void Compile() { 1445 GenerateTargetLabel(); 1446 1447 if (load_) { 1448 m2l_->LoadRefDisp(m2l_->TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1449 m2l_->TargetReg(kArg1, kRef), kNotVolatile); 1450 } 1451 if (m2l_->cu_->target64) { 1452 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pCheckCast), 1453 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1454 true); 1455 } else { 1456 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pCheckCast), 1457 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1458 true); 1459 } 1460 1461 m2l_->OpUnconditionalBranch(cont_); 1462 } 1463 1464 private: 1465 const bool load_; 1466 }; 1467 1468 if (type_known_abstract) { 1469 // Easier case, run slow path if target is non-null (slow path will load from target) 1470 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0, kRef), 0, nullptr); 1471 LIR* cont = NewLIR0(kPseudoTargetLabel); 1472 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1473 } else { 1474 // Harder, more common case. We need to generate a forward branch over the load 1475 // if the target is null. If it's non-null we perform the load and branch to the 1476 // slow path if the classes are not equal. 1477 1478 /* Null is OK - continue */ 1479 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, nullptr); 1480 /* load object->klass_ */ 1481 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1482 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1483 TargetReg(kArg1, kRef), kNotVolatile); 1484 1485 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), class_reg, nullptr); 1486 LIR* cont = NewLIR0(kPseudoTargetLabel); 1487 1488 // Add the slow path that will not perform load since this is already done. 1489 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1490 1491 // Set the null check to branch to the continuation. 1492 branch1->target = cont; 1493 } 1494} 1495 1496void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1497 RegLocation rl_src1, RegLocation rl_src2) { 1498 RegLocation rl_result; 1499 if (cu_->instruction_set == kThumb2) { 1500 /* 1501 * NOTE: This is the one place in the code in which we might have 1502 * as many as six live temporary registers. There are 5 in the normal 1503 * set for Arm. Until we have spill capabilities, temporarily add 1504 * lr to the temp set. It is safe to do this locally, but note that 1505 * lr is used explicitly elsewhere in the code generator and cannot 1506 * normally be used as a general temp register. 1507 */ 1508 MarkTemp(TargetReg(kLr, kNotWide)); // Add lr to the temp pool 1509 FreeTemp(TargetReg(kLr, kNotWide)); // and make it available 1510 } 1511 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1512 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1513 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1514 // The longs may overlap - use intermediate temp if so 1515 if ((rl_result.reg.GetLowReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg())) { 1516 RegStorage t_reg = AllocTemp(); 1517 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1518 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1519 OpRegCopy(rl_result.reg.GetLow(), t_reg); 1520 FreeTemp(t_reg); 1521 } else { 1522 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1523 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1524 } 1525 /* 1526 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1527 * following StoreValueWide might need to allocate a temp register. 1528 * To further work around the lack of a spill capability, explicitly 1529 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1530 * Remove when spill is functional. 1531 */ 1532 FreeRegLocTemps(rl_result, rl_src1); 1533 FreeRegLocTemps(rl_result, rl_src2); 1534 StoreValueWide(rl_dest, rl_result); 1535 if (cu_->instruction_set == kThumb2) { 1536 Clobber(TargetReg(kLr, kNotWide)); 1537 UnmarkTemp(TargetReg(kLr, kNotWide)); // Remove lr from the temp pool 1538 } 1539} 1540 1541 1542template <size_t pointer_size> 1543static void GenShiftOpLongCall(Mir2Lir* mir_to_lir, Instruction::Code opcode, RegLocation rl_src1, 1544 RegLocation rl_shift) { 1545 ThreadOffset<pointer_size> func_offset(-1); 1546 1547 switch (opcode) { 1548 case Instruction::SHL_LONG: 1549 case Instruction::SHL_LONG_2ADDR: 1550 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShlLong); 1551 break; 1552 case Instruction::SHR_LONG: 1553 case Instruction::SHR_LONG_2ADDR: 1554 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShrLong); 1555 break; 1556 case Instruction::USHR_LONG: 1557 case Instruction::USHR_LONG_2ADDR: 1558 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pUshrLong); 1559 break; 1560 default: 1561 LOG(FATAL) << "Unexpected case"; 1562 } 1563 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 1564 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1565} 1566 1567void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1568 RegLocation rl_src1, RegLocation rl_shift) { 1569 if (cu_->target64) { 1570 GenShiftOpLongCall<8>(this, opcode, rl_src1, rl_shift); 1571 } else { 1572 GenShiftOpLongCall<4>(this, opcode, rl_src1, rl_shift); 1573 } 1574 RegLocation rl_result = GetReturnWide(kCoreReg); 1575 StoreValueWide(rl_dest, rl_result); 1576} 1577 1578 1579void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1580 RegLocation rl_src1, RegLocation rl_src2) { 1581 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1582 OpKind op = kOpBkpt; 1583 bool is_div_rem = false; 1584 bool check_zero = false; 1585 bool unary = false; 1586 RegLocation rl_result; 1587 bool shift_op = false; 1588 switch (opcode) { 1589 case Instruction::NEG_INT: 1590 op = kOpNeg; 1591 unary = true; 1592 break; 1593 case Instruction::NOT_INT: 1594 op = kOpMvn; 1595 unary = true; 1596 break; 1597 case Instruction::ADD_INT: 1598 case Instruction::ADD_INT_2ADDR: 1599 op = kOpAdd; 1600 break; 1601 case Instruction::SUB_INT: 1602 case Instruction::SUB_INT_2ADDR: 1603 op = kOpSub; 1604 break; 1605 case Instruction::MUL_INT: 1606 case Instruction::MUL_INT_2ADDR: 1607 op = kOpMul; 1608 break; 1609 case Instruction::DIV_INT: 1610 case Instruction::DIV_INT_2ADDR: 1611 check_zero = true; 1612 op = kOpDiv; 1613 is_div_rem = true; 1614 break; 1615 /* NOTE: returns in kArg1 */ 1616 case Instruction::REM_INT: 1617 case Instruction::REM_INT_2ADDR: 1618 check_zero = true; 1619 op = kOpRem; 1620 is_div_rem = true; 1621 break; 1622 case Instruction::AND_INT: 1623 case Instruction::AND_INT_2ADDR: 1624 op = kOpAnd; 1625 break; 1626 case Instruction::OR_INT: 1627 case Instruction::OR_INT_2ADDR: 1628 op = kOpOr; 1629 break; 1630 case Instruction::XOR_INT: 1631 case Instruction::XOR_INT_2ADDR: 1632 op = kOpXor; 1633 break; 1634 case Instruction::SHL_INT: 1635 case Instruction::SHL_INT_2ADDR: 1636 shift_op = true; 1637 op = kOpLsl; 1638 break; 1639 case Instruction::SHR_INT: 1640 case Instruction::SHR_INT_2ADDR: 1641 shift_op = true; 1642 op = kOpAsr; 1643 break; 1644 case Instruction::USHR_INT: 1645 case Instruction::USHR_INT_2ADDR: 1646 shift_op = true; 1647 op = kOpLsr; 1648 break; 1649 default: 1650 LOG(FATAL) << "Invalid word arith op: " << opcode; 1651 } 1652 if (!is_div_rem) { 1653 if (unary) { 1654 rl_src1 = LoadValue(rl_src1, kCoreReg); 1655 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1656 OpRegReg(op, rl_result.reg, rl_src1.reg); 1657 } else { 1658 if ((shift_op) && (cu_->instruction_set != kArm64)) { 1659 rl_src2 = LoadValue(rl_src2, kCoreReg); 1660 RegStorage t_reg = AllocTemp(); 1661 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg, 31); 1662 rl_src1 = LoadValue(rl_src1, kCoreReg); 1663 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1664 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 1665 FreeTemp(t_reg); 1666 } else { 1667 rl_src1 = LoadValue(rl_src1, kCoreReg); 1668 rl_src2 = LoadValue(rl_src2, kCoreReg); 1669 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1670 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); 1671 } 1672 } 1673 StoreValue(rl_dest, rl_result); 1674 } else { 1675 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1676 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1677 rl_src1 = LoadValue(rl_src1, kCoreReg); 1678 rl_src2 = LoadValue(rl_src2, kCoreReg); 1679 if (check_zero) { 1680 GenDivZeroCheck(rl_src2.reg); 1681 } 1682 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1683 done = true; 1684 } else if (cu_->instruction_set == kThumb2) { 1685 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1686 // Use ARM SDIV instruction for division. For remainder we also need to 1687 // calculate using a MUL and subtract. 1688 rl_src1 = LoadValue(rl_src1, kCoreReg); 1689 rl_src2 = LoadValue(rl_src2, kCoreReg); 1690 if (check_zero) { 1691 GenDivZeroCheck(rl_src2.reg); 1692 } 1693 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1694 done = true; 1695 } 1696 } 1697 1698 // If we haven't already generated the code use the callout function. 1699 if (!done) { 1700 FlushAllRegs(); /* Send everything to home location */ 1701 LoadValueDirectFixed(rl_src2, TargetReg(kArg1, kNotWide)); 1702 RegStorage r_tgt = cu_->target64 ? 1703 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod)) : 1704 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod)); 1705 LoadValueDirectFixed(rl_src1, TargetReg(kArg0, kNotWide)); 1706 if (check_zero) { 1707 GenDivZeroCheck(TargetReg(kArg1, kNotWide)); 1708 } 1709 // NOTE: callout here is not a safepoint. 1710 if (cu_->target64) { 1711 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), false /* not a safepoint */); 1712 } else { 1713 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), false /* not a safepoint */); 1714 } 1715 if (op == kOpDiv) 1716 rl_result = GetReturn(kCoreReg); 1717 else 1718 rl_result = GetReturnAlt(); 1719 } 1720 StoreValue(rl_dest, rl_result); 1721 } 1722} 1723 1724/* 1725 * The following are the first-level codegen routines that analyze the format 1726 * of each bytecode then either dispatch special purpose codegen routines 1727 * or produce corresponding Thumb instructions directly. 1728 */ 1729 1730// Returns true if no more than two bits are set in 'x'. 1731static bool IsPopCountLE2(unsigned int x) { 1732 x &= x - 1; 1733 return (x & (x - 1)) == 0; 1734} 1735 1736// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1737// and store the result in 'rl_dest'. 1738bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1739 RegLocation rl_src, RegLocation rl_dest, int lit) { 1740 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1741 return false; 1742 } 1743 // No divide instruction for Arm, so check for more special cases 1744 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1745 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1746 } 1747 int k = LowestSetBit(lit); 1748 if (k >= 30) { 1749 // Avoid special cases. 1750 return false; 1751 } 1752 rl_src = LoadValue(rl_src, kCoreReg); 1753 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1754 if (is_div) { 1755 RegStorage t_reg = AllocTemp(); 1756 if (lit == 2) { 1757 // Division by 2 is by far the most common division by constant. 1758 OpRegRegImm(kOpLsr, t_reg, rl_src.reg, 32 - k); 1759 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1760 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1761 } else { 1762 OpRegRegImm(kOpAsr, t_reg, rl_src.reg, 31); 1763 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1764 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1765 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1766 } 1767 } else { 1768 RegStorage t_reg1 = AllocTemp(); 1769 RegStorage t_reg2 = AllocTemp(); 1770 if (lit == 2) { 1771 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg, 32 - k); 1772 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1773 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1774 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1775 } else { 1776 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg, 31); 1777 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1778 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1779 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1780 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1781 } 1782 } 1783 StoreValue(rl_dest, rl_result); 1784 return true; 1785} 1786 1787// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1788// and store the result in 'rl_dest'. 1789bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1790 if (lit < 0) { 1791 return false; 1792 } 1793 if (lit == 0) { 1794 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1795 LoadConstant(rl_result.reg, 0); 1796 StoreValue(rl_dest, rl_result); 1797 return true; 1798 } 1799 if (lit == 1) { 1800 rl_src = LoadValue(rl_src, kCoreReg); 1801 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1802 OpRegCopy(rl_result.reg, rl_src.reg); 1803 StoreValue(rl_dest, rl_result); 1804 return true; 1805 } 1806 // There is RegRegRegShift on Arm, so check for more special cases 1807 if (cu_->instruction_set == kThumb2) { 1808 return EasyMultiply(rl_src, rl_dest, lit); 1809 } 1810 // Can we simplify this multiplication? 1811 bool power_of_two = false; 1812 bool pop_count_le2 = false; 1813 bool power_of_two_minus_one = false; 1814 if (IsPowerOfTwo(lit)) { 1815 power_of_two = true; 1816 } else if (IsPopCountLE2(lit)) { 1817 pop_count_le2 = true; 1818 } else if (IsPowerOfTwo(lit + 1)) { 1819 power_of_two_minus_one = true; 1820 } else { 1821 return false; 1822 } 1823 rl_src = LoadValue(rl_src, kCoreReg); 1824 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1825 if (power_of_two) { 1826 // Shift. 1827 OpRegRegImm(kOpLsl, rl_result.reg, rl_src.reg, LowestSetBit(lit)); 1828 } else if (pop_count_le2) { 1829 // Shift and add and shift. 1830 int first_bit = LowestSetBit(lit); 1831 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1832 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1833 } else { 1834 // Reverse subtract: (src << (shift + 1)) - src. 1835 DCHECK(power_of_two_minus_one); 1836 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1837 RegStorage t_reg = AllocTemp(); 1838 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, LowestSetBit(lit + 1)); 1839 OpRegRegReg(kOpSub, rl_result.reg, t_reg, rl_src.reg); 1840 } 1841 StoreValue(rl_dest, rl_result); 1842 return true; 1843} 1844 1845void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1846 int lit) { 1847 RegLocation rl_result; 1848 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1849 int shift_op = false; 1850 bool is_div = false; 1851 1852 switch (opcode) { 1853 case Instruction::RSUB_INT_LIT8: 1854 case Instruction::RSUB_INT: { 1855 rl_src = LoadValue(rl_src, kCoreReg); 1856 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1857 if (cu_->instruction_set == kThumb2) { 1858 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, lit); 1859 } else { 1860 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1861 OpRegImm(kOpAdd, rl_result.reg, lit); 1862 } 1863 StoreValue(rl_dest, rl_result); 1864 return; 1865 } 1866 1867 case Instruction::SUB_INT: 1868 case Instruction::SUB_INT_2ADDR: 1869 lit = -lit; 1870 // Intended fallthrough 1871 case Instruction::ADD_INT: 1872 case Instruction::ADD_INT_2ADDR: 1873 case Instruction::ADD_INT_LIT8: 1874 case Instruction::ADD_INT_LIT16: 1875 op = kOpAdd; 1876 break; 1877 case Instruction::MUL_INT: 1878 case Instruction::MUL_INT_2ADDR: 1879 case Instruction::MUL_INT_LIT8: 1880 case Instruction::MUL_INT_LIT16: { 1881 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1882 return; 1883 } 1884 op = kOpMul; 1885 break; 1886 } 1887 case Instruction::AND_INT: 1888 case Instruction::AND_INT_2ADDR: 1889 case Instruction::AND_INT_LIT8: 1890 case Instruction::AND_INT_LIT16: 1891 op = kOpAnd; 1892 break; 1893 case Instruction::OR_INT: 1894 case Instruction::OR_INT_2ADDR: 1895 case Instruction::OR_INT_LIT8: 1896 case Instruction::OR_INT_LIT16: 1897 op = kOpOr; 1898 break; 1899 case Instruction::XOR_INT: 1900 case Instruction::XOR_INT_2ADDR: 1901 case Instruction::XOR_INT_LIT8: 1902 case Instruction::XOR_INT_LIT16: 1903 op = kOpXor; 1904 break; 1905 case Instruction::SHL_INT_LIT8: 1906 case Instruction::SHL_INT: 1907 case Instruction::SHL_INT_2ADDR: 1908 lit &= 31; 1909 shift_op = true; 1910 op = kOpLsl; 1911 break; 1912 case Instruction::SHR_INT_LIT8: 1913 case Instruction::SHR_INT: 1914 case Instruction::SHR_INT_2ADDR: 1915 lit &= 31; 1916 shift_op = true; 1917 op = kOpAsr; 1918 break; 1919 case Instruction::USHR_INT_LIT8: 1920 case Instruction::USHR_INT: 1921 case Instruction::USHR_INT_2ADDR: 1922 lit &= 31; 1923 shift_op = true; 1924 op = kOpLsr; 1925 break; 1926 1927 case Instruction::DIV_INT: 1928 case Instruction::DIV_INT_2ADDR: 1929 case Instruction::DIV_INT_LIT8: 1930 case Instruction::DIV_INT_LIT16: 1931 case Instruction::REM_INT: 1932 case Instruction::REM_INT_2ADDR: 1933 case Instruction::REM_INT_LIT8: 1934 case Instruction::REM_INT_LIT16: { 1935 if (lit == 0) { 1936 GenDivZeroException(); 1937 return; 1938 } 1939 if ((opcode == Instruction::DIV_INT) || 1940 (opcode == Instruction::DIV_INT_2ADDR) || 1941 (opcode == Instruction::DIV_INT_LIT8) || 1942 (opcode == Instruction::DIV_INT_LIT16)) { 1943 is_div = true; 1944 } else { 1945 is_div = false; 1946 } 1947 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1948 return; 1949 } 1950 1951 bool done = false; 1952 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1953 rl_src = LoadValue(rl_src, kCoreReg); 1954 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1955 done = true; 1956 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1957 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1958 done = true; 1959 } else if (cu_->instruction_set == kThumb2) { 1960 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1961 // Use ARM SDIV instruction for division. For remainder we also need to 1962 // calculate using a MUL and subtract. 1963 rl_src = LoadValue(rl_src, kCoreReg); 1964 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1965 done = true; 1966 } 1967 } 1968 1969 if (!done) { 1970 FlushAllRegs(); /* Everything to home location. */ 1971 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kNotWide)); 1972 Clobber(TargetReg(kArg0, kNotWide)); 1973 if (cu_->target64) { 1974 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), TargetReg(kArg0, kNotWide), 1975 lit, false); 1976 } else { 1977 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), TargetReg(kArg0, kNotWide), 1978 lit, false); 1979 } 1980 if (is_div) 1981 rl_result = GetReturn(kCoreReg); 1982 else 1983 rl_result = GetReturnAlt(); 1984 } 1985 StoreValue(rl_dest, rl_result); 1986 return; 1987 } 1988 default: 1989 LOG(FATAL) << "Unexpected opcode " << opcode; 1990 } 1991 rl_src = LoadValue(rl_src, kCoreReg); 1992 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1993 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 1994 if (shift_op && (lit == 0)) { 1995 OpRegCopy(rl_result.reg, rl_src.reg); 1996 } else { 1997 OpRegRegImm(op, rl_result.reg, rl_src.reg, lit); 1998 } 1999 StoreValue(rl_dest, rl_result); 2000} 2001 2002template <size_t pointer_size> 2003static void GenArithOpLongImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, Instruction::Code opcode, 2004 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 2005 RegLocation rl_result; 2006 OpKind first_op = kOpBkpt; 2007 OpKind second_op = kOpBkpt; 2008 bool call_out = false; 2009 bool check_zero = false; 2010 ThreadOffset<pointer_size> func_offset(-1); 2011 int ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2012 2013 switch (opcode) { 2014 case Instruction::NOT_LONG: 2015 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2016 mir_to_lir->GenNotLong(rl_dest, rl_src2); 2017 return; 2018 } 2019 rl_src2 = mir_to_lir->LoadValueWide(rl_src2, kCoreReg); 2020 rl_result = mir_to_lir->EvalLoc(rl_dest, kCoreReg, true); 2021 // Check for destructive overlap 2022 if (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg()) { 2023 RegStorage t_reg = mir_to_lir->AllocTemp(); 2024 mir_to_lir->OpRegCopy(t_reg, rl_src2.reg.GetHigh()); 2025 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2026 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), t_reg); 2027 mir_to_lir->FreeTemp(t_reg); 2028 } else { 2029 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2030 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); 2031 } 2032 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2033 return; 2034 case Instruction::ADD_LONG: 2035 case Instruction::ADD_LONG_2ADDR: 2036 if (cu->instruction_set != kThumb2) { 2037 mir_to_lir->GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 2038 return; 2039 } 2040 first_op = kOpAdd; 2041 second_op = kOpAdc; 2042 break; 2043 case Instruction::SUB_LONG: 2044 case Instruction::SUB_LONG_2ADDR: 2045 if (cu->instruction_set != kThumb2) { 2046 mir_to_lir->GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 2047 return; 2048 } 2049 first_op = kOpSub; 2050 second_op = kOpSbc; 2051 break; 2052 case Instruction::MUL_LONG: 2053 case Instruction::MUL_LONG_2ADDR: 2054 if (cu->instruction_set != kMips) { 2055 mir_to_lir->GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 2056 return; 2057 } else { 2058 call_out = true; 2059 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2060 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmul); 2061 } 2062 break; 2063 case Instruction::DIV_LONG: 2064 case Instruction::DIV_LONG_2ADDR: 2065 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2066 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); 2067 return; 2068 } 2069 call_out = true; 2070 check_zero = true; 2071 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2072 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLdiv); 2073 break; 2074 case Instruction::REM_LONG: 2075 case Instruction::REM_LONG_2ADDR: 2076 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2077 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); 2078 return; 2079 } 2080 call_out = true; 2081 check_zero = true; 2082 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmod); 2083 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 2084 ret_reg = (cu->instruction_set == kThumb2) ? mir_to_lir->TargetReg(kArg2, kNotWide).GetReg() : 2085 mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2086 break; 2087 case Instruction::AND_LONG_2ADDR: 2088 case Instruction::AND_LONG: 2089 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2090 cu->instruction_set == kArm64) { 2091 return mir_to_lir->GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 2092 } 2093 first_op = kOpAnd; 2094 second_op = kOpAnd; 2095 break; 2096 case Instruction::OR_LONG: 2097 case Instruction::OR_LONG_2ADDR: 2098 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2099 cu->instruction_set == kArm64) { 2100 mir_to_lir->GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 2101 return; 2102 } 2103 first_op = kOpOr; 2104 second_op = kOpOr; 2105 break; 2106 case Instruction::XOR_LONG: 2107 case Instruction::XOR_LONG_2ADDR: 2108 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2109 cu->instruction_set == kArm64) { 2110 mir_to_lir->GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 2111 return; 2112 } 2113 first_op = kOpXor; 2114 second_op = kOpXor; 2115 break; 2116 case Instruction::NEG_LONG: { 2117 mir_to_lir->GenNegLong(rl_dest, rl_src2); 2118 return; 2119 } 2120 default: 2121 LOG(FATAL) << "Invalid long arith op"; 2122 } 2123 if (!call_out) { 2124 mir_to_lir->GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 2125 } else { 2126 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 2127 if (check_zero) { 2128 RegStorage r_tmp1 = mir_to_lir->TargetReg(kArg0, kWide); 2129 RegStorage r_tmp2 = mir_to_lir->TargetReg(kArg2, kWide); 2130 mir_to_lir->LoadValueDirectWideFixed(rl_src2, r_tmp2); 2131 RegStorage r_tgt = mir_to_lir->CallHelperSetup(func_offset); 2132 mir_to_lir->GenDivZeroCheckWide(r_tmp2); 2133 mir_to_lir->LoadValueDirectWideFixed(rl_src1, r_tmp1); 2134 // NOTE: callout here is not a safepoint 2135 mir_to_lir->CallHelper(r_tgt, func_offset, false /* not safepoint */); 2136 } else { 2137 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 2138 } 2139 // Adjust return regs in to handle case of rem returning kArg2/kArg3 2140 if (ret_reg == mir_to_lir->TargetReg(kRet0, kNotWide).GetReg()) 2141 rl_result = mir_to_lir->GetReturnWide(kCoreReg); 2142 else 2143 rl_result = mir_to_lir->GetReturnWideAlt(); 2144 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2145 } 2146} 2147 2148void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 2149 RegLocation rl_src1, RegLocation rl_src2) { 2150 if (cu_->target64) { 2151 GenArithOpLongImpl<8>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2152 } else { 2153 GenArithOpLongImpl<4>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2154 } 2155} 2156 2157void Mir2Lir::GenConst(RegLocation rl_dest, int value) { 2158 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2159 LoadConstantNoClobber(rl_result.reg, value); 2160 StoreValue(rl_dest, rl_result); 2161 if (value == 0) { 2162 Workaround7250540(rl_dest, rl_result.reg); 2163 } 2164} 2165 2166template <size_t pointer_size> 2167void Mir2Lir::GenConversionCall(ThreadOffset<pointer_size> func_offset, 2168 RegLocation rl_dest, RegLocation rl_src) { 2169 /* 2170 * Don't optimize the register usage since it calls out to support 2171 * functions 2172 */ 2173 DCHECK_EQ(pointer_size, GetInstructionSetPointerSize(cu_->instruction_set)); 2174 2175 FlushAllRegs(); /* Send everything to home location */ 2176 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 2177 if (rl_dest.wide) { 2178 RegLocation rl_result; 2179 rl_result = GetReturnWide(LocToRegClass(rl_dest)); 2180 StoreValueWide(rl_dest, rl_result); 2181 } else { 2182 RegLocation rl_result; 2183 rl_result = GetReturn(LocToRegClass(rl_dest)); 2184 StoreValue(rl_dest, rl_result); 2185 } 2186} 2187template void Mir2Lir::GenConversionCall(ThreadOffset<4> func_offset, 2188 RegLocation rl_dest, RegLocation rl_src); 2189template void Mir2Lir::GenConversionCall(ThreadOffset<8> func_offset, 2190 RegLocation rl_dest, RegLocation rl_src); 2191 2192class SuspendCheckSlowPath : public Mir2Lir::LIRSlowPath { 2193 public: 2194 SuspendCheckSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont) 2195 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont) { 2196 } 2197 2198 void Compile() OVERRIDE { 2199 m2l_->ResetRegPool(); 2200 m2l_->ResetDefTracking(); 2201 GenerateTargetLabel(kPseudoSuspendTarget); 2202 if (cu_->target64) { 2203 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pTestSuspend), true); 2204 } else { 2205 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pTestSuspend), true); 2206 } 2207 if (cont_ != nullptr) { 2208 m2l_->OpUnconditionalBranch(cont_); 2209 } 2210 } 2211}; 2212 2213/* Check if we need to check for pending suspend request */ 2214void Mir2Lir::GenSuspendTest(int opt_flags) { 2215 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitSuspendChecks()) { 2216 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2217 return; 2218 } 2219 FlushAllRegs(); 2220 LIR* branch = OpTestSuspend(NULL); 2221 LIR* cont = NewLIR0(kPseudoTargetLabel); 2222 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, cont)); 2223 } else { 2224 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2225 return; 2226 } 2227 FlushAllRegs(); // TODO: needed? 2228 LIR* inst = CheckSuspendUsingLoad(); 2229 MarkSafepointPC(inst); 2230 } 2231} 2232 2233/* Check if we need to check for pending suspend request */ 2234void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 2235 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitSuspendChecks()) { 2236 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2237 OpUnconditionalBranch(target); 2238 return; 2239 } 2240 OpTestSuspend(target); 2241 FlushAllRegs(); 2242 LIR* branch = OpUnconditionalBranch(nullptr); 2243 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, target)); 2244 } else { 2245 // For the implicit suspend check, just perform the trigger 2246 // load and branch to the target. 2247 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2248 OpUnconditionalBranch(target); 2249 return; 2250 } 2251 FlushAllRegs(); 2252 LIR* inst = CheckSuspendUsingLoad(); 2253 MarkSafepointPC(inst); 2254 OpUnconditionalBranch(target); 2255 } 2256} 2257 2258/* Call out to helper assembly routine that will null check obj and then lock it. */ 2259void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2260 FlushAllRegs(); 2261 if (cu_->target64) { 2262 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pLockObject), rl_src, true); 2263 } else { 2264 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pLockObject), rl_src, true); 2265 } 2266} 2267 2268/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2269void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2270 FlushAllRegs(); 2271 if (cu_->target64) { 2272 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject), rl_src, true); 2273 } else { 2274 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject), rl_src, true); 2275 } 2276} 2277 2278/* Generic code for generating a wide constant into a VR. */ 2279void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2280 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2281 LoadConstantWide(rl_result.reg, value); 2282 StoreValueWide(rl_dest, rl_result); 2283} 2284 2285} // namespace art 2286