gen_common.cc revision 9ee4519afd97121f893f82d41d23164fc6c9ed34
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include "dex/compiler_ir.h" 17#include "dex/compiler_internals.h" 18#include "dex/quick/arm/arm_lir.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object_array-inl.h" 23#include "mirror/object-inl.h" 24#include "verifier/method_verifier.h" 25#include <functional> 26 27namespace art { 28 29// Shortcuts to repeatedly used long types. 30typedef mirror::ObjectArray<mirror::Object> ObjArray; 31typedef mirror::ObjectArray<mirror::Class> ClassArray; 32 33/* 34 * This source files contains "gen" codegen routines that should 35 * be applicable to most targets. Only mid-level support utilities 36 * and "op" calls may be used here. 37 */ 38 39/* 40 * Generate a kPseudoBarrier marker to indicate the boundary of special 41 * blocks. 42 */ 43void Mir2Lir::GenBarrier() { 44 LIR* barrier = NewLIR0(kPseudoBarrier); 45 /* Mark all resources as being clobbered */ 46 DCHECK(!barrier->flags.use_def_invalid); 47 barrier->u.m.def_mask = &kEncodeAll; 48} 49 50void Mir2Lir::GenDivZeroException() { 51 LIR* branch = OpUnconditionalBranch(nullptr); 52 AddDivZeroCheckSlowPath(branch); 53} 54 55void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { 56 LIR* branch = OpCondBranch(c_code, nullptr); 57 AddDivZeroCheckSlowPath(branch); 58} 59 60void Mir2Lir::GenDivZeroCheck(RegStorage reg) { 61 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 62 AddDivZeroCheckSlowPath(branch); 63} 64 65void Mir2Lir::AddDivZeroCheckSlowPath(LIR* branch) { 66 class DivZeroCheckSlowPath : public Mir2Lir::LIRSlowPath { 67 public: 68 DivZeroCheckSlowPath(Mir2Lir* m2l, LIR* branch) 69 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 70 } 71 72 void Compile() OVERRIDE { 73 m2l_->ResetRegPool(); 74 m2l_->ResetDefTracking(); 75 GenerateTargetLabel(kPseudoThrowTarget); 76 if (m2l_->cu_->target64) { 77 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowDivZero), true); 78 } else { 79 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowDivZero), true); 80 } 81 } 82 }; 83 84 AddSlowPath(new (arena_) DivZeroCheckSlowPath(this, branch)); 85} 86 87void Mir2Lir::GenArrayBoundsCheck(RegStorage index, RegStorage length) { 88 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 89 public: 90 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, RegStorage index, RegStorage length) 91 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 92 index_(index), length_(length) { 93 } 94 95 void Compile() OVERRIDE { 96 m2l_->ResetRegPool(); 97 m2l_->ResetDefTracking(); 98 GenerateTargetLabel(kPseudoThrowTarget); 99 if (m2l_->cu_->target64) { 100 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 101 index_, length_, true); 102 } else { 103 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 104 index_, length_, true); 105 } 106 } 107 108 private: 109 const RegStorage index_; 110 const RegStorage length_; 111 }; 112 113 LIR* branch = OpCmpBranch(kCondUge, index, length, nullptr); 114 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 115} 116 117void Mir2Lir::GenArrayBoundsCheck(int index, RegStorage length) { 118 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 119 public: 120 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, int index, RegStorage length) 121 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 122 index_(index), length_(length) { 123 } 124 125 void Compile() OVERRIDE { 126 m2l_->ResetRegPool(); 127 m2l_->ResetDefTracking(); 128 GenerateTargetLabel(kPseudoThrowTarget); 129 130 RegStorage arg1_32 = m2l_->TargetReg(kArg1, kNotWide); 131 RegStorage arg0_32 = m2l_->TargetReg(kArg0, kNotWide); 132 133 m2l_->OpRegCopy(arg1_32, length_); 134 m2l_->LoadConstant(arg0_32, index_); 135 if (m2l_->cu_->target64) { 136 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 137 arg0_32, arg1_32, true); 138 } else { 139 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 140 arg0_32, arg1_32, true); 141 } 142 } 143 144 private: 145 const int32_t index_; 146 const RegStorage length_; 147 }; 148 149 LIR* branch = OpCmpImmBranch(kCondLs, length, index, nullptr); 150 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 151} 152 153LIR* Mir2Lir::GenNullCheck(RegStorage reg) { 154 class NullCheckSlowPath : public Mir2Lir::LIRSlowPath { 155 public: 156 NullCheckSlowPath(Mir2Lir* m2l, LIR* branch) 157 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 158 } 159 160 void Compile() OVERRIDE { 161 m2l_->ResetRegPool(); 162 m2l_->ResetDefTracking(); 163 GenerateTargetLabel(kPseudoThrowTarget); 164 if (m2l_->cu_->target64) { 165 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowNullPointer), true); 166 } else { 167 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowNullPointer), true); 168 } 169 } 170 }; 171 172 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 173 AddSlowPath(new (arena_) NullCheckSlowPath(this, branch)); 174 return branch; 175} 176 177/* Perform null-check on a register. */ 178LIR* Mir2Lir::GenNullCheck(RegStorage m_reg, int opt_flags) { 179 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 180 return GenExplicitNullCheck(m_reg, opt_flags); 181 } 182 return nullptr; 183} 184 185/* Perform an explicit null-check on a register. */ 186LIR* Mir2Lir::GenExplicitNullCheck(RegStorage m_reg, int opt_flags) { 187 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 188 return NULL; 189 } 190 return GenNullCheck(m_reg); 191} 192 193void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 194 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 195 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 196 return; 197 } 198 // Insert after last instruction. 199 MarkSafepointPC(last_lir_insn_); 200 } 201} 202 203void Mir2Lir::MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after) { 204 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 205 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 206 return; 207 } 208 MarkSafepointPCAfter(after); 209 } 210} 211 212void Mir2Lir::MarkPossibleStackOverflowException() { 213 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitStackOverflowChecks()) { 214 MarkSafepointPC(last_lir_insn_); 215 } 216} 217 218void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { 219 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 220 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 221 return; 222 } 223 // Force an implicit null check by performing a memory operation (load) from the given 224 // register with offset 0. This will cause a signal if the register contains 0 (null). 225 RegStorage tmp = AllocTemp(); 226 // TODO: for Mips, would be best to use rZERO as the bogus register target. 227 LIR* load = Load32Disp(reg, 0, tmp); 228 FreeTemp(tmp); 229 MarkSafepointPC(load); 230 } 231} 232 233void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 234 RegLocation rl_src2, LIR* taken, 235 LIR* fall_through) { 236 DCHECK(!rl_src1.fp); 237 DCHECK(!rl_src2.fp); 238 ConditionCode cond; 239 switch (opcode) { 240 case Instruction::IF_EQ: 241 cond = kCondEq; 242 break; 243 case Instruction::IF_NE: 244 cond = kCondNe; 245 break; 246 case Instruction::IF_LT: 247 cond = kCondLt; 248 break; 249 case Instruction::IF_GE: 250 cond = kCondGe; 251 break; 252 case Instruction::IF_GT: 253 cond = kCondGt; 254 break; 255 case Instruction::IF_LE: 256 cond = kCondLe; 257 break; 258 default: 259 cond = static_cast<ConditionCode>(0); 260 LOG(FATAL) << "Unexpected opcode " << opcode; 261 } 262 263 // Normalize such that if either operand is constant, src2 will be constant 264 if (rl_src1.is_const) { 265 RegLocation rl_temp = rl_src1; 266 rl_src1 = rl_src2; 267 rl_src2 = rl_temp; 268 cond = FlipComparisonOrder(cond); 269 } 270 271 rl_src1 = LoadValue(rl_src1); 272 // Is this really an immediate comparison? 273 if (rl_src2.is_const) { 274 // If it's already live in a register or not easily materialized, just keep going 275 RegLocation rl_temp = UpdateLoc(rl_src2); 276 if ((rl_temp.location == kLocDalvikFrame) && 277 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 278 // OK - convert this to a compare immediate and branch 279 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); 280 return; 281 } 282 } 283 rl_src2 = LoadValue(rl_src2); 284 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken); 285} 286 287void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 288 LIR* fall_through) { 289 ConditionCode cond; 290 DCHECK(!rl_src.fp); 291 rl_src = LoadValue(rl_src); 292 switch (opcode) { 293 case Instruction::IF_EQZ: 294 cond = kCondEq; 295 break; 296 case Instruction::IF_NEZ: 297 cond = kCondNe; 298 break; 299 case Instruction::IF_LTZ: 300 cond = kCondLt; 301 break; 302 case Instruction::IF_GEZ: 303 cond = kCondGe; 304 break; 305 case Instruction::IF_GTZ: 306 cond = kCondGt; 307 break; 308 case Instruction::IF_LEZ: 309 cond = kCondLe; 310 break; 311 default: 312 cond = static_cast<ConditionCode>(0); 313 LOG(FATAL) << "Unexpected opcode " << opcode; 314 } 315 OpCmpImmBranch(cond, rl_src.reg, 0, taken); 316} 317 318void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 319 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 320 if (rl_src.location == kLocPhysReg) { 321 OpRegCopy(rl_result.reg, rl_src.reg); 322 } else { 323 LoadValueDirect(rl_src, rl_result.reg.GetLow()); 324 } 325 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_result.reg.GetLow(), 31); 326 StoreValueWide(rl_dest, rl_result); 327} 328 329void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 330 RegLocation rl_src) { 331 rl_src = LoadValue(rl_src, kCoreReg); 332 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 333 OpKind op = kOpInvalid; 334 switch (opcode) { 335 case Instruction::INT_TO_BYTE: 336 op = kOp2Byte; 337 break; 338 case Instruction::INT_TO_SHORT: 339 op = kOp2Short; 340 break; 341 case Instruction::INT_TO_CHAR: 342 op = kOp2Char; 343 break; 344 default: 345 LOG(ERROR) << "Bad int conversion type"; 346 } 347 OpRegReg(op, rl_result.reg, rl_src.reg); 348 StoreValue(rl_dest, rl_result); 349} 350 351template <size_t pointer_size> 352static void GenNewArrayImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, 353 uint32_t type_idx, RegLocation rl_dest, 354 RegLocation rl_src) { 355 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 356 ThreadOffset<pointer_size> func_offset(-1); 357 const DexFile* dex_file = cu->dex_file; 358 CompilerDriver* driver = cu->compiler_driver; 359 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *dex_file, 360 type_idx)) { 361 bool is_type_initialized; // Ignored as an array does not have an initializer. 362 bool use_direct_type_ptr; 363 uintptr_t direct_type_ptr; 364 bool is_finalizable; 365 if (kEmbedClassInCode && 366 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 367 &direct_type_ptr, &is_finalizable)) { 368 // The fast path. 369 if (!use_direct_type_ptr) { 370 mir_to_lir->LoadClassType(type_idx, kArg0); 371 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 372 mir_to_lir->CallRuntimeHelperRegMethodRegLocation(func_offset, 373 mir_to_lir->TargetReg(kArg0, kNotWide), 374 rl_src, true); 375 } else { 376 // Use the direct pointer. 377 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 378 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, 379 true); 380 } 381 } else { 382 // The slow path. 383 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArray); 384 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 385 } 386 DCHECK_NE(func_offset.Int32Value(), -1); 387 } else { 388 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayWithAccessCheck); 389 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 390 } 391 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 392 mir_to_lir->StoreValue(rl_dest, rl_result); 393} 394 395/* 396 * Let helper function take care of everything. Will call 397 * Array::AllocFromCode(type_idx, method, count); 398 * Note: AllocFromCode will handle checks for errNegativeArraySize. 399 */ 400void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 401 RegLocation rl_src) { 402 if (cu_->target64) { 403 GenNewArrayImpl<8>(this, cu_, type_idx, rl_dest, rl_src); 404 } else { 405 GenNewArrayImpl<4>(this, cu_, type_idx, rl_dest, rl_src); 406 } 407} 408 409template <size_t pointer_size> 410static void GenFilledNewArrayCall(Mir2Lir* mir_to_lir, CompilationUnit* cu, int elems, int type_idx) { 411 ThreadOffset<pointer_size> func_offset(-1); 412 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *cu->dex_file, 413 type_idx)) { 414 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArray); 415 } else { 416 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArrayWithAccessCheck); 417 } 418 mir_to_lir->CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 419} 420 421/* 422 * Similar to GenNewArray, but with post-allocation initialization. 423 * Verifier guarantees we're dealing with an array class. Current 424 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 425 * Current code also throws internal unimp if not 'L', '[' or 'I'. 426 */ 427void Mir2Lir::GenFilledNewArray(CallInfo* info) { 428 int elems = info->num_arg_words; 429 int type_idx = info->index; 430 FlushAllRegs(); /* Everything to home location */ 431 if (cu_->target64) { 432 GenFilledNewArrayCall<8>(this, cu_, elems, type_idx); 433 } else { 434 GenFilledNewArrayCall<4>(this, cu_, elems, type_idx); 435 } 436 FreeTemp(TargetReg(kArg2, kNotWide)); 437 FreeTemp(TargetReg(kArg1, kNotWide)); 438 /* 439 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 440 * return region. Because AllocFromCode placed the new array 441 * in kRet0, we'll just lock it into place. When debugger support is 442 * added, it may be necessary to additionally copy all return 443 * values to a home location in thread-local storage 444 */ 445 RegStorage ref_reg = TargetReg(kRet0, kRef); 446 LockTemp(ref_reg); 447 448 // TODO: use the correct component size, currently all supported types 449 // share array alignment with ints (see comment at head of function) 450 size_t component_size = sizeof(int32_t); 451 452 // Having a range of 0 is legal 453 if (info->is_range && (elems > 0)) { 454 /* 455 * Bit of ugliness here. We're going generate a mem copy loop 456 * on the register range, but it is possible that some regs 457 * in the range have been promoted. This is unlikely, but 458 * before generating the copy, we'll just force a flush 459 * of any regs in the source range that have been promoted to 460 * home location. 461 */ 462 for (int i = 0; i < elems; i++) { 463 RegLocation loc = UpdateLoc(info->args[i]); 464 if (loc.location == kLocPhysReg) { 465 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 466 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 467 } 468 } 469 /* 470 * TUNING note: generated code here could be much improved, but 471 * this is an uncommon operation and isn't especially performance 472 * critical. 473 */ 474 // This is addressing the stack, which may be out of the 4G area. 475 RegStorage r_src = AllocTempRef(); 476 RegStorage r_dst = AllocTempRef(); 477 RegStorage r_idx = AllocTempRef(); // Not really a reference, but match src/dst. 478 RegStorage r_val; 479 switch (cu_->instruction_set) { 480 case kThumb2: 481 case kArm64: 482 r_val = TargetReg(kLr, kNotWide); 483 break; 484 case kX86: 485 case kX86_64: 486 FreeTemp(ref_reg); 487 r_val = AllocTemp(); 488 break; 489 case kMips: 490 r_val = AllocTemp(); 491 break; 492 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 493 } 494 // Set up source pointer 495 RegLocation rl_first = info->args[0]; 496 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); 497 // Set up the target pointer 498 OpRegRegImm(kOpAdd, r_dst, ref_reg, 499 mirror::Array::DataOffset(component_size).Int32Value()); 500 // Set up the loop counter (known to be > 0) 501 LoadConstant(r_idx, elems - 1); 502 // Generate the copy loop. Going backwards for convenience 503 LIR* target = NewLIR0(kPseudoTargetLabel); 504 // Copy next element 505 { 506 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 507 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32); 508 // NOTE: No dalvik register annotation, local optimizations will be stopped 509 // by the loop boundaries. 510 } 511 StoreBaseIndexed(r_dst, r_idx, r_val, 2, k32); 512 FreeTemp(r_val); 513 OpDecAndBranch(kCondGe, r_idx, target); 514 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 515 // Restore the target pointer 516 OpRegRegImm(kOpAdd, ref_reg, r_dst, 517 -mirror::Array::DataOffset(component_size).Int32Value()); 518 } 519 } else if (!info->is_range) { 520 // TUNING: interleave 521 for (int i = 0; i < elems; i++) { 522 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 523 Store32Disp(ref_reg, 524 mirror::Array::DataOffset(component_size).Int32Value() + i * 4, rl_arg.reg); 525 // If the LoadValue caused a temp to be allocated, free it 526 if (IsTemp(rl_arg.reg)) { 527 FreeTemp(rl_arg.reg); 528 } 529 } 530 } 531 if (info->result.location != kLocInvalid) { 532 StoreValue(info->result, GetReturn(kRefReg)); 533 } 534} 535 536// 537// Slow path to ensure a class is initialized for sget/sput. 538// 539class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 540 public: 541 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, int storage_index, 542 RegStorage r_base) : 543 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), 544 storage_index_(storage_index), r_base_(r_base) { 545 } 546 547 void Compile() { 548 LIR* unresolved_target = GenerateTargetLabel(); 549 uninit_->target = unresolved_target; 550 if (cu_->target64) { 551 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeStaticStorage), 552 storage_index_, true); 553 } else { 554 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeStaticStorage), 555 storage_index_, true); 556 } 557 // Copy helper's result into r_base, a no-op on all but MIPS. 558 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0, kRef)); 559 560 m2l_->OpUnconditionalBranch(cont_); 561 } 562 563 private: 564 LIR* const uninit_; 565 const int storage_index_; 566 const RegStorage r_base_; 567}; 568 569template <size_t pointer_size> 570static void GenSputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 571 const MirSFieldLoweringInfo* field_info, RegLocation rl_src) { 572 ThreadOffset<pointer_size> setter_offset = 573 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Static) 574 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjStatic) 575 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Static)); 576 mir_to_lir->CallRuntimeHelperImmRegLocation(setter_offset, field_info->FieldIndex(), rl_src, 577 true); 578} 579 580void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 581 bool is_object) { 582 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 583 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 584 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 585 if (!SLOW_FIELD_PATH && field_info.FastPut()) { 586 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 587 RegStorage r_base; 588 if (field_info.IsReferrersClass()) { 589 // Fast path, static storage base is this method's class 590 RegLocation rl_method = LoadCurrMethod(); 591 r_base = AllocTempRef(); 592 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 593 kNotVolatile); 594 if (IsTemp(rl_method.reg)) { 595 FreeTemp(rl_method.reg); 596 } 597 } else { 598 // Medium path, static storage base in a different class which requires checks that the other 599 // class is initialized. 600 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 601 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 602 // May do runtime call so everything to home locations. 603 FlushAllRegs(); 604 // Using fixed register to sync with possible call to runtime support. 605 RegStorage r_method = TargetReg(kArg1, kRef); 606 LockTemp(r_method); 607 LoadCurrMethodDirect(r_method); 608 r_base = TargetReg(kArg0, kRef); 609 LockTemp(r_base); 610 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 611 kNotVolatile); 612 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 613 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 614 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 615 if (!field_info.IsInitialized() && 616 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 617 // Check if r_base is NULL or a not yet initialized class. 618 619 // The slow path is invoked if the r_base is NULL or the class pointed 620 // to by it is not initialized. 621 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 622 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 623 LockTemp(r_tmp); 624 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 625 mirror::Class::StatusOffset().Int32Value(), 626 mirror::Class::kStatusInitialized, nullptr, nullptr); 627 LIR* cont = NewLIR0(kPseudoTargetLabel); 628 629 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 630 field_info.StorageIndex(), r_base)); 631 632 FreeTemp(r_tmp); 633 // Ensure load of status and store of value don't re-order. 634 // TODO: Presumably the actual value store is control-dependent on the status load, 635 // and will thus not be reordered in any case, since stores are never speculated. 636 // Does later code "know" that the class is now initialized? If so, we still 637 // need the barrier to guard later static loads. 638 GenMemBarrier(kLoadAny); 639 } 640 FreeTemp(r_method); 641 } 642 // rBase now holds static storage base 643 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 644 if (is_long_or_double) { 645 rl_src = LoadValueWide(rl_src, reg_class); 646 } else { 647 rl_src = LoadValue(rl_src, reg_class); 648 } 649 if (is_object) { 650 StoreRefDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, 651 field_info.IsVolatile() ? kVolatile : kNotVolatile); 652 } else { 653 StoreBaseDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, store_size, 654 field_info.IsVolatile() ? kVolatile : kNotVolatile); 655 } 656 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 657 MarkGCCard(rl_src.reg, r_base); 658 } 659 FreeTemp(r_base); 660 } else { 661 FlushAllRegs(); // Everything to home locations 662 if (cu_->target64) { 663 GenSputCall<8>(this, is_long_or_double, is_object, &field_info, rl_src); 664 } else { 665 GenSputCall<4>(this, is_long_or_double, is_object, &field_info, rl_src); 666 } 667 } 668} 669 670template <size_t pointer_size> 671static void GenSgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 672 const MirSFieldLoweringInfo* field_info) { 673 ThreadOffset<pointer_size> getter_offset = 674 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Static) 675 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjStatic) 676 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Static)); 677 mir_to_lir->CallRuntimeHelperImm(getter_offset, field_info->FieldIndex(), true); 678} 679 680void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 681 bool is_long_or_double, bool is_object) { 682 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 683 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 684 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 685 if (!SLOW_FIELD_PATH && field_info.FastGet()) { 686 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 687 RegStorage r_base; 688 if (field_info.IsReferrersClass()) { 689 // Fast path, static storage base is this method's class 690 RegLocation rl_method = LoadCurrMethod(); 691 r_base = AllocTempRef(); 692 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 693 kNotVolatile); 694 } else { 695 // Medium path, static storage base in a different class which requires checks that the other 696 // class is initialized 697 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 698 // May do runtime call so everything to home locations. 699 FlushAllRegs(); 700 // Using fixed register to sync with possible call to runtime support. 701 RegStorage r_method = TargetReg(kArg1, kRef); 702 LockTemp(r_method); 703 LoadCurrMethodDirect(r_method); 704 r_base = TargetReg(kArg0, kRef); 705 LockTemp(r_base); 706 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 707 kNotVolatile); 708 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 709 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 710 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 711 if (!field_info.IsInitialized() && 712 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 713 // Check if r_base is NULL or a not yet initialized class. 714 715 // The slow path is invoked if the r_base is NULL or the class pointed 716 // to by it is not initialized. 717 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 718 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 719 LockTemp(r_tmp); 720 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 721 mirror::Class::StatusOffset().Int32Value(), 722 mirror::Class::kStatusInitialized, nullptr, nullptr); 723 LIR* cont = NewLIR0(kPseudoTargetLabel); 724 725 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 726 field_info.StorageIndex(), r_base)); 727 728 FreeTemp(r_tmp); 729 // Ensure load of status and load of value don't re-order. 730 GenMemBarrier(kLoadAny); 731 } 732 FreeTemp(r_method); 733 } 734 // r_base now holds static storage base 735 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 736 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 737 738 int field_offset = field_info.FieldOffset().Int32Value(); 739 if (is_object) { 740 LoadRefDisp(r_base, field_offset, rl_result.reg, field_info.IsVolatile() ? kVolatile : 741 kNotVolatile); 742 } else { 743 LoadBaseDisp(r_base, field_offset, rl_result.reg, load_size, field_info.IsVolatile() ? 744 kVolatile : kNotVolatile); 745 } 746 FreeTemp(r_base); 747 748 if (is_long_or_double) { 749 StoreValueWide(rl_dest, rl_result); 750 } else { 751 StoreValue(rl_dest, rl_result); 752 } 753 } else { 754 FlushAllRegs(); // Everything to home locations 755 if (cu_->target64) { 756 GenSgetCall<8>(this, is_long_or_double, is_object, &field_info); 757 } else { 758 GenSgetCall<4>(this, is_long_or_double, is_object, &field_info); 759 } 760 // FIXME: pGetXXStatic always return an int or int64 regardless of rl_dest.fp. 761 if (is_long_or_double) { 762 RegLocation rl_result = GetReturnWide(kCoreReg); 763 StoreValueWide(rl_dest, rl_result); 764 } else { 765 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 766 StoreValue(rl_dest, rl_result); 767 } 768 } 769} 770 771// Generate code for all slow paths. 772void Mir2Lir::HandleSlowPaths() { 773 // We should check slow_paths_.Size() every time, because a new slow path 774 // may be created during slowpath->Compile(). 775 for (size_t i = 0; i < slow_paths_.Size(); ++i) { 776 LIRSlowPath* slowpath = slow_paths_.Get(i); 777 slowpath->Compile(); 778 } 779 slow_paths_.Reset(); 780} 781 782template <size_t pointer_size> 783static void GenIgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 784 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj) { 785 ThreadOffset<pointer_size> getter_offset = 786 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Instance) 787 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjInstance) 788 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Instance)); 789 // Second argument of pGetXXInstance is always a reference. 790 DCHECK_EQ(static_cast<unsigned int>(rl_obj.wide), 0U); 791 mir_to_lir->CallRuntimeHelperImmRegLocation(getter_offset, field_info->FieldIndex(), rl_obj, 792 true); 793} 794 795void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 796 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 797 bool is_object) { 798 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 799 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 800 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 801 if (!SLOW_FIELD_PATH && field_info.FastGet()) { 802 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 803 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 804 rl_obj = LoadValue(rl_obj, kRefReg); 805 GenNullCheck(rl_obj.reg, opt_flags); 806 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 807 int field_offset = field_info.FieldOffset().Int32Value(); 808 LIR* load_lir; 809 if (is_object) { 810 load_lir = LoadRefDisp(rl_obj.reg, field_offset, rl_result.reg, field_info.IsVolatile() ? 811 kVolatile : kNotVolatile); 812 } else { 813 load_lir = LoadBaseDisp(rl_obj.reg, field_offset, rl_result.reg, load_size, 814 field_info.IsVolatile() ? kVolatile : kNotVolatile); 815 } 816 MarkPossibleNullPointerExceptionAfter(opt_flags, load_lir); 817 if (is_long_or_double) { 818 StoreValueWide(rl_dest, rl_result); 819 } else { 820 StoreValue(rl_dest, rl_result); 821 } 822 } else { 823 if (cu_->target64) { 824 GenIgetCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj); 825 } else { 826 GenIgetCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj); 827 } 828 // FIXME: pGetXXInstance always return an int or int64 regardless of rl_dest.fp. 829 if (is_long_or_double) { 830 RegLocation rl_result = GetReturnWide(kCoreReg); 831 StoreValueWide(rl_dest, rl_result); 832 } else { 833 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 834 StoreValue(rl_dest, rl_result); 835 } 836 } 837} 838 839template <size_t pointer_size> 840static void GenIputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 841 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj, 842 RegLocation rl_src) { 843 ThreadOffset<pointer_size> setter_offset = 844 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Instance) 845 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjInstance) 846 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Instance)); 847 mir_to_lir->CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info->FieldIndex(), 848 rl_obj, rl_src, true); 849} 850 851void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 852 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 853 bool is_object) { 854 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 855 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 856 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 857 if (!SLOW_FIELD_PATH && field_info.FastPut()) { 858 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 859 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 860 rl_obj = LoadValue(rl_obj, kRefReg); 861 if (is_long_or_double) { 862 rl_src = LoadValueWide(rl_src, reg_class); 863 } else { 864 rl_src = LoadValue(rl_src, reg_class); 865 } 866 GenNullCheck(rl_obj.reg, opt_flags); 867 int field_offset = field_info.FieldOffset().Int32Value(); 868 LIR* store; 869 if (is_object) { 870 store = StoreRefDisp(rl_obj.reg, field_offset, rl_src.reg, field_info.IsVolatile() ? 871 kVolatile : kNotVolatile); 872 } else { 873 store = StoreBaseDisp(rl_obj.reg, field_offset, rl_src.reg, store_size, 874 field_info.IsVolatile() ? kVolatile : kNotVolatile); 875 } 876 MarkPossibleNullPointerExceptionAfter(opt_flags, store); 877 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 878 MarkGCCard(rl_src.reg, rl_obj.reg); 879 } 880 } else { 881 if (cu_->target64) { 882 GenIputCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 883 } else { 884 GenIputCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 885 } 886 } 887} 888 889template <size_t pointer_size> 890static void GenArrayObjPutCall(Mir2Lir* mir_to_lir, bool needs_range_check, bool needs_null_check, 891 RegLocation rl_array, RegLocation rl_index, RegLocation rl_src) { 892 ThreadOffset<pointer_size> helper = needs_range_check 893 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithNullAndBoundCheck) 894 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithBoundCheck)) 895 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObject); 896 mir_to_lir->CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, 897 true); 898} 899 900void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 901 RegLocation rl_src) { 902 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 903 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 904 (opt_flags & MIR_IGNORE_NULL_CHECK)); 905 if (cu_->target64) { 906 GenArrayObjPutCall<8>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 907 } else { 908 GenArrayObjPutCall<4>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 909 } 910} 911 912void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 913 RegLocation rl_method = LoadCurrMethod(); 914 CheckRegLocation(rl_method); 915 RegStorage res_reg = AllocTempRef(); 916 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 917 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 918 *cu_->dex_file, 919 type_idx)) { 920 // Call out to helper which resolves type and verifies access. 921 // Resolved type returned in kRet0. 922 if (cu_->target64) { 923 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 924 type_idx, rl_method.reg, true); 925 } else { 926 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 927 type_idx, rl_method.reg, true); 928 } 929 RegLocation rl_result = GetReturn(kRefReg); 930 StoreValue(rl_dest, rl_result); 931 } else { 932 // We're don't need access checks, load type from dex cache 933 int32_t dex_cache_offset = 934 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 935 LoadRefDisp(rl_method.reg, dex_cache_offset, res_reg, kNotVolatile); 936 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 937 LoadRefDisp(res_reg, offset_of_type, rl_result.reg, kNotVolatile); 938 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 939 type_idx) || SLOW_TYPE_PATH) { 940 // Slow path, at runtime test if type is null and if so initialize 941 FlushAllRegs(); 942 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg, 0, NULL); 943 LIR* cont = NewLIR0(kPseudoTargetLabel); 944 945 // Object to generate the slow path for class resolution. 946 class SlowPath : public LIRSlowPath { 947 public: 948 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 949 const RegLocation& rl_method, const RegLocation& rl_result) : 950 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 951 rl_method_(rl_method), rl_result_(rl_result) { 952 } 953 954 void Compile() { 955 GenerateTargetLabel(); 956 957 if (cu_->target64) { 958 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 959 rl_method_.reg, true); 960 } else { 961 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 962 rl_method_.reg, true); 963 } 964 m2l_->OpRegCopy(rl_result_.reg, m2l_->TargetReg(kRet0, kRef)); 965 966 m2l_->OpUnconditionalBranch(cont_); 967 } 968 969 private: 970 const int type_idx_; 971 const RegLocation rl_method_; 972 const RegLocation rl_result_; 973 }; 974 975 // Add to list for future. 976 AddSlowPath(new (arena_) SlowPath(this, branch, cont, type_idx, rl_method, rl_result)); 977 978 StoreValue(rl_dest, rl_result); 979 } else { 980 // Fast path, we're done - just store result 981 StoreValue(rl_dest, rl_result); 982 } 983 } 984} 985 986void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 987 /* NOTE: Most strings should be available at compile time */ 988 int32_t offset_of_string = mirror::ObjectArray<mirror::String>::OffsetOfElement(string_idx). 989 Int32Value(); 990 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 991 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 992 // slow path, resolve string if not in dex cache 993 FlushAllRegs(); 994 LockCallTemps(); // Using explicit registers 995 996 // If the Method* is already in a register, we can save a copy. 997 RegLocation rl_method = mir_graph_->GetMethodLoc(); 998 RegStorage r_method; 999 if (rl_method.location == kLocPhysReg) { 1000 // A temp would conflict with register use below. 1001 DCHECK(!IsTemp(rl_method.reg)); 1002 r_method = rl_method.reg; 1003 } else { 1004 r_method = TargetReg(kArg2, kRef); 1005 LoadCurrMethodDirect(r_method); 1006 } 1007 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 1008 TargetReg(kArg0, kRef), kNotVolatile); 1009 1010 // Might call out to helper, which will return resolved string in kRet0 1011 LoadRefDisp(TargetReg(kArg0, kRef), offset_of_string, TargetReg(kRet0, kRef), kNotVolatile); 1012 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0, kRef), 0, NULL); 1013 LIR* cont = NewLIR0(kPseudoTargetLabel); 1014 1015 { 1016 // Object to generate the slow path for string resolution. 1017 class SlowPath : public LIRSlowPath { 1018 public: 1019 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, RegStorage r_method, int32_t string_idx) : 1020 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), 1021 r_method_(r_method), string_idx_(string_idx) { 1022 } 1023 1024 void Compile() { 1025 GenerateTargetLabel(); 1026 if (cu_->target64) { 1027 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pResolveString), 1028 r_method_, string_idx_, true); 1029 } else { 1030 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pResolveString), 1031 r_method_, string_idx_, true); 1032 } 1033 m2l_->OpUnconditionalBranch(cont_); 1034 } 1035 1036 private: 1037 const RegStorage r_method_; 1038 const int32_t string_idx_; 1039 }; 1040 1041 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method, string_idx)); 1042 } 1043 1044 GenBarrier(); 1045 StoreValue(rl_dest, GetReturn(kRefReg)); 1046 } else { 1047 RegLocation rl_method = LoadCurrMethod(); 1048 RegStorage res_reg = AllocTempRef(); 1049 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1050 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg, 1051 kNotVolatile); 1052 LoadRefDisp(res_reg, offset_of_string, rl_result.reg, kNotVolatile); 1053 StoreValue(rl_dest, rl_result); 1054 } 1055} 1056 1057template <size_t pointer_size> 1058static void GenNewInstanceImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, uint32_t type_idx, 1059 RegLocation rl_dest) { 1060 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 1061 // alloc will always check for resolution, do we also need to verify 1062 // access because the verifier was unable to? 1063 ThreadOffset<pointer_size> func_offset(-1); 1064 const DexFile* dex_file = cu->dex_file; 1065 CompilerDriver* driver = cu->compiler_driver; 1066 if (driver->CanAccessInstantiableTypeWithoutChecks( 1067 cu->method_idx, *dex_file, type_idx)) { 1068 bool is_type_initialized; 1069 bool use_direct_type_ptr; 1070 uintptr_t direct_type_ptr; 1071 bool is_finalizable; 1072 if (kEmbedClassInCode && 1073 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 1074 &direct_type_ptr, &is_finalizable) && 1075 !is_finalizable) { 1076 // The fast path. 1077 if (!use_direct_type_ptr) { 1078 mir_to_lir->LoadClassType(type_idx, kArg0); 1079 if (!is_type_initialized) { 1080 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1081 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1082 true); 1083 } else { 1084 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1085 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1086 true); 1087 } 1088 } else { 1089 // Use the direct pointer. 1090 if (!is_type_initialized) { 1091 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1092 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1093 } else { 1094 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1095 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1096 } 1097 } 1098 } else { 1099 // The slow path. 1100 DCHECK_EQ(func_offset.Int32Value(), -1); 1101 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObject); 1102 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1103 } 1104 DCHECK_NE(func_offset.Int32Value(), -1); 1105 } else { 1106 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectWithAccessCheck); 1107 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1108 } 1109 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 1110 mir_to_lir->StoreValue(rl_dest, rl_result); 1111} 1112 1113/* 1114 * Let helper function take care of everything. Will 1115 * call Class::NewInstanceFromCode(type_idx, method); 1116 */ 1117void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 1118 if (cu_->target64) { 1119 GenNewInstanceImpl<8>(this, cu_, type_idx, rl_dest); 1120 } else { 1121 GenNewInstanceImpl<4>(this, cu_, type_idx, rl_dest); 1122 } 1123} 1124 1125void Mir2Lir::GenThrow(RegLocation rl_src) { 1126 FlushAllRegs(); 1127 if (cu_->target64) { 1128 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), rl_src, true); 1129 } else { 1130 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException), rl_src, true); 1131 } 1132} 1133 1134// For final classes there are no sub-classes to check and so we can answer the instance-of 1135// question with simple comparisons. 1136void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1137 RegLocation rl_src) { 1138 // X86 has its own implementation. 1139 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1140 1141 RegLocation object = LoadValue(rl_src, kRefReg); 1142 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1143 RegStorage result_reg = rl_result.reg; 1144 if (IsSameReg(result_reg, object.reg)) { 1145 result_reg = AllocTypedTemp(false, kCoreReg); 1146 DCHECK(!IsSameReg(result_reg, object.reg)); 1147 } 1148 LoadConstant(result_reg, 0); // assume false 1149 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 1150 1151 RegStorage check_class = AllocTypedTemp(false, kRefReg); 1152 RegStorage object_class = AllocTypedTemp(false, kRefReg); 1153 1154 LoadCurrMethodDirect(check_class); 1155 if (use_declaring_class) { 1156 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), check_class, 1157 kNotVolatile); 1158 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1159 kNotVolatile); 1160 } else { 1161 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1162 check_class, kNotVolatile); 1163 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1164 kNotVolatile); 1165 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1166 LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); 1167 } 1168 1169 // FIXME: what should we be comparing here? compressed or decompressed references? 1170 if (cu_->instruction_set == kThumb2) { 1171 OpRegReg(kOpCmp, check_class, object_class); // Same? 1172 LIR* it = OpIT(kCondEq, ""); // if-convert the test 1173 LoadConstant(result_reg, 1); // .eq case - load true 1174 OpEndIT(it); 1175 } else { 1176 GenSelectConst32(check_class, object_class, kCondEq, 1, 0, result_reg, kCoreReg); 1177 } 1178 LIR* target = NewLIR0(kPseudoTargetLabel); 1179 null_branchover->target = target; 1180 FreeTemp(object_class); 1181 FreeTemp(check_class); 1182 if (IsTemp(result_reg)) { 1183 OpRegCopy(rl_result.reg, result_reg); 1184 FreeTemp(result_reg); 1185 } 1186 StoreValue(rl_dest, rl_result); 1187} 1188 1189void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1190 bool type_known_abstract, bool use_declaring_class, 1191 bool can_assume_type_is_in_dex_cache, 1192 uint32_t type_idx, RegLocation rl_dest, 1193 RegLocation rl_src) { 1194 FlushAllRegs(); 1195 // May generate a call - use explicit registers 1196 LockCallTemps(); 1197 RegStorage method_reg = TargetReg(kArg1, kRef); 1198 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1199 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1200 RegStorage ref_reg = TargetReg(kArg0, kRef); // kArg0 will hold the ref. 1201 RegStorage ret_reg = GetReturn(kRefReg).reg; 1202 if (needs_access_check) { 1203 // Check we have access to type_idx and if not throw IllegalAccessError, 1204 // returns Class* in kArg0 1205 if (cu_->target64) { 1206 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1207 type_idx, true); 1208 } else { 1209 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1210 type_idx, true); 1211 } 1212 OpRegCopy(class_reg, ret_reg); // Align usage with fast path 1213 LoadValueDirectFixed(rl_src, ref_reg); // kArg0 <= ref 1214 } else if (use_declaring_class) { 1215 LoadValueDirectFixed(rl_src, ref_reg); // kArg0 <= ref 1216 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1217 class_reg, kNotVolatile); 1218 } else { 1219 if (can_assume_type_is_in_dex_cache) { 1220 // Conditionally, as in the other case we will also load it. 1221 LoadValueDirectFixed(rl_src, ref_reg); // kArg0 <= ref 1222 } 1223 1224 // Load dex cache entry into class_reg (kArg2) 1225 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1226 class_reg, kNotVolatile); 1227 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1228 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1229 if (!can_assume_type_is_in_dex_cache) { 1230 LIR* slow_path_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1231 LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); 1232 1233 // Should load value here. 1234 LoadValueDirectFixed(rl_src, ref_reg); // kArg0 <= ref 1235 1236 class InitTypeSlowPath : public Mir2Lir::LIRSlowPath { 1237 public: 1238 InitTypeSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont, uint32_t type_idx, 1239 RegLocation rl_src) 1240 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont), type_idx_(type_idx), 1241 rl_src_(rl_src) { 1242 } 1243 1244 void Compile() OVERRIDE { 1245 GenerateTargetLabel(); 1246 1247 if (cu_->target64) { 1248 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1249 true); 1250 } else { 1251 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1252 true); 1253 } 1254 m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kRef), 1255 m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1256 1257 m2l_->OpUnconditionalBranch(cont_); 1258 } 1259 1260 private: 1261 uint32_t type_idx_; 1262 RegLocation rl_src_; 1263 }; 1264 1265 AddSlowPath(new (arena_) InitTypeSlowPath(this, slow_path_branch, slow_path_target, 1266 type_idx, rl_src)); 1267 } 1268 } 1269 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1270 RegLocation rl_result = GetReturn(kCoreReg); 1271 if (!IsSameReg(rl_result.reg, ref_reg)) { 1272 // On MIPS and x86_64 rArg0 != rl_result, place false in result if branch is taken. 1273 LoadConstant(rl_result.reg, 0); 1274 } 1275 LIR* branch1 = OpCmpImmBranch(kCondEq, ref_reg, 0, NULL); 1276 1277 /* load object->klass_ */ 1278 RegStorage ref_class_reg = TargetReg(kArg1, kRef); // kArg1 will hold the Class* of ref. 1279 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1280 LoadRefDisp(ref_reg, mirror::Object::ClassOffset().Int32Value(), 1281 ref_class_reg, kNotVolatile); 1282 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1283 LIR* branchover = NULL; 1284 if (type_known_final) { 1285 // rl_result == ref == class. 1286 GenSelectConst32(ref_class_reg, class_reg, kCondEq, 1, 0, rl_result.reg, 1287 kCoreReg); 1288 } else { 1289 if (cu_->instruction_set == kThumb2) { 1290 RegStorage r_tgt = cu_->target64 ? 1291 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1292 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1293 LIR* it = nullptr; 1294 if (!type_known_abstract) { 1295 /* Uses conditional nullification */ 1296 OpRegReg(kOpCmp, ref_class_reg, class_reg); // Same? 1297 it = OpIT(kCondEq, "EE"); // if-convert the test 1298 LoadConstant(rl_result.reg, 1); // .eq case - load true 1299 } 1300 OpRegCopy(ref_reg, class_reg); // .ne case - arg0 <= class 1301 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1302 if (it != nullptr) { 1303 OpEndIT(it); 1304 } 1305 FreeTemp(r_tgt); 1306 } else { 1307 if (!type_known_abstract) { 1308 /* Uses branchovers */ 1309 LoadConstant(rl_result.reg, 1); // assume true 1310 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1311 } 1312 1313 OpRegCopy(TargetReg(kArg0, kRef), class_reg); // .ne case - arg0 <= class 1314 if (cu_->target64) { 1315 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial), false); 1316 } else { 1317 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial), false); 1318 } 1319 } 1320 } 1321 // TODO: only clobber when type isn't final? 1322 ClobberCallerSave(); 1323 /* branch targets here */ 1324 LIR* target = NewLIR0(kPseudoTargetLabel); 1325 StoreValue(rl_dest, rl_result); 1326 branch1->target = target; 1327 if (branchover != NULL) { 1328 branchover->target = target; 1329 } 1330} 1331 1332void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1333 bool type_known_final, type_known_abstract, use_declaring_class; 1334 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1335 *cu_->dex_file, 1336 type_idx, 1337 &type_known_final, 1338 &type_known_abstract, 1339 &use_declaring_class); 1340 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1341 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1342 1343 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1344 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1345 } else { 1346 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1347 use_declaring_class, can_assume_type_is_in_dex_cache, 1348 type_idx, rl_dest, rl_src); 1349 } 1350} 1351 1352void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1353 bool type_known_final, type_known_abstract, use_declaring_class; 1354 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1355 *cu_->dex_file, 1356 type_idx, 1357 &type_known_final, 1358 &type_known_abstract, 1359 &use_declaring_class); 1360 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1361 // of the exception throw path. 1362 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1363 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1364 // Verifier type analysis proved this check cast would never cause an exception. 1365 return; 1366 } 1367 FlushAllRegs(); 1368 // May generate a call - use explicit registers 1369 LockCallTemps(); 1370 RegStorage method_reg = TargetReg(kArg1, kRef); 1371 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1372 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1373 if (needs_access_check) { 1374 // Check we have access to type_idx and if not throw IllegalAccessError, 1375 // returns Class* in kRet0 1376 // InitializeTypeAndVerifyAccess(idx, method) 1377 if (cu_->target64) { 1378 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1379 type_idx, true); 1380 } else { 1381 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1382 type_idx, true); 1383 } 1384 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1385 } else if (use_declaring_class) { 1386 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1387 class_reg, kNotVolatile); 1388 } else { 1389 // Load dex cache entry into class_reg (kArg2) 1390 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1391 class_reg, kNotVolatile); 1392 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1393 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1394 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1395 // Need to test presence of type in dex cache at runtime 1396 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1397 LIR* cont = NewLIR0(kPseudoTargetLabel); 1398 1399 // Slow path to initialize the type. Executed if the type is NULL. 1400 class SlowPath : public LIRSlowPath { 1401 public: 1402 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1403 const RegStorage class_reg) : 1404 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1405 class_reg_(class_reg) { 1406 } 1407 1408 void Compile() { 1409 GenerateTargetLabel(); 1410 1411 // Call out to helper, which will return resolved type in kArg0 1412 // InitializeTypeFromCode(idx, method) 1413 if (m2l_->cu_->target64) { 1414 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1415 m2l_->TargetReg(kArg1, kRef), true); 1416 } else { 1417 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1418 m2l_->TargetReg(kArg1, kRef), true); 1419 } 1420 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1421 m2l_->OpUnconditionalBranch(cont_); 1422 } 1423 1424 public: 1425 const int type_idx_; 1426 const RegStorage class_reg_; 1427 }; 1428 1429 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, type_idx, class_reg)); 1430 } 1431 } 1432 // At this point, class_reg (kArg2) has class 1433 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1434 1435 // Slow path for the case where the classes are not equal. In this case we need 1436 // to call a helper function to do the check. 1437 class SlowPath : public LIRSlowPath { 1438 public: 1439 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1440 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1441 } 1442 1443 void Compile() { 1444 GenerateTargetLabel(); 1445 1446 if (load_) { 1447 m2l_->LoadRefDisp(m2l_->TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1448 m2l_->TargetReg(kArg1, kRef), kNotVolatile); 1449 } 1450 if (m2l_->cu_->target64) { 1451 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pCheckCast), 1452 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1453 true); 1454 } else { 1455 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pCheckCast), 1456 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1457 true); 1458 } 1459 1460 m2l_->OpUnconditionalBranch(cont_); 1461 } 1462 1463 private: 1464 const bool load_; 1465 }; 1466 1467 if (type_known_abstract) { 1468 // Easier case, run slow path if target is non-null (slow path will load from target) 1469 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0, kRef), 0, nullptr); 1470 LIR* cont = NewLIR0(kPseudoTargetLabel); 1471 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1472 } else { 1473 // Harder, more common case. We need to generate a forward branch over the load 1474 // if the target is null. If it's non-null we perform the load and branch to the 1475 // slow path if the classes are not equal. 1476 1477 /* Null is OK - continue */ 1478 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, nullptr); 1479 /* load object->klass_ */ 1480 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1481 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1482 TargetReg(kArg1, kRef), kNotVolatile); 1483 1484 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), class_reg, nullptr); 1485 LIR* cont = NewLIR0(kPseudoTargetLabel); 1486 1487 // Add the slow path that will not perform load since this is already done. 1488 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1489 1490 // Set the null check to branch to the continuation. 1491 branch1->target = cont; 1492 } 1493} 1494 1495void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1496 RegLocation rl_src1, RegLocation rl_src2) { 1497 RegLocation rl_result; 1498 if (cu_->instruction_set == kThumb2) { 1499 /* 1500 * NOTE: This is the one place in the code in which we might have 1501 * as many as six live temporary registers. There are 5 in the normal 1502 * set for Arm. Until we have spill capabilities, temporarily add 1503 * lr to the temp set. It is safe to do this locally, but note that 1504 * lr is used explicitly elsewhere in the code generator and cannot 1505 * normally be used as a general temp register. 1506 */ 1507 MarkTemp(TargetReg(kLr, kNotWide)); // Add lr to the temp pool 1508 FreeTemp(TargetReg(kLr, kNotWide)); // and make it available 1509 } 1510 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1511 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1512 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1513 // The longs may overlap - use intermediate temp if so 1514 if ((rl_result.reg.GetLowReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg())) { 1515 RegStorage t_reg = AllocTemp(); 1516 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1517 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1518 OpRegCopy(rl_result.reg.GetLow(), t_reg); 1519 FreeTemp(t_reg); 1520 } else { 1521 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1522 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1523 } 1524 /* 1525 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1526 * following StoreValueWide might need to allocate a temp register. 1527 * To further work around the lack of a spill capability, explicitly 1528 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1529 * Remove when spill is functional. 1530 */ 1531 FreeRegLocTemps(rl_result, rl_src1); 1532 FreeRegLocTemps(rl_result, rl_src2); 1533 StoreValueWide(rl_dest, rl_result); 1534 if (cu_->instruction_set == kThumb2) { 1535 Clobber(TargetReg(kLr, kNotWide)); 1536 UnmarkTemp(TargetReg(kLr, kNotWide)); // Remove lr from the temp pool 1537 } 1538} 1539 1540 1541template <size_t pointer_size> 1542static void GenShiftOpLongCall(Mir2Lir* mir_to_lir, Instruction::Code opcode, RegLocation rl_src1, 1543 RegLocation rl_shift) { 1544 ThreadOffset<pointer_size> func_offset(-1); 1545 1546 switch (opcode) { 1547 case Instruction::SHL_LONG: 1548 case Instruction::SHL_LONG_2ADDR: 1549 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShlLong); 1550 break; 1551 case Instruction::SHR_LONG: 1552 case Instruction::SHR_LONG_2ADDR: 1553 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShrLong); 1554 break; 1555 case Instruction::USHR_LONG: 1556 case Instruction::USHR_LONG_2ADDR: 1557 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pUshrLong); 1558 break; 1559 default: 1560 LOG(FATAL) << "Unexpected case"; 1561 } 1562 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 1563 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1564} 1565 1566void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1567 RegLocation rl_src1, RegLocation rl_shift) { 1568 if (cu_->target64) { 1569 GenShiftOpLongCall<8>(this, opcode, rl_src1, rl_shift); 1570 } else { 1571 GenShiftOpLongCall<4>(this, opcode, rl_src1, rl_shift); 1572 } 1573 RegLocation rl_result = GetReturnWide(kCoreReg); 1574 StoreValueWide(rl_dest, rl_result); 1575} 1576 1577 1578void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1579 RegLocation rl_src1, RegLocation rl_src2) { 1580 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1581 OpKind op = kOpBkpt; 1582 bool is_div_rem = false; 1583 bool check_zero = false; 1584 bool unary = false; 1585 RegLocation rl_result; 1586 bool shift_op = false; 1587 switch (opcode) { 1588 case Instruction::NEG_INT: 1589 op = kOpNeg; 1590 unary = true; 1591 break; 1592 case Instruction::NOT_INT: 1593 op = kOpMvn; 1594 unary = true; 1595 break; 1596 case Instruction::ADD_INT: 1597 case Instruction::ADD_INT_2ADDR: 1598 op = kOpAdd; 1599 break; 1600 case Instruction::SUB_INT: 1601 case Instruction::SUB_INT_2ADDR: 1602 op = kOpSub; 1603 break; 1604 case Instruction::MUL_INT: 1605 case Instruction::MUL_INT_2ADDR: 1606 op = kOpMul; 1607 break; 1608 case Instruction::DIV_INT: 1609 case Instruction::DIV_INT_2ADDR: 1610 check_zero = true; 1611 op = kOpDiv; 1612 is_div_rem = true; 1613 break; 1614 /* NOTE: returns in kArg1 */ 1615 case Instruction::REM_INT: 1616 case Instruction::REM_INT_2ADDR: 1617 check_zero = true; 1618 op = kOpRem; 1619 is_div_rem = true; 1620 break; 1621 case Instruction::AND_INT: 1622 case Instruction::AND_INT_2ADDR: 1623 op = kOpAnd; 1624 break; 1625 case Instruction::OR_INT: 1626 case Instruction::OR_INT_2ADDR: 1627 op = kOpOr; 1628 break; 1629 case Instruction::XOR_INT: 1630 case Instruction::XOR_INT_2ADDR: 1631 op = kOpXor; 1632 break; 1633 case Instruction::SHL_INT: 1634 case Instruction::SHL_INT_2ADDR: 1635 shift_op = true; 1636 op = kOpLsl; 1637 break; 1638 case Instruction::SHR_INT: 1639 case Instruction::SHR_INT_2ADDR: 1640 shift_op = true; 1641 op = kOpAsr; 1642 break; 1643 case Instruction::USHR_INT: 1644 case Instruction::USHR_INT_2ADDR: 1645 shift_op = true; 1646 op = kOpLsr; 1647 break; 1648 default: 1649 LOG(FATAL) << "Invalid word arith op: " << opcode; 1650 } 1651 if (!is_div_rem) { 1652 if (unary) { 1653 rl_src1 = LoadValue(rl_src1, kCoreReg); 1654 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1655 OpRegReg(op, rl_result.reg, rl_src1.reg); 1656 } else { 1657 if ((shift_op) && (cu_->instruction_set != kArm64)) { 1658 rl_src2 = LoadValue(rl_src2, kCoreReg); 1659 RegStorage t_reg = AllocTemp(); 1660 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg, 31); 1661 rl_src1 = LoadValue(rl_src1, kCoreReg); 1662 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1663 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 1664 FreeTemp(t_reg); 1665 } else { 1666 rl_src1 = LoadValue(rl_src1, kCoreReg); 1667 rl_src2 = LoadValue(rl_src2, kCoreReg); 1668 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1669 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); 1670 } 1671 } 1672 StoreValue(rl_dest, rl_result); 1673 } else { 1674 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1675 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1676 rl_src1 = LoadValue(rl_src1, kCoreReg); 1677 rl_src2 = LoadValue(rl_src2, kCoreReg); 1678 if (check_zero) { 1679 GenDivZeroCheck(rl_src2.reg); 1680 } 1681 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1682 done = true; 1683 } else if (cu_->instruction_set == kThumb2) { 1684 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1685 // Use ARM SDIV instruction for division. For remainder we also need to 1686 // calculate using a MUL and subtract. 1687 rl_src1 = LoadValue(rl_src1, kCoreReg); 1688 rl_src2 = LoadValue(rl_src2, kCoreReg); 1689 if (check_zero) { 1690 GenDivZeroCheck(rl_src2.reg); 1691 } 1692 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1693 done = true; 1694 } 1695 } 1696 1697 // If we haven't already generated the code use the callout function. 1698 if (!done) { 1699 FlushAllRegs(); /* Send everything to home location */ 1700 LoadValueDirectFixed(rl_src2, TargetReg(kArg1, kNotWide)); 1701 RegStorage r_tgt = cu_->target64 ? 1702 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod)) : 1703 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod)); 1704 LoadValueDirectFixed(rl_src1, TargetReg(kArg0, kNotWide)); 1705 if (check_zero) { 1706 GenDivZeroCheck(TargetReg(kArg1, kNotWide)); 1707 } 1708 // NOTE: callout here is not a safepoint. 1709 if (cu_->target64) { 1710 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), false /* not a safepoint */); 1711 } else { 1712 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), false /* not a safepoint */); 1713 } 1714 if (op == kOpDiv) 1715 rl_result = GetReturn(kCoreReg); 1716 else 1717 rl_result = GetReturnAlt(); 1718 } 1719 StoreValue(rl_dest, rl_result); 1720 } 1721} 1722 1723/* 1724 * The following are the first-level codegen routines that analyze the format 1725 * of each bytecode then either dispatch special purpose codegen routines 1726 * or produce corresponding Thumb instructions directly. 1727 */ 1728 1729// Returns true if no more than two bits are set in 'x'. 1730static bool IsPopCountLE2(unsigned int x) { 1731 x &= x - 1; 1732 return (x & (x - 1)) == 0; 1733} 1734 1735// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1736// and store the result in 'rl_dest'. 1737bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1738 RegLocation rl_src, RegLocation rl_dest, int lit) { 1739 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1740 return false; 1741 } 1742 // No divide instruction for Arm, so check for more special cases 1743 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1744 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1745 } 1746 int k = LowestSetBit(lit); 1747 if (k >= 30) { 1748 // Avoid special cases. 1749 return false; 1750 } 1751 rl_src = LoadValue(rl_src, kCoreReg); 1752 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1753 if (is_div) { 1754 RegStorage t_reg = AllocTemp(); 1755 if (lit == 2) { 1756 // Division by 2 is by far the most common division by constant. 1757 OpRegRegImm(kOpLsr, t_reg, rl_src.reg, 32 - k); 1758 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1759 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1760 } else { 1761 OpRegRegImm(kOpAsr, t_reg, rl_src.reg, 31); 1762 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1763 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1764 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1765 } 1766 } else { 1767 RegStorage t_reg1 = AllocTemp(); 1768 RegStorage t_reg2 = AllocTemp(); 1769 if (lit == 2) { 1770 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg, 32 - k); 1771 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1772 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1773 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1774 } else { 1775 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg, 31); 1776 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1777 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1778 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1779 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1780 } 1781 } 1782 StoreValue(rl_dest, rl_result); 1783 return true; 1784} 1785 1786// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1787// and store the result in 'rl_dest'. 1788bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1789 if (lit < 0) { 1790 return false; 1791 } 1792 if (lit == 0) { 1793 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1794 LoadConstant(rl_result.reg, 0); 1795 StoreValue(rl_dest, rl_result); 1796 return true; 1797 } 1798 if (lit == 1) { 1799 rl_src = LoadValue(rl_src, kCoreReg); 1800 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1801 OpRegCopy(rl_result.reg, rl_src.reg); 1802 StoreValue(rl_dest, rl_result); 1803 return true; 1804 } 1805 // There is RegRegRegShift on Arm, so check for more special cases 1806 if (cu_->instruction_set == kThumb2) { 1807 return EasyMultiply(rl_src, rl_dest, lit); 1808 } 1809 // Can we simplify this multiplication? 1810 bool power_of_two = false; 1811 bool pop_count_le2 = false; 1812 bool power_of_two_minus_one = false; 1813 if (IsPowerOfTwo(lit)) { 1814 power_of_two = true; 1815 } else if (IsPopCountLE2(lit)) { 1816 pop_count_le2 = true; 1817 } else if (IsPowerOfTwo(lit + 1)) { 1818 power_of_two_minus_one = true; 1819 } else { 1820 return false; 1821 } 1822 rl_src = LoadValue(rl_src, kCoreReg); 1823 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1824 if (power_of_two) { 1825 // Shift. 1826 OpRegRegImm(kOpLsl, rl_result.reg, rl_src.reg, LowestSetBit(lit)); 1827 } else if (pop_count_le2) { 1828 // Shift and add and shift. 1829 int first_bit = LowestSetBit(lit); 1830 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1831 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1832 } else { 1833 // Reverse subtract: (src << (shift + 1)) - src. 1834 DCHECK(power_of_two_minus_one); 1835 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1836 RegStorage t_reg = AllocTemp(); 1837 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, LowestSetBit(lit + 1)); 1838 OpRegRegReg(kOpSub, rl_result.reg, t_reg, rl_src.reg); 1839 } 1840 StoreValue(rl_dest, rl_result); 1841 return true; 1842} 1843 1844void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1845 int lit) { 1846 RegLocation rl_result; 1847 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1848 int shift_op = false; 1849 bool is_div = false; 1850 1851 switch (opcode) { 1852 case Instruction::RSUB_INT_LIT8: 1853 case Instruction::RSUB_INT: { 1854 rl_src = LoadValue(rl_src, kCoreReg); 1855 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1856 if (cu_->instruction_set == kThumb2) { 1857 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, lit); 1858 } else { 1859 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1860 OpRegImm(kOpAdd, rl_result.reg, lit); 1861 } 1862 StoreValue(rl_dest, rl_result); 1863 return; 1864 } 1865 1866 case Instruction::SUB_INT: 1867 case Instruction::SUB_INT_2ADDR: 1868 lit = -lit; 1869 // Intended fallthrough 1870 case Instruction::ADD_INT: 1871 case Instruction::ADD_INT_2ADDR: 1872 case Instruction::ADD_INT_LIT8: 1873 case Instruction::ADD_INT_LIT16: 1874 op = kOpAdd; 1875 break; 1876 case Instruction::MUL_INT: 1877 case Instruction::MUL_INT_2ADDR: 1878 case Instruction::MUL_INT_LIT8: 1879 case Instruction::MUL_INT_LIT16: { 1880 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1881 return; 1882 } 1883 op = kOpMul; 1884 break; 1885 } 1886 case Instruction::AND_INT: 1887 case Instruction::AND_INT_2ADDR: 1888 case Instruction::AND_INT_LIT8: 1889 case Instruction::AND_INT_LIT16: 1890 op = kOpAnd; 1891 break; 1892 case Instruction::OR_INT: 1893 case Instruction::OR_INT_2ADDR: 1894 case Instruction::OR_INT_LIT8: 1895 case Instruction::OR_INT_LIT16: 1896 op = kOpOr; 1897 break; 1898 case Instruction::XOR_INT: 1899 case Instruction::XOR_INT_2ADDR: 1900 case Instruction::XOR_INT_LIT8: 1901 case Instruction::XOR_INT_LIT16: 1902 op = kOpXor; 1903 break; 1904 case Instruction::SHL_INT_LIT8: 1905 case Instruction::SHL_INT: 1906 case Instruction::SHL_INT_2ADDR: 1907 lit &= 31; 1908 shift_op = true; 1909 op = kOpLsl; 1910 break; 1911 case Instruction::SHR_INT_LIT8: 1912 case Instruction::SHR_INT: 1913 case Instruction::SHR_INT_2ADDR: 1914 lit &= 31; 1915 shift_op = true; 1916 op = kOpAsr; 1917 break; 1918 case Instruction::USHR_INT_LIT8: 1919 case Instruction::USHR_INT: 1920 case Instruction::USHR_INT_2ADDR: 1921 lit &= 31; 1922 shift_op = true; 1923 op = kOpLsr; 1924 break; 1925 1926 case Instruction::DIV_INT: 1927 case Instruction::DIV_INT_2ADDR: 1928 case Instruction::DIV_INT_LIT8: 1929 case Instruction::DIV_INT_LIT16: 1930 case Instruction::REM_INT: 1931 case Instruction::REM_INT_2ADDR: 1932 case Instruction::REM_INT_LIT8: 1933 case Instruction::REM_INT_LIT16: { 1934 if (lit == 0) { 1935 GenDivZeroException(); 1936 return; 1937 } 1938 if ((opcode == Instruction::DIV_INT) || 1939 (opcode == Instruction::DIV_INT_2ADDR) || 1940 (opcode == Instruction::DIV_INT_LIT8) || 1941 (opcode == Instruction::DIV_INT_LIT16)) { 1942 is_div = true; 1943 } else { 1944 is_div = false; 1945 } 1946 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1947 return; 1948 } 1949 1950 bool done = false; 1951 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1952 rl_src = LoadValue(rl_src, kCoreReg); 1953 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1954 done = true; 1955 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1956 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1957 done = true; 1958 } else if (cu_->instruction_set == kThumb2) { 1959 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1960 // Use ARM SDIV instruction for division. For remainder we also need to 1961 // calculate using a MUL and subtract. 1962 rl_src = LoadValue(rl_src, kCoreReg); 1963 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1964 done = true; 1965 } 1966 } 1967 1968 if (!done) { 1969 FlushAllRegs(); /* Everything to home location. */ 1970 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kNotWide)); 1971 Clobber(TargetReg(kArg0, kNotWide)); 1972 if (cu_->target64) { 1973 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), TargetReg(kArg0, kNotWide), 1974 lit, false); 1975 } else { 1976 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), TargetReg(kArg0, kNotWide), 1977 lit, false); 1978 } 1979 if (is_div) 1980 rl_result = GetReturn(kCoreReg); 1981 else 1982 rl_result = GetReturnAlt(); 1983 } 1984 StoreValue(rl_dest, rl_result); 1985 return; 1986 } 1987 default: 1988 LOG(FATAL) << "Unexpected opcode " << opcode; 1989 } 1990 rl_src = LoadValue(rl_src, kCoreReg); 1991 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1992 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 1993 if (shift_op && (lit == 0)) { 1994 OpRegCopy(rl_result.reg, rl_src.reg); 1995 } else { 1996 OpRegRegImm(op, rl_result.reg, rl_src.reg, lit); 1997 } 1998 StoreValue(rl_dest, rl_result); 1999} 2000 2001template <size_t pointer_size> 2002static void GenArithOpLongImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, Instruction::Code opcode, 2003 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 2004 RegLocation rl_result; 2005 OpKind first_op = kOpBkpt; 2006 OpKind second_op = kOpBkpt; 2007 bool call_out = false; 2008 bool check_zero = false; 2009 ThreadOffset<pointer_size> func_offset(-1); 2010 int ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2011 2012 switch (opcode) { 2013 case Instruction::NOT_LONG: 2014 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2015 mir_to_lir->GenNotLong(rl_dest, rl_src2); 2016 return; 2017 } 2018 rl_src2 = mir_to_lir->LoadValueWide(rl_src2, kCoreReg); 2019 rl_result = mir_to_lir->EvalLoc(rl_dest, kCoreReg, true); 2020 // Check for destructive overlap 2021 if (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg()) { 2022 RegStorage t_reg = mir_to_lir->AllocTemp(); 2023 mir_to_lir->OpRegCopy(t_reg, rl_src2.reg.GetHigh()); 2024 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2025 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), t_reg); 2026 mir_to_lir->FreeTemp(t_reg); 2027 } else { 2028 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2029 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); 2030 } 2031 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2032 return; 2033 case Instruction::ADD_LONG: 2034 case Instruction::ADD_LONG_2ADDR: 2035 if (cu->instruction_set != kThumb2) { 2036 mir_to_lir->GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 2037 return; 2038 } 2039 first_op = kOpAdd; 2040 second_op = kOpAdc; 2041 break; 2042 case Instruction::SUB_LONG: 2043 case Instruction::SUB_LONG_2ADDR: 2044 if (cu->instruction_set != kThumb2) { 2045 mir_to_lir->GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 2046 return; 2047 } 2048 first_op = kOpSub; 2049 second_op = kOpSbc; 2050 break; 2051 case Instruction::MUL_LONG: 2052 case Instruction::MUL_LONG_2ADDR: 2053 if (cu->instruction_set != kMips) { 2054 mir_to_lir->GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 2055 return; 2056 } else { 2057 call_out = true; 2058 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2059 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmul); 2060 } 2061 break; 2062 case Instruction::DIV_LONG: 2063 case Instruction::DIV_LONG_2ADDR: 2064 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2065 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); 2066 return; 2067 } 2068 call_out = true; 2069 check_zero = true; 2070 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2071 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLdiv); 2072 break; 2073 case Instruction::REM_LONG: 2074 case Instruction::REM_LONG_2ADDR: 2075 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2076 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); 2077 return; 2078 } 2079 call_out = true; 2080 check_zero = true; 2081 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmod); 2082 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 2083 ret_reg = (cu->instruction_set == kThumb2) ? mir_to_lir->TargetReg(kArg2, kNotWide).GetReg() : 2084 mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2085 break; 2086 case Instruction::AND_LONG_2ADDR: 2087 case Instruction::AND_LONG: 2088 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2089 cu->instruction_set == kArm64) { 2090 return mir_to_lir->GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 2091 } 2092 first_op = kOpAnd; 2093 second_op = kOpAnd; 2094 break; 2095 case Instruction::OR_LONG: 2096 case Instruction::OR_LONG_2ADDR: 2097 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2098 cu->instruction_set == kArm64) { 2099 mir_to_lir->GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 2100 return; 2101 } 2102 first_op = kOpOr; 2103 second_op = kOpOr; 2104 break; 2105 case Instruction::XOR_LONG: 2106 case Instruction::XOR_LONG_2ADDR: 2107 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2108 cu->instruction_set == kArm64) { 2109 mir_to_lir->GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 2110 return; 2111 } 2112 first_op = kOpXor; 2113 second_op = kOpXor; 2114 break; 2115 case Instruction::NEG_LONG: { 2116 mir_to_lir->GenNegLong(rl_dest, rl_src2); 2117 return; 2118 } 2119 default: 2120 LOG(FATAL) << "Invalid long arith op"; 2121 } 2122 if (!call_out) { 2123 mir_to_lir->GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 2124 } else { 2125 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 2126 if (check_zero) { 2127 RegStorage r_tmp1 = mir_to_lir->TargetReg(kArg0, kWide); 2128 RegStorage r_tmp2 = mir_to_lir->TargetReg(kArg2, kWide); 2129 mir_to_lir->LoadValueDirectWideFixed(rl_src2, r_tmp2); 2130 RegStorage r_tgt = mir_to_lir->CallHelperSetup(func_offset); 2131 mir_to_lir->GenDivZeroCheckWide(r_tmp2); 2132 mir_to_lir->LoadValueDirectWideFixed(rl_src1, r_tmp1); 2133 // NOTE: callout here is not a safepoint 2134 mir_to_lir->CallHelper(r_tgt, func_offset, false /* not safepoint */); 2135 } else { 2136 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 2137 } 2138 // Adjust return regs in to handle case of rem returning kArg2/kArg3 2139 if (ret_reg == mir_to_lir->TargetReg(kRet0, kNotWide).GetReg()) 2140 rl_result = mir_to_lir->GetReturnWide(kCoreReg); 2141 else 2142 rl_result = mir_to_lir->GetReturnWideAlt(); 2143 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2144 } 2145} 2146 2147void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 2148 RegLocation rl_src1, RegLocation rl_src2) { 2149 if (cu_->target64) { 2150 GenArithOpLongImpl<8>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2151 } else { 2152 GenArithOpLongImpl<4>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2153 } 2154} 2155 2156void Mir2Lir::GenConst(RegLocation rl_dest, int value) { 2157 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2158 LoadConstantNoClobber(rl_result.reg, value); 2159 StoreValue(rl_dest, rl_result); 2160 if (value == 0) { 2161 Workaround7250540(rl_dest, rl_result.reg); 2162 } 2163} 2164 2165template <size_t pointer_size> 2166void Mir2Lir::GenConversionCall(ThreadOffset<pointer_size> func_offset, 2167 RegLocation rl_dest, RegLocation rl_src) { 2168 /* 2169 * Don't optimize the register usage since it calls out to support 2170 * functions 2171 */ 2172 DCHECK_EQ(pointer_size, GetInstructionSetPointerSize(cu_->instruction_set)); 2173 2174 FlushAllRegs(); /* Send everything to home location */ 2175 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 2176 if (rl_dest.wide) { 2177 RegLocation rl_result; 2178 rl_result = GetReturnWide(LocToRegClass(rl_dest)); 2179 StoreValueWide(rl_dest, rl_result); 2180 } else { 2181 RegLocation rl_result; 2182 rl_result = GetReturn(LocToRegClass(rl_dest)); 2183 StoreValue(rl_dest, rl_result); 2184 } 2185} 2186template void Mir2Lir::GenConversionCall(ThreadOffset<4> func_offset, 2187 RegLocation rl_dest, RegLocation rl_src); 2188template void Mir2Lir::GenConversionCall(ThreadOffset<8> func_offset, 2189 RegLocation rl_dest, RegLocation rl_src); 2190 2191class SuspendCheckSlowPath : public Mir2Lir::LIRSlowPath { 2192 public: 2193 SuspendCheckSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont) 2194 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont) { 2195 } 2196 2197 void Compile() OVERRIDE { 2198 m2l_->ResetRegPool(); 2199 m2l_->ResetDefTracking(); 2200 GenerateTargetLabel(kPseudoSuspendTarget); 2201 if (cu_->target64) { 2202 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pTestSuspend), true); 2203 } else { 2204 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pTestSuspend), true); 2205 } 2206 if (cont_ != nullptr) { 2207 m2l_->OpUnconditionalBranch(cont_); 2208 } 2209 } 2210}; 2211 2212/* Check if we need to check for pending suspend request */ 2213void Mir2Lir::GenSuspendTest(int opt_flags) { 2214 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2215 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2216 return; 2217 } 2218 FlushAllRegs(); 2219 LIR* branch = OpTestSuspend(NULL); 2220 LIR* cont = NewLIR0(kPseudoTargetLabel); 2221 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, cont)); 2222 } else { 2223 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2224 return; 2225 } 2226 FlushAllRegs(); // TODO: needed? 2227 LIR* inst = CheckSuspendUsingLoad(); 2228 MarkSafepointPC(inst); 2229 } 2230} 2231 2232/* Check if we need to check for pending suspend request */ 2233void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 2234 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2235 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2236 OpUnconditionalBranch(target); 2237 return; 2238 } 2239 OpTestSuspend(target); 2240 FlushAllRegs(); 2241 LIR* branch = OpUnconditionalBranch(nullptr); 2242 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, target)); 2243 } else { 2244 // For the implicit suspend check, just perform the trigger 2245 // load and branch to the target. 2246 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2247 OpUnconditionalBranch(target); 2248 return; 2249 } 2250 FlushAllRegs(); 2251 LIR* inst = CheckSuspendUsingLoad(); 2252 MarkSafepointPC(inst); 2253 OpUnconditionalBranch(target); 2254 } 2255} 2256 2257/* Call out to helper assembly routine that will null check obj and then lock it. */ 2258void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2259 FlushAllRegs(); 2260 if (cu_->target64) { 2261 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pLockObject), rl_src, true); 2262 } else { 2263 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pLockObject), rl_src, true); 2264 } 2265} 2266 2267/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2268void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2269 FlushAllRegs(); 2270 if (cu_->target64) { 2271 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject), rl_src, true); 2272 } else { 2273 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject), rl_src, true); 2274 } 2275} 2276 2277/* Generic code for generating a wide constant into a VR. */ 2278void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2279 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2280 LoadConstantWide(rl_result.reg, value); 2281 StoreValueWide(rl_dest, rl_result); 2282} 2283 2284} // namespace art 2285