gen_common.cc revision b373e091eac39b1a79c11f2dcbd610af01e9e8a9
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "dex/compiler_ir.h" 18#include "dex/compiler_internals.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object-inl.h" 23#include "verifier/method_verifier.h" 24#include <functional> 25 26namespace art { 27 28/* 29 * This source files contains "gen" codegen routines that should 30 * be applicable to most targets. Only mid-level support utilities 31 * and "op" calls may be used here. 32 */ 33 34/* 35 * Generate a kPseudoBarrier marker to indicate the boundary of special 36 * blocks. 37 */ 38void Mir2Lir::GenBarrier() { 39 LIR* barrier = NewLIR0(kPseudoBarrier); 40 /* Mark all resources as being clobbered */ 41 DCHECK(!barrier->flags.use_def_invalid); 42 barrier->u.m.def_mask = ENCODE_ALL; 43} 44 45// TODO: need to do some work to split out targets with 46// condition codes and those without 47LIR* Mir2Lir::GenCheck(ConditionCode c_code, ThrowKind kind) { 48 DCHECK_NE(cu_->instruction_set, kMips); 49 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_); 50 LIR* branch = OpCondBranch(c_code, tgt); 51 // Remember branch target - will process later 52 throw_launchpads_.Insert(tgt); 53 return branch; 54} 55 56LIR* Mir2Lir::GenImmedCheck(ConditionCode c_code, int reg, int imm_val, ThrowKind kind) { 57 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg, imm_val); 58 LIR* branch; 59 if (c_code == kCondAl) { 60 branch = OpUnconditionalBranch(tgt); 61 } else { 62 branch = OpCmpImmBranch(c_code, reg, imm_val, tgt); 63 } 64 // Remember branch target - will process later 65 throw_launchpads_.Insert(tgt); 66 return branch; 67} 68 69 70/* Perform null-check on a register. */ 71LIR* Mir2Lir::GenNullCheck(int m_reg, int opt_flags) { 72 if (Runtime::Current()->ExplicitNullChecks()) { 73 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 74 return NULL; 75 } 76 return GenImmedCheck(kCondEq, m_reg, 0, kThrowNullPointer); 77 } 78 return nullptr; 79} 80 81void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 82 if (!Runtime::Current()->ExplicitNullChecks()) { 83 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 84 return; 85 } 86 MarkSafepointPC(last_lir_insn_); 87 } 88} 89 90void Mir2Lir::MarkPossibleStackOverflowException() { 91 if (!Runtime::Current()->ExplicitStackOverflowChecks()) { 92 MarkSafepointPC(last_lir_insn_); 93 } 94} 95 96void Mir2Lir::ForceImplicitNullCheck(int reg, int opt_flags) { 97 if (!Runtime::Current()->ExplicitNullChecks()) { 98 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 99 return; 100 } 101 // Force an implicit null check by performing a memory operation (load) from the given 102 // register with offset 0. This will cause a signal if the register contains 0 (null). 103 int tmp = AllocTemp(); 104 LIR* load = LoadWordDisp(reg, 0, tmp); 105 FreeTemp(tmp); 106 MarkSafepointPC(load); 107 } 108} 109 110/* Perform check on two registers */ 111LIR* Mir2Lir::GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 112 ThrowKind kind) { 113 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg1, reg2); 114 LIR* branch = OpCmpBranch(c_code, reg1, reg2, tgt); 115 // Remember branch target - will process later 116 throw_launchpads_.Insert(tgt); 117 return branch; 118} 119 120void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 121 RegLocation rl_src2, LIR* taken, 122 LIR* fall_through) { 123 ConditionCode cond; 124 switch (opcode) { 125 case Instruction::IF_EQ: 126 cond = kCondEq; 127 break; 128 case Instruction::IF_NE: 129 cond = kCondNe; 130 break; 131 case Instruction::IF_LT: 132 cond = kCondLt; 133 break; 134 case Instruction::IF_GE: 135 cond = kCondGe; 136 break; 137 case Instruction::IF_GT: 138 cond = kCondGt; 139 break; 140 case Instruction::IF_LE: 141 cond = kCondLe; 142 break; 143 default: 144 cond = static_cast<ConditionCode>(0); 145 LOG(FATAL) << "Unexpected opcode " << opcode; 146 } 147 148 // Normalize such that if either operand is constant, src2 will be constant 149 if (rl_src1.is_const) { 150 RegLocation rl_temp = rl_src1; 151 rl_src1 = rl_src2; 152 rl_src2 = rl_temp; 153 cond = FlipComparisonOrder(cond); 154 } 155 156 rl_src1 = LoadValue(rl_src1, kCoreReg); 157 // Is this really an immediate comparison? 158 if (rl_src2.is_const) { 159 // If it's already live in a register or not easily materialized, just keep going 160 RegLocation rl_temp = UpdateLoc(rl_src2); 161 if ((rl_temp.location == kLocDalvikFrame) && 162 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 163 // OK - convert this to a compare immediate and branch 164 OpCmpImmBranch(cond, rl_src1.reg.GetReg(), mir_graph_->ConstantValue(rl_src2), taken); 165 return; 166 } 167 } 168 rl_src2 = LoadValue(rl_src2, kCoreReg); 169 OpCmpBranch(cond, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), taken); 170} 171 172void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 173 LIR* fall_through) { 174 ConditionCode cond; 175 rl_src = LoadValue(rl_src, kCoreReg); 176 switch (opcode) { 177 case Instruction::IF_EQZ: 178 cond = kCondEq; 179 break; 180 case Instruction::IF_NEZ: 181 cond = kCondNe; 182 break; 183 case Instruction::IF_LTZ: 184 cond = kCondLt; 185 break; 186 case Instruction::IF_GEZ: 187 cond = kCondGe; 188 break; 189 case Instruction::IF_GTZ: 190 cond = kCondGt; 191 break; 192 case Instruction::IF_LEZ: 193 cond = kCondLe; 194 break; 195 default: 196 cond = static_cast<ConditionCode>(0); 197 LOG(FATAL) << "Unexpected opcode " << opcode; 198 } 199 OpCmpImmBranch(cond, rl_src.reg.GetReg(), 0, taken); 200} 201 202void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 203 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 204 if (rl_src.location == kLocPhysReg) { 205 OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg()); 206 } else { 207 LoadValueDirect(rl_src, rl_result.reg.GetReg()); 208 } 209 OpRegRegImm(kOpAsr, rl_result.reg.GetHighReg(), rl_result.reg.GetReg(), 31); 210 StoreValueWide(rl_dest, rl_result); 211} 212 213void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 214 RegLocation rl_src) { 215 rl_src = LoadValue(rl_src, kCoreReg); 216 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 217 OpKind op = kOpInvalid; 218 switch (opcode) { 219 case Instruction::INT_TO_BYTE: 220 op = kOp2Byte; 221 break; 222 case Instruction::INT_TO_SHORT: 223 op = kOp2Short; 224 break; 225 case Instruction::INT_TO_CHAR: 226 op = kOp2Char; 227 break; 228 default: 229 LOG(ERROR) << "Bad int conversion type"; 230 } 231 OpRegReg(op, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 232 StoreValue(rl_dest, rl_result); 233} 234 235/* 236 * Let helper function take care of everything. Will call 237 * Array::AllocFromCode(type_idx, method, count); 238 * Note: AllocFromCode will handle checks for errNegativeArraySize. 239 */ 240void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 241 RegLocation rl_src) { 242 FlushAllRegs(); /* Everything to home location */ 243 ThreadOffset func_offset(-1); 244 const DexFile* dex_file = cu_->dex_file; 245 CompilerDriver* driver = cu_->compiler_driver; 246 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *dex_file, 247 type_idx)) { 248 bool is_type_initialized; // Ignored as an array does not have an initializer. 249 bool use_direct_type_ptr; 250 uintptr_t direct_type_ptr; 251 if (kEmbedClassInCode && 252 driver->CanEmbedTypeInCode(*dex_file, type_idx, 253 &is_type_initialized, &use_direct_type_ptr, &direct_type_ptr)) { 254 // The fast path. 255 if (!use_direct_type_ptr) { 256 LoadClassType(type_idx, kArg0); 257 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved); 258 CallRuntimeHelperRegMethodRegLocation(func_offset, TargetReg(kArg0), rl_src, true); 259 } else { 260 // Use the direct pointer. 261 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved); 262 CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, true); 263 } 264 } else { 265 // The slow path. 266 DCHECK_EQ(func_offset.Int32Value(), -1); 267 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArray); 268 CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 269 } 270 DCHECK_NE(func_offset.Int32Value(), -1); 271 } else { 272 func_offset= QUICK_ENTRYPOINT_OFFSET(pAllocArrayWithAccessCheck); 273 CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 274 } 275 RegLocation rl_result = GetReturn(false); 276 StoreValue(rl_dest, rl_result); 277} 278 279/* 280 * Similar to GenNewArray, but with post-allocation initialization. 281 * Verifier guarantees we're dealing with an array class. Current 282 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 283 * Current code also throws internal unimp if not 'L', '[' or 'I'. 284 */ 285void Mir2Lir::GenFilledNewArray(CallInfo* info) { 286 int elems = info->num_arg_words; 287 int type_idx = info->index; 288 FlushAllRegs(); /* Everything to home location */ 289 ThreadOffset func_offset(-1); 290 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *cu_->dex_file, 291 type_idx)) { 292 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArray); 293 } else { 294 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArrayWithAccessCheck); 295 } 296 CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 297 FreeTemp(TargetReg(kArg2)); 298 FreeTemp(TargetReg(kArg1)); 299 /* 300 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 301 * return region. Because AllocFromCode placed the new array 302 * in kRet0, we'll just lock it into place. When debugger support is 303 * added, it may be necessary to additionally copy all return 304 * values to a home location in thread-local storage 305 */ 306 LockTemp(TargetReg(kRet0)); 307 308 // TODO: use the correct component size, currently all supported types 309 // share array alignment with ints (see comment at head of function) 310 size_t component_size = sizeof(int32_t); 311 312 // Having a range of 0 is legal 313 if (info->is_range && (elems > 0)) { 314 /* 315 * Bit of ugliness here. We're going generate a mem copy loop 316 * on the register range, but it is possible that some regs 317 * in the range have been promoted. This is unlikely, but 318 * before generating the copy, we'll just force a flush 319 * of any regs in the source range that have been promoted to 320 * home location. 321 */ 322 for (int i = 0; i < elems; i++) { 323 RegLocation loc = UpdateLoc(info->args[i]); 324 if (loc.location == kLocPhysReg) { 325 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), 326 loc.reg.GetReg(), kWord); 327 } 328 } 329 /* 330 * TUNING note: generated code here could be much improved, but 331 * this is an uncommon operation and isn't especially performance 332 * critical. 333 */ 334 int r_src = AllocTemp(); 335 int r_dst = AllocTemp(); 336 int r_idx = AllocTemp(); 337 int r_val = INVALID_REG; 338 switch (cu_->instruction_set) { 339 case kThumb2: 340 r_val = TargetReg(kLr); 341 break; 342 case kX86: 343 FreeTemp(TargetReg(kRet0)); 344 r_val = AllocTemp(); 345 break; 346 case kMips: 347 r_val = AllocTemp(); 348 break; 349 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 350 } 351 // Set up source pointer 352 RegLocation rl_first = info->args[0]; 353 OpRegRegImm(kOpAdd, r_src, TargetReg(kSp), SRegOffset(rl_first.s_reg_low)); 354 // Set up the target pointer 355 OpRegRegImm(kOpAdd, r_dst, TargetReg(kRet0), 356 mirror::Array::DataOffset(component_size).Int32Value()); 357 // Set up the loop counter (known to be > 0) 358 LoadConstant(r_idx, elems - 1); 359 // Generate the copy loop. Going backwards for convenience 360 LIR* target = NewLIR0(kPseudoTargetLabel); 361 // Copy next element 362 LoadBaseIndexed(r_src, r_idx, r_val, 2, kWord); 363 StoreBaseIndexed(r_dst, r_idx, r_val, 2, kWord); 364 FreeTemp(r_val); 365 OpDecAndBranch(kCondGe, r_idx, target); 366 if (cu_->instruction_set == kX86) { 367 // Restore the target pointer 368 OpRegRegImm(kOpAdd, TargetReg(kRet0), r_dst, 369 -mirror::Array::DataOffset(component_size).Int32Value()); 370 } 371 } else if (!info->is_range) { 372 // TUNING: interleave 373 for (int i = 0; i < elems; i++) { 374 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 375 StoreBaseDisp(TargetReg(kRet0), 376 mirror::Array::DataOffset(component_size).Int32Value() + 377 i * 4, rl_arg.reg.GetReg(), kWord); 378 // If the LoadValue caused a temp to be allocated, free it 379 if (IsTemp(rl_arg.reg.GetReg())) { 380 FreeTemp(rl_arg.reg.GetReg()); 381 } 382 } 383 } 384 if (info->result.location != kLocInvalid) { 385 StoreValue(info->result, GetReturn(false /* not fp */)); 386 } 387} 388 389// 390// Slow path to ensure a class is initialized for sget/sput. 391// 392class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 393 public: 394 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, 395 int storage_index, int r_base) : 396 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), storage_index_(storage_index), 397 r_base_(r_base) { 398 } 399 400 void Compile() { 401 LIR* unresolved_target = GenerateTargetLabel(); 402 uninit_->target = unresolved_target; 403 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeStaticStorage), 404 storage_index_, true); 405 // Copy helper's result into r_base, a no-op on all but MIPS. 406 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0)); 407 408 m2l_->OpUnconditionalBranch(cont_); 409 } 410 411 private: 412 LIR* const uninit_; 413 const int storage_index_; 414 const int r_base_; 415}; 416 417void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 418 bool is_object) { 419 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 420 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 421 if (field_info.FastPut() && !SLOW_FIELD_PATH) { 422 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 423 int r_base; 424 if (field_info.IsReferrersClass()) { 425 // Fast path, static storage base is this method's class 426 RegLocation rl_method = LoadCurrMethod(); 427 r_base = AllocTemp(); 428 LoadWordDisp(rl_method.reg.GetReg(), 429 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base); 430 if (IsTemp(rl_method.reg.GetReg())) { 431 FreeTemp(rl_method.reg.GetReg()); 432 } 433 } else { 434 // Medium path, static storage base in a different class which requires checks that the other 435 // class is initialized. 436 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 437 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 438 // May do runtime call so everything to home locations. 439 FlushAllRegs(); 440 // Using fixed register to sync with possible call to runtime support. 441 int r_method = TargetReg(kArg1); 442 LockTemp(r_method); 443 LoadCurrMethodDirect(r_method); 444 r_base = TargetReg(kArg0); 445 LockTemp(r_base); 446 LoadWordDisp(r_method, 447 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 448 r_base); 449 LoadWordDisp(r_base, mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 450 sizeof(int32_t*) * field_info.StorageIndex(), r_base); 451 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 452 if (!field_info.IsInitialized()) { 453 // Check if r_base is NULL or a not yet initialized class. 454 455 // The slow path is invoked if the r_base is NULL or the class pointed 456 // to by it is not initialized. 457 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 458 int r_tmp = TargetReg(kArg2); 459 LockTemp(r_tmp); 460 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 461 mirror::Class::StatusOffset().Int32Value(), 462 mirror::Class::kStatusInitialized, NULL); 463 LIR* cont = NewLIR0(kPseudoTargetLabel); 464 465 AddSlowPath(new (arena_) StaticFieldSlowPath(this, 466 unresolved_branch, uninit_branch, cont, 467 field_info.StorageIndex(), r_base)); 468 469 FreeTemp(r_tmp); 470 } 471 FreeTemp(r_method); 472 } 473 // rBase now holds static storage base 474 if (is_long_or_double) { 475 rl_src = LoadValueWide(rl_src, kAnyReg); 476 } else { 477 rl_src = LoadValue(rl_src, kAnyReg); 478 } 479 if (field_info.IsVolatile()) { 480 GenMemBarrier(kStoreStore); 481 } 482 if (is_long_or_double) { 483 StoreBaseDispWide(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg.GetReg(), 484 rl_src.reg.GetHighReg()); 485 } else { 486 StoreWordDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg.GetReg()); 487 } 488 if (field_info.IsVolatile()) { 489 GenMemBarrier(kStoreLoad); 490 } 491 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 492 MarkGCCard(rl_src.reg.GetReg(), r_base); 493 } 494 FreeTemp(r_base); 495 } else { 496 FlushAllRegs(); // Everything to home locations 497 ThreadOffset setter_offset = 498 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Static) 499 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjStatic) 500 : QUICK_ENTRYPOINT_OFFSET(pSet32Static)); 501 CallRuntimeHelperImmRegLocation(setter_offset, field_info.FieldIndex(), rl_src, true); 502 } 503} 504 505void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 506 bool is_long_or_double, bool is_object) { 507 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 508 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 509 if (field_info.FastGet() && !SLOW_FIELD_PATH) { 510 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 511 int r_base; 512 if (field_info.IsReferrersClass()) { 513 // Fast path, static storage base is this method's class 514 RegLocation rl_method = LoadCurrMethod(); 515 r_base = AllocTemp(); 516 LoadWordDisp(rl_method.reg.GetReg(), 517 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base); 518 } else { 519 // Medium path, static storage base in a different class which requires checks that the other 520 // class is initialized 521 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 522 // May do runtime call so everything to home locations. 523 FlushAllRegs(); 524 // Using fixed register to sync with possible call to runtime support. 525 int r_method = TargetReg(kArg1); 526 LockTemp(r_method); 527 LoadCurrMethodDirect(r_method); 528 r_base = TargetReg(kArg0); 529 LockTemp(r_base); 530 LoadWordDisp(r_method, 531 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 532 r_base); 533 LoadWordDisp(r_base, mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 534 sizeof(int32_t*) * field_info.StorageIndex(), r_base); 535 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 536 if (!field_info.IsInitialized()) { 537 // Check if r_base is NULL or a not yet initialized class. 538 539 // The slow path is invoked if the r_base is NULL or the class pointed 540 // to by it is not initialized. 541 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 542 int r_tmp = TargetReg(kArg2); 543 LockTemp(r_tmp); 544 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 545 mirror::Class::StatusOffset().Int32Value(), 546 mirror::Class::kStatusInitialized, NULL); 547 LIR* cont = NewLIR0(kPseudoTargetLabel); 548 549 AddSlowPath(new (arena_) StaticFieldSlowPath(this, 550 unresolved_branch, uninit_branch, cont, 551 field_info.StorageIndex(), r_base)); 552 553 FreeTemp(r_tmp); 554 } 555 FreeTemp(r_method); 556 } 557 // r_base now holds static storage base 558 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 559 if (field_info.IsVolatile()) { 560 GenMemBarrier(kLoadLoad); 561 } 562 if (is_long_or_double) { 563 LoadBaseDispWide(r_base, field_info.FieldOffset().Int32Value(), rl_result.reg.GetReg(), 564 rl_result.reg.GetHighReg(), INVALID_SREG); 565 } else { 566 LoadWordDisp(r_base, field_info.FieldOffset().Int32Value(), rl_result.reg.GetReg()); 567 } 568 FreeTemp(r_base); 569 if (is_long_or_double) { 570 StoreValueWide(rl_dest, rl_result); 571 } else { 572 StoreValue(rl_dest, rl_result); 573 } 574 } else { 575 FlushAllRegs(); // Everything to home locations 576 ThreadOffset getterOffset = 577 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Static) 578 :(is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjStatic) 579 : QUICK_ENTRYPOINT_OFFSET(pGet32Static)); 580 CallRuntimeHelperImm(getterOffset, field_info.FieldIndex(), true); 581 if (is_long_or_double) { 582 RegLocation rl_result = GetReturnWide(rl_dest.fp); 583 StoreValueWide(rl_dest, rl_result); 584 } else { 585 RegLocation rl_result = GetReturn(rl_dest.fp); 586 StoreValue(rl_dest, rl_result); 587 } 588 } 589} 590 591// Generate code for all slow paths. 592void Mir2Lir::HandleSlowPaths() { 593 int n = slow_paths_.Size(); 594 for (int i = 0; i < n; ++i) { 595 LIRSlowPath* slowpath = slow_paths_.Get(i); 596 slowpath->Compile(); 597 } 598 slow_paths_.Reset(); 599} 600 601void Mir2Lir::HandleSuspendLaunchPads() { 602 int num_elems = suspend_launchpads_.Size(); 603 ThreadOffset helper_offset = QUICK_ENTRYPOINT_OFFSET(pTestSuspend); 604 for (int i = 0; i < num_elems; i++) { 605 ResetRegPool(); 606 ResetDefTracking(); 607 LIR* lab = suspend_launchpads_.Get(i); 608 LIR* resume_lab = reinterpret_cast<LIR*>(UnwrapPointer(lab->operands[0])); 609 current_dalvik_offset_ = lab->operands[1]; 610 AppendLIR(lab); 611 int r_tgt = CallHelperSetup(helper_offset); 612 CallHelper(r_tgt, helper_offset, true /* MarkSafepointPC */); 613 OpUnconditionalBranch(resume_lab); 614 } 615} 616 617void Mir2Lir::HandleThrowLaunchPads() { 618 int num_elems = throw_launchpads_.Size(); 619 for (int i = 0; i < num_elems; i++) { 620 ResetRegPool(); 621 ResetDefTracking(); 622 LIR* lab = throw_launchpads_.Get(i); 623 current_dalvik_offset_ = lab->operands[1]; 624 AppendLIR(lab); 625 ThreadOffset func_offset(-1); 626 int v1 = lab->operands[2]; 627 int v2 = lab->operands[3]; 628 bool target_x86 = (cu_->instruction_set == kX86); 629 switch (lab->operands[0]) { 630 case kThrowNullPointer: 631 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowNullPointer); 632 break; 633 case kThrowConstantArrayBounds: // v1 is length reg (for Arm/Mips), v2 constant index 634 // v1 holds the constant array index. Mips/Arm uses v2 for length, x86 reloads. 635 if (target_x86) { 636 OpRegMem(kOpMov, TargetReg(kArg1), v1, mirror::Array::LengthOffset().Int32Value()); 637 } else { 638 OpRegCopy(TargetReg(kArg1), v1); 639 } 640 // Make sure the following LoadConstant doesn't mess with kArg1. 641 LockTemp(TargetReg(kArg1)); 642 LoadConstant(TargetReg(kArg0), v2); 643 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 644 break; 645 case kThrowArrayBounds: 646 // Move v1 (array index) to kArg0 and v2 (array length) to kArg1 647 if (v2 != TargetReg(kArg0)) { 648 OpRegCopy(TargetReg(kArg0), v1); 649 if (target_x86) { 650 // x86 leaves the array pointer in v2, so load the array length that the handler expects 651 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 652 } else { 653 OpRegCopy(TargetReg(kArg1), v2); 654 } 655 } else { 656 if (v1 == TargetReg(kArg1)) { 657 // Swap v1 and v2, using kArg2 as a temp 658 OpRegCopy(TargetReg(kArg2), v1); 659 if (target_x86) { 660 // x86 leaves the array pointer in v2; load the array length that the handler expects 661 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 662 } else { 663 OpRegCopy(TargetReg(kArg1), v2); 664 } 665 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 666 } else { 667 if (target_x86) { 668 // x86 leaves the array pointer in v2; load the array length that the handler expects 669 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 670 } else { 671 OpRegCopy(TargetReg(kArg1), v2); 672 } 673 OpRegCopy(TargetReg(kArg0), v1); 674 } 675 } 676 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 677 break; 678 case kThrowDivZero: 679 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowDivZero); 680 break; 681 case kThrowNoSuchMethod: 682 OpRegCopy(TargetReg(kArg0), v1); 683 func_offset = 684 QUICK_ENTRYPOINT_OFFSET(pThrowNoSuchMethod); 685 break; 686 case kThrowStackOverflow: 687 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow); 688 // Restore stack alignment 689 if (target_x86) { 690 OpRegImm(kOpAdd, TargetReg(kSp), frame_size_); 691 } else { 692 OpRegImm(kOpAdd, TargetReg(kSp), (num_core_spills_ + num_fp_spills_) * 4); 693 } 694 break; 695 default: 696 LOG(FATAL) << "Unexpected throw kind: " << lab->operands[0]; 697 } 698 ClobberCallerSave(); 699 int r_tgt = CallHelperSetup(func_offset); 700 CallHelper(r_tgt, func_offset, true /* MarkSafepointPC */); 701 } 702} 703 704void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 705 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 706 bool is_object) { 707 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 708 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 709 if (field_info.FastGet() && !SLOW_FIELD_PATH) { 710 RegLocation rl_result; 711 RegisterClass reg_class = oat_reg_class_by_size(size); 712 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 713 rl_obj = LoadValue(rl_obj, kCoreReg); 714 if (is_long_or_double) { 715 DCHECK(rl_dest.wide); 716 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 717 if (cu_->instruction_set == kX86) { 718 rl_result = EvalLoc(rl_dest, reg_class, true); 719 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 720 LoadBaseDispWide(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 721 rl_result.reg.GetReg(), 722 rl_result.reg.GetHighReg(), rl_obj.s_reg_low); 723 MarkPossibleNullPointerException(opt_flags); 724 if (field_info.IsVolatile()) { 725 GenMemBarrier(kLoadLoad); 726 } 727 } else { 728 int reg_ptr = AllocTemp(); 729 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value()); 730 rl_result = EvalLoc(rl_dest, reg_class, true); 731 LoadBaseDispWide(reg_ptr, 0, rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), 732 INVALID_SREG); 733 if (field_info.IsVolatile()) { 734 GenMemBarrier(kLoadLoad); 735 } 736 FreeTemp(reg_ptr); 737 } 738 StoreValueWide(rl_dest, rl_result); 739 } else { 740 rl_result = EvalLoc(rl_dest, reg_class, true); 741 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 742 LoadBaseDisp(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 743 rl_result.reg.GetReg(), kWord, rl_obj.s_reg_low); 744 MarkPossibleNullPointerException(opt_flags); 745 if (field_info.IsVolatile()) { 746 GenMemBarrier(kLoadLoad); 747 } 748 StoreValue(rl_dest, rl_result); 749 } 750 } else { 751 ThreadOffset getterOffset = 752 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Instance) 753 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjInstance) 754 : QUICK_ENTRYPOINT_OFFSET(pGet32Instance)); 755 CallRuntimeHelperImmRegLocation(getterOffset, field_info.FieldIndex(), rl_obj, true); 756 if (is_long_or_double) { 757 RegLocation rl_result = GetReturnWide(rl_dest.fp); 758 StoreValueWide(rl_dest, rl_result); 759 } else { 760 RegLocation rl_result = GetReturn(rl_dest.fp); 761 StoreValue(rl_dest, rl_result); 762 } 763 } 764} 765 766void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 767 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 768 bool is_object) { 769 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 770 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 771 if (field_info.FastPut() && !SLOW_FIELD_PATH) { 772 RegisterClass reg_class = oat_reg_class_by_size(size); 773 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 774 rl_obj = LoadValue(rl_obj, kCoreReg); 775 if (is_long_or_double) { 776 int reg_ptr; 777 rl_src = LoadValueWide(rl_src, kAnyReg); 778 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 779 reg_ptr = AllocTemp(); 780 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value()); 781 if (field_info.IsVolatile()) { 782 GenMemBarrier(kStoreStore); 783 } 784 StoreBaseDispWide(reg_ptr, 0, rl_src.reg.GetReg(), rl_src.reg.GetHighReg()); 785 MarkPossibleNullPointerException(opt_flags); 786 if (field_info.IsVolatile()) { 787 GenMemBarrier(kLoadLoad); 788 } 789 FreeTemp(reg_ptr); 790 } else { 791 rl_src = LoadValue(rl_src, reg_class); 792 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 793 if (field_info.IsVolatile()) { 794 GenMemBarrier(kStoreStore); 795 } 796 StoreBaseDisp(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 797 rl_src.reg.GetReg(), kWord); 798 MarkPossibleNullPointerException(opt_flags); 799 if (field_info.IsVolatile()) { 800 GenMemBarrier(kLoadLoad); 801 } 802 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 803 MarkGCCard(rl_src.reg.GetReg(), rl_obj.reg.GetReg()); 804 } 805 } 806 } else { 807 ThreadOffset setter_offset = 808 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Instance) 809 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjInstance) 810 : QUICK_ENTRYPOINT_OFFSET(pSet32Instance)); 811 CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info.FieldIndex(), 812 rl_obj, rl_src, true); 813 } 814} 815 816void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 817 RegLocation rl_src) { 818 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 819 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 820 (opt_flags & MIR_IGNORE_NULL_CHECK)); 821 ThreadOffset helper = needs_range_check 822 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pAputObjectWithNullAndBoundCheck) 823 : QUICK_ENTRYPOINT_OFFSET(pAputObjectWithBoundCheck)) 824 : QUICK_ENTRYPOINT_OFFSET(pAputObject); 825 CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, true); 826} 827 828void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 829 RegLocation rl_method = LoadCurrMethod(); 830 int res_reg = AllocTemp(); 831 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 832 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 833 *cu_->dex_file, 834 type_idx)) { 835 // Call out to helper which resolves type and verifies access. 836 // Resolved type returned in kRet0. 837 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 838 type_idx, rl_method.reg.GetReg(), true); 839 RegLocation rl_result = GetReturn(false); 840 StoreValue(rl_dest, rl_result); 841 } else { 842 // We're don't need access checks, load type from dex cache 843 int32_t dex_cache_offset = 844 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 845 LoadWordDisp(rl_method.reg.GetReg(), dex_cache_offset, res_reg); 846 int32_t offset_of_type = 847 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 848 * type_idx); 849 LoadWordDisp(res_reg, offset_of_type, rl_result.reg.GetReg()); 850 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 851 type_idx) || SLOW_TYPE_PATH) { 852 // Slow path, at runtime test if type is null and if so initialize 853 FlushAllRegs(); 854 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg.GetReg(), 0, NULL); 855 LIR* cont = NewLIR0(kPseudoTargetLabel); 856 857 // Object to generate the slow path for class resolution. 858 class SlowPath : public LIRSlowPath { 859 public: 860 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 861 const RegLocation& rl_method, const RegLocation& rl_result) : 862 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 863 rl_method_(rl_method), rl_result_(rl_result) { 864 } 865 866 void Compile() { 867 GenerateTargetLabel(); 868 869 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_, 870 rl_method_.reg.GetReg(), true); 871 m2l_->OpRegCopy(rl_result_.reg.GetReg(), m2l_->TargetReg(kRet0)); 872 873 m2l_->OpUnconditionalBranch(cont_); 874 } 875 876 private: 877 const int type_idx_; 878 const RegLocation rl_method_; 879 const RegLocation rl_result_; 880 }; 881 882 // Add to list for future. 883 AddSlowPath(new (arena_) SlowPath(this, branch, cont, 884 type_idx, rl_method, rl_result)); 885 886 StoreValue(rl_dest, rl_result); 887 } else { 888 // Fast path, we're done - just store result 889 StoreValue(rl_dest, rl_result); 890 } 891 } 892} 893 894void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 895 /* NOTE: Most strings should be available at compile time */ 896 int32_t offset_of_string = mirror::Array::DataOffset(sizeof(mirror::String*)).Int32Value() + 897 (sizeof(mirror::String*) * string_idx); 898 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 899 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 900 // slow path, resolve string if not in dex cache 901 FlushAllRegs(); 902 LockCallTemps(); // Using explicit registers 903 904 // If the Method* is already in a register, we can save a copy. 905 RegLocation rl_method = mir_graph_->GetMethodLoc(); 906 int r_method; 907 if (rl_method.location == kLocPhysReg) { 908 // A temp would conflict with register use below. 909 DCHECK(!IsTemp(rl_method.reg.GetReg())); 910 r_method = rl_method.reg.GetReg(); 911 } else { 912 r_method = TargetReg(kArg2); 913 LoadCurrMethodDirect(r_method); 914 } 915 LoadWordDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 916 TargetReg(kArg0)); 917 918 // Might call out to helper, which will return resolved string in kRet0 919 LoadWordDisp(TargetReg(kArg0), offset_of_string, TargetReg(kRet0)); 920 if (cu_->instruction_set == kThumb2 || 921 cu_->instruction_set == kMips) { 922 // OpRegImm(kOpCmp, TargetReg(kRet0), 0); // Is resolved? 923 LoadConstant(TargetReg(kArg1), string_idx); 924 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0), 0, NULL); 925 LIR* cont = NewLIR0(kPseudoTargetLabel); 926 GenBarrier(); 927 928 // Object to generate the slow path for string resolution. 929 class SlowPath : public LIRSlowPath { 930 public: 931 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, int r_method) : 932 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), r_method_(r_method) { 933 } 934 935 void Compile() { 936 GenerateTargetLabel(); 937 938 int r_tgt = m2l_->CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(pResolveString)); 939 940 m2l_->OpRegCopy(m2l_->TargetReg(kArg0), r_method_); // .eq 941 LIR* call_inst = m2l_->OpReg(kOpBlx, r_tgt); 942 m2l_->MarkSafepointPC(call_inst); 943 m2l_->FreeTemp(r_tgt); 944 945 m2l_->OpUnconditionalBranch(cont_); 946 } 947 948 private: 949 int r_method_; 950 }; 951 952 // Add to list for future. 953 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method)); 954 } else { 955 DCHECK_EQ(cu_->instruction_set, kX86); 956 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kRet0), 0, NULL); 957 LoadConstant(TargetReg(kArg1), string_idx); 958 CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pResolveString), r_method, 959 TargetReg(kArg1), true); 960 LIR* target = NewLIR0(kPseudoTargetLabel); 961 branch->target = target; 962 } 963 GenBarrier(); 964 StoreValue(rl_dest, GetReturn(false)); 965 } else { 966 RegLocation rl_method = LoadCurrMethod(); 967 int res_reg = AllocTemp(); 968 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 969 LoadWordDisp(rl_method.reg.GetReg(), 970 mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg); 971 LoadWordDisp(res_reg, offset_of_string, rl_result.reg.GetReg()); 972 StoreValue(rl_dest, rl_result); 973 } 974} 975 976/* 977 * Let helper function take care of everything. Will 978 * call Class::NewInstanceFromCode(type_idx, method); 979 */ 980void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 981 FlushAllRegs(); /* Everything to home location */ 982 // alloc will always check for resolution, do we also need to verify 983 // access because the verifier was unable to? 984 ThreadOffset func_offset(-1); 985 const DexFile* dex_file = cu_->dex_file; 986 CompilerDriver* driver = cu_->compiler_driver; 987 if (driver->CanAccessInstantiableTypeWithoutChecks( 988 cu_->method_idx, *dex_file, type_idx)) { 989 bool is_type_initialized; 990 bool use_direct_type_ptr; 991 uintptr_t direct_type_ptr; 992 if (kEmbedClassInCode && 993 driver->CanEmbedTypeInCode(*dex_file, type_idx, 994 &is_type_initialized, &use_direct_type_ptr, &direct_type_ptr)) { 995 // The fast path. 996 if (!use_direct_type_ptr) { 997 LoadClassType(type_idx, kArg0); 998 if (!is_type_initialized) { 999 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved); 1000 CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true); 1001 } else { 1002 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized); 1003 CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true); 1004 } 1005 } else { 1006 // Use the direct pointer. 1007 if (!is_type_initialized) { 1008 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved); 1009 CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1010 } else { 1011 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized); 1012 CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1013 } 1014 } 1015 } else { 1016 // The slow path. 1017 DCHECK_EQ(func_offset.Int32Value(), -1); 1018 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObject); 1019 CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1020 } 1021 DCHECK_NE(func_offset.Int32Value(), -1); 1022 } else { 1023 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectWithAccessCheck); 1024 CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1025 } 1026 RegLocation rl_result = GetReturn(false); 1027 StoreValue(rl_dest, rl_result); 1028} 1029 1030void Mir2Lir::GenThrow(RegLocation rl_src) { 1031 FlushAllRegs(); 1032 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pDeliverException), rl_src, true); 1033} 1034 1035// For final classes there are no sub-classes to check and so we can answer the instance-of 1036// question with simple comparisons. 1037void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1038 RegLocation rl_src) { 1039 // X86 has its own implementation. 1040 DCHECK_NE(cu_->instruction_set, kX86); 1041 1042 RegLocation object = LoadValue(rl_src, kCoreReg); 1043 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1044 int result_reg = rl_result.reg.GetReg(); 1045 if (result_reg == object.reg.GetReg()) { 1046 result_reg = AllocTypedTemp(false, kCoreReg); 1047 } 1048 LoadConstant(result_reg, 0); // assume false 1049 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg.GetReg(), 0, NULL); 1050 1051 int check_class = AllocTypedTemp(false, kCoreReg); 1052 int object_class = AllocTypedTemp(false, kCoreReg); 1053 1054 LoadCurrMethodDirect(check_class); 1055 if (use_declaring_class) { 1056 LoadWordDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1057 check_class); 1058 LoadWordDisp(object.reg.GetReg(), mirror::Object::ClassOffset().Int32Value(), object_class); 1059 } else { 1060 LoadWordDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1061 check_class); 1062 LoadWordDisp(object.reg.GetReg(), mirror::Object::ClassOffset().Int32Value(), object_class); 1063 int32_t offset_of_type = 1064 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 1065 (sizeof(mirror::Class*) * type_idx); 1066 LoadWordDisp(check_class, offset_of_type, check_class); 1067 } 1068 1069 LIR* ne_branchover = NULL; 1070 if (cu_->instruction_set == kThumb2) { 1071 OpRegReg(kOpCmp, check_class, object_class); // Same? 1072 OpIT(kCondEq, ""); // if-convert the test 1073 LoadConstant(result_reg, 1); // .eq case - load true 1074 } else { 1075 ne_branchover = OpCmpBranch(kCondNe, check_class, object_class, NULL); 1076 LoadConstant(result_reg, 1); // eq case - load true 1077 } 1078 LIR* target = NewLIR0(kPseudoTargetLabel); 1079 null_branchover->target = target; 1080 if (ne_branchover != NULL) { 1081 ne_branchover->target = target; 1082 } 1083 FreeTemp(object_class); 1084 FreeTemp(check_class); 1085 if (IsTemp(result_reg)) { 1086 OpRegCopy(rl_result.reg.GetReg(), result_reg); 1087 FreeTemp(result_reg); 1088 } 1089 StoreValue(rl_dest, rl_result); 1090} 1091 1092void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1093 bool type_known_abstract, bool use_declaring_class, 1094 bool can_assume_type_is_in_dex_cache, 1095 uint32_t type_idx, RegLocation rl_dest, 1096 RegLocation rl_src) { 1097 // X86 has its own implementation. 1098 DCHECK_NE(cu_->instruction_set, kX86); 1099 1100 FlushAllRegs(); 1101 // May generate a call - use explicit registers 1102 LockCallTemps(); 1103 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 1104 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 1105 if (needs_access_check) { 1106 // Check we have access to type_idx and if not throw IllegalAccessError, 1107 // returns Class* in kArg0 1108 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 1109 type_idx, true); 1110 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1111 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1112 } else if (use_declaring_class) { 1113 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1114 LoadWordDisp(TargetReg(kArg1), 1115 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 1116 } else { 1117 // Load dex cache entry into class_reg (kArg2) 1118 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1119 LoadWordDisp(TargetReg(kArg1), 1120 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 1121 int32_t offset_of_type = 1122 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 1123 * type_idx); 1124 LoadWordDisp(class_reg, offset_of_type, class_reg); 1125 if (!can_assume_type_is_in_dex_cache) { 1126 // Need to test presence of type in dex cache at runtime 1127 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 1128 // Not resolved 1129 // Call out to helper, which will return resolved type in kRet0 1130 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, true); 1131 OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path 1132 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* reload Ref */ 1133 // Rejoin code paths 1134 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 1135 hop_branch->target = hop_target; 1136 } 1137 } 1138 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1139 RegLocation rl_result = GetReturn(false); 1140 if (cu_->instruction_set == kMips) { 1141 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1142 LoadConstant(rl_result.reg.GetReg(), 0); 1143 } 1144 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 1145 1146 /* load object->klass_ */ 1147 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1148 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 1149 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1150 LIR* branchover = NULL; 1151 if (type_known_final) { 1152 // rl_result == ref == null == 0. 1153 if (cu_->instruction_set == kThumb2) { 1154 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 1155 OpIT(kCondEq, "E"); // if-convert the test 1156 LoadConstant(rl_result.reg.GetReg(), 1); // .eq case - load true 1157 LoadConstant(rl_result.reg.GetReg(), 0); // .ne case - load false 1158 } else { 1159 LoadConstant(rl_result.reg.GetReg(), 0); // ne case - load false 1160 branchover = OpCmpBranch(kCondNe, TargetReg(kArg1), TargetReg(kArg2), NULL); 1161 LoadConstant(rl_result.reg.GetReg(), 1); // eq case - load true 1162 } 1163 } else { 1164 if (cu_->instruction_set == kThumb2) { 1165 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1166 if (!type_known_abstract) { 1167 /* Uses conditional nullification */ 1168 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 1169 OpIT(kCondEq, "EE"); // if-convert the test 1170 LoadConstant(TargetReg(kArg0), 1); // .eq case - load true 1171 } 1172 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 1173 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1174 FreeTemp(r_tgt); 1175 } else { 1176 if (!type_known_abstract) { 1177 /* Uses branchovers */ 1178 LoadConstant(rl_result.reg.GetReg(), 1); // assume true 1179 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); 1180 } 1181 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1182 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 1183 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1184 FreeTemp(r_tgt); 1185 } 1186 } 1187 // TODO: only clobber when type isn't final? 1188 ClobberCallerSave(); 1189 /* branch targets here */ 1190 LIR* target = NewLIR0(kPseudoTargetLabel); 1191 StoreValue(rl_dest, rl_result); 1192 branch1->target = target; 1193 if (branchover != NULL) { 1194 branchover->target = target; 1195 } 1196} 1197 1198void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1199 bool type_known_final, type_known_abstract, use_declaring_class; 1200 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1201 *cu_->dex_file, 1202 type_idx, 1203 &type_known_final, 1204 &type_known_abstract, 1205 &use_declaring_class); 1206 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1207 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1208 1209 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1210 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1211 } else { 1212 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1213 use_declaring_class, can_assume_type_is_in_dex_cache, 1214 type_idx, rl_dest, rl_src); 1215 } 1216} 1217 1218void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1219 bool type_known_final, type_known_abstract, use_declaring_class; 1220 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1221 *cu_->dex_file, 1222 type_idx, 1223 &type_known_final, 1224 &type_known_abstract, 1225 &use_declaring_class); 1226 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1227 // of the exception throw path. 1228 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1229 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1230 // Verifier type analysis proved this check cast would never cause an exception. 1231 return; 1232 } 1233 FlushAllRegs(); 1234 // May generate a call - use explicit registers 1235 LockCallTemps(); 1236 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 1237 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 1238 if (needs_access_check) { 1239 // Check we have access to type_idx and if not throw IllegalAccessError, 1240 // returns Class* in kRet0 1241 // InitializeTypeAndVerifyAccess(idx, method) 1242 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 1243 type_idx, TargetReg(kArg1), true); 1244 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1245 } else if (use_declaring_class) { 1246 LoadWordDisp(TargetReg(kArg1), 1247 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 1248 } else { 1249 // Load dex cache entry into class_reg (kArg2) 1250 LoadWordDisp(TargetReg(kArg1), 1251 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 1252 int32_t offset_of_type = 1253 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 1254 (sizeof(mirror::Class*) * type_idx); 1255 LoadWordDisp(class_reg, offset_of_type, class_reg); 1256 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1257 // Need to test presence of type in dex cache at runtime 1258 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1259 LIR* cont = NewLIR0(kPseudoTargetLabel); 1260 1261 // Slow path to initialize the type. Executed if the type is NULL. 1262 class SlowPath : public LIRSlowPath { 1263 public: 1264 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1265 const int class_reg) : 1266 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1267 class_reg_(class_reg) { 1268 } 1269 1270 void Compile() { 1271 GenerateTargetLabel(); 1272 1273 // Call out to helper, which will return resolved type in kArg0 1274 // InitializeTypeFromCode(idx, method) 1275 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_, 1276 m2l_->TargetReg(kArg1), true); 1277 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0)); // Align usage with fast path 1278 m2l_->OpUnconditionalBranch(cont_); 1279 } 1280 public: 1281 const int type_idx_; 1282 const int class_reg_; 1283 }; 1284 1285 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, 1286 type_idx, class_reg)); 1287 } 1288 } 1289 // At this point, class_reg (kArg2) has class 1290 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1291 1292 // Slow path for the case where the classes are not equal. In this case we need 1293 // to call a helper function to do the check. 1294 class SlowPath : public LIRSlowPath { 1295 public: 1296 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1297 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1298 } 1299 1300 void Compile() { 1301 GenerateTargetLabel(); 1302 1303 if (load_) { 1304 m2l_->LoadWordDisp(m2l_->TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), 1305 m2l_->TargetReg(kArg1)); 1306 } 1307 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pCheckCast), m2l_->TargetReg(kArg2), 1308 m2l_->TargetReg(kArg1), true); 1309 1310 m2l_->OpUnconditionalBranch(cont_); 1311 } 1312 1313 private: 1314 bool load_; 1315 }; 1316 1317 if (type_known_abstract) { 1318 // Easier case, run slow path if target is non-null (slow path will load from target) 1319 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0), 0, NULL); 1320 LIR* cont = NewLIR0(kPseudoTargetLabel); 1321 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1322 } else { 1323 // Harder, more common case. We need to generate a forward branch over the load 1324 // if the target is null. If it's non-null we perform the load and branch to the 1325 // slow path if the classes are not equal. 1326 1327 /* Null is OK - continue */ 1328 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 1329 /* load object->klass_ */ 1330 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1331 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), 1332 TargetReg(kArg1)); 1333 1334 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1), class_reg, NULL); 1335 LIR* cont = NewLIR0(kPseudoTargetLabel); 1336 1337 // Add the slow path that will not perform load since this is already done. 1338 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1339 1340 // Set the null check to branch to the continuation. 1341 branch1->target = cont; 1342 } 1343} 1344 1345void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1346 RegLocation rl_src1, RegLocation rl_src2) { 1347 RegLocation rl_result; 1348 if (cu_->instruction_set == kThumb2) { 1349 /* 1350 * NOTE: This is the one place in the code in which we might have 1351 * as many as six live temporary registers. There are 5 in the normal 1352 * set for Arm. Until we have spill capabilities, temporarily add 1353 * lr to the temp set. It is safe to do this locally, but note that 1354 * lr is used explicitly elsewhere in the code generator and cannot 1355 * normally be used as a general temp register. 1356 */ 1357 MarkTemp(TargetReg(kLr)); // Add lr to the temp pool 1358 FreeTemp(TargetReg(kLr)); // and make it available 1359 } 1360 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1361 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1362 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1363 // The longs may overlap - use intermediate temp if so 1364 if ((rl_result.reg.GetReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetReg() == rl_src2.reg.GetHighReg())) { 1365 int t_reg = AllocTemp(); 1366 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1367 OpRegRegReg(second_op, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1368 OpRegCopy(rl_result.reg.GetReg(), t_reg); 1369 FreeTemp(t_reg); 1370 } else { 1371 OpRegRegReg(first_op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1372 OpRegRegReg(second_op, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), 1373 rl_src2.reg.GetHighReg()); 1374 } 1375 /* 1376 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1377 * following StoreValueWide might need to allocate a temp register. 1378 * To further work around the lack of a spill capability, explicitly 1379 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1380 * Remove when spill is functional. 1381 */ 1382 FreeRegLocTemps(rl_result, rl_src1); 1383 FreeRegLocTemps(rl_result, rl_src2); 1384 StoreValueWide(rl_dest, rl_result); 1385 if (cu_->instruction_set == kThumb2) { 1386 Clobber(TargetReg(kLr)); 1387 UnmarkTemp(TargetReg(kLr)); // Remove lr from the temp pool 1388 } 1389} 1390 1391 1392void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1393 RegLocation rl_src1, RegLocation rl_shift) { 1394 ThreadOffset func_offset(-1); 1395 1396 switch (opcode) { 1397 case Instruction::SHL_LONG: 1398 case Instruction::SHL_LONG_2ADDR: 1399 func_offset = QUICK_ENTRYPOINT_OFFSET(pShlLong); 1400 break; 1401 case Instruction::SHR_LONG: 1402 case Instruction::SHR_LONG_2ADDR: 1403 func_offset = QUICK_ENTRYPOINT_OFFSET(pShrLong); 1404 break; 1405 case Instruction::USHR_LONG: 1406 case Instruction::USHR_LONG_2ADDR: 1407 func_offset = QUICK_ENTRYPOINT_OFFSET(pUshrLong); 1408 break; 1409 default: 1410 LOG(FATAL) << "Unexpected case"; 1411 } 1412 FlushAllRegs(); /* Send everything to home location */ 1413 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1414 RegLocation rl_result = GetReturnWide(false); 1415 StoreValueWide(rl_dest, rl_result); 1416} 1417 1418 1419void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1420 RegLocation rl_src1, RegLocation rl_src2) { 1421 DCHECK_NE(cu_->instruction_set, kX86); 1422 OpKind op = kOpBkpt; 1423 bool is_div_rem = false; 1424 bool check_zero = false; 1425 bool unary = false; 1426 RegLocation rl_result; 1427 bool shift_op = false; 1428 switch (opcode) { 1429 case Instruction::NEG_INT: 1430 op = kOpNeg; 1431 unary = true; 1432 break; 1433 case Instruction::NOT_INT: 1434 op = kOpMvn; 1435 unary = true; 1436 break; 1437 case Instruction::ADD_INT: 1438 case Instruction::ADD_INT_2ADDR: 1439 op = kOpAdd; 1440 break; 1441 case Instruction::SUB_INT: 1442 case Instruction::SUB_INT_2ADDR: 1443 op = kOpSub; 1444 break; 1445 case Instruction::MUL_INT: 1446 case Instruction::MUL_INT_2ADDR: 1447 op = kOpMul; 1448 break; 1449 case Instruction::DIV_INT: 1450 case Instruction::DIV_INT_2ADDR: 1451 check_zero = true; 1452 op = kOpDiv; 1453 is_div_rem = true; 1454 break; 1455 /* NOTE: returns in kArg1 */ 1456 case Instruction::REM_INT: 1457 case Instruction::REM_INT_2ADDR: 1458 check_zero = true; 1459 op = kOpRem; 1460 is_div_rem = true; 1461 break; 1462 case Instruction::AND_INT: 1463 case Instruction::AND_INT_2ADDR: 1464 op = kOpAnd; 1465 break; 1466 case Instruction::OR_INT: 1467 case Instruction::OR_INT_2ADDR: 1468 op = kOpOr; 1469 break; 1470 case Instruction::XOR_INT: 1471 case Instruction::XOR_INT_2ADDR: 1472 op = kOpXor; 1473 break; 1474 case Instruction::SHL_INT: 1475 case Instruction::SHL_INT_2ADDR: 1476 shift_op = true; 1477 op = kOpLsl; 1478 break; 1479 case Instruction::SHR_INT: 1480 case Instruction::SHR_INT_2ADDR: 1481 shift_op = true; 1482 op = kOpAsr; 1483 break; 1484 case Instruction::USHR_INT: 1485 case Instruction::USHR_INT_2ADDR: 1486 shift_op = true; 1487 op = kOpLsr; 1488 break; 1489 default: 1490 LOG(FATAL) << "Invalid word arith op: " << opcode; 1491 } 1492 if (!is_div_rem) { 1493 if (unary) { 1494 rl_src1 = LoadValue(rl_src1, kCoreReg); 1495 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1496 OpRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); 1497 } else { 1498 if (shift_op) { 1499 int t_reg = INVALID_REG; 1500 rl_src2 = LoadValue(rl_src2, kCoreReg); 1501 t_reg = AllocTemp(); 1502 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg.GetReg(), 31); 1503 rl_src1 = LoadValue(rl_src1, kCoreReg); 1504 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1505 OpRegRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), t_reg); 1506 FreeTemp(t_reg); 1507 } else { 1508 rl_src1 = LoadValue(rl_src1, kCoreReg); 1509 rl_src2 = LoadValue(rl_src2, kCoreReg); 1510 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1511 OpRegRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1512 } 1513 } 1514 StoreValue(rl_dest, rl_result); 1515 } else { 1516 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1517 if (cu_->instruction_set == kMips) { 1518 rl_src1 = LoadValue(rl_src1, kCoreReg); 1519 rl_src2 = LoadValue(rl_src2, kCoreReg); 1520 if (check_zero) { 1521 GenImmedCheck(kCondEq, rl_src2.reg.GetReg(), 0, kThrowDivZero); 1522 } 1523 rl_result = GenDivRem(rl_dest, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), op == kOpDiv); 1524 done = true; 1525 } else if (cu_->instruction_set == kThumb2) { 1526 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1527 // Use ARM SDIV instruction for division. For remainder we also need to 1528 // calculate using a MUL and subtract. 1529 rl_src1 = LoadValue(rl_src1, kCoreReg); 1530 rl_src2 = LoadValue(rl_src2, kCoreReg); 1531 if (check_zero) { 1532 GenImmedCheck(kCondEq, rl_src2.reg.GetReg(), 0, kThrowDivZero); 1533 } 1534 rl_result = GenDivRem(rl_dest, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), op == kOpDiv); 1535 done = true; 1536 } 1537 } 1538 1539 // If we haven't already generated the code use the callout function. 1540 if (!done) { 1541 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1542 FlushAllRegs(); /* Send everything to home location */ 1543 LoadValueDirectFixed(rl_src2, TargetReg(kArg1)); 1544 int r_tgt = CallHelperSetup(func_offset); 1545 LoadValueDirectFixed(rl_src1, TargetReg(kArg0)); 1546 if (check_zero) { 1547 GenImmedCheck(kCondEq, TargetReg(kArg1), 0, kThrowDivZero); 1548 } 1549 // NOTE: callout here is not a safepoint. 1550 CallHelper(r_tgt, func_offset, false /* not a safepoint */); 1551 if (op == kOpDiv) 1552 rl_result = GetReturn(false); 1553 else 1554 rl_result = GetReturnAlt(); 1555 } 1556 StoreValue(rl_dest, rl_result); 1557 } 1558} 1559 1560/* 1561 * The following are the first-level codegen routines that analyze the format 1562 * of each bytecode then either dispatch special purpose codegen routines 1563 * or produce corresponding Thumb instructions directly. 1564 */ 1565 1566// Returns true if no more than two bits are set in 'x'. 1567static bool IsPopCountLE2(unsigned int x) { 1568 x &= x - 1; 1569 return (x & (x - 1)) == 0; 1570} 1571 1572// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1573// and store the result in 'rl_dest'. 1574bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1575 RegLocation rl_src, RegLocation rl_dest, int lit) { 1576 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1577 return false; 1578 } 1579 // No divide instruction for Arm, so check for more special cases 1580 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1581 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1582 } 1583 int k = LowestSetBit(lit); 1584 if (k >= 30) { 1585 // Avoid special cases. 1586 return false; 1587 } 1588 rl_src = LoadValue(rl_src, kCoreReg); 1589 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1590 if (is_div) { 1591 int t_reg = AllocTemp(); 1592 if (lit == 2) { 1593 // Division by 2 is by far the most common division by constant. 1594 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetReg(), 32 - k); 1595 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg.GetReg()); 1596 OpRegRegImm(kOpAsr, rl_result.reg.GetReg(), t_reg, k); 1597 } else { 1598 OpRegRegImm(kOpAsr, t_reg, rl_src.reg.GetReg(), 31); 1599 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1600 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg.GetReg()); 1601 OpRegRegImm(kOpAsr, rl_result.reg.GetReg(), t_reg, k); 1602 } 1603 } else { 1604 int t_reg1 = AllocTemp(); 1605 int t_reg2 = AllocTemp(); 1606 if (lit == 2) { 1607 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg.GetReg(), 32 - k); 1608 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg.GetReg()); 1609 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1610 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg2, t_reg1); 1611 } else { 1612 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg.GetReg(), 31); 1613 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1614 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg.GetReg()); 1615 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1616 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg2, t_reg1); 1617 } 1618 } 1619 StoreValue(rl_dest, rl_result); 1620 return true; 1621} 1622 1623// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1624// and store the result in 'rl_dest'. 1625bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1626 // Can we simplify this multiplication? 1627 bool power_of_two = false; 1628 bool pop_count_le2 = false; 1629 bool power_of_two_minus_one = false; 1630 if (lit < 2) { 1631 // Avoid special cases. 1632 return false; 1633 } else if (IsPowerOfTwo(lit)) { 1634 power_of_two = true; 1635 } else if (IsPopCountLE2(lit)) { 1636 pop_count_le2 = true; 1637 } else if (IsPowerOfTwo(lit + 1)) { 1638 power_of_two_minus_one = true; 1639 } else { 1640 return false; 1641 } 1642 rl_src = LoadValue(rl_src, kCoreReg); 1643 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1644 if (power_of_two) { 1645 // Shift. 1646 OpRegRegImm(kOpLsl, rl_result.reg.GetReg(), rl_src.reg.GetReg(), LowestSetBit(lit)); 1647 } else if (pop_count_le2) { 1648 // Shift and add and shift. 1649 int first_bit = LowestSetBit(lit); 1650 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1651 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1652 } else { 1653 // Reverse subtract: (src << (shift + 1)) - src. 1654 DCHECK(power_of_two_minus_one); 1655 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1656 int t_reg = AllocTemp(); 1657 OpRegRegImm(kOpLsl, t_reg, rl_src.reg.GetReg(), LowestSetBit(lit + 1)); 1658 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg, rl_src.reg.GetReg()); 1659 } 1660 StoreValue(rl_dest, rl_result); 1661 return true; 1662} 1663 1664void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1665 int lit) { 1666 RegLocation rl_result; 1667 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1668 int shift_op = false; 1669 bool is_div = false; 1670 1671 switch (opcode) { 1672 case Instruction::RSUB_INT_LIT8: 1673 case Instruction::RSUB_INT: { 1674 rl_src = LoadValue(rl_src, kCoreReg); 1675 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1676 if (cu_->instruction_set == kThumb2) { 1677 OpRegRegImm(kOpRsub, rl_result.reg.GetReg(), rl_src.reg.GetReg(), lit); 1678 } else { 1679 OpRegReg(kOpNeg, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 1680 OpRegImm(kOpAdd, rl_result.reg.GetReg(), lit); 1681 } 1682 StoreValue(rl_dest, rl_result); 1683 return; 1684 } 1685 1686 case Instruction::SUB_INT: 1687 case Instruction::SUB_INT_2ADDR: 1688 lit = -lit; 1689 // Intended fallthrough 1690 case Instruction::ADD_INT: 1691 case Instruction::ADD_INT_2ADDR: 1692 case Instruction::ADD_INT_LIT8: 1693 case Instruction::ADD_INT_LIT16: 1694 op = kOpAdd; 1695 break; 1696 case Instruction::MUL_INT: 1697 case Instruction::MUL_INT_2ADDR: 1698 case Instruction::MUL_INT_LIT8: 1699 case Instruction::MUL_INT_LIT16: { 1700 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1701 return; 1702 } 1703 op = kOpMul; 1704 break; 1705 } 1706 case Instruction::AND_INT: 1707 case Instruction::AND_INT_2ADDR: 1708 case Instruction::AND_INT_LIT8: 1709 case Instruction::AND_INT_LIT16: 1710 op = kOpAnd; 1711 break; 1712 case Instruction::OR_INT: 1713 case Instruction::OR_INT_2ADDR: 1714 case Instruction::OR_INT_LIT8: 1715 case Instruction::OR_INT_LIT16: 1716 op = kOpOr; 1717 break; 1718 case Instruction::XOR_INT: 1719 case Instruction::XOR_INT_2ADDR: 1720 case Instruction::XOR_INT_LIT8: 1721 case Instruction::XOR_INT_LIT16: 1722 op = kOpXor; 1723 break; 1724 case Instruction::SHL_INT_LIT8: 1725 case Instruction::SHL_INT: 1726 case Instruction::SHL_INT_2ADDR: 1727 lit &= 31; 1728 shift_op = true; 1729 op = kOpLsl; 1730 break; 1731 case Instruction::SHR_INT_LIT8: 1732 case Instruction::SHR_INT: 1733 case Instruction::SHR_INT_2ADDR: 1734 lit &= 31; 1735 shift_op = true; 1736 op = kOpAsr; 1737 break; 1738 case Instruction::USHR_INT_LIT8: 1739 case Instruction::USHR_INT: 1740 case Instruction::USHR_INT_2ADDR: 1741 lit &= 31; 1742 shift_op = true; 1743 op = kOpLsr; 1744 break; 1745 1746 case Instruction::DIV_INT: 1747 case Instruction::DIV_INT_2ADDR: 1748 case Instruction::DIV_INT_LIT8: 1749 case Instruction::DIV_INT_LIT16: 1750 case Instruction::REM_INT: 1751 case Instruction::REM_INT_2ADDR: 1752 case Instruction::REM_INT_LIT8: 1753 case Instruction::REM_INT_LIT16: { 1754 if (lit == 0) { 1755 GenImmedCheck(kCondAl, 0, 0, kThrowDivZero); 1756 return; 1757 } 1758 if ((opcode == Instruction::DIV_INT) || 1759 (opcode == Instruction::DIV_INT_2ADDR) || 1760 (opcode == Instruction::DIV_INT_LIT8) || 1761 (opcode == Instruction::DIV_INT_LIT16)) { 1762 is_div = true; 1763 } else { 1764 is_div = false; 1765 } 1766 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1767 return; 1768 } 1769 1770 bool done = false; 1771 if (cu_->instruction_set == kMips) { 1772 rl_src = LoadValue(rl_src, kCoreReg); 1773 rl_result = GenDivRemLit(rl_dest, rl_src.reg.GetReg(), lit, is_div); 1774 done = true; 1775 } else if (cu_->instruction_set == kX86) { 1776 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1777 done = true; 1778 } else if (cu_->instruction_set == kThumb2) { 1779 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1780 // Use ARM SDIV instruction for division. For remainder we also need to 1781 // calculate using a MUL and subtract. 1782 rl_src = LoadValue(rl_src, kCoreReg); 1783 rl_result = GenDivRemLit(rl_dest, rl_src.reg.GetReg(), lit, is_div); 1784 done = true; 1785 } 1786 } 1787 1788 if (!done) { 1789 FlushAllRegs(); /* Everything to home location. */ 1790 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 1791 Clobber(TargetReg(kArg0)); 1792 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1793 CallRuntimeHelperRegImm(func_offset, TargetReg(kArg0), lit, false); 1794 if (is_div) 1795 rl_result = GetReturn(false); 1796 else 1797 rl_result = GetReturnAlt(); 1798 } 1799 StoreValue(rl_dest, rl_result); 1800 return; 1801 } 1802 default: 1803 LOG(FATAL) << "Unexpected opcode " << opcode; 1804 } 1805 rl_src = LoadValue(rl_src, kCoreReg); 1806 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1807 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 1808 if (shift_op && (lit == 0)) { 1809 OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg()); 1810 } else { 1811 OpRegRegImm(op, rl_result.reg.GetReg(), rl_src.reg.GetReg(), lit); 1812 } 1813 StoreValue(rl_dest, rl_result); 1814} 1815 1816void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 1817 RegLocation rl_src1, RegLocation rl_src2) { 1818 RegLocation rl_result; 1819 OpKind first_op = kOpBkpt; 1820 OpKind second_op = kOpBkpt; 1821 bool call_out = false; 1822 bool check_zero = false; 1823 ThreadOffset func_offset(-1); 1824 int ret_reg = TargetReg(kRet0); 1825 1826 switch (opcode) { 1827 case Instruction::NOT_LONG: 1828 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1829 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1830 // Check for destructive overlap 1831 if (rl_result.reg.GetReg() == rl_src2.reg.GetHighReg()) { 1832 int t_reg = AllocTemp(); 1833 OpRegCopy(t_reg, rl_src2.reg.GetHighReg()); 1834 OpRegReg(kOpMvn, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1835 OpRegReg(kOpMvn, rl_result.reg.GetHighReg(), t_reg); 1836 FreeTemp(t_reg); 1837 } else { 1838 OpRegReg(kOpMvn, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1839 OpRegReg(kOpMvn, rl_result.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1840 } 1841 StoreValueWide(rl_dest, rl_result); 1842 return; 1843 case Instruction::ADD_LONG: 1844 case Instruction::ADD_LONG_2ADDR: 1845 if (cu_->instruction_set != kThumb2) { 1846 GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 1847 return; 1848 } 1849 first_op = kOpAdd; 1850 second_op = kOpAdc; 1851 break; 1852 case Instruction::SUB_LONG: 1853 case Instruction::SUB_LONG_2ADDR: 1854 if (cu_->instruction_set != kThumb2) { 1855 GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 1856 return; 1857 } 1858 first_op = kOpSub; 1859 second_op = kOpSbc; 1860 break; 1861 case Instruction::MUL_LONG: 1862 case Instruction::MUL_LONG_2ADDR: 1863 if (cu_->instruction_set != kMips) { 1864 GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 1865 return; 1866 } else { 1867 call_out = true; 1868 ret_reg = TargetReg(kRet0); 1869 func_offset = QUICK_ENTRYPOINT_OFFSET(pLmul); 1870 } 1871 break; 1872 case Instruction::DIV_LONG: 1873 case Instruction::DIV_LONG_2ADDR: 1874 call_out = true; 1875 check_zero = true; 1876 ret_reg = TargetReg(kRet0); 1877 func_offset = QUICK_ENTRYPOINT_OFFSET(pLdiv); 1878 break; 1879 case Instruction::REM_LONG: 1880 case Instruction::REM_LONG_2ADDR: 1881 call_out = true; 1882 check_zero = true; 1883 func_offset = QUICK_ENTRYPOINT_OFFSET(pLmod); 1884 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 1885 ret_reg = (cu_->instruction_set == kThumb2) ? TargetReg(kArg2) : TargetReg(kRet0); 1886 break; 1887 case Instruction::AND_LONG_2ADDR: 1888 case Instruction::AND_LONG: 1889 if (cu_->instruction_set == kX86) { 1890 return GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 1891 } 1892 first_op = kOpAnd; 1893 second_op = kOpAnd; 1894 break; 1895 case Instruction::OR_LONG: 1896 case Instruction::OR_LONG_2ADDR: 1897 if (cu_->instruction_set == kX86) { 1898 GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 1899 return; 1900 } 1901 first_op = kOpOr; 1902 second_op = kOpOr; 1903 break; 1904 case Instruction::XOR_LONG: 1905 case Instruction::XOR_LONG_2ADDR: 1906 if (cu_->instruction_set == kX86) { 1907 GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 1908 return; 1909 } 1910 first_op = kOpXor; 1911 second_op = kOpXor; 1912 break; 1913 case Instruction::NEG_LONG: { 1914 GenNegLong(rl_dest, rl_src2); 1915 return; 1916 } 1917 default: 1918 LOG(FATAL) << "Invalid long arith op"; 1919 } 1920 if (!call_out) { 1921 GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 1922 } else { 1923 FlushAllRegs(); /* Send everything to home location */ 1924 if (check_zero) { 1925 LoadValueDirectWideFixed(rl_src2, TargetReg(kArg2), TargetReg(kArg3)); 1926 int r_tgt = CallHelperSetup(func_offset); 1927 GenDivZeroCheck(TargetReg(kArg2), TargetReg(kArg3)); 1928 LoadValueDirectWideFixed(rl_src1, TargetReg(kArg0), TargetReg(kArg1)); 1929 // NOTE: callout here is not a safepoint 1930 CallHelper(r_tgt, func_offset, false /* not safepoint */); 1931 } else { 1932 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 1933 } 1934 // Adjust return regs in to handle case of rem returning kArg2/kArg3 1935 if (ret_reg == TargetReg(kRet0)) 1936 rl_result = GetReturnWide(false); 1937 else 1938 rl_result = GetReturnWideAlt(); 1939 StoreValueWide(rl_dest, rl_result); 1940 } 1941} 1942 1943void Mir2Lir::GenConversionCall(ThreadOffset func_offset, 1944 RegLocation rl_dest, RegLocation rl_src) { 1945 /* 1946 * Don't optimize the register usage since it calls out to support 1947 * functions 1948 */ 1949 FlushAllRegs(); /* Send everything to home location */ 1950 if (rl_src.wide) { 1951 LoadValueDirectWideFixed(rl_src, rl_src.fp ? TargetReg(kFArg0) : TargetReg(kArg0), 1952 rl_src.fp ? TargetReg(kFArg1) : TargetReg(kArg1)); 1953 } else { 1954 LoadValueDirectFixed(rl_src, rl_src.fp ? TargetReg(kFArg0) : TargetReg(kArg0)); 1955 } 1956 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 1957 if (rl_dest.wide) { 1958 RegLocation rl_result; 1959 rl_result = GetReturnWide(rl_dest.fp); 1960 StoreValueWide(rl_dest, rl_result); 1961 } else { 1962 RegLocation rl_result; 1963 rl_result = GetReturn(rl_dest.fp); 1964 StoreValue(rl_dest, rl_result); 1965 } 1966} 1967 1968/* Check if we need to check for pending suspend request */ 1969void Mir2Lir::GenSuspendTest(int opt_flags) { 1970 if (Runtime::Current()->ExplicitSuspendChecks()) { 1971 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1972 return; 1973 } 1974 FlushAllRegs(); 1975 LIR* branch = OpTestSuspend(NULL); 1976 LIR* ret_lab = NewLIR0(kPseudoTargetLabel); 1977 LIR* target = RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, WrapPointer(ret_lab), 1978 current_dalvik_offset_); 1979 branch->target = target; 1980 suspend_launchpads_.Insert(target); 1981 } else { 1982 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1983 return; 1984 } 1985 FlushAllRegs(); // TODO: needed? 1986 LIR* inst = CheckSuspendUsingLoad(); 1987 MarkSafepointPC(inst); 1988 } 1989} 1990 1991/* Check if we need to check for pending suspend request */ 1992void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 1993 if (Runtime::Current()->ExplicitSuspendChecks()) { 1994 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1995 OpUnconditionalBranch(target); 1996 return; 1997 } 1998 OpTestSuspend(target); 1999 LIR* launch_pad = 2000 RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, WrapPointer(target), 2001 current_dalvik_offset_); 2002 FlushAllRegs(); 2003 OpUnconditionalBranch(launch_pad); 2004 suspend_launchpads_.Insert(launch_pad); 2005 } else { 2006 // For the implicit suspend check, just perform the trigger 2007 // load and branch to the target. 2008 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2009 OpUnconditionalBranch(target); 2010 return; 2011 } 2012 FlushAllRegs(); 2013 LIR* inst = CheckSuspendUsingLoad(); 2014 MarkSafepointPC(inst); 2015 OpUnconditionalBranch(target); 2016 } 2017} 2018 2019/* Call out to helper assembly routine that will null check obj and then lock it. */ 2020void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2021 FlushAllRegs(); 2022 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pLockObject), rl_src, true); 2023} 2024 2025/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2026void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2027 FlushAllRegs(); 2028 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pUnlockObject), rl_src, true); 2029} 2030 2031/* Generic code for generating a wide constant into a VR. */ 2032void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2033 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2034 LoadConstantWide(rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), value); 2035 StoreValueWide(rl_dest, rl_result); 2036} 2037 2038} // namespace art 2039