gen_common.cc revision b99b8d6cffe08d8c9d30175c936e5c88d3101802
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include "dex/compiler_ir.h" 17#include "dex/compiler_internals.h" 18#include "dex/quick/arm/arm_lir.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object_array-inl.h" 23#include "mirror/object-inl.h" 24#include "mirror/object_reference.h" 25#include "verifier/method_verifier.h" 26#include <functional> 27 28namespace art { 29 30// Shortcuts to repeatedly used long types. 31typedef mirror::ObjectArray<mirror::Object> ObjArray; 32typedef mirror::ObjectArray<mirror::Class> ClassArray; 33 34/* 35 * This source files contains "gen" codegen routines that should 36 * be applicable to most targets. Only mid-level support utilities 37 * and "op" calls may be used here. 38 */ 39 40/* 41 * Generate a kPseudoBarrier marker to indicate the boundary of special 42 * blocks. 43 */ 44void Mir2Lir::GenBarrier() { 45 LIR* barrier = NewLIR0(kPseudoBarrier); 46 /* Mark all resources as being clobbered */ 47 DCHECK(!barrier->flags.use_def_invalid); 48 barrier->u.m.def_mask = &kEncodeAll; 49} 50 51void Mir2Lir::GenDivZeroException() { 52 LIR* branch = OpUnconditionalBranch(nullptr); 53 AddDivZeroCheckSlowPath(branch); 54} 55 56void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { 57 LIR* branch = OpCondBranch(c_code, nullptr); 58 AddDivZeroCheckSlowPath(branch); 59} 60 61void Mir2Lir::GenDivZeroCheck(RegStorage reg) { 62 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 63 AddDivZeroCheckSlowPath(branch); 64} 65 66void Mir2Lir::AddDivZeroCheckSlowPath(LIR* branch) { 67 class DivZeroCheckSlowPath : public Mir2Lir::LIRSlowPath { 68 public: 69 DivZeroCheckSlowPath(Mir2Lir* m2l, LIR* branch) 70 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 71 } 72 73 void Compile() OVERRIDE { 74 m2l_->ResetRegPool(); 75 m2l_->ResetDefTracking(); 76 GenerateTargetLabel(kPseudoThrowTarget); 77 if (m2l_->cu_->target64) { 78 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowDivZero), true); 79 } else { 80 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowDivZero), true); 81 } 82 } 83 }; 84 85 AddSlowPath(new (arena_) DivZeroCheckSlowPath(this, branch)); 86} 87 88void Mir2Lir::GenArrayBoundsCheck(RegStorage index, RegStorage length) { 89 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 90 public: 91 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, RegStorage index, RegStorage length) 92 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 93 index_(index), length_(length) { 94 } 95 96 void Compile() OVERRIDE { 97 m2l_->ResetRegPool(); 98 m2l_->ResetDefTracking(); 99 GenerateTargetLabel(kPseudoThrowTarget); 100 if (m2l_->cu_->target64) { 101 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 102 index_, length_, true); 103 } else { 104 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 105 index_, length_, true); 106 } 107 } 108 109 private: 110 const RegStorage index_; 111 const RegStorage length_; 112 }; 113 114 LIR* branch = OpCmpBranch(kCondUge, index, length, nullptr); 115 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 116} 117 118void Mir2Lir::GenArrayBoundsCheck(int index, RegStorage length) { 119 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 120 public: 121 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, int index, RegStorage length) 122 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 123 index_(index), length_(length) { 124 } 125 126 void Compile() OVERRIDE { 127 m2l_->ResetRegPool(); 128 m2l_->ResetDefTracking(); 129 GenerateTargetLabel(kPseudoThrowTarget); 130 131 RegStorage arg1_32 = m2l_->TargetReg(kArg1, kNotWide); 132 RegStorage arg0_32 = m2l_->TargetReg(kArg0, kNotWide); 133 134 m2l_->OpRegCopy(arg1_32, length_); 135 m2l_->LoadConstant(arg0_32, index_); 136 if (m2l_->cu_->target64) { 137 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 138 arg0_32, arg1_32, true); 139 } else { 140 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 141 arg0_32, arg1_32, true); 142 } 143 } 144 145 private: 146 const int32_t index_; 147 const RegStorage length_; 148 }; 149 150 LIR* branch = OpCmpImmBranch(kCondLs, length, index, nullptr); 151 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 152} 153 154LIR* Mir2Lir::GenNullCheck(RegStorage reg) { 155 class NullCheckSlowPath : public Mir2Lir::LIRSlowPath { 156 public: 157 NullCheckSlowPath(Mir2Lir* m2l, LIR* branch) 158 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 159 } 160 161 void Compile() OVERRIDE { 162 m2l_->ResetRegPool(); 163 m2l_->ResetDefTracking(); 164 GenerateTargetLabel(kPseudoThrowTarget); 165 if (m2l_->cu_->target64) { 166 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowNullPointer), true); 167 } else { 168 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowNullPointer), true); 169 } 170 } 171 }; 172 173 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 174 AddSlowPath(new (arena_) NullCheckSlowPath(this, branch)); 175 return branch; 176} 177 178/* Perform null-check on a register. */ 179LIR* Mir2Lir::GenNullCheck(RegStorage m_reg, int opt_flags) { 180 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 181 return GenExplicitNullCheck(m_reg, opt_flags); 182 } 183 return nullptr; 184} 185 186/* Perform an explicit null-check on a register. */ 187LIR* Mir2Lir::GenExplicitNullCheck(RegStorage m_reg, int opt_flags) { 188 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 189 return NULL; 190 } 191 return GenNullCheck(m_reg); 192} 193 194void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 195 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 196 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 197 return; 198 } 199 // Insert after last instruction. 200 MarkSafepointPC(last_lir_insn_); 201 } 202} 203 204void Mir2Lir::MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after) { 205 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 206 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 207 return; 208 } 209 MarkSafepointPCAfter(after); 210 } 211} 212 213void Mir2Lir::MarkPossibleStackOverflowException() { 214 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitStackOverflowChecks()) { 215 MarkSafepointPC(last_lir_insn_); 216 } 217} 218 219void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { 220 if (cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 221 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 222 return; 223 } 224 // Force an implicit null check by performing a memory operation (load) from the given 225 // register with offset 0. This will cause a signal if the register contains 0 (null). 226 RegStorage tmp = AllocTemp(); 227 // TODO: for Mips, would be best to use rZERO as the bogus register target. 228 LIR* load = Load32Disp(reg, 0, tmp); 229 FreeTemp(tmp); 230 MarkSafepointPC(load); 231 } 232} 233 234void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 235 RegLocation rl_src2, LIR* taken, 236 LIR* fall_through) { 237 DCHECK(!rl_src1.fp); 238 DCHECK(!rl_src2.fp); 239 ConditionCode cond; 240 switch (opcode) { 241 case Instruction::IF_EQ: 242 cond = kCondEq; 243 break; 244 case Instruction::IF_NE: 245 cond = kCondNe; 246 break; 247 case Instruction::IF_LT: 248 cond = kCondLt; 249 break; 250 case Instruction::IF_GE: 251 cond = kCondGe; 252 break; 253 case Instruction::IF_GT: 254 cond = kCondGt; 255 break; 256 case Instruction::IF_LE: 257 cond = kCondLe; 258 break; 259 default: 260 cond = static_cast<ConditionCode>(0); 261 LOG(FATAL) << "Unexpected opcode " << opcode; 262 } 263 264 // Normalize such that if either operand is constant, src2 will be constant 265 if (rl_src1.is_const) { 266 RegLocation rl_temp = rl_src1; 267 rl_src1 = rl_src2; 268 rl_src2 = rl_temp; 269 cond = FlipComparisonOrder(cond); 270 } 271 272 rl_src1 = LoadValue(rl_src1); 273 // Is this really an immediate comparison? 274 if (rl_src2.is_const) { 275 // If it's already live in a register or not easily materialized, just keep going 276 RegLocation rl_temp = UpdateLoc(rl_src2); 277 int32_t constant_value = mir_graph_->ConstantValue(rl_src2); 278 if ((rl_temp.location == kLocDalvikFrame) && 279 InexpensiveConstantInt(constant_value)) { 280 // OK - convert this to a compare immediate and branch 281 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); 282 return; 283 } 284 285 // It's also commonly more efficient to have a test against zero with Eq/Ne. This is not worse 286 // for x86, and allows a cbz/cbnz for Arm and Mips. At the same time, it works around a register 287 // mismatch for 64b systems, where a reference is compared against null, as dex bytecode uses 288 // the 32b literal 0 for null. 289 if (constant_value == 0 && (cond == kCondEq || cond == kCondNe)) { 290 // Use the OpCmpImmBranch and ignore the value in the register. 291 OpCmpImmBranch(cond, rl_src1.reg, 0, taken); 292 return; 293 } 294 } 295 296 rl_src2 = LoadValue(rl_src2); 297 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken); 298} 299 300void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 301 LIR* fall_through) { 302 ConditionCode cond; 303 DCHECK(!rl_src.fp); 304 rl_src = LoadValue(rl_src); 305 switch (opcode) { 306 case Instruction::IF_EQZ: 307 cond = kCondEq; 308 break; 309 case Instruction::IF_NEZ: 310 cond = kCondNe; 311 break; 312 case Instruction::IF_LTZ: 313 cond = kCondLt; 314 break; 315 case Instruction::IF_GEZ: 316 cond = kCondGe; 317 break; 318 case Instruction::IF_GTZ: 319 cond = kCondGt; 320 break; 321 case Instruction::IF_LEZ: 322 cond = kCondLe; 323 break; 324 default: 325 cond = static_cast<ConditionCode>(0); 326 LOG(FATAL) << "Unexpected opcode " << opcode; 327 } 328 OpCmpImmBranch(cond, rl_src.reg, 0, taken); 329} 330 331void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 332 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 333 if (rl_src.location == kLocPhysReg) { 334 OpRegCopy(rl_result.reg, rl_src.reg); 335 } else { 336 LoadValueDirect(rl_src, rl_result.reg.GetLow()); 337 } 338 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_result.reg.GetLow(), 31); 339 StoreValueWide(rl_dest, rl_result); 340} 341 342void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 343 RegLocation rl_src) { 344 rl_src = LoadValue(rl_src, kCoreReg); 345 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 346 OpKind op = kOpInvalid; 347 switch (opcode) { 348 case Instruction::INT_TO_BYTE: 349 op = kOp2Byte; 350 break; 351 case Instruction::INT_TO_SHORT: 352 op = kOp2Short; 353 break; 354 case Instruction::INT_TO_CHAR: 355 op = kOp2Char; 356 break; 357 default: 358 LOG(ERROR) << "Bad int conversion type"; 359 } 360 OpRegReg(op, rl_result.reg, rl_src.reg); 361 StoreValue(rl_dest, rl_result); 362} 363 364template <size_t pointer_size> 365static void GenNewArrayImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, 366 uint32_t type_idx, RegLocation rl_dest, 367 RegLocation rl_src) { 368 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 369 ThreadOffset<pointer_size> func_offset(-1); 370 const DexFile* dex_file = cu->dex_file; 371 CompilerDriver* driver = cu->compiler_driver; 372 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *dex_file, 373 type_idx)) { 374 bool is_type_initialized; // Ignored as an array does not have an initializer. 375 bool use_direct_type_ptr; 376 uintptr_t direct_type_ptr; 377 bool is_finalizable; 378 if (kEmbedClassInCode && 379 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 380 &direct_type_ptr, &is_finalizable)) { 381 // The fast path. 382 if (!use_direct_type_ptr) { 383 mir_to_lir->LoadClassType(type_idx, kArg0); 384 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 385 mir_to_lir->CallRuntimeHelperRegMethodRegLocation(func_offset, 386 mir_to_lir->TargetReg(kArg0, kNotWide), 387 rl_src, true); 388 } else { 389 // Use the direct pointer. 390 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 391 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, 392 true); 393 } 394 } else { 395 // The slow path. 396 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArray); 397 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 398 } 399 DCHECK_NE(func_offset.Int32Value(), -1); 400 } else { 401 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayWithAccessCheck); 402 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 403 } 404 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 405 mir_to_lir->StoreValue(rl_dest, rl_result); 406} 407 408/* 409 * Let helper function take care of everything. Will call 410 * Array::AllocFromCode(type_idx, method, count); 411 * Note: AllocFromCode will handle checks for errNegativeArraySize. 412 */ 413void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 414 RegLocation rl_src) { 415 if (cu_->target64) { 416 GenNewArrayImpl<8>(this, cu_, type_idx, rl_dest, rl_src); 417 } else { 418 GenNewArrayImpl<4>(this, cu_, type_idx, rl_dest, rl_src); 419 } 420} 421 422template <size_t pointer_size> 423static void GenFilledNewArrayCall(Mir2Lir* mir_to_lir, CompilationUnit* cu, int elems, int type_idx) { 424 ThreadOffset<pointer_size> func_offset(-1); 425 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *cu->dex_file, 426 type_idx)) { 427 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArray); 428 } else { 429 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArrayWithAccessCheck); 430 } 431 mir_to_lir->CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 432} 433 434/* 435 * Similar to GenNewArray, but with post-allocation initialization. 436 * Verifier guarantees we're dealing with an array class. Current 437 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 438 * Current code also throws internal unimp if not 'L', '[' or 'I'. 439 */ 440void Mir2Lir::GenFilledNewArray(CallInfo* info) { 441 int elems = info->num_arg_words; 442 int type_idx = info->index; 443 FlushAllRegs(); /* Everything to home location */ 444 if (cu_->target64) { 445 GenFilledNewArrayCall<8>(this, cu_, elems, type_idx); 446 } else { 447 GenFilledNewArrayCall<4>(this, cu_, elems, type_idx); 448 } 449 FreeTemp(TargetReg(kArg2, kNotWide)); 450 FreeTemp(TargetReg(kArg1, kNotWide)); 451 /* 452 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 453 * return region. Because AllocFromCode placed the new array 454 * in kRet0, we'll just lock it into place. When debugger support is 455 * added, it may be necessary to additionally copy all return 456 * values to a home location in thread-local storage 457 */ 458 RegStorage ref_reg = TargetReg(kRet0, kRef); 459 LockTemp(ref_reg); 460 461 // TODO: use the correct component size, currently all supported types 462 // share array alignment with ints (see comment at head of function) 463 size_t component_size = sizeof(int32_t); 464 465 // Having a range of 0 is legal 466 if (info->is_range && (elems > 0)) { 467 /* 468 * Bit of ugliness here. We're going generate a mem copy loop 469 * on the register range, but it is possible that some regs 470 * in the range have been promoted. This is unlikely, but 471 * before generating the copy, we'll just force a flush 472 * of any regs in the source range that have been promoted to 473 * home location. 474 */ 475 for (int i = 0; i < elems; i++) { 476 RegLocation loc = UpdateLoc(info->args[i]); 477 if (loc.location == kLocPhysReg) { 478 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 479 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 480 } 481 } 482 /* 483 * TUNING note: generated code here could be much improved, but 484 * this is an uncommon operation and isn't especially performance 485 * critical. 486 */ 487 // This is addressing the stack, which may be out of the 4G area. 488 RegStorage r_src = AllocTempRef(); 489 RegStorage r_dst = AllocTempRef(); 490 RegStorage r_idx = AllocTempRef(); // Not really a reference, but match src/dst. 491 RegStorage r_val; 492 switch (cu_->instruction_set) { 493 case kThumb2: 494 case kArm64: 495 r_val = TargetReg(kLr, kNotWide); 496 break; 497 case kX86: 498 case kX86_64: 499 FreeTemp(ref_reg); 500 r_val = AllocTemp(); 501 break; 502 case kMips: 503 r_val = AllocTemp(); 504 break; 505 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 506 } 507 // Set up source pointer 508 RegLocation rl_first = info->args[0]; 509 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); 510 // Set up the target pointer 511 OpRegRegImm(kOpAdd, r_dst, ref_reg, 512 mirror::Array::DataOffset(component_size).Int32Value()); 513 // Set up the loop counter (known to be > 0) 514 LoadConstant(r_idx, elems - 1); 515 // Generate the copy loop. Going backwards for convenience 516 LIR* target = NewLIR0(kPseudoTargetLabel); 517 // Copy next element 518 { 519 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 520 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32); 521 // NOTE: No dalvik register annotation, local optimizations will be stopped 522 // by the loop boundaries. 523 } 524 StoreBaseIndexed(r_dst, r_idx, r_val, 2, k32); 525 FreeTemp(r_val); 526 OpDecAndBranch(kCondGe, r_idx, target); 527 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 528 // Restore the target pointer 529 OpRegRegImm(kOpAdd, ref_reg, r_dst, 530 -mirror::Array::DataOffset(component_size).Int32Value()); 531 } 532 } else if (!info->is_range) { 533 // TUNING: interleave 534 for (int i = 0; i < elems; i++) { 535 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 536 Store32Disp(ref_reg, 537 mirror::Array::DataOffset(component_size).Int32Value() + i * 4, rl_arg.reg); 538 // If the LoadValue caused a temp to be allocated, free it 539 if (IsTemp(rl_arg.reg)) { 540 FreeTemp(rl_arg.reg); 541 } 542 } 543 } 544 if (info->result.location != kLocInvalid) { 545 StoreValue(info->result, GetReturn(kRefReg)); 546 } 547} 548 549// 550// Slow path to ensure a class is initialized for sget/sput. 551// 552class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 553 public: 554 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, int storage_index, 555 RegStorage r_base) : 556 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), 557 storage_index_(storage_index), r_base_(r_base) { 558 } 559 560 void Compile() { 561 LIR* unresolved_target = GenerateTargetLabel(); 562 uninit_->target = unresolved_target; 563 if (cu_->target64) { 564 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeStaticStorage), 565 storage_index_, true); 566 } else { 567 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeStaticStorage), 568 storage_index_, true); 569 } 570 // Copy helper's result into r_base, a no-op on all but MIPS. 571 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0, kRef)); 572 573 m2l_->OpUnconditionalBranch(cont_); 574 } 575 576 private: 577 LIR* const uninit_; 578 const int storage_index_; 579 const RegStorage r_base_; 580}; 581 582template <size_t pointer_size> 583static void GenSputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 584 const MirSFieldLoweringInfo* field_info, RegLocation rl_src) { 585 ThreadOffset<pointer_size> setter_offset = 586 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Static) 587 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjStatic) 588 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Static)); 589 mir_to_lir->CallRuntimeHelperImmRegLocation(setter_offset, field_info->FieldIndex(), rl_src, 590 true); 591} 592 593void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 594 bool is_object) { 595 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 596 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 597 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 598 if (!SLOW_FIELD_PATH && field_info.FastPut() && 599 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 600 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 601 RegStorage r_base; 602 if (field_info.IsReferrersClass()) { 603 // Fast path, static storage base is this method's class 604 RegLocation rl_method = LoadCurrMethod(); 605 r_base = AllocTempRef(); 606 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 607 kNotVolatile); 608 if (IsTemp(rl_method.reg)) { 609 FreeTemp(rl_method.reg); 610 } 611 } else { 612 // Medium path, static storage base in a different class which requires checks that the other 613 // class is initialized. 614 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 615 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 616 // May do runtime call so everything to home locations. 617 FlushAllRegs(); 618 // Using fixed register to sync with possible call to runtime support. 619 RegStorage r_method = TargetReg(kArg1, kRef); 620 LockTemp(r_method); 621 LoadCurrMethodDirect(r_method); 622 r_base = TargetReg(kArg0, kRef); 623 LockTemp(r_base); 624 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 625 kNotVolatile); 626 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 627 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 628 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 629 if (!field_info.IsInitialized() && 630 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 631 // Check if r_base is NULL or a not yet initialized class. 632 633 // The slow path is invoked if the r_base is NULL or the class pointed 634 // to by it is not initialized. 635 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 636 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 637 LockTemp(r_tmp); 638 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 639 mirror::Class::StatusOffset().Int32Value(), 640 mirror::Class::kStatusInitialized, nullptr, nullptr); 641 LIR* cont = NewLIR0(kPseudoTargetLabel); 642 643 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 644 field_info.StorageIndex(), r_base)); 645 646 FreeTemp(r_tmp); 647 // Ensure load of status and store of value don't re-order. 648 // TODO: Presumably the actual value store is control-dependent on the status load, 649 // and will thus not be reordered in any case, since stores are never speculated. 650 // Does later code "know" that the class is now initialized? If so, we still 651 // need the barrier to guard later static loads. 652 GenMemBarrier(kLoadAny); 653 } 654 FreeTemp(r_method); 655 } 656 // rBase now holds static storage base 657 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 658 if (is_long_or_double) { 659 rl_src = LoadValueWide(rl_src, reg_class); 660 } else { 661 rl_src = LoadValue(rl_src, reg_class); 662 } 663 if (is_object) { 664 StoreRefDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, 665 field_info.IsVolatile() ? kVolatile : kNotVolatile); 666 } else { 667 StoreBaseDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, store_size, 668 field_info.IsVolatile() ? kVolatile : kNotVolatile); 669 } 670 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 671 MarkGCCard(rl_src.reg, r_base); 672 } 673 FreeTemp(r_base); 674 } else { 675 FlushAllRegs(); // Everything to home locations 676 if (cu_->target64) { 677 GenSputCall<8>(this, is_long_or_double, is_object, &field_info, rl_src); 678 } else { 679 GenSputCall<4>(this, is_long_or_double, is_object, &field_info, rl_src); 680 } 681 } 682} 683 684template <size_t pointer_size> 685static void GenSgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 686 const MirSFieldLoweringInfo* field_info) { 687 ThreadOffset<pointer_size> getter_offset = 688 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Static) 689 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjStatic) 690 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Static)); 691 mir_to_lir->CallRuntimeHelperImm(getter_offset, field_info->FieldIndex(), true); 692} 693 694void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 695 bool is_long_or_double, bool is_object) { 696 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 697 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 698 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 699 if (!SLOW_FIELD_PATH && field_info.FastGet() && 700 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 701 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 702 RegStorage r_base; 703 if (field_info.IsReferrersClass()) { 704 // Fast path, static storage base is this method's class 705 RegLocation rl_method = LoadCurrMethod(); 706 r_base = AllocTempRef(); 707 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 708 kNotVolatile); 709 } else { 710 // Medium path, static storage base in a different class which requires checks that the other 711 // class is initialized 712 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 713 // May do runtime call so everything to home locations. 714 FlushAllRegs(); 715 // Using fixed register to sync with possible call to runtime support. 716 RegStorage r_method = TargetReg(kArg1, kRef); 717 LockTemp(r_method); 718 LoadCurrMethodDirect(r_method); 719 r_base = TargetReg(kArg0, kRef); 720 LockTemp(r_base); 721 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 722 kNotVolatile); 723 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 724 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 725 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 726 if (!field_info.IsInitialized() && 727 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 728 // Check if r_base is NULL or a not yet initialized class. 729 730 // The slow path is invoked if the r_base is NULL or the class pointed 731 // to by it is not initialized. 732 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 733 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 734 LockTemp(r_tmp); 735 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 736 mirror::Class::StatusOffset().Int32Value(), 737 mirror::Class::kStatusInitialized, nullptr, nullptr); 738 LIR* cont = NewLIR0(kPseudoTargetLabel); 739 740 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 741 field_info.StorageIndex(), r_base)); 742 743 FreeTemp(r_tmp); 744 // Ensure load of status and load of value don't re-order. 745 GenMemBarrier(kLoadAny); 746 } 747 FreeTemp(r_method); 748 } 749 // r_base now holds static storage base 750 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 751 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 752 753 int field_offset = field_info.FieldOffset().Int32Value(); 754 if (is_object) { 755 LoadRefDisp(r_base, field_offset, rl_result.reg, field_info.IsVolatile() ? kVolatile : 756 kNotVolatile); 757 } else { 758 LoadBaseDisp(r_base, field_offset, rl_result.reg, load_size, field_info.IsVolatile() ? 759 kVolatile : kNotVolatile); 760 } 761 FreeTemp(r_base); 762 763 if (is_long_or_double) { 764 StoreValueWide(rl_dest, rl_result); 765 } else { 766 StoreValue(rl_dest, rl_result); 767 } 768 } else { 769 FlushAllRegs(); // Everything to home locations 770 if (cu_->target64) { 771 GenSgetCall<8>(this, is_long_or_double, is_object, &field_info); 772 } else { 773 GenSgetCall<4>(this, is_long_or_double, is_object, &field_info); 774 } 775 // FIXME: pGetXXStatic always return an int or int64 regardless of rl_dest.fp. 776 if (is_long_or_double) { 777 RegLocation rl_result = GetReturnWide(kCoreReg); 778 StoreValueWide(rl_dest, rl_result); 779 } else { 780 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 781 StoreValue(rl_dest, rl_result); 782 } 783 } 784} 785 786// Generate code for all slow paths. 787void Mir2Lir::HandleSlowPaths() { 788 // We should check slow_paths_.Size() every time, because a new slow path 789 // may be created during slowpath->Compile(). 790 for (size_t i = 0; i < slow_paths_.Size(); ++i) { 791 LIRSlowPath* slowpath = slow_paths_.Get(i); 792 slowpath->Compile(); 793 } 794 slow_paths_.Reset(); 795} 796 797template <size_t pointer_size> 798static void GenIgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 799 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj) { 800 ThreadOffset<pointer_size> getter_offset = 801 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Instance) 802 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjInstance) 803 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Instance)); 804 mir_to_lir->CallRuntimeHelperImmRegLocation(getter_offset, field_info->FieldIndex(), rl_obj, 805 true); 806} 807 808void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 809 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 810 bool is_object) { 811 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 812 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 813 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 814 if (!SLOW_FIELD_PATH && field_info.FastGet() && 815 (!field_info.IsVolatile() || SupportsVolatileLoadStore(load_size))) { 816 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 817 // A load of the class will lead to an iget with offset 0. 818 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 819 rl_obj = LoadValue(rl_obj, kRefReg); 820 GenNullCheck(rl_obj.reg, opt_flags); 821 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 822 int field_offset = field_info.FieldOffset().Int32Value(); 823 LIR* load_lir; 824 if (is_object) { 825 load_lir = LoadRefDisp(rl_obj.reg, field_offset, rl_result.reg, field_info.IsVolatile() ? 826 kVolatile : kNotVolatile); 827 } else { 828 load_lir = LoadBaseDisp(rl_obj.reg, field_offset, rl_result.reg, load_size, 829 field_info.IsVolatile() ? kVolatile : kNotVolatile); 830 } 831 MarkPossibleNullPointerExceptionAfter(opt_flags, load_lir); 832 if (is_long_or_double) { 833 StoreValueWide(rl_dest, rl_result); 834 } else { 835 StoreValue(rl_dest, rl_result); 836 } 837 } else { 838 if (cu_->target64) { 839 GenIgetCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj); 840 } else { 841 GenIgetCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj); 842 } 843 // FIXME: pGetXXInstance always return an int or int64 regardless of rl_dest.fp. 844 if (is_long_or_double) { 845 RegLocation rl_result = GetReturnWide(kCoreReg); 846 StoreValueWide(rl_dest, rl_result); 847 } else { 848 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 849 StoreValue(rl_dest, rl_result); 850 } 851 } 852} 853 854template <size_t pointer_size> 855static void GenIputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 856 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj, 857 RegLocation rl_src) { 858 ThreadOffset<pointer_size> setter_offset = 859 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Instance) 860 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjInstance) 861 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Instance)); 862 mir_to_lir->CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info->FieldIndex(), 863 rl_obj, rl_src, true); 864} 865 866void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 867 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 868 bool is_object) { 869 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 870 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 871 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 872 if (!SLOW_FIELD_PATH && field_info.FastPut() && 873 (!field_info.IsVolatile() || SupportsVolatileLoadStore(store_size))) { 874 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 875 // Dex code never writes to the class field. 876 DCHECK_GE(static_cast<uint32_t>(field_info.FieldOffset().Int32Value()), 877 sizeof(mirror::HeapReference<mirror::Class>)); 878 rl_obj = LoadValue(rl_obj, kRefReg); 879 if (is_long_or_double) { 880 rl_src = LoadValueWide(rl_src, reg_class); 881 } else { 882 rl_src = LoadValue(rl_src, reg_class); 883 } 884 GenNullCheck(rl_obj.reg, opt_flags); 885 int field_offset = field_info.FieldOffset().Int32Value(); 886 LIR* store; 887 if (is_object) { 888 store = StoreRefDisp(rl_obj.reg, field_offset, rl_src.reg, field_info.IsVolatile() ? 889 kVolatile : kNotVolatile); 890 } else { 891 store = StoreBaseDisp(rl_obj.reg, field_offset, rl_src.reg, store_size, 892 field_info.IsVolatile() ? kVolatile : kNotVolatile); 893 } 894 MarkPossibleNullPointerExceptionAfter(opt_flags, store); 895 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 896 MarkGCCard(rl_src.reg, rl_obj.reg); 897 } 898 } else { 899 if (cu_->target64) { 900 GenIputCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 901 } else { 902 GenIputCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 903 } 904 } 905} 906 907template <size_t pointer_size> 908static void GenArrayObjPutCall(Mir2Lir* mir_to_lir, bool needs_range_check, bool needs_null_check, 909 RegLocation rl_array, RegLocation rl_index, RegLocation rl_src) { 910 ThreadOffset<pointer_size> helper = needs_range_check 911 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithNullAndBoundCheck) 912 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithBoundCheck)) 913 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObject); 914 mir_to_lir->CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, 915 true); 916} 917 918void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 919 RegLocation rl_src) { 920 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 921 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 922 (opt_flags & MIR_IGNORE_NULL_CHECK)); 923 if (cu_->target64) { 924 GenArrayObjPutCall<8>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 925 } else { 926 GenArrayObjPutCall<4>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 927 } 928} 929 930void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 931 RegLocation rl_method = LoadCurrMethod(); 932 CheckRegLocation(rl_method); 933 RegStorage res_reg = AllocTempRef(); 934 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 935 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 936 *cu_->dex_file, 937 type_idx)) { 938 // Call out to helper which resolves type and verifies access. 939 // Resolved type returned in kRet0. 940 if (cu_->target64) { 941 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 942 type_idx, rl_method.reg, true); 943 } else { 944 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 945 type_idx, rl_method.reg, true); 946 } 947 RegLocation rl_result = GetReturn(kRefReg); 948 StoreValue(rl_dest, rl_result); 949 } else { 950 // We're don't need access checks, load type from dex cache 951 int32_t dex_cache_offset = 952 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 953 LoadRefDisp(rl_method.reg, dex_cache_offset, res_reg, kNotVolatile); 954 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 955 LoadRefDisp(res_reg, offset_of_type, rl_result.reg, kNotVolatile); 956 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 957 type_idx) || SLOW_TYPE_PATH) { 958 // Slow path, at runtime test if type is null and if so initialize 959 FlushAllRegs(); 960 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg, 0, NULL); 961 LIR* cont = NewLIR0(kPseudoTargetLabel); 962 963 // Object to generate the slow path for class resolution. 964 class SlowPath : public LIRSlowPath { 965 public: 966 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 967 const RegLocation& rl_method, const RegLocation& rl_result) : 968 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 969 rl_method_(rl_method), rl_result_(rl_result) { 970 } 971 972 void Compile() { 973 GenerateTargetLabel(); 974 975 if (cu_->target64) { 976 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 977 rl_method_.reg, true); 978 } else { 979 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 980 rl_method_.reg, true); 981 } 982 m2l_->OpRegCopy(rl_result_.reg, m2l_->TargetReg(kRet0, kRef)); 983 984 m2l_->OpUnconditionalBranch(cont_); 985 } 986 987 private: 988 const int type_idx_; 989 const RegLocation rl_method_; 990 const RegLocation rl_result_; 991 }; 992 993 // Add to list for future. 994 AddSlowPath(new (arena_) SlowPath(this, branch, cont, type_idx, rl_method, rl_result)); 995 996 StoreValue(rl_dest, rl_result); 997 } else { 998 // Fast path, we're done - just store result 999 StoreValue(rl_dest, rl_result); 1000 } 1001 } 1002} 1003 1004void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 1005 /* NOTE: Most strings should be available at compile time */ 1006 int32_t offset_of_string = mirror::ObjectArray<mirror::String>::OffsetOfElement(string_idx). 1007 Int32Value(); 1008 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 1009 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 1010 // slow path, resolve string if not in dex cache 1011 FlushAllRegs(); 1012 LockCallTemps(); // Using explicit registers 1013 1014 // If the Method* is already in a register, we can save a copy. 1015 RegLocation rl_method = mir_graph_->GetMethodLoc(); 1016 RegStorage r_method; 1017 if (rl_method.location == kLocPhysReg) { 1018 // A temp would conflict with register use below. 1019 DCHECK(!IsTemp(rl_method.reg)); 1020 r_method = rl_method.reg; 1021 } else { 1022 r_method = TargetReg(kArg2, kRef); 1023 LoadCurrMethodDirect(r_method); 1024 } 1025 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 1026 TargetReg(kArg0, kRef), kNotVolatile); 1027 1028 // Might call out to helper, which will return resolved string in kRet0 1029 LoadRefDisp(TargetReg(kArg0, kRef), offset_of_string, TargetReg(kRet0, kRef), kNotVolatile); 1030 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0, kRef), 0, NULL); 1031 LIR* cont = NewLIR0(kPseudoTargetLabel); 1032 1033 { 1034 // Object to generate the slow path for string resolution. 1035 class SlowPath : public LIRSlowPath { 1036 public: 1037 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, RegStorage r_method, int32_t string_idx) : 1038 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), 1039 r_method_(r_method), string_idx_(string_idx) { 1040 } 1041 1042 void Compile() { 1043 GenerateTargetLabel(); 1044 if (cu_->target64) { 1045 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pResolveString), 1046 r_method_, string_idx_, true); 1047 } else { 1048 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pResolveString), 1049 r_method_, string_idx_, true); 1050 } 1051 m2l_->OpUnconditionalBranch(cont_); 1052 } 1053 1054 private: 1055 const RegStorage r_method_; 1056 const int32_t string_idx_; 1057 }; 1058 1059 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method, string_idx)); 1060 } 1061 1062 GenBarrier(); 1063 StoreValue(rl_dest, GetReturn(kRefReg)); 1064 } else { 1065 RegLocation rl_method = LoadCurrMethod(); 1066 RegStorage res_reg = AllocTempRef(); 1067 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1068 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg, 1069 kNotVolatile); 1070 LoadRefDisp(res_reg, offset_of_string, rl_result.reg, kNotVolatile); 1071 StoreValue(rl_dest, rl_result); 1072 } 1073} 1074 1075template <size_t pointer_size> 1076static void GenNewInstanceImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, uint32_t type_idx, 1077 RegLocation rl_dest) { 1078 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 1079 // alloc will always check for resolution, do we also need to verify 1080 // access because the verifier was unable to? 1081 ThreadOffset<pointer_size> func_offset(-1); 1082 const DexFile* dex_file = cu->dex_file; 1083 CompilerDriver* driver = cu->compiler_driver; 1084 if (driver->CanAccessInstantiableTypeWithoutChecks( 1085 cu->method_idx, *dex_file, type_idx)) { 1086 bool is_type_initialized; 1087 bool use_direct_type_ptr; 1088 uintptr_t direct_type_ptr; 1089 bool is_finalizable; 1090 if (kEmbedClassInCode && 1091 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 1092 &direct_type_ptr, &is_finalizable) && 1093 !is_finalizable) { 1094 // The fast path. 1095 if (!use_direct_type_ptr) { 1096 mir_to_lir->LoadClassType(type_idx, kArg0); 1097 if (!is_type_initialized) { 1098 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1099 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1100 true); 1101 } else { 1102 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1103 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1104 true); 1105 } 1106 } else { 1107 // Use the direct pointer. 1108 if (!is_type_initialized) { 1109 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1110 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1111 } else { 1112 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1113 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1114 } 1115 } 1116 } else { 1117 // The slow path. 1118 DCHECK_EQ(func_offset.Int32Value(), -1); 1119 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObject); 1120 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1121 } 1122 DCHECK_NE(func_offset.Int32Value(), -1); 1123 } else { 1124 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectWithAccessCheck); 1125 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1126 } 1127 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 1128 mir_to_lir->StoreValue(rl_dest, rl_result); 1129} 1130 1131/* 1132 * Let helper function take care of everything. Will 1133 * call Class::NewInstanceFromCode(type_idx, method); 1134 */ 1135void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 1136 if (cu_->target64) { 1137 GenNewInstanceImpl<8>(this, cu_, type_idx, rl_dest); 1138 } else { 1139 GenNewInstanceImpl<4>(this, cu_, type_idx, rl_dest); 1140 } 1141} 1142 1143void Mir2Lir::GenThrow(RegLocation rl_src) { 1144 FlushAllRegs(); 1145 if (cu_->target64) { 1146 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), rl_src, true); 1147 } else { 1148 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException), rl_src, true); 1149 } 1150} 1151 1152// For final classes there are no sub-classes to check and so we can answer the instance-of 1153// question with simple comparisons. 1154void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1155 RegLocation rl_src) { 1156 // X86 has its own implementation. 1157 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1158 1159 RegLocation object = LoadValue(rl_src, kRefReg); 1160 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1161 RegStorage result_reg = rl_result.reg; 1162 if (IsSameReg(result_reg, object.reg)) { 1163 result_reg = AllocTypedTemp(false, kCoreReg); 1164 DCHECK(!IsSameReg(result_reg, object.reg)); 1165 } 1166 LoadConstant(result_reg, 0); // assume false 1167 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 1168 1169 RegStorage check_class = AllocTypedTemp(false, kRefReg); 1170 RegStorage object_class = AllocTypedTemp(false, kRefReg); 1171 1172 LoadCurrMethodDirect(check_class); 1173 if (use_declaring_class) { 1174 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), check_class, 1175 kNotVolatile); 1176 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1177 kNotVolatile); 1178 } else { 1179 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1180 check_class, kNotVolatile); 1181 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1182 kNotVolatile); 1183 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1184 LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); 1185 } 1186 1187 // FIXME: what should we be comparing here? compressed or decompressed references? 1188 if (cu_->instruction_set == kThumb2) { 1189 OpRegReg(kOpCmp, check_class, object_class); // Same? 1190 LIR* it = OpIT(kCondEq, ""); // if-convert the test 1191 LoadConstant(result_reg, 1); // .eq case - load true 1192 OpEndIT(it); 1193 } else { 1194 GenSelectConst32(check_class, object_class, kCondEq, 1, 0, result_reg, kCoreReg); 1195 } 1196 LIR* target = NewLIR0(kPseudoTargetLabel); 1197 null_branchover->target = target; 1198 FreeTemp(object_class); 1199 FreeTemp(check_class); 1200 if (IsTemp(result_reg)) { 1201 OpRegCopy(rl_result.reg, result_reg); 1202 FreeTemp(result_reg); 1203 } 1204 StoreValue(rl_dest, rl_result); 1205} 1206 1207void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1208 bool type_known_abstract, bool use_declaring_class, 1209 bool can_assume_type_is_in_dex_cache, 1210 uint32_t type_idx, RegLocation rl_dest, 1211 RegLocation rl_src) { 1212 // X86 has its own implementation. 1213 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1214 1215 FlushAllRegs(); 1216 // May generate a call - use explicit registers 1217 LockCallTemps(); 1218 RegStorage method_reg = TargetReg(kArg1, kRef); 1219 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1220 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1221 if (needs_access_check) { 1222 // Check we have access to type_idx and if not throw IllegalAccessError, 1223 // returns Class* in kArg0 1224 if (cu_->target64) { 1225 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1226 type_idx, true); 1227 } else { 1228 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1229 type_idx, true); 1230 } 1231 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1232 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1233 } else if (use_declaring_class) { 1234 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1235 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1236 class_reg, kNotVolatile); 1237 } else { 1238 if (can_assume_type_is_in_dex_cache) { 1239 // Conditionally, as in the other case we will also load it. 1240 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1241 } 1242 1243 // Load dex cache entry into class_reg (kArg2) 1244 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1245 class_reg, kNotVolatile); 1246 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1247 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1248 if (!can_assume_type_is_in_dex_cache) { 1249 LIR* slow_path_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1250 LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); 1251 1252 // Should load value here. 1253 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1254 1255 class InitTypeSlowPath : public Mir2Lir::LIRSlowPath { 1256 public: 1257 InitTypeSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont, uint32_t type_idx, 1258 RegLocation rl_src) 1259 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont), type_idx_(type_idx), 1260 rl_src_(rl_src) { 1261 } 1262 1263 void Compile() OVERRIDE { 1264 GenerateTargetLabel(); 1265 1266 if (cu_->target64) { 1267 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1268 true); 1269 } else { 1270 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1271 true); 1272 } 1273 m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kRef), 1274 m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1275 1276 m2l_->OpUnconditionalBranch(cont_); 1277 } 1278 1279 private: 1280 uint32_t type_idx_; 1281 RegLocation rl_src_; 1282 }; 1283 1284 AddSlowPath(new (arena_) InitTypeSlowPath(this, slow_path_branch, slow_path_target, 1285 type_idx, rl_src)); 1286 } 1287 } 1288 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1289 RegLocation rl_result = GetReturn(kCoreReg); 1290 if (cu_->instruction_set == kMips) { 1291 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1292 LoadConstant(rl_result.reg, 0); 1293 } 1294 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, NULL); 1295 1296 /* load object->klass_ */ 1297 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1298 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1299 TargetReg(kArg1, kRef), kNotVolatile); 1300 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1301 LIR* branchover = NULL; 1302 if (type_known_final) { 1303 // rl_result == ref == null == 0. 1304 GenSelectConst32(TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), kCondEq, 1, 0, rl_result.reg, 1305 kCoreReg); 1306 } else { 1307 if (cu_->instruction_set == kThumb2) { 1308 RegStorage r_tgt = cu_->target64 ? 1309 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1310 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1311 LIR* it = nullptr; 1312 if (!type_known_abstract) { 1313 /* Uses conditional nullification */ 1314 OpRegReg(kOpCmp, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef)); // Same? 1315 it = OpIT(kCondEq, "EE"); // if-convert the test 1316 LoadConstant(TargetReg(kArg0, kNotWide), 1); // .eq case - load true 1317 } 1318 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1319 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1320 if (it != nullptr) { 1321 OpEndIT(it); 1322 } 1323 FreeTemp(r_tgt); 1324 } else { 1325 if (!type_known_abstract) { 1326 /* Uses branchovers */ 1327 LoadConstant(rl_result.reg, 1); // assume true 1328 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1329 } 1330 1331 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1332 if (cu_->target64) { 1333 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial), false); 1334 } else { 1335 CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial), false); 1336 } 1337 } 1338 } 1339 // TODO: only clobber when type isn't final? 1340 ClobberCallerSave(); 1341 /* branch targets here */ 1342 LIR* target = NewLIR0(kPseudoTargetLabel); 1343 StoreValue(rl_dest, rl_result); 1344 branch1->target = target; 1345 if (branchover != NULL) { 1346 branchover->target = target; 1347 } 1348} 1349 1350void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1351 bool type_known_final, type_known_abstract, use_declaring_class; 1352 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1353 *cu_->dex_file, 1354 type_idx, 1355 &type_known_final, 1356 &type_known_abstract, 1357 &use_declaring_class); 1358 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1359 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1360 1361 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1362 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1363 } else { 1364 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1365 use_declaring_class, can_assume_type_is_in_dex_cache, 1366 type_idx, rl_dest, rl_src); 1367 } 1368} 1369 1370void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1371 bool type_known_final, type_known_abstract, use_declaring_class; 1372 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1373 *cu_->dex_file, 1374 type_idx, 1375 &type_known_final, 1376 &type_known_abstract, 1377 &use_declaring_class); 1378 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1379 // of the exception throw path. 1380 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1381 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1382 // Verifier type analysis proved this check cast would never cause an exception. 1383 return; 1384 } 1385 FlushAllRegs(); 1386 // May generate a call - use explicit registers 1387 LockCallTemps(); 1388 RegStorage method_reg = TargetReg(kArg1, kRef); 1389 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1390 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1391 if (needs_access_check) { 1392 // Check we have access to type_idx and if not throw IllegalAccessError, 1393 // returns Class* in kRet0 1394 // InitializeTypeAndVerifyAccess(idx, method) 1395 if (cu_->target64) { 1396 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1397 type_idx, true); 1398 } else { 1399 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1400 type_idx, true); 1401 } 1402 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1403 } else if (use_declaring_class) { 1404 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1405 class_reg, kNotVolatile); 1406 } else { 1407 // Load dex cache entry into class_reg (kArg2) 1408 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1409 class_reg, kNotVolatile); 1410 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1411 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1412 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1413 // Need to test presence of type in dex cache at runtime 1414 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1415 LIR* cont = NewLIR0(kPseudoTargetLabel); 1416 1417 // Slow path to initialize the type. Executed if the type is NULL. 1418 class SlowPath : public LIRSlowPath { 1419 public: 1420 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1421 const RegStorage class_reg) : 1422 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1423 class_reg_(class_reg) { 1424 } 1425 1426 void Compile() { 1427 GenerateTargetLabel(); 1428 1429 // Call out to helper, which will return resolved type in kArg0 1430 // InitializeTypeFromCode(idx, method) 1431 if (m2l_->cu_->target64) { 1432 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1433 m2l_->TargetReg(kArg1, kRef), true); 1434 } else { 1435 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1436 m2l_->TargetReg(kArg1, kRef), true); 1437 } 1438 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1439 m2l_->OpUnconditionalBranch(cont_); 1440 } 1441 1442 public: 1443 const int type_idx_; 1444 const RegStorage class_reg_; 1445 }; 1446 1447 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, type_idx, class_reg)); 1448 } 1449 } 1450 // At this point, class_reg (kArg2) has class 1451 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1452 1453 // Slow path for the case where the classes are not equal. In this case we need 1454 // to call a helper function to do the check. 1455 class SlowPath : public LIRSlowPath { 1456 public: 1457 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1458 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1459 } 1460 1461 void Compile() { 1462 GenerateTargetLabel(); 1463 1464 if (load_) { 1465 m2l_->LoadRefDisp(m2l_->TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1466 m2l_->TargetReg(kArg1, kRef), kNotVolatile); 1467 } 1468 if (m2l_->cu_->target64) { 1469 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pCheckCast), 1470 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1471 true); 1472 } else { 1473 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pCheckCast), 1474 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1475 true); 1476 } 1477 1478 m2l_->OpUnconditionalBranch(cont_); 1479 } 1480 1481 private: 1482 const bool load_; 1483 }; 1484 1485 if (type_known_abstract) { 1486 // Easier case, run slow path if target is non-null (slow path will load from target) 1487 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0, kRef), 0, nullptr); 1488 LIR* cont = NewLIR0(kPseudoTargetLabel); 1489 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1490 } else { 1491 // Harder, more common case. We need to generate a forward branch over the load 1492 // if the target is null. If it's non-null we perform the load and branch to the 1493 // slow path if the classes are not equal. 1494 1495 /* Null is OK - continue */ 1496 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, nullptr); 1497 /* load object->klass_ */ 1498 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1499 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1500 TargetReg(kArg1, kRef), kNotVolatile); 1501 1502 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), class_reg, nullptr); 1503 LIR* cont = NewLIR0(kPseudoTargetLabel); 1504 1505 // Add the slow path that will not perform load since this is already done. 1506 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1507 1508 // Set the null check to branch to the continuation. 1509 branch1->target = cont; 1510 } 1511} 1512 1513void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1514 RegLocation rl_src1, RegLocation rl_src2) { 1515 RegLocation rl_result; 1516 if (cu_->instruction_set == kThumb2) { 1517 /* 1518 * NOTE: This is the one place in the code in which we might have 1519 * as many as six live temporary registers. There are 5 in the normal 1520 * set for Arm. Until we have spill capabilities, temporarily add 1521 * lr to the temp set. It is safe to do this locally, but note that 1522 * lr is used explicitly elsewhere in the code generator and cannot 1523 * normally be used as a general temp register. 1524 */ 1525 MarkTemp(TargetReg(kLr, kNotWide)); // Add lr to the temp pool 1526 FreeTemp(TargetReg(kLr, kNotWide)); // and make it available 1527 } 1528 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1529 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1530 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1531 // The longs may overlap - use intermediate temp if so 1532 if ((rl_result.reg.GetLowReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg())) { 1533 RegStorage t_reg = AllocTemp(); 1534 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1535 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1536 OpRegCopy(rl_result.reg.GetLow(), t_reg); 1537 FreeTemp(t_reg); 1538 } else { 1539 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1540 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1541 } 1542 /* 1543 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1544 * following StoreValueWide might need to allocate a temp register. 1545 * To further work around the lack of a spill capability, explicitly 1546 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1547 * Remove when spill is functional. 1548 */ 1549 FreeRegLocTemps(rl_result, rl_src1); 1550 FreeRegLocTemps(rl_result, rl_src2); 1551 StoreValueWide(rl_dest, rl_result); 1552 if (cu_->instruction_set == kThumb2) { 1553 Clobber(TargetReg(kLr, kNotWide)); 1554 UnmarkTemp(TargetReg(kLr, kNotWide)); // Remove lr from the temp pool 1555 } 1556} 1557 1558 1559template <size_t pointer_size> 1560static void GenShiftOpLongCall(Mir2Lir* mir_to_lir, Instruction::Code opcode, RegLocation rl_src1, 1561 RegLocation rl_shift) { 1562 ThreadOffset<pointer_size> func_offset(-1); 1563 1564 switch (opcode) { 1565 case Instruction::SHL_LONG: 1566 case Instruction::SHL_LONG_2ADDR: 1567 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShlLong); 1568 break; 1569 case Instruction::SHR_LONG: 1570 case Instruction::SHR_LONG_2ADDR: 1571 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShrLong); 1572 break; 1573 case Instruction::USHR_LONG: 1574 case Instruction::USHR_LONG_2ADDR: 1575 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pUshrLong); 1576 break; 1577 default: 1578 LOG(FATAL) << "Unexpected case"; 1579 } 1580 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 1581 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1582} 1583 1584void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1585 RegLocation rl_src1, RegLocation rl_shift) { 1586 if (cu_->target64) { 1587 GenShiftOpLongCall<8>(this, opcode, rl_src1, rl_shift); 1588 } else { 1589 GenShiftOpLongCall<4>(this, opcode, rl_src1, rl_shift); 1590 } 1591 RegLocation rl_result = GetReturnWide(kCoreReg); 1592 StoreValueWide(rl_dest, rl_result); 1593} 1594 1595 1596void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1597 RegLocation rl_src1, RegLocation rl_src2) { 1598 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1599 OpKind op = kOpBkpt; 1600 bool is_div_rem = false; 1601 bool check_zero = false; 1602 bool unary = false; 1603 RegLocation rl_result; 1604 bool shift_op = false; 1605 switch (opcode) { 1606 case Instruction::NEG_INT: 1607 op = kOpNeg; 1608 unary = true; 1609 break; 1610 case Instruction::NOT_INT: 1611 op = kOpMvn; 1612 unary = true; 1613 break; 1614 case Instruction::ADD_INT: 1615 case Instruction::ADD_INT_2ADDR: 1616 op = kOpAdd; 1617 break; 1618 case Instruction::SUB_INT: 1619 case Instruction::SUB_INT_2ADDR: 1620 op = kOpSub; 1621 break; 1622 case Instruction::MUL_INT: 1623 case Instruction::MUL_INT_2ADDR: 1624 op = kOpMul; 1625 break; 1626 case Instruction::DIV_INT: 1627 case Instruction::DIV_INT_2ADDR: 1628 check_zero = true; 1629 op = kOpDiv; 1630 is_div_rem = true; 1631 break; 1632 /* NOTE: returns in kArg1 */ 1633 case Instruction::REM_INT: 1634 case Instruction::REM_INT_2ADDR: 1635 check_zero = true; 1636 op = kOpRem; 1637 is_div_rem = true; 1638 break; 1639 case Instruction::AND_INT: 1640 case Instruction::AND_INT_2ADDR: 1641 op = kOpAnd; 1642 break; 1643 case Instruction::OR_INT: 1644 case Instruction::OR_INT_2ADDR: 1645 op = kOpOr; 1646 break; 1647 case Instruction::XOR_INT: 1648 case Instruction::XOR_INT_2ADDR: 1649 op = kOpXor; 1650 break; 1651 case Instruction::SHL_INT: 1652 case Instruction::SHL_INT_2ADDR: 1653 shift_op = true; 1654 op = kOpLsl; 1655 break; 1656 case Instruction::SHR_INT: 1657 case Instruction::SHR_INT_2ADDR: 1658 shift_op = true; 1659 op = kOpAsr; 1660 break; 1661 case Instruction::USHR_INT: 1662 case Instruction::USHR_INT_2ADDR: 1663 shift_op = true; 1664 op = kOpLsr; 1665 break; 1666 default: 1667 LOG(FATAL) << "Invalid word arith op: " << opcode; 1668 } 1669 if (!is_div_rem) { 1670 if (unary) { 1671 rl_src1 = LoadValue(rl_src1, kCoreReg); 1672 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1673 OpRegReg(op, rl_result.reg, rl_src1.reg); 1674 } else { 1675 if ((shift_op) && (cu_->instruction_set != kArm64)) { 1676 rl_src2 = LoadValue(rl_src2, kCoreReg); 1677 RegStorage t_reg = AllocTemp(); 1678 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg, 31); 1679 rl_src1 = LoadValue(rl_src1, kCoreReg); 1680 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1681 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 1682 FreeTemp(t_reg); 1683 } else { 1684 rl_src1 = LoadValue(rl_src1, kCoreReg); 1685 rl_src2 = LoadValue(rl_src2, kCoreReg); 1686 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1687 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); 1688 } 1689 } 1690 StoreValue(rl_dest, rl_result); 1691 } else { 1692 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1693 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1694 rl_src1 = LoadValue(rl_src1, kCoreReg); 1695 rl_src2 = LoadValue(rl_src2, kCoreReg); 1696 if (check_zero) { 1697 GenDivZeroCheck(rl_src2.reg); 1698 } 1699 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1700 done = true; 1701 } else if (cu_->instruction_set == kThumb2) { 1702 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1703 // Use ARM SDIV instruction for division. For remainder we also need to 1704 // calculate using a MUL and subtract. 1705 rl_src1 = LoadValue(rl_src1, kCoreReg); 1706 rl_src2 = LoadValue(rl_src2, kCoreReg); 1707 if (check_zero) { 1708 GenDivZeroCheck(rl_src2.reg); 1709 } 1710 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1711 done = true; 1712 } 1713 } 1714 1715 // If we haven't already generated the code use the callout function. 1716 if (!done) { 1717 FlushAllRegs(); /* Send everything to home location */ 1718 LoadValueDirectFixed(rl_src2, TargetReg(kArg1, kNotWide)); 1719 RegStorage r_tgt = cu_->target64 ? 1720 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod)) : 1721 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod)); 1722 LoadValueDirectFixed(rl_src1, TargetReg(kArg0, kNotWide)); 1723 if (check_zero) { 1724 GenDivZeroCheck(TargetReg(kArg1, kNotWide)); 1725 } 1726 // NOTE: callout here is not a safepoint. 1727 if (cu_->target64) { 1728 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), false /* not a safepoint */); 1729 } else { 1730 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), false /* not a safepoint */); 1731 } 1732 if (op == kOpDiv) 1733 rl_result = GetReturn(kCoreReg); 1734 else 1735 rl_result = GetReturnAlt(); 1736 } 1737 StoreValue(rl_dest, rl_result); 1738 } 1739} 1740 1741/* 1742 * The following are the first-level codegen routines that analyze the format 1743 * of each bytecode then either dispatch special purpose codegen routines 1744 * or produce corresponding Thumb instructions directly. 1745 */ 1746 1747// Returns true if no more than two bits are set in 'x'. 1748static bool IsPopCountLE2(unsigned int x) { 1749 x &= x - 1; 1750 return (x & (x - 1)) == 0; 1751} 1752 1753// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1754// and store the result in 'rl_dest'. 1755bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1756 RegLocation rl_src, RegLocation rl_dest, int lit) { 1757 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1758 return false; 1759 } 1760 // No divide instruction for Arm, so check for more special cases 1761 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1762 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1763 } 1764 int k = LowestSetBit(lit); 1765 if (k >= 30) { 1766 // Avoid special cases. 1767 return false; 1768 } 1769 rl_src = LoadValue(rl_src, kCoreReg); 1770 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1771 if (is_div) { 1772 RegStorage t_reg = AllocTemp(); 1773 if (lit == 2) { 1774 // Division by 2 is by far the most common division by constant. 1775 OpRegRegImm(kOpLsr, t_reg, rl_src.reg, 32 - k); 1776 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1777 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1778 } else { 1779 OpRegRegImm(kOpAsr, t_reg, rl_src.reg, 31); 1780 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1781 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1782 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1783 } 1784 } else { 1785 RegStorage t_reg1 = AllocTemp(); 1786 RegStorage t_reg2 = AllocTemp(); 1787 if (lit == 2) { 1788 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg, 32 - k); 1789 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1790 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1791 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1792 } else { 1793 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg, 31); 1794 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1795 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1796 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1797 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1798 } 1799 } 1800 StoreValue(rl_dest, rl_result); 1801 return true; 1802} 1803 1804// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1805// and store the result in 'rl_dest'. 1806bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1807 if (lit < 0) { 1808 return false; 1809 } 1810 if (lit == 0) { 1811 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1812 LoadConstant(rl_result.reg, 0); 1813 StoreValue(rl_dest, rl_result); 1814 return true; 1815 } 1816 if (lit == 1) { 1817 rl_src = LoadValue(rl_src, kCoreReg); 1818 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1819 OpRegCopy(rl_result.reg, rl_src.reg); 1820 StoreValue(rl_dest, rl_result); 1821 return true; 1822 } 1823 // There is RegRegRegShift on Arm, so check for more special cases 1824 if (cu_->instruction_set == kThumb2) { 1825 return EasyMultiply(rl_src, rl_dest, lit); 1826 } 1827 // Can we simplify this multiplication? 1828 bool power_of_two = false; 1829 bool pop_count_le2 = false; 1830 bool power_of_two_minus_one = false; 1831 if (IsPowerOfTwo(lit)) { 1832 power_of_two = true; 1833 } else if (IsPopCountLE2(lit)) { 1834 pop_count_le2 = true; 1835 } else if (IsPowerOfTwo(lit + 1)) { 1836 power_of_two_minus_one = true; 1837 } else { 1838 return false; 1839 } 1840 rl_src = LoadValue(rl_src, kCoreReg); 1841 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1842 if (power_of_two) { 1843 // Shift. 1844 OpRegRegImm(kOpLsl, rl_result.reg, rl_src.reg, LowestSetBit(lit)); 1845 } else if (pop_count_le2) { 1846 // Shift and add and shift. 1847 int first_bit = LowestSetBit(lit); 1848 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1849 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1850 } else { 1851 // Reverse subtract: (src << (shift + 1)) - src. 1852 DCHECK(power_of_two_minus_one); 1853 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1854 RegStorage t_reg = AllocTemp(); 1855 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, LowestSetBit(lit + 1)); 1856 OpRegRegReg(kOpSub, rl_result.reg, t_reg, rl_src.reg); 1857 } 1858 StoreValue(rl_dest, rl_result); 1859 return true; 1860} 1861 1862void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1863 int lit) { 1864 RegLocation rl_result; 1865 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1866 int shift_op = false; 1867 bool is_div = false; 1868 1869 switch (opcode) { 1870 case Instruction::RSUB_INT_LIT8: 1871 case Instruction::RSUB_INT: { 1872 rl_src = LoadValue(rl_src, kCoreReg); 1873 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1874 if (cu_->instruction_set == kThumb2) { 1875 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, lit); 1876 } else { 1877 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1878 OpRegImm(kOpAdd, rl_result.reg, lit); 1879 } 1880 StoreValue(rl_dest, rl_result); 1881 return; 1882 } 1883 1884 case Instruction::SUB_INT: 1885 case Instruction::SUB_INT_2ADDR: 1886 lit = -lit; 1887 // Intended fallthrough 1888 case Instruction::ADD_INT: 1889 case Instruction::ADD_INT_2ADDR: 1890 case Instruction::ADD_INT_LIT8: 1891 case Instruction::ADD_INT_LIT16: 1892 op = kOpAdd; 1893 break; 1894 case Instruction::MUL_INT: 1895 case Instruction::MUL_INT_2ADDR: 1896 case Instruction::MUL_INT_LIT8: 1897 case Instruction::MUL_INT_LIT16: { 1898 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1899 return; 1900 } 1901 op = kOpMul; 1902 break; 1903 } 1904 case Instruction::AND_INT: 1905 case Instruction::AND_INT_2ADDR: 1906 case Instruction::AND_INT_LIT8: 1907 case Instruction::AND_INT_LIT16: 1908 op = kOpAnd; 1909 break; 1910 case Instruction::OR_INT: 1911 case Instruction::OR_INT_2ADDR: 1912 case Instruction::OR_INT_LIT8: 1913 case Instruction::OR_INT_LIT16: 1914 op = kOpOr; 1915 break; 1916 case Instruction::XOR_INT: 1917 case Instruction::XOR_INT_2ADDR: 1918 case Instruction::XOR_INT_LIT8: 1919 case Instruction::XOR_INT_LIT16: 1920 op = kOpXor; 1921 break; 1922 case Instruction::SHL_INT_LIT8: 1923 case Instruction::SHL_INT: 1924 case Instruction::SHL_INT_2ADDR: 1925 lit &= 31; 1926 shift_op = true; 1927 op = kOpLsl; 1928 break; 1929 case Instruction::SHR_INT_LIT8: 1930 case Instruction::SHR_INT: 1931 case Instruction::SHR_INT_2ADDR: 1932 lit &= 31; 1933 shift_op = true; 1934 op = kOpAsr; 1935 break; 1936 case Instruction::USHR_INT_LIT8: 1937 case Instruction::USHR_INT: 1938 case Instruction::USHR_INT_2ADDR: 1939 lit &= 31; 1940 shift_op = true; 1941 op = kOpLsr; 1942 break; 1943 1944 case Instruction::DIV_INT: 1945 case Instruction::DIV_INT_2ADDR: 1946 case Instruction::DIV_INT_LIT8: 1947 case Instruction::DIV_INT_LIT16: 1948 case Instruction::REM_INT: 1949 case Instruction::REM_INT_2ADDR: 1950 case Instruction::REM_INT_LIT8: 1951 case Instruction::REM_INT_LIT16: { 1952 if (lit == 0) { 1953 GenDivZeroException(); 1954 return; 1955 } 1956 if ((opcode == Instruction::DIV_INT) || 1957 (opcode == Instruction::DIV_INT_2ADDR) || 1958 (opcode == Instruction::DIV_INT_LIT8) || 1959 (opcode == Instruction::DIV_INT_LIT16)) { 1960 is_div = true; 1961 } else { 1962 is_div = false; 1963 } 1964 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1965 return; 1966 } 1967 1968 bool done = false; 1969 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1970 rl_src = LoadValue(rl_src, kCoreReg); 1971 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1972 done = true; 1973 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1974 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1975 done = true; 1976 } else if (cu_->instruction_set == kThumb2) { 1977 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1978 // Use ARM SDIV instruction for division. For remainder we also need to 1979 // calculate using a MUL and subtract. 1980 rl_src = LoadValue(rl_src, kCoreReg); 1981 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1982 done = true; 1983 } 1984 } 1985 1986 if (!done) { 1987 FlushAllRegs(); /* Everything to home location. */ 1988 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kNotWide)); 1989 Clobber(TargetReg(kArg0, kNotWide)); 1990 if (cu_->target64) { 1991 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), TargetReg(kArg0, kNotWide), 1992 lit, false); 1993 } else { 1994 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), TargetReg(kArg0, kNotWide), 1995 lit, false); 1996 } 1997 if (is_div) 1998 rl_result = GetReturn(kCoreReg); 1999 else 2000 rl_result = GetReturnAlt(); 2001 } 2002 StoreValue(rl_dest, rl_result); 2003 return; 2004 } 2005 default: 2006 LOG(FATAL) << "Unexpected opcode " << opcode; 2007 } 2008 rl_src = LoadValue(rl_src, kCoreReg); 2009 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2010 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 2011 if (shift_op && (lit == 0)) { 2012 OpRegCopy(rl_result.reg, rl_src.reg); 2013 } else { 2014 OpRegRegImm(op, rl_result.reg, rl_src.reg, lit); 2015 } 2016 StoreValue(rl_dest, rl_result); 2017} 2018 2019template <size_t pointer_size> 2020static void GenArithOpLongImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, Instruction::Code opcode, 2021 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 2022 RegLocation rl_result; 2023 OpKind first_op = kOpBkpt; 2024 OpKind second_op = kOpBkpt; 2025 bool call_out = false; 2026 bool check_zero = false; 2027 ThreadOffset<pointer_size> func_offset(-1); 2028 int ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2029 2030 switch (opcode) { 2031 case Instruction::NOT_LONG: 2032 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2033 mir_to_lir->GenNotLong(rl_dest, rl_src2); 2034 return; 2035 } 2036 rl_src2 = mir_to_lir->LoadValueWide(rl_src2, kCoreReg); 2037 rl_result = mir_to_lir->EvalLoc(rl_dest, kCoreReg, true); 2038 // Check for destructive overlap 2039 if (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg()) { 2040 RegStorage t_reg = mir_to_lir->AllocTemp(); 2041 mir_to_lir->OpRegCopy(t_reg, rl_src2.reg.GetHigh()); 2042 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2043 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), t_reg); 2044 mir_to_lir->FreeTemp(t_reg); 2045 } else { 2046 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2047 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); 2048 } 2049 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2050 return; 2051 case Instruction::ADD_LONG: 2052 case Instruction::ADD_LONG_2ADDR: 2053 if (cu->instruction_set != kThumb2) { 2054 mir_to_lir->GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 2055 return; 2056 } 2057 first_op = kOpAdd; 2058 second_op = kOpAdc; 2059 break; 2060 case Instruction::SUB_LONG: 2061 case Instruction::SUB_LONG_2ADDR: 2062 if (cu->instruction_set != kThumb2) { 2063 mir_to_lir->GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 2064 return; 2065 } 2066 first_op = kOpSub; 2067 second_op = kOpSbc; 2068 break; 2069 case Instruction::MUL_LONG: 2070 case Instruction::MUL_LONG_2ADDR: 2071 if (cu->instruction_set != kMips) { 2072 mir_to_lir->GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 2073 return; 2074 } else { 2075 call_out = true; 2076 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2077 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmul); 2078 } 2079 break; 2080 case Instruction::DIV_LONG: 2081 case Instruction::DIV_LONG_2ADDR: 2082 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2083 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); 2084 return; 2085 } 2086 call_out = true; 2087 check_zero = true; 2088 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2089 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLdiv); 2090 break; 2091 case Instruction::REM_LONG: 2092 case Instruction::REM_LONG_2ADDR: 2093 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2094 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); 2095 return; 2096 } 2097 call_out = true; 2098 check_zero = true; 2099 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmod); 2100 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 2101 ret_reg = (cu->instruction_set == kThumb2) ? mir_to_lir->TargetReg(kArg2, kNotWide).GetReg() : 2102 mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2103 break; 2104 case Instruction::AND_LONG_2ADDR: 2105 case Instruction::AND_LONG: 2106 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2107 cu->instruction_set == kArm64) { 2108 return mir_to_lir->GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 2109 } 2110 first_op = kOpAnd; 2111 second_op = kOpAnd; 2112 break; 2113 case Instruction::OR_LONG: 2114 case Instruction::OR_LONG_2ADDR: 2115 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2116 cu->instruction_set == kArm64) { 2117 mir_to_lir->GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 2118 return; 2119 } 2120 first_op = kOpOr; 2121 second_op = kOpOr; 2122 break; 2123 case Instruction::XOR_LONG: 2124 case Instruction::XOR_LONG_2ADDR: 2125 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2126 cu->instruction_set == kArm64) { 2127 mir_to_lir->GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 2128 return; 2129 } 2130 first_op = kOpXor; 2131 second_op = kOpXor; 2132 break; 2133 case Instruction::NEG_LONG: { 2134 mir_to_lir->GenNegLong(rl_dest, rl_src2); 2135 return; 2136 } 2137 default: 2138 LOG(FATAL) << "Invalid long arith op"; 2139 } 2140 if (!call_out) { 2141 mir_to_lir->GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 2142 } else { 2143 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 2144 if (check_zero) { 2145 RegStorage r_tmp1 = mir_to_lir->TargetReg(kArg0, kWide); 2146 RegStorage r_tmp2 = mir_to_lir->TargetReg(kArg2, kWide); 2147 mir_to_lir->LoadValueDirectWideFixed(rl_src2, r_tmp2); 2148 RegStorage r_tgt = mir_to_lir->CallHelperSetup(func_offset); 2149 mir_to_lir->GenDivZeroCheckWide(r_tmp2); 2150 mir_to_lir->LoadValueDirectWideFixed(rl_src1, r_tmp1); 2151 // NOTE: callout here is not a safepoint 2152 mir_to_lir->CallHelper(r_tgt, func_offset, false /* not safepoint */); 2153 } else { 2154 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 2155 } 2156 // Adjust return regs in to handle case of rem returning kArg2/kArg3 2157 if (ret_reg == mir_to_lir->TargetReg(kRet0, kNotWide).GetReg()) 2158 rl_result = mir_to_lir->GetReturnWide(kCoreReg); 2159 else 2160 rl_result = mir_to_lir->GetReturnWideAlt(); 2161 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2162 } 2163} 2164 2165void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 2166 RegLocation rl_src1, RegLocation rl_src2) { 2167 if (cu_->target64) { 2168 GenArithOpLongImpl<8>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2169 } else { 2170 GenArithOpLongImpl<4>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2171 } 2172} 2173 2174void Mir2Lir::GenConst(RegLocation rl_dest, int value) { 2175 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2176 LoadConstantNoClobber(rl_result.reg, value); 2177 StoreValue(rl_dest, rl_result); 2178 if (value == 0) { 2179 Workaround7250540(rl_dest, rl_result.reg); 2180 } 2181} 2182 2183template <size_t pointer_size> 2184void Mir2Lir::GenConversionCall(ThreadOffset<pointer_size> func_offset, 2185 RegLocation rl_dest, RegLocation rl_src) { 2186 /* 2187 * Don't optimize the register usage since it calls out to support 2188 * functions 2189 */ 2190 DCHECK_EQ(pointer_size, GetInstructionSetPointerSize(cu_->instruction_set)); 2191 2192 FlushAllRegs(); /* Send everything to home location */ 2193 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 2194 if (rl_dest.wide) { 2195 RegLocation rl_result; 2196 rl_result = GetReturnWide(LocToRegClass(rl_dest)); 2197 StoreValueWide(rl_dest, rl_result); 2198 } else { 2199 RegLocation rl_result; 2200 rl_result = GetReturn(LocToRegClass(rl_dest)); 2201 StoreValue(rl_dest, rl_result); 2202 } 2203} 2204template void Mir2Lir::GenConversionCall(ThreadOffset<4> func_offset, 2205 RegLocation rl_dest, RegLocation rl_src); 2206template void Mir2Lir::GenConversionCall(ThreadOffset<8> func_offset, 2207 RegLocation rl_dest, RegLocation rl_src); 2208 2209class SuspendCheckSlowPath : public Mir2Lir::LIRSlowPath { 2210 public: 2211 SuspendCheckSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont) 2212 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont) { 2213 } 2214 2215 void Compile() OVERRIDE { 2216 m2l_->ResetRegPool(); 2217 m2l_->ResetDefTracking(); 2218 GenerateTargetLabel(kPseudoSuspendTarget); 2219 if (cu_->target64) { 2220 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pTestSuspend), true); 2221 } else { 2222 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pTestSuspend), true); 2223 } 2224 if (cont_ != nullptr) { 2225 m2l_->OpUnconditionalBranch(cont_); 2226 } 2227 } 2228}; 2229 2230/* Check if we need to check for pending suspend request */ 2231void Mir2Lir::GenSuspendTest(int opt_flags) { 2232 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2233 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2234 return; 2235 } 2236 FlushAllRegs(); 2237 LIR* branch = OpTestSuspend(NULL); 2238 LIR* cont = NewLIR0(kPseudoTargetLabel); 2239 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, cont)); 2240 } else { 2241 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2242 return; 2243 } 2244 FlushAllRegs(); // TODO: needed? 2245 LIR* inst = CheckSuspendUsingLoad(); 2246 MarkSafepointPC(inst); 2247 } 2248} 2249 2250/* Check if we need to check for pending suspend request */ 2251void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 2252 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitSuspendChecks()) { 2253 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2254 OpUnconditionalBranch(target); 2255 return; 2256 } 2257 OpTestSuspend(target); 2258 FlushAllRegs(); 2259 LIR* branch = OpUnconditionalBranch(nullptr); 2260 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, target)); 2261 } else { 2262 // For the implicit suspend check, just perform the trigger 2263 // load and branch to the target. 2264 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2265 OpUnconditionalBranch(target); 2266 return; 2267 } 2268 FlushAllRegs(); 2269 LIR* inst = CheckSuspendUsingLoad(); 2270 MarkSafepointPC(inst); 2271 OpUnconditionalBranch(target); 2272 } 2273} 2274 2275/* Call out to helper assembly routine that will null check obj and then lock it. */ 2276void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2277 FlushAllRegs(); 2278 if (cu_->target64) { 2279 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pLockObject), rl_src, true); 2280 } else { 2281 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pLockObject), rl_src, true); 2282 } 2283} 2284 2285/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2286void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2287 FlushAllRegs(); 2288 if (cu_->target64) { 2289 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject), rl_src, true); 2290 } else { 2291 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject), rl_src, true); 2292 } 2293} 2294 2295/* Generic code for generating a wide constant into a VR. */ 2296void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2297 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2298 LoadConstantWide(rl_result.reg, value); 2299 StoreValueWide(rl_dest, rl_result); 2300} 2301 2302} // namespace art 2303