gen_common.cc revision d9cb8ae2ed78f957a773af61759432d7a7bf78af
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include "dex/compiler_ir.h" 17#include "dex/compiler_internals.h" 18#include "dex/quick/arm/arm_lir.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object_array-inl.h" 23#include "mirror/object-inl.h" 24#include "verifier/method_verifier.h" 25#include <functional> 26 27namespace art { 28 29// Shortcuts to repeatedly used long types. 30typedef mirror::ObjectArray<mirror::Object> ObjArray; 31typedef mirror::ObjectArray<mirror::Class> ClassArray; 32 33/* 34 * This source files contains "gen" codegen routines that should 35 * be applicable to most targets. Only mid-level support utilities 36 * and "op" calls may be used here. 37 */ 38 39/* 40 * Generate a kPseudoBarrier marker to indicate the boundary of special 41 * blocks. 42 */ 43void Mir2Lir::GenBarrier() { 44 LIR* barrier = NewLIR0(kPseudoBarrier); 45 /* Mark all resources as being clobbered */ 46 DCHECK(!barrier->flags.use_def_invalid); 47 barrier->u.m.def_mask = &kEncodeAll; 48} 49 50void Mir2Lir::GenDivZeroException() { 51 LIR* branch = OpUnconditionalBranch(nullptr); 52 AddDivZeroCheckSlowPath(branch); 53} 54 55void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { 56 LIR* branch = OpCondBranch(c_code, nullptr); 57 AddDivZeroCheckSlowPath(branch); 58} 59 60void Mir2Lir::GenDivZeroCheck(RegStorage reg) { 61 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 62 AddDivZeroCheckSlowPath(branch); 63} 64 65void Mir2Lir::AddDivZeroCheckSlowPath(LIR* branch) { 66 class DivZeroCheckSlowPath : public Mir2Lir::LIRSlowPath { 67 public: 68 DivZeroCheckSlowPath(Mir2Lir* m2l, LIR* branch) 69 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 70 } 71 72 void Compile() OVERRIDE { 73 m2l_->ResetRegPool(); 74 m2l_->ResetDefTracking(); 75 GenerateTargetLabel(kPseudoThrowTarget); 76 if (m2l_->cu_->target64) { 77 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowDivZero), true); 78 } else { 79 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowDivZero), true); 80 } 81 } 82 }; 83 84 AddSlowPath(new (arena_) DivZeroCheckSlowPath(this, branch)); 85} 86 87void Mir2Lir::GenArrayBoundsCheck(RegStorage index, RegStorage length) { 88 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 89 public: 90 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, RegStorage index, RegStorage length) 91 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 92 index_(index), length_(length) { 93 } 94 95 void Compile() OVERRIDE { 96 m2l_->ResetRegPool(); 97 m2l_->ResetDefTracking(); 98 GenerateTargetLabel(kPseudoThrowTarget); 99 if (m2l_->cu_->target64) { 100 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 101 index_, length_, true); 102 } else { 103 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 104 index_, length_, true); 105 } 106 } 107 108 private: 109 const RegStorage index_; 110 const RegStorage length_; 111 }; 112 113 LIR* branch = OpCmpBranch(kCondUge, index, length, nullptr); 114 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 115} 116 117void Mir2Lir::GenArrayBoundsCheck(int index, RegStorage length) { 118 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 119 public: 120 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, int index, RegStorage length) 121 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 122 index_(index), length_(length) { 123 } 124 125 void Compile() OVERRIDE { 126 m2l_->ResetRegPool(); 127 m2l_->ResetDefTracking(); 128 GenerateTargetLabel(kPseudoThrowTarget); 129 130 RegStorage arg1_32 = m2l_->TargetReg(kArg1, kNotWide); 131 RegStorage arg0_32 = m2l_->TargetReg(kArg0, kNotWide); 132 133 m2l_->OpRegCopy(arg1_32, length_); 134 m2l_->LoadConstant(arg0_32, index_); 135 if (m2l_->cu_->target64) { 136 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 137 arg0_32, arg1_32, true); 138 } else { 139 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 140 arg0_32, arg1_32, true); 141 } 142 } 143 144 private: 145 const int32_t index_; 146 const RegStorage length_; 147 }; 148 149 LIR* branch = OpCmpImmBranch(kCondLs, length, index, nullptr); 150 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, index, length)); 151} 152 153LIR* Mir2Lir::GenNullCheck(RegStorage reg) { 154 class NullCheckSlowPath : public Mir2Lir::LIRSlowPath { 155 public: 156 NullCheckSlowPath(Mir2Lir* m2l, LIR* branch) 157 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch) { 158 } 159 160 void Compile() OVERRIDE { 161 m2l_->ResetRegPool(); 162 m2l_->ResetDefTracking(); 163 GenerateTargetLabel(kPseudoThrowTarget); 164 if (m2l_->cu_->target64) { 165 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pThrowNullPointer), true); 166 } else { 167 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pThrowNullPointer), true); 168 } 169 } 170 }; 171 172 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); 173 AddSlowPath(new (arena_) NullCheckSlowPath(this, branch)); 174 return branch; 175} 176 177/* Perform null-check on a register. */ 178LIR* Mir2Lir::GenNullCheck(RegStorage m_reg, int opt_flags) { 179 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 180 return GenExplicitNullCheck(m_reg, opt_flags); 181 } 182 return nullptr; 183} 184 185/* Perform an explicit null-check on a register. */ 186LIR* Mir2Lir::GenExplicitNullCheck(RegStorage m_reg, int opt_flags) { 187 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 188 return NULL; 189 } 190 return GenNullCheck(m_reg); 191} 192 193void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 194 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 195 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 196 return; 197 } 198 MarkSafepointPC(last_lir_insn_); 199 } 200} 201 202void Mir2Lir::MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after) { 203 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 204 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 205 return; 206 } 207 MarkSafepointPCAfter(after); 208 } 209} 210 211void Mir2Lir::MarkPossibleStackOverflowException() { 212 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitStackOverflowChecks()) { 213 MarkSafepointPC(last_lir_insn_); 214 } 215} 216 217void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { 218 if (!cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 219 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 220 return; 221 } 222 // Force an implicit null check by performing a memory operation (load) from the given 223 // register with offset 0. This will cause a signal if the register contains 0 (null). 224 RegStorage tmp = AllocTemp(); 225 // TODO: for Mips, would be best to use rZERO as the bogus register target. 226 LIR* load = Load32Disp(reg, 0, tmp); 227 FreeTemp(tmp); 228 MarkSafepointPC(load); 229 } 230} 231 232void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 233 RegLocation rl_src2, LIR* taken, 234 LIR* fall_through) { 235 DCHECK(!rl_src1.fp); 236 DCHECK(!rl_src2.fp); 237 ConditionCode cond; 238 switch (opcode) { 239 case Instruction::IF_EQ: 240 cond = kCondEq; 241 break; 242 case Instruction::IF_NE: 243 cond = kCondNe; 244 break; 245 case Instruction::IF_LT: 246 cond = kCondLt; 247 break; 248 case Instruction::IF_GE: 249 cond = kCondGe; 250 break; 251 case Instruction::IF_GT: 252 cond = kCondGt; 253 break; 254 case Instruction::IF_LE: 255 cond = kCondLe; 256 break; 257 default: 258 cond = static_cast<ConditionCode>(0); 259 LOG(FATAL) << "Unexpected opcode " << opcode; 260 } 261 262 // Normalize such that if either operand is constant, src2 will be constant 263 if (rl_src1.is_const) { 264 RegLocation rl_temp = rl_src1; 265 rl_src1 = rl_src2; 266 rl_src2 = rl_temp; 267 cond = FlipComparisonOrder(cond); 268 } 269 270 rl_src1 = LoadValue(rl_src1); 271 // Is this really an immediate comparison? 272 if (rl_src2.is_const) { 273 // If it's already live in a register or not easily materialized, just keep going 274 RegLocation rl_temp = UpdateLoc(rl_src2); 275 if ((rl_temp.location == kLocDalvikFrame) && 276 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 277 // OK - convert this to a compare immediate and branch 278 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); 279 return; 280 } 281 } 282 rl_src2 = LoadValue(rl_src2); 283 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken); 284} 285 286void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 287 LIR* fall_through) { 288 ConditionCode cond; 289 DCHECK(!rl_src.fp); 290 rl_src = LoadValue(rl_src); 291 switch (opcode) { 292 case Instruction::IF_EQZ: 293 cond = kCondEq; 294 break; 295 case Instruction::IF_NEZ: 296 cond = kCondNe; 297 break; 298 case Instruction::IF_LTZ: 299 cond = kCondLt; 300 break; 301 case Instruction::IF_GEZ: 302 cond = kCondGe; 303 break; 304 case Instruction::IF_GTZ: 305 cond = kCondGt; 306 break; 307 case Instruction::IF_LEZ: 308 cond = kCondLe; 309 break; 310 default: 311 cond = static_cast<ConditionCode>(0); 312 LOG(FATAL) << "Unexpected opcode " << opcode; 313 } 314 OpCmpImmBranch(cond, rl_src.reg, 0, taken); 315} 316 317void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 318 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 319 if (rl_src.location == kLocPhysReg) { 320 OpRegCopy(rl_result.reg, rl_src.reg); 321 } else { 322 LoadValueDirect(rl_src, rl_result.reg.GetLow()); 323 } 324 OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_result.reg.GetLow(), 31); 325 StoreValueWide(rl_dest, rl_result); 326} 327 328void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 329 RegLocation rl_src) { 330 rl_src = LoadValue(rl_src, kCoreReg); 331 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 332 OpKind op = kOpInvalid; 333 switch (opcode) { 334 case Instruction::INT_TO_BYTE: 335 op = kOp2Byte; 336 break; 337 case Instruction::INT_TO_SHORT: 338 op = kOp2Short; 339 break; 340 case Instruction::INT_TO_CHAR: 341 op = kOp2Char; 342 break; 343 default: 344 LOG(ERROR) << "Bad int conversion type"; 345 } 346 OpRegReg(op, rl_result.reg, rl_src.reg); 347 StoreValue(rl_dest, rl_result); 348} 349 350template <size_t pointer_size> 351static void GenNewArrayImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, 352 uint32_t type_idx, RegLocation rl_dest, 353 RegLocation rl_src) { 354 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 355 ThreadOffset<pointer_size> func_offset(-1); 356 const DexFile* dex_file = cu->dex_file; 357 CompilerDriver* driver = cu->compiler_driver; 358 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *dex_file, 359 type_idx)) { 360 bool is_type_initialized; // Ignored as an array does not have an initializer. 361 bool use_direct_type_ptr; 362 uintptr_t direct_type_ptr; 363 bool is_finalizable; 364 if (kEmbedClassInCode && 365 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 366 &direct_type_ptr, &is_finalizable)) { 367 // The fast path. 368 if (!use_direct_type_ptr) { 369 mir_to_lir->LoadClassType(type_idx, kArg0); 370 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 371 mir_to_lir->CallRuntimeHelperRegMethodRegLocation(func_offset, 372 mir_to_lir->TargetReg(kArg0, kNotWide), 373 rl_src, true); 374 } else { 375 // Use the direct pointer. 376 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayResolved); 377 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, 378 true); 379 } 380 } else { 381 // The slow path. 382 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArray); 383 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 384 } 385 DCHECK_NE(func_offset.Int32Value(), -1); 386 } else { 387 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocArrayWithAccessCheck); 388 mir_to_lir->CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 389 } 390 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 391 mir_to_lir->StoreValue(rl_dest, rl_result); 392} 393 394/* 395 * Let helper function take care of everything. Will call 396 * Array::AllocFromCode(type_idx, method, count); 397 * Note: AllocFromCode will handle checks for errNegativeArraySize. 398 */ 399void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 400 RegLocation rl_src) { 401 if (cu_->target64) { 402 GenNewArrayImpl<8>(this, cu_, type_idx, rl_dest, rl_src); 403 } else { 404 GenNewArrayImpl<4>(this, cu_, type_idx, rl_dest, rl_src); 405 } 406} 407 408template <size_t pointer_size> 409static void GenFilledNewArrayCall(Mir2Lir* mir_to_lir, CompilationUnit* cu, int elems, int type_idx) { 410 ThreadOffset<pointer_size> func_offset(-1); 411 if (cu->compiler_driver->CanAccessTypeWithoutChecks(cu->method_idx, *cu->dex_file, 412 type_idx)) { 413 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArray); 414 } else { 415 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pCheckAndAllocArrayWithAccessCheck); 416 } 417 mir_to_lir->CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 418} 419 420/* 421 * Similar to GenNewArray, but with post-allocation initialization. 422 * Verifier guarantees we're dealing with an array class. Current 423 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 424 * Current code also throws internal unimp if not 'L', '[' or 'I'. 425 */ 426void Mir2Lir::GenFilledNewArray(CallInfo* info) { 427 int elems = info->num_arg_words; 428 int type_idx = info->index; 429 FlushAllRegs(); /* Everything to home location */ 430 if (cu_->target64) { 431 GenFilledNewArrayCall<8>(this, cu_, elems, type_idx); 432 } else { 433 GenFilledNewArrayCall<4>(this, cu_, elems, type_idx); 434 } 435 FreeTemp(TargetReg(kArg2, kNotWide)); 436 FreeTemp(TargetReg(kArg1, kNotWide)); 437 /* 438 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 439 * return region. Because AllocFromCode placed the new array 440 * in kRet0, we'll just lock it into place. When debugger support is 441 * added, it may be necessary to additionally copy all return 442 * values to a home location in thread-local storage 443 */ 444 RegStorage ref_reg = TargetReg(kRet0, kRef); 445 LockTemp(ref_reg); 446 447 // TODO: use the correct component size, currently all supported types 448 // share array alignment with ints (see comment at head of function) 449 size_t component_size = sizeof(int32_t); 450 451 // Having a range of 0 is legal 452 if (info->is_range && (elems > 0)) { 453 /* 454 * Bit of ugliness here. We're going generate a mem copy loop 455 * on the register range, but it is possible that some regs 456 * in the range have been promoted. This is unlikely, but 457 * before generating the copy, we'll just force a flush 458 * of any regs in the source range that have been promoted to 459 * home location. 460 */ 461 for (int i = 0; i < elems; i++) { 462 RegLocation loc = UpdateLoc(info->args[i]); 463 if (loc.location == kLocPhysReg) { 464 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 465 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 466 } 467 } 468 /* 469 * TUNING note: generated code here could be much improved, but 470 * this is an uncommon operation and isn't especially performance 471 * critical. 472 */ 473 // This is addressing the stack, which may be out of the 4G area. 474 RegStorage r_src = AllocTempRef(); 475 RegStorage r_dst = AllocTempRef(); 476 RegStorage r_idx = AllocTempRef(); // Not really a reference, but match src/dst. 477 RegStorage r_val; 478 switch (cu_->instruction_set) { 479 case kThumb2: 480 case kArm64: 481 r_val = TargetReg(kLr, kNotWide); 482 break; 483 case kX86: 484 case kX86_64: 485 FreeTemp(ref_reg); 486 r_val = AllocTemp(); 487 break; 488 case kMips: 489 r_val = AllocTemp(); 490 break; 491 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 492 } 493 // Set up source pointer 494 RegLocation rl_first = info->args[0]; 495 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); 496 // Set up the target pointer 497 OpRegRegImm(kOpAdd, r_dst, ref_reg, 498 mirror::Array::DataOffset(component_size).Int32Value()); 499 // Set up the loop counter (known to be > 0) 500 LoadConstant(r_idx, elems - 1); 501 // Generate the copy loop. Going backwards for convenience 502 LIR* target = NewLIR0(kPseudoTargetLabel); 503 // Copy next element 504 { 505 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 506 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32); 507 // NOTE: No dalvik register annotation, local optimizations will be stopped 508 // by the loop boundaries. 509 } 510 StoreBaseIndexed(r_dst, r_idx, r_val, 2, k32); 511 FreeTemp(r_val); 512 OpDecAndBranch(kCondGe, r_idx, target); 513 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 514 // Restore the target pointer 515 OpRegRegImm(kOpAdd, ref_reg, r_dst, 516 -mirror::Array::DataOffset(component_size).Int32Value()); 517 } 518 } else if (!info->is_range) { 519 // TUNING: interleave 520 for (int i = 0; i < elems; i++) { 521 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 522 Store32Disp(ref_reg, 523 mirror::Array::DataOffset(component_size).Int32Value() + i * 4, rl_arg.reg); 524 // If the LoadValue caused a temp to be allocated, free it 525 if (IsTemp(rl_arg.reg)) { 526 FreeTemp(rl_arg.reg); 527 } 528 } 529 } 530 if (info->result.location != kLocInvalid) { 531 StoreValue(info->result, GetReturn(kRefReg)); 532 } 533} 534 535// 536// Slow path to ensure a class is initialized for sget/sput. 537// 538class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 539 public: 540 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, int storage_index, 541 RegStorage r_base) : 542 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), 543 storage_index_(storage_index), r_base_(r_base) { 544 } 545 546 void Compile() { 547 LIR* unresolved_target = GenerateTargetLabel(); 548 uninit_->target = unresolved_target; 549 if (cu_->target64) { 550 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeStaticStorage), 551 storage_index_, true); 552 } else { 553 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeStaticStorage), 554 storage_index_, true); 555 } 556 // Copy helper's result into r_base, a no-op on all but MIPS. 557 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0, kRef)); 558 559 m2l_->OpUnconditionalBranch(cont_); 560 } 561 562 private: 563 LIR* const uninit_; 564 const int storage_index_; 565 const RegStorage r_base_; 566}; 567 568template <size_t pointer_size> 569static void GenSputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 570 const MirSFieldLoweringInfo* field_info, RegLocation rl_src) { 571 ThreadOffset<pointer_size> setter_offset = 572 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Static) 573 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjStatic) 574 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Static)); 575 mir_to_lir->CallRuntimeHelperImmRegLocation(setter_offset, field_info->FieldIndex(), rl_src, 576 true); 577} 578 579void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 580 bool is_object) { 581 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 582 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 583 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 584 if (!SLOW_FIELD_PATH && field_info.FastPut()) { 585 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 586 RegStorage r_base; 587 if (field_info.IsReferrersClass()) { 588 // Fast path, static storage base is this method's class 589 RegLocation rl_method = LoadCurrMethod(); 590 r_base = AllocTempRef(); 591 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 592 kNotVolatile); 593 if (IsTemp(rl_method.reg)) { 594 FreeTemp(rl_method.reg); 595 } 596 } else { 597 // Medium path, static storage base in a different class which requires checks that the other 598 // class is initialized. 599 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 600 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 601 // May do runtime call so everything to home locations. 602 FlushAllRegs(); 603 // Using fixed register to sync with possible call to runtime support. 604 RegStorage r_method = TargetReg(kArg1, kRef); 605 LockTemp(r_method); 606 LoadCurrMethodDirect(r_method); 607 r_base = TargetReg(kArg0, kRef); 608 LockTemp(r_base); 609 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 610 kNotVolatile); 611 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 612 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 613 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 614 if (!field_info.IsInitialized() && 615 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 616 // Check if r_base is NULL or a not yet initialized class. 617 618 // The slow path is invoked if the r_base is NULL or the class pointed 619 // to by it is not initialized. 620 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 621 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 622 LockTemp(r_tmp); 623 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 624 mirror::Class::StatusOffset().Int32Value(), 625 mirror::Class::kStatusInitialized, NULL); 626 LIR* cont = NewLIR0(kPseudoTargetLabel); 627 628 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 629 field_info.StorageIndex(), r_base)); 630 631 FreeTemp(r_tmp); 632 // Ensure load of status and store of value don't re-order. 633 // TODO: Presumably the actual value store is control-dependent on the status load, 634 // and will thus not be reordered in any case, since stores are never speculated. 635 // Does later code "know" that the class is now initialized? If so, we still 636 // need the barrier to guard later static loads. 637 GenMemBarrier(kLoadAny); 638 } 639 FreeTemp(r_method); 640 } 641 // rBase now holds static storage base 642 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 643 if (is_long_or_double) { 644 rl_src = LoadValueWide(rl_src, reg_class); 645 } else { 646 rl_src = LoadValue(rl_src, reg_class); 647 } 648 if (is_object) { 649 StoreRefDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, 650 field_info.IsVolatile() ? kVolatile : kNotVolatile); 651 } else { 652 StoreBaseDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg, store_size, 653 field_info.IsVolatile() ? kVolatile : kNotVolatile); 654 } 655 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 656 MarkGCCard(rl_src.reg, r_base); 657 } 658 FreeTemp(r_base); 659 } else { 660 FlushAllRegs(); // Everything to home locations 661 if (cu_->target64) { 662 GenSputCall<8>(this, is_long_or_double, is_object, &field_info, rl_src); 663 } else { 664 GenSputCall<4>(this, is_long_or_double, is_object, &field_info, rl_src); 665 } 666 } 667} 668 669template <size_t pointer_size> 670static void GenSgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 671 const MirSFieldLoweringInfo* field_info) { 672 ThreadOffset<pointer_size> getter_offset = 673 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Static) 674 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjStatic) 675 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Static)); 676 mir_to_lir->CallRuntimeHelperImm(getter_offset, field_info->FieldIndex(), true); 677} 678 679void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 680 bool is_long_or_double, bool is_object) { 681 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 682 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 683 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 684 if (!SLOW_FIELD_PATH && field_info.FastGet()) { 685 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 686 RegStorage r_base; 687 if (field_info.IsReferrersClass()) { 688 // Fast path, static storage base is this method's class 689 RegLocation rl_method = LoadCurrMethod(); 690 r_base = AllocTempRef(); 691 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 692 kNotVolatile); 693 } else { 694 // Medium path, static storage base in a different class which requires checks that the other 695 // class is initialized 696 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 697 // May do runtime call so everything to home locations. 698 FlushAllRegs(); 699 // Using fixed register to sync with possible call to runtime support. 700 RegStorage r_method = TargetReg(kArg1, kRef); 701 LockTemp(r_method); 702 LoadCurrMethodDirect(r_method); 703 r_base = TargetReg(kArg0, kRef); 704 LockTemp(r_base); 705 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 706 kNotVolatile); 707 int32_t offset_of_field = ObjArray::OffsetOfElement(field_info.StorageIndex()).Int32Value(); 708 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile); 709 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 710 if (!field_info.IsInitialized() && 711 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 712 // Check if r_base is NULL or a not yet initialized class. 713 714 // The slow path is invoked if the r_base is NULL or the class pointed 715 // to by it is not initialized. 716 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 717 RegStorage r_tmp = TargetReg(kArg2, kNotWide); 718 LockTemp(r_tmp); 719 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 720 mirror::Class::StatusOffset().Int32Value(), 721 mirror::Class::kStatusInitialized, NULL); 722 LIR* cont = NewLIR0(kPseudoTargetLabel); 723 724 AddSlowPath(new (arena_) StaticFieldSlowPath(this, unresolved_branch, uninit_branch, cont, 725 field_info.StorageIndex(), r_base)); 726 727 FreeTemp(r_tmp); 728 // Ensure load of status and load of value don't re-order. 729 GenMemBarrier(kLoadAny); 730 } 731 FreeTemp(r_method); 732 } 733 // r_base now holds static storage base 734 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 735 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 736 737 int field_offset = field_info.FieldOffset().Int32Value(); 738 if (is_object) { 739 LoadRefDisp(r_base, field_offset, rl_result.reg, field_info.IsVolatile() ? kVolatile : 740 kNotVolatile); 741 } else { 742 LoadBaseDisp(r_base, field_offset, rl_result.reg, load_size, field_info.IsVolatile() ? 743 kVolatile : kNotVolatile); 744 } 745 FreeTemp(r_base); 746 747 if (is_long_or_double) { 748 StoreValueWide(rl_dest, rl_result); 749 } else { 750 StoreValue(rl_dest, rl_result); 751 } 752 } else { 753 FlushAllRegs(); // Everything to home locations 754 if (cu_->target64) { 755 GenSgetCall<8>(this, is_long_or_double, is_object, &field_info); 756 } else { 757 GenSgetCall<4>(this, is_long_or_double, is_object, &field_info); 758 } 759 // FIXME: pGetXXStatic always return an int or int64 regardless of rl_dest.fp. 760 if (is_long_or_double) { 761 RegLocation rl_result = GetReturnWide(kCoreReg); 762 StoreValueWide(rl_dest, rl_result); 763 } else { 764 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 765 StoreValue(rl_dest, rl_result); 766 } 767 } 768} 769 770// Generate code for all slow paths. 771void Mir2Lir::HandleSlowPaths() { 772 // We should check slow_paths_.Size() every time, because a new slow path 773 // may be created during slowpath->Compile(). 774 for (size_t i = 0; i < slow_paths_.Size(); ++i) { 775 LIRSlowPath* slowpath = slow_paths_.Get(i); 776 slowpath->Compile(); 777 } 778 slow_paths_.Reset(); 779} 780 781template <size_t pointer_size> 782static void GenIgetCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 783 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj) { 784 ThreadOffset<pointer_size> getter_offset = 785 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet64Instance) 786 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pGetObjInstance) 787 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pGet32Instance)); 788 // Second argument of pGetXXInstance is always a reference. 789 DCHECK_EQ(static_cast<unsigned int>(rl_obj.wide), 0U); 790 mir_to_lir->CallRuntimeHelperImmRegLocation(getter_offset, field_info->FieldIndex(), rl_obj, 791 true); 792} 793 794void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 795 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 796 bool is_object) { 797 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 798 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 799 OpSize load_size = LoadStoreOpSize(is_long_or_double, is_object); 800 if (!SLOW_FIELD_PATH && field_info.FastGet()) { 801 RegisterClass reg_class = RegClassForFieldLoadStore(load_size, field_info.IsVolatile()); 802 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 803 rl_obj = LoadValue(rl_obj, kRefReg); 804 GenNullCheck(rl_obj.reg, opt_flags); 805 RegLocation rl_result = EvalLoc(rl_dest, reg_class, true); 806 int field_offset = field_info.FieldOffset().Int32Value(); 807 LIR* load_lir; 808 if (is_object) { 809 load_lir = LoadRefDisp(rl_obj.reg, field_offset, rl_result.reg, field_info.IsVolatile() ? 810 kVolatile : kNotVolatile); 811 } else { 812 load_lir = LoadBaseDisp(rl_obj.reg, field_offset, rl_result.reg, load_size, 813 field_info.IsVolatile() ? kVolatile : kNotVolatile); 814 } 815 MarkPossibleNullPointerExceptionAfter(opt_flags, load_lir); 816 if (is_long_or_double) { 817 StoreValueWide(rl_dest, rl_result); 818 } else { 819 StoreValue(rl_dest, rl_result); 820 } 821 } else { 822 if (cu_->target64) { 823 GenIgetCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj); 824 } else { 825 GenIgetCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj); 826 } 827 // FIXME: pGetXXInstance always return an int or int64 regardless of rl_dest.fp. 828 if (is_long_or_double) { 829 RegLocation rl_result = GetReturnWide(kCoreReg); 830 StoreValueWide(rl_dest, rl_result); 831 } else { 832 RegLocation rl_result = GetReturn(rl_dest.ref ? kRefReg : kCoreReg); 833 StoreValue(rl_dest, rl_result); 834 } 835 } 836} 837 838template <size_t pointer_size> 839static void GenIputCall(Mir2Lir* mir_to_lir, bool is_long_or_double, bool is_object, 840 const MirIFieldLoweringInfo* field_info, RegLocation rl_obj, 841 RegLocation rl_src) { 842 ThreadOffset<pointer_size> setter_offset = 843 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet64Instance) 844 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pSetObjInstance) 845 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pSet32Instance)); 846 mir_to_lir->CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info->FieldIndex(), 847 rl_obj, rl_src, true); 848} 849 850void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 851 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 852 bool is_object) { 853 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 854 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 855 OpSize store_size = LoadStoreOpSize(is_long_or_double, is_object); 856 if (!SLOW_FIELD_PATH && field_info.FastPut()) { 857 RegisterClass reg_class = RegClassForFieldLoadStore(store_size, field_info.IsVolatile()); 858 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 859 rl_obj = LoadValue(rl_obj, kRefReg); 860 if (is_long_or_double) { 861 rl_src = LoadValueWide(rl_src, reg_class); 862 } else { 863 rl_src = LoadValue(rl_src, reg_class); 864 } 865 GenNullCheck(rl_obj.reg, opt_flags); 866 int field_offset = field_info.FieldOffset().Int32Value(); 867 LIR* store; 868 if (is_object) { 869 store = StoreRefDisp(rl_obj.reg, field_offset, rl_src.reg, field_info.IsVolatile() ? 870 kVolatile : kNotVolatile); 871 } else { 872 store = StoreBaseDisp(rl_obj.reg, field_offset, rl_src.reg, store_size, 873 field_info.IsVolatile() ? kVolatile : kNotVolatile); 874 } 875 MarkPossibleNullPointerExceptionAfter(opt_flags, store); 876 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 877 MarkGCCard(rl_src.reg, rl_obj.reg); 878 } 879 } else { 880 if (cu_->target64) { 881 GenIputCall<8>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 882 } else { 883 GenIputCall<4>(this, is_long_or_double, is_object, &field_info, rl_obj, rl_src); 884 } 885 } 886} 887 888template <size_t pointer_size> 889static void GenArrayObjPutCall(Mir2Lir* mir_to_lir, bool needs_range_check, bool needs_null_check, 890 RegLocation rl_array, RegLocation rl_index, RegLocation rl_src) { 891 ThreadOffset<pointer_size> helper = needs_range_check 892 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithNullAndBoundCheck) 893 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObjectWithBoundCheck)) 894 : QUICK_ENTRYPOINT_OFFSET(pointer_size, pAputObject); 895 mir_to_lir->CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, 896 true); 897} 898 899void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 900 RegLocation rl_src) { 901 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 902 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 903 (opt_flags & MIR_IGNORE_NULL_CHECK)); 904 if (cu_->target64) { 905 GenArrayObjPutCall<8>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 906 } else { 907 GenArrayObjPutCall<4>(this, needs_range_check, needs_null_check, rl_array, rl_index, rl_src); 908 } 909} 910 911void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 912 RegLocation rl_method = LoadCurrMethod(); 913 CheckRegLocation(rl_method); 914 RegStorage res_reg = AllocTempRef(); 915 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 916 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 917 *cu_->dex_file, 918 type_idx)) { 919 // Call out to helper which resolves type and verifies access. 920 // Resolved type returned in kRet0. 921 if (cu_->target64) { 922 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 923 type_idx, rl_method.reg, true); 924 } else { 925 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 926 type_idx, rl_method.reg, true); 927 } 928 RegLocation rl_result = GetReturn(kRefReg); 929 StoreValue(rl_dest, rl_result); 930 } else { 931 // We're don't need access checks, load type from dex cache 932 int32_t dex_cache_offset = 933 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 934 LoadRefDisp(rl_method.reg, dex_cache_offset, res_reg, kNotVolatile); 935 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 936 LoadRefDisp(res_reg, offset_of_type, rl_result.reg, kNotVolatile); 937 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 938 type_idx) || SLOW_TYPE_PATH) { 939 // Slow path, at runtime test if type is null and if so initialize 940 FlushAllRegs(); 941 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg, 0, NULL); 942 LIR* cont = NewLIR0(kPseudoTargetLabel); 943 944 // Object to generate the slow path for class resolution. 945 class SlowPath : public LIRSlowPath { 946 public: 947 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 948 const RegLocation& rl_method, const RegLocation& rl_result) : 949 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 950 rl_method_(rl_method), rl_result_(rl_result) { 951 } 952 953 void Compile() { 954 GenerateTargetLabel(); 955 956 if (cu_->target64) { 957 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 958 rl_method_.reg, true); 959 } else { 960 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 961 rl_method_.reg, true); 962 } 963 m2l_->OpRegCopy(rl_result_.reg, m2l_->TargetReg(kRet0, kRef)); 964 965 m2l_->OpUnconditionalBranch(cont_); 966 } 967 968 private: 969 const int type_idx_; 970 const RegLocation rl_method_; 971 const RegLocation rl_result_; 972 }; 973 974 // Add to list for future. 975 AddSlowPath(new (arena_) SlowPath(this, branch, cont, type_idx, rl_method, rl_result)); 976 977 StoreValue(rl_dest, rl_result); 978 } else { 979 // Fast path, we're done - just store result 980 StoreValue(rl_dest, rl_result); 981 } 982 } 983} 984 985void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 986 /* NOTE: Most strings should be available at compile time */ 987 int32_t offset_of_string = mirror::ObjectArray<mirror::String>::OffsetOfElement(string_idx). 988 Int32Value(); 989 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 990 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 991 // slow path, resolve string if not in dex cache 992 FlushAllRegs(); 993 LockCallTemps(); // Using explicit registers 994 995 // If the Method* is already in a register, we can save a copy. 996 RegLocation rl_method = mir_graph_->GetMethodLoc(); 997 RegStorage r_method; 998 if (rl_method.location == kLocPhysReg) { 999 // A temp would conflict with register use below. 1000 DCHECK(!IsTemp(rl_method.reg)); 1001 r_method = rl_method.reg; 1002 } else { 1003 r_method = TargetReg(kArg2, kRef); 1004 LoadCurrMethodDirect(r_method); 1005 } 1006 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 1007 TargetReg(kArg0, kRef), kNotVolatile); 1008 1009 // Might call out to helper, which will return resolved string in kRet0 1010 LoadRefDisp(TargetReg(kArg0, kRef), offset_of_string, TargetReg(kRet0, kRef), kNotVolatile); 1011 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0, kRef), 0, NULL); 1012 LIR* cont = NewLIR0(kPseudoTargetLabel); 1013 1014 { 1015 // Object to generate the slow path for string resolution. 1016 class SlowPath : public LIRSlowPath { 1017 public: 1018 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, RegStorage r_method, int32_t string_idx) : 1019 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), 1020 r_method_(r_method), string_idx_(string_idx) { 1021 } 1022 1023 void Compile() { 1024 GenerateTargetLabel(); 1025 if (cu_->target64) { 1026 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pResolveString), 1027 r_method_, string_idx_, true); 1028 } else { 1029 m2l_->CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pResolveString), 1030 r_method_, string_idx_, true); 1031 } 1032 m2l_->OpUnconditionalBranch(cont_); 1033 } 1034 1035 private: 1036 const RegStorage r_method_; 1037 const int32_t string_idx_; 1038 }; 1039 1040 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method, string_idx)); 1041 } 1042 1043 GenBarrier(); 1044 StoreValue(rl_dest, GetReturn(kRefReg)); 1045 } else { 1046 RegLocation rl_method = LoadCurrMethod(); 1047 RegStorage res_reg = AllocTempRef(); 1048 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1049 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg, 1050 kNotVolatile); 1051 LoadRefDisp(res_reg, offset_of_string, rl_result.reg, kNotVolatile); 1052 StoreValue(rl_dest, rl_result); 1053 } 1054} 1055 1056template <size_t pointer_size> 1057static void GenNewInstanceImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, uint32_t type_idx, 1058 RegLocation rl_dest) { 1059 mir_to_lir->FlushAllRegs(); /* Everything to home location */ 1060 // alloc will always check for resolution, do we also need to verify 1061 // access because the verifier was unable to? 1062 ThreadOffset<pointer_size> func_offset(-1); 1063 const DexFile* dex_file = cu->dex_file; 1064 CompilerDriver* driver = cu->compiler_driver; 1065 if (driver->CanAccessInstantiableTypeWithoutChecks( 1066 cu->method_idx, *dex_file, type_idx)) { 1067 bool is_type_initialized; 1068 bool use_direct_type_ptr; 1069 uintptr_t direct_type_ptr; 1070 bool is_finalizable; 1071 if (kEmbedClassInCode && 1072 driver->CanEmbedTypeInCode(*dex_file, type_idx, &is_type_initialized, &use_direct_type_ptr, 1073 &direct_type_ptr, &is_finalizable) && 1074 !is_finalizable) { 1075 // The fast path. 1076 if (!use_direct_type_ptr) { 1077 mir_to_lir->LoadClassType(type_idx, kArg0); 1078 if (!is_type_initialized) { 1079 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1080 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1081 true); 1082 } else { 1083 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1084 mir_to_lir->CallRuntimeHelperRegMethod(func_offset, mir_to_lir->TargetReg(kArg0, kRef), 1085 true); 1086 } 1087 } else { 1088 // Use the direct pointer. 1089 if (!is_type_initialized) { 1090 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectResolved); 1091 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1092 } else { 1093 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectInitialized); 1094 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1095 } 1096 } 1097 } else { 1098 // The slow path. 1099 DCHECK_EQ(func_offset.Int32Value(), -1); 1100 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObject); 1101 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1102 } 1103 DCHECK_NE(func_offset.Int32Value(), -1); 1104 } else { 1105 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pAllocObjectWithAccessCheck); 1106 mir_to_lir->CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1107 } 1108 RegLocation rl_result = mir_to_lir->GetReturn(kRefReg); 1109 mir_to_lir->StoreValue(rl_dest, rl_result); 1110} 1111 1112/* 1113 * Let helper function take care of everything. Will 1114 * call Class::NewInstanceFromCode(type_idx, method); 1115 */ 1116void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 1117 if (cu_->target64) { 1118 GenNewInstanceImpl<8>(this, cu_, type_idx, rl_dest); 1119 } else { 1120 GenNewInstanceImpl<4>(this, cu_, type_idx, rl_dest); 1121 } 1122} 1123 1124void Mir2Lir::GenThrow(RegLocation rl_src) { 1125 FlushAllRegs(); 1126 if (cu_->target64) { 1127 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), rl_src, true); 1128 } else { 1129 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException), rl_src, true); 1130 } 1131} 1132 1133// For final classes there are no sub-classes to check and so we can answer the instance-of 1134// question with simple comparisons. 1135void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1136 RegLocation rl_src) { 1137 // X86 has its own implementation. 1138 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1139 1140 RegLocation object = LoadValue(rl_src, kRefReg); 1141 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1142 RegStorage result_reg = rl_result.reg; 1143 if (IsSameReg(result_reg, object.reg)) { 1144 result_reg = AllocTypedTemp(false, kCoreReg); 1145 DCHECK(!IsSameReg(result_reg, object.reg)); 1146 } 1147 LoadConstant(result_reg, 0); // assume false 1148 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 1149 1150 RegStorage check_class = AllocTypedTemp(false, kRefReg); 1151 RegStorage object_class = AllocTypedTemp(false, kRefReg); 1152 1153 LoadCurrMethodDirect(check_class); 1154 if (use_declaring_class) { 1155 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), check_class, 1156 kNotVolatile); 1157 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1158 kNotVolatile); 1159 } else { 1160 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1161 check_class, kNotVolatile); 1162 LoadRefDisp(object.reg, mirror::Object::ClassOffset().Int32Value(), object_class, 1163 kNotVolatile); 1164 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1165 LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); 1166 } 1167 1168 LIR* ne_branchover = NULL; 1169 // FIXME: what should we be comparing here? compressed or decompressed references? 1170 if (cu_->instruction_set == kThumb2) { 1171 OpRegReg(kOpCmp, check_class, object_class); // Same? 1172 LIR* it = OpIT(kCondEq, ""); // if-convert the test 1173 LoadConstant(result_reg, 1); // .eq case - load true 1174 OpEndIT(it); 1175 } else { 1176 ne_branchover = OpCmpBranch(kCondNe, check_class, object_class, NULL); 1177 LoadConstant(result_reg, 1); // eq case - load true 1178 } 1179 LIR* target = NewLIR0(kPseudoTargetLabel); 1180 null_branchover->target = target; 1181 if (ne_branchover != NULL) { 1182 ne_branchover->target = target; 1183 } 1184 FreeTemp(object_class); 1185 FreeTemp(check_class); 1186 if (IsTemp(result_reg)) { 1187 OpRegCopy(rl_result.reg, result_reg); 1188 FreeTemp(result_reg); 1189 } 1190 StoreValue(rl_dest, rl_result); 1191} 1192 1193void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1194 bool type_known_abstract, bool use_declaring_class, 1195 bool can_assume_type_is_in_dex_cache, 1196 uint32_t type_idx, RegLocation rl_dest, 1197 RegLocation rl_src) { 1198 // X86 has its own implementation. 1199 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1200 1201 FlushAllRegs(); 1202 // May generate a call - use explicit registers 1203 LockCallTemps(); 1204 RegStorage method_reg = TargetReg(kArg1, kRef); 1205 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1206 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1207 if (needs_access_check) { 1208 // Check we have access to type_idx and if not throw IllegalAccessError, 1209 // returns Class* in kArg0 1210 if (cu_->target64) { 1211 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1212 type_idx, true); 1213 } else { 1214 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1215 type_idx, true); 1216 } 1217 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1218 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1219 } else if (use_declaring_class) { 1220 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1221 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1222 class_reg, kNotVolatile); 1223 } else { 1224 // Load dex cache entry into class_reg (kArg2) 1225 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1226 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1227 class_reg, kNotVolatile); 1228 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1229 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1230 if (!can_assume_type_is_in_dex_cache) { 1231 // Need to test presence of type in dex cache at runtime 1232 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 1233 // Not resolved 1234 // Call out to helper, which will return resolved type in kRet0 1235 if (cu_->target64) { 1236 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx, true); 1237 } else { 1238 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true); 1239 } 1240 OpRegCopy(TargetReg(kArg2, kRef), TargetReg(kRet0, kRef)); // Align usage with fast path 1241 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); /* reload Ref */ 1242 // Rejoin code paths 1243 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 1244 hop_branch->target = hop_target; 1245 } 1246 } 1247 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1248 RegLocation rl_result = GetReturn(kCoreReg); 1249 if (cu_->instruction_set == kMips) { 1250 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1251 LoadConstant(rl_result.reg, 0); 1252 } 1253 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, NULL); 1254 1255 /* load object->klass_ */ 1256 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1257 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1258 TargetReg(kArg1, kRef), kNotVolatile); 1259 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1260 LIR* branchover = NULL; 1261 if (type_known_final) { 1262 // rl_result == ref == null == 0. 1263 if (cu_->instruction_set == kThumb2) { 1264 OpRegReg(kOpCmp, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef)); // Same? 1265 LIR* it = OpIT(kCondEq, "E"); // if-convert the test 1266 LoadConstant(rl_result.reg, 1); // .eq case - load true 1267 LoadConstant(rl_result.reg, 0); // .ne case - load false 1268 OpEndIT(it); 1269 } else { 1270 LoadConstant(rl_result.reg, 0); // ne case - load false 1271 branchover = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1272 LoadConstant(rl_result.reg, 1); // eq case - load true 1273 } 1274 } else { 1275 if (cu_->instruction_set == kThumb2) { 1276 RegStorage r_tgt = cu_->target64 ? 1277 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1278 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1279 LIR* it = nullptr; 1280 if (!type_known_abstract) { 1281 /* Uses conditional nullification */ 1282 OpRegReg(kOpCmp, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef)); // Same? 1283 it = OpIT(kCondEq, "EE"); // if-convert the test 1284 LoadConstant(TargetReg(kArg0, kNotWide), 1); // .eq case - load true 1285 } 1286 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1287 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1288 if (it != nullptr) { 1289 OpEndIT(it); 1290 } 1291 FreeTemp(r_tgt); 1292 } else { 1293 if (!type_known_abstract) { 1294 /* Uses branchovers */ 1295 LoadConstant(rl_result.reg, 1); // assume true 1296 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1, kRef), TargetReg(kArg2, kRef), NULL); 1297 } 1298 RegStorage r_tgt = cu_->target64 ? 1299 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)) : 1300 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 1301 OpRegCopy(TargetReg(kArg0, kRef), TargetReg(kArg2, kRef)); // .ne case - arg0 <= class 1302 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1303 FreeTemp(r_tgt); 1304 } 1305 } 1306 // TODO: only clobber when type isn't final? 1307 ClobberCallerSave(); 1308 /* branch targets here */ 1309 LIR* target = NewLIR0(kPseudoTargetLabel); 1310 StoreValue(rl_dest, rl_result); 1311 branch1->target = target; 1312 if (branchover != NULL) { 1313 branchover->target = target; 1314 } 1315} 1316 1317void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1318 bool type_known_final, type_known_abstract, use_declaring_class; 1319 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1320 *cu_->dex_file, 1321 type_idx, 1322 &type_known_final, 1323 &type_known_abstract, 1324 &use_declaring_class); 1325 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1326 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1327 1328 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1329 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1330 } else { 1331 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1332 use_declaring_class, can_assume_type_is_in_dex_cache, 1333 type_idx, rl_dest, rl_src); 1334 } 1335} 1336 1337void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1338 bool type_known_final, type_known_abstract, use_declaring_class; 1339 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1340 *cu_->dex_file, 1341 type_idx, 1342 &type_known_final, 1343 &type_known_abstract, 1344 &use_declaring_class); 1345 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1346 // of the exception throw path. 1347 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1348 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1349 // Verifier type analysis proved this check cast would never cause an exception. 1350 return; 1351 } 1352 FlushAllRegs(); 1353 // May generate a call - use explicit registers 1354 LockCallTemps(); 1355 RegStorage method_reg = TargetReg(kArg1, kRef); 1356 LoadCurrMethodDirect(method_reg); // kArg1 <= current Method* 1357 RegStorage class_reg = TargetReg(kArg2, kRef); // kArg2 will hold the Class* 1358 if (needs_access_check) { 1359 // Check we have access to type_idx and if not throw IllegalAccessError, 1360 // returns Class* in kRet0 1361 // InitializeTypeAndVerifyAccess(idx, method) 1362 if (cu_->target64) { 1363 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 1364 type_idx, true); 1365 } else { 1366 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 1367 type_idx, true); 1368 } 1369 OpRegCopy(class_reg, TargetReg(kRet0, kRef)); // Align usage with fast path 1370 } else if (use_declaring_class) { 1371 LoadRefDisp(method_reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1372 class_reg, kNotVolatile); 1373 } else { 1374 // Load dex cache entry into class_reg (kArg2) 1375 LoadRefDisp(method_reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1376 class_reg, kNotVolatile); 1377 int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); 1378 LoadRefDisp(class_reg, offset_of_type, class_reg, kNotVolatile); 1379 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1380 // Need to test presence of type in dex cache at runtime 1381 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1382 LIR* cont = NewLIR0(kPseudoTargetLabel); 1383 1384 // Slow path to initialize the type. Executed if the type is NULL. 1385 class SlowPath : public LIRSlowPath { 1386 public: 1387 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1388 const RegStorage class_reg) : 1389 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1390 class_reg_(class_reg) { 1391 } 1392 1393 void Compile() { 1394 GenerateTargetLabel(); 1395 1396 // Call out to helper, which will return resolved type in kArg0 1397 // InitializeTypeFromCode(idx, method) 1398 if (m2l_->cu_->target64) { 1399 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx_, 1400 m2l_->TargetReg(kArg1, kRef), true); 1401 } else { 1402 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_, 1403 m2l_->TargetReg(kArg1, kRef), true); 1404 } 1405 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0, kRef)); // Align usage with fast path 1406 m2l_->OpUnconditionalBranch(cont_); 1407 } 1408 1409 public: 1410 const int type_idx_; 1411 const RegStorage class_reg_; 1412 }; 1413 1414 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, type_idx, class_reg)); 1415 } 1416 } 1417 // At this point, class_reg (kArg2) has class 1418 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kRef)); // kArg0 <= ref 1419 1420 // Slow path for the case where the classes are not equal. In this case we need 1421 // to call a helper function to do the check. 1422 class SlowPath : public LIRSlowPath { 1423 public: 1424 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1425 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1426 } 1427 1428 void Compile() { 1429 GenerateTargetLabel(); 1430 1431 if (load_) { 1432 m2l_->LoadRefDisp(m2l_->TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1433 m2l_->TargetReg(kArg1, kRef), kNotVolatile); 1434 } 1435 if (m2l_->cu_->target64) { 1436 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pCheckCast), 1437 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1438 true); 1439 } else { 1440 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pCheckCast), 1441 m2l_->TargetReg(kArg2, kRef), m2l_->TargetReg(kArg1, kRef), 1442 true); 1443 } 1444 1445 m2l_->OpUnconditionalBranch(cont_); 1446 } 1447 1448 private: 1449 const bool load_; 1450 }; 1451 1452 if (type_known_abstract) { 1453 // Easier case, run slow path if target is non-null (slow path will load from target) 1454 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0, kRef), 0, nullptr); 1455 LIR* cont = NewLIR0(kPseudoTargetLabel); 1456 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1457 } else { 1458 // Harder, more common case. We need to generate a forward branch over the load 1459 // if the target is null. If it's non-null we perform the load and branch to the 1460 // slow path if the classes are not equal. 1461 1462 /* Null is OK - continue */ 1463 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0, kRef), 0, nullptr); 1464 /* load object->klass_ */ 1465 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1466 LoadRefDisp(TargetReg(kArg0, kRef), mirror::Object::ClassOffset().Int32Value(), 1467 TargetReg(kArg1, kRef), kNotVolatile); 1468 1469 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1, kRef), class_reg, nullptr); 1470 LIR* cont = NewLIR0(kPseudoTargetLabel); 1471 1472 // Add the slow path that will not perform load since this is already done. 1473 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1474 1475 // Set the null check to branch to the continuation. 1476 branch1->target = cont; 1477 } 1478} 1479 1480void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1481 RegLocation rl_src1, RegLocation rl_src2) { 1482 RegLocation rl_result; 1483 if (cu_->instruction_set == kThumb2) { 1484 /* 1485 * NOTE: This is the one place in the code in which we might have 1486 * as many as six live temporary registers. There are 5 in the normal 1487 * set for Arm. Until we have spill capabilities, temporarily add 1488 * lr to the temp set. It is safe to do this locally, but note that 1489 * lr is used explicitly elsewhere in the code generator and cannot 1490 * normally be used as a general temp register. 1491 */ 1492 MarkTemp(TargetReg(kLr, kNotWide)); // Add lr to the temp pool 1493 FreeTemp(TargetReg(kLr, kNotWide)); // and make it available 1494 } 1495 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1496 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1497 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1498 // The longs may overlap - use intermediate temp if so 1499 if ((rl_result.reg.GetLowReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg())) { 1500 RegStorage t_reg = AllocTemp(); 1501 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1502 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1503 OpRegCopy(rl_result.reg.GetLow(), t_reg); 1504 FreeTemp(t_reg); 1505 } else { 1506 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); 1507 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); 1508 } 1509 /* 1510 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1511 * following StoreValueWide might need to allocate a temp register. 1512 * To further work around the lack of a spill capability, explicitly 1513 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1514 * Remove when spill is functional. 1515 */ 1516 FreeRegLocTemps(rl_result, rl_src1); 1517 FreeRegLocTemps(rl_result, rl_src2); 1518 StoreValueWide(rl_dest, rl_result); 1519 if (cu_->instruction_set == kThumb2) { 1520 Clobber(TargetReg(kLr, kNotWide)); 1521 UnmarkTemp(TargetReg(kLr, kNotWide)); // Remove lr from the temp pool 1522 } 1523} 1524 1525 1526template <size_t pointer_size> 1527static void GenShiftOpLongCall(Mir2Lir* mir_to_lir, Instruction::Code opcode, RegLocation rl_src1, 1528 RegLocation rl_shift) { 1529 ThreadOffset<pointer_size> func_offset(-1); 1530 1531 switch (opcode) { 1532 case Instruction::SHL_LONG: 1533 case Instruction::SHL_LONG_2ADDR: 1534 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShlLong); 1535 break; 1536 case Instruction::SHR_LONG: 1537 case Instruction::SHR_LONG_2ADDR: 1538 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pShrLong); 1539 break; 1540 case Instruction::USHR_LONG: 1541 case Instruction::USHR_LONG_2ADDR: 1542 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pUshrLong); 1543 break; 1544 default: 1545 LOG(FATAL) << "Unexpected case"; 1546 } 1547 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 1548 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1549} 1550 1551void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1552 RegLocation rl_src1, RegLocation rl_shift) { 1553 if (cu_->target64) { 1554 GenShiftOpLongCall<8>(this, opcode, rl_src1, rl_shift); 1555 } else { 1556 GenShiftOpLongCall<4>(this, opcode, rl_src1, rl_shift); 1557 } 1558 RegLocation rl_result = GetReturnWide(kCoreReg); 1559 StoreValueWide(rl_dest, rl_result); 1560} 1561 1562 1563void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1564 RegLocation rl_src1, RegLocation rl_src2) { 1565 DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64); 1566 OpKind op = kOpBkpt; 1567 bool is_div_rem = false; 1568 bool check_zero = false; 1569 bool unary = false; 1570 RegLocation rl_result; 1571 bool shift_op = false; 1572 switch (opcode) { 1573 case Instruction::NEG_INT: 1574 op = kOpNeg; 1575 unary = true; 1576 break; 1577 case Instruction::NOT_INT: 1578 op = kOpMvn; 1579 unary = true; 1580 break; 1581 case Instruction::ADD_INT: 1582 case Instruction::ADD_INT_2ADDR: 1583 op = kOpAdd; 1584 break; 1585 case Instruction::SUB_INT: 1586 case Instruction::SUB_INT_2ADDR: 1587 op = kOpSub; 1588 break; 1589 case Instruction::MUL_INT: 1590 case Instruction::MUL_INT_2ADDR: 1591 op = kOpMul; 1592 break; 1593 case Instruction::DIV_INT: 1594 case Instruction::DIV_INT_2ADDR: 1595 check_zero = true; 1596 op = kOpDiv; 1597 is_div_rem = true; 1598 break; 1599 /* NOTE: returns in kArg1 */ 1600 case Instruction::REM_INT: 1601 case Instruction::REM_INT_2ADDR: 1602 check_zero = true; 1603 op = kOpRem; 1604 is_div_rem = true; 1605 break; 1606 case Instruction::AND_INT: 1607 case Instruction::AND_INT_2ADDR: 1608 op = kOpAnd; 1609 break; 1610 case Instruction::OR_INT: 1611 case Instruction::OR_INT_2ADDR: 1612 op = kOpOr; 1613 break; 1614 case Instruction::XOR_INT: 1615 case Instruction::XOR_INT_2ADDR: 1616 op = kOpXor; 1617 break; 1618 case Instruction::SHL_INT: 1619 case Instruction::SHL_INT_2ADDR: 1620 shift_op = true; 1621 op = kOpLsl; 1622 break; 1623 case Instruction::SHR_INT: 1624 case Instruction::SHR_INT_2ADDR: 1625 shift_op = true; 1626 op = kOpAsr; 1627 break; 1628 case Instruction::USHR_INT: 1629 case Instruction::USHR_INT_2ADDR: 1630 shift_op = true; 1631 op = kOpLsr; 1632 break; 1633 default: 1634 LOG(FATAL) << "Invalid word arith op: " << opcode; 1635 } 1636 if (!is_div_rem) { 1637 if (unary) { 1638 rl_src1 = LoadValue(rl_src1, kCoreReg); 1639 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1640 OpRegReg(op, rl_result.reg, rl_src1.reg); 1641 } else { 1642 if ((shift_op) && (cu_->instruction_set != kArm64)) { 1643 rl_src2 = LoadValue(rl_src2, kCoreReg); 1644 RegStorage t_reg = AllocTemp(); 1645 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg, 31); 1646 rl_src1 = LoadValue(rl_src1, kCoreReg); 1647 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1648 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 1649 FreeTemp(t_reg); 1650 } else { 1651 rl_src1 = LoadValue(rl_src1, kCoreReg); 1652 rl_src2 = LoadValue(rl_src2, kCoreReg); 1653 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1654 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); 1655 } 1656 } 1657 StoreValue(rl_dest, rl_result); 1658 } else { 1659 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1660 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1661 rl_src1 = LoadValue(rl_src1, kCoreReg); 1662 rl_src2 = LoadValue(rl_src2, kCoreReg); 1663 if (check_zero) { 1664 GenDivZeroCheck(rl_src2.reg); 1665 } 1666 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1667 done = true; 1668 } else if (cu_->instruction_set == kThumb2) { 1669 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1670 // Use ARM SDIV instruction for division. For remainder we also need to 1671 // calculate using a MUL and subtract. 1672 rl_src1 = LoadValue(rl_src1, kCoreReg); 1673 rl_src2 = LoadValue(rl_src2, kCoreReg); 1674 if (check_zero) { 1675 GenDivZeroCheck(rl_src2.reg); 1676 } 1677 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); 1678 done = true; 1679 } 1680 } 1681 1682 // If we haven't already generated the code use the callout function. 1683 if (!done) { 1684 FlushAllRegs(); /* Send everything to home location */ 1685 LoadValueDirectFixed(rl_src2, TargetReg(kArg1, kNotWide)); 1686 RegStorage r_tgt = cu_->target64 ? 1687 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod)) : 1688 CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod)); 1689 LoadValueDirectFixed(rl_src1, TargetReg(kArg0, kNotWide)); 1690 if (check_zero) { 1691 GenDivZeroCheck(TargetReg(kArg1, kNotWide)); 1692 } 1693 // NOTE: callout here is not a safepoint. 1694 if (cu_->target64) { 1695 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), false /* not a safepoint */); 1696 } else { 1697 CallHelper(r_tgt, QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), false /* not a safepoint */); 1698 } 1699 if (op == kOpDiv) 1700 rl_result = GetReturn(kCoreReg); 1701 else 1702 rl_result = GetReturnAlt(); 1703 } 1704 StoreValue(rl_dest, rl_result); 1705 } 1706} 1707 1708/* 1709 * The following are the first-level codegen routines that analyze the format 1710 * of each bytecode then either dispatch special purpose codegen routines 1711 * or produce corresponding Thumb instructions directly. 1712 */ 1713 1714// Returns true if no more than two bits are set in 'x'. 1715static bool IsPopCountLE2(unsigned int x) { 1716 x &= x - 1; 1717 return (x & (x - 1)) == 0; 1718} 1719 1720// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1721// and store the result in 'rl_dest'. 1722bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1723 RegLocation rl_src, RegLocation rl_dest, int lit) { 1724 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1725 return false; 1726 } 1727 // No divide instruction for Arm, so check for more special cases 1728 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1729 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1730 } 1731 int k = LowestSetBit(lit); 1732 if (k >= 30) { 1733 // Avoid special cases. 1734 return false; 1735 } 1736 rl_src = LoadValue(rl_src, kCoreReg); 1737 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1738 if (is_div) { 1739 RegStorage t_reg = AllocTemp(); 1740 if (lit == 2) { 1741 // Division by 2 is by far the most common division by constant. 1742 OpRegRegImm(kOpLsr, t_reg, rl_src.reg, 32 - k); 1743 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1744 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1745 } else { 1746 OpRegRegImm(kOpAsr, t_reg, rl_src.reg, 31); 1747 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1748 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); 1749 OpRegRegImm(kOpAsr, rl_result.reg, t_reg, k); 1750 } 1751 } else { 1752 RegStorage t_reg1 = AllocTemp(); 1753 RegStorage t_reg2 = AllocTemp(); 1754 if (lit == 2) { 1755 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg, 32 - k); 1756 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1757 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1758 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1759 } else { 1760 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg, 31); 1761 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1762 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); 1763 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1764 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); 1765 } 1766 } 1767 StoreValue(rl_dest, rl_result); 1768 return true; 1769} 1770 1771// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1772// and store the result in 'rl_dest'. 1773bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1774 if (lit < 0) { 1775 return false; 1776 } 1777 if (lit == 0) { 1778 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1779 LoadConstant(rl_result.reg, 0); 1780 StoreValue(rl_dest, rl_result); 1781 return true; 1782 } 1783 if (lit == 1) { 1784 rl_src = LoadValue(rl_src, kCoreReg); 1785 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1786 OpRegCopy(rl_result.reg, rl_src.reg); 1787 StoreValue(rl_dest, rl_result); 1788 return true; 1789 } 1790 // There is RegRegRegShift on Arm, so check for more special cases 1791 if (cu_->instruction_set == kThumb2) { 1792 return EasyMultiply(rl_src, rl_dest, lit); 1793 } 1794 // Can we simplify this multiplication? 1795 bool power_of_two = false; 1796 bool pop_count_le2 = false; 1797 bool power_of_two_minus_one = false; 1798 if (IsPowerOfTwo(lit)) { 1799 power_of_two = true; 1800 } else if (IsPopCountLE2(lit)) { 1801 pop_count_le2 = true; 1802 } else if (IsPowerOfTwo(lit + 1)) { 1803 power_of_two_minus_one = true; 1804 } else { 1805 return false; 1806 } 1807 rl_src = LoadValue(rl_src, kCoreReg); 1808 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1809 if (power_of_two) { 1810 // Shift. 1811 OpRegRegImm(kOpLsl, rl_result.reg, rl_src.reg, LowestSetBit(lit)); 1812 } else if (pop_count_le2) { 1813 // Shift and add and shift. 1814 int first_bit = LowestSetBit(lit); 1815 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1816 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1817 } else { 1818 // Reverse subtract: (src << (shift + 1)) - src. 1819 DCHECK(power_of_two_minus_one); 1820 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1821 RegStorage t_reg = AllocTemp(); 1822 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, LowestSetBit(lit + 1)); 1823 OpRegRegReg(kOpSub, rl_result.reg, t_reg, rl_src.reg); 1824 } 1825 StoreValue(rl_dest, rl_result); 1826 return true; 1827} 1828 1829void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1830 int lit) { 1831 RegLocation rl_result; 1832 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1833 int shift_op = false; 1834 bool is_div = false; 1835 1836 switch (opcode) { 1837 case Instruction::RSUB_INT_LIT8: 1838 case Instruction::RSUB_INT: { 1839 rl_src = LoadValue(rl_src, kCoreReg); 1840 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1841 if (cu_->instruction_set == kThumb2) { 1842 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, lit); 1843 } else { 1844 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1845 OpRegImm(kOpAdd, rl_result.reg, lit); 1846 } 1847 StoreValue(rl_dest, rl_result); 1848 return; 1849 } 1850 1851 case Instruction::SUB_INT: 1852 case Instruction::SUB_INT_2ADDR: 1853 lit = -lit; 1854 // Intended fallthrough 1855 case Instruction::ADD_INT: 1856 case Instruction::ADD_INT_2ADDR: 1857 case Instruction::ADD_INT_LIT8: 1858 case Instruction::ADD_INT_LIT16: 1859 op = kOpAdd; 1860 break; 1861 case Instruction::MUL_INT: 1862 case Instruction::MUL_INT_2ADDR: 1863 case Instruction::MUL_INT_LIT8: 1864 case Instruction::MUL_INT_LIT16: { 1865 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1866 return; 1867 } 1868 op = kOpMul; 1869 break; 1870 } 1871 case Instruction::AND_INT: 1872 case Instruction::AND_INT_2ADDR: 1873 case Instruction::AND_INT_LIT8: 1874 case Instruction::AND_INT_LIT16: 1875 op = kOpAnd; 1876 break; 1877 case Instruction::OR_INT: 1878 case Instruction::OR_INT_2ADDR: 1879 case Instruction::OR_INT_LIT8: 1880 case Instruction::OR_INT_LIT16: 1881 op = kOpOr; 1882 break; 1883 case Instruction::XOR_INT: 1884 case Instruction::XOR_INT_2ADDR: 1885 case Instruction::XOR_INT_LIT8: 1886 case Instruction::XOR_INT_LIT16: 1887 op = kOpXor; 1888 break; 1889 case Instruction::SHL_INT_LIT8: 1890 case Instruction::SHL_INT: 1891 case Instruction::SHL_INT_2ADDR: 1892 lit &= 31; 1893 shift_op = true; 1894 op = kOpLsl; 1895 break; 1896 case Instruction::SHR_INT_LIT8: 1897 case Instruction::SHR_INT: 1898 case Instruction::SHR_INT_2ADDR: 1899 lit &= 31; 1900 shift_op = true; 1901 op = kOpAsr; 1902 break; 1903 case Instruction::USHR_INT_LIT8: 1904 case Instruction::USHR_INT: 1905 case Instruction::USHR_INT_2ADDR: 1906 lit &= 31; 1907 shift_op = true; 1908 op = kOpLsr; 1909 break; 1910 1911 case Instruction::DIV_INT: 1912 case Instruction::DIV_INT_2ADDR: 1913 case Instruction::DIV_INT_LIT8: 1914 case Instruction::DIV_INT_LIT16: 1915 case Instruction::REM_INT: 1916 case Instruction::REM_INT_2ADDR: 1917 case Instruction::REM_INT_LIT8: 1918 case Instruction::REM_INT_LIT16: { 1919 if (lit == 0) { 1920 GenDivZeroException(); 1921 return; 1922 } 1923 if ((opcode == Instruction::DIV_INT) || 1924 (opcode == Instruction::DIV_INT_2ADDR) || 1925 (opcode == Instruction::DIV_INT_LIT8) || 1926 (opcode == Instruction::DIV_INT_LIT16)) { 1927 is_div = true; 1928 } else { 1929 is_div = false; 1930 } 1931 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1932 return; 1933 } 1934 1935 bool done = false; 1936 if (cu_->instruction_set == kMips || cu_->instruction_set == kArm64) { 1937 rl_src = LoadValue(rl_src, kCoreReg); 1938 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1939 done = true; 1940 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1941 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1942 done = true; 1943 } else if (cu_->instruction_set == kThumb2) { 1944 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1945 // Use ARM SDIV instruction for division. For remainder we also need to 1946 // calculate using a MUL and subtract. 1947 rl_src = LoadValue(rl_src, kCoreReg); 1948 rl_result = GenDivRemLit(rl_dest, rl_src.reg, lit, is_div); 1949 done = true; 1950 } 1951 } 1952 1953 if (!done) { 1954 FlushAllRegs(); /* Everything to home location. */ 1955 LoadValueDirectFixed(rl_src, TargetReg(kArg0, kNotWide)); 1956 Clobber(TargetReg(kArg0, kNotWide)); 1957 if (cu_->target64) { 1958 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(8, pIdivmod), TargetReg(kArg0, kNotWide), 1959 lit, false); 1960 } else { 1961 CallRuntimeHelperRegImm(QUICK_ENTRYPOINT_OFFSET(4, pIdivmod), TargetReg(kArg0, kNotWide), 1962 lit, false); 1963 } 1964 if (is_div) 1965 rl_result = GetReturn(kCoreReg); 1966 else 1967 rl_result = GetReturnAlt(); 1968 } 1969 StoreValue(rl_dest, rl_result); 1970 return; 1971 } 1972 default: 1973 LOG(FATAL) << "Unexpected opcode " << opcode; 1974 } 1975 rl_src = LoadValue(rl_src, kCoreReg); 1976 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1977 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 1978 if (shift_op && (lit == 0)) { 1979 OpRegCopy(rl_result.reg, rl_src.reg); 1980 } else { 1981 OpRegRegImm(op, rl_result.reg, rl_src.reg, lit); 1982 } 1983 StoreValue(rl_dest, rl_result); 1984} 1985 1986template <size_t pointer_size> 1987static void GenArithOpLongImpl(Mir2Lir* mir_to_lir, CompilationUnit* cu, Instruction::Code opcode, 1988 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 1989 RegLocation rl_result; 1990 OpKind first_op = kOpBkpt; 1991 OpKind second_op = kOpBkpt; 1992 bool call_out = false; 1993 bool check_zero = false; 1994 ThreadOffset<pointer_size> func_offset(-1); 1995 int ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 1996 1997 switch (opcode) { 1998 case Instruction::NOT_LONG: 1999 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2000 mir_to_lir->GenNotLong(rl_dest, rl_src2); 2001 return; 2002 } 2003 rl_src2 = mir_to_lir->LoadValueWide(rl_src2, kCoreReg); 2004 rl_result = mir_to_lir->EvalLoc(rl_dest, kCoreReg, true); 2005 // Check for destructive overlap 2006 if (rl_result.reg.GetLowReg() == rl_src2.reg.GetHighReg()) { 2007 RegStorage t_reg = mir_to_lir->AllocTemp(); 2008 mir_to_lir->OpRegCopy(t_reg, rl_src2.reg.GetHigh()); 2009 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2010 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), t_reg); 2011 mir_to_lir->FreeTemp(t_reg); 2012 } else { 2013 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); 2014 mir_to_lir->OpRegReg(kOpMvn, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); 2015 } 2016 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2017 return; 2018 case Instruction::ADD_LONG: 2019 case Instruction::ADD_LONG_2ADDR: 2020 if (cu->instruction_set != kThumb2) { 2021 mir_to_lir->GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 2022 return; 2023 } 2024 first_op = kOpAdd; 2025 second_op = kOpAdc; 2026 break; 2027 case Instruction::SUB_LONG: 2028 case Instruction::SUB_LONG_2ADDR: 2029 if (cu->instruction_set != kThumb2) { 2030 mir_to_lir->GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 2031 return; 2032 } 2033 first_op = kOpSub; 2034 second_op = kOpSbc; 2035 break; 2036 case Instruction::MUL_LONG: 2037 case Instruction::MUL_LONG_2ADDR: 2038 if (cu->instruction_set != kMips) { 2039 mir_to_lir->GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 2040 return; 2041 } else { 2042 call_out = true; 2043 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2044 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmul); 2045 } 2046 break; 2047 case Instruction::DIV_LONG: 2048 case Instruction::DIV_LONG_2ADDR: 2049 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2050 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); 2051 return; 2052 } 2053 call_out = true; 2054 check_zero = true; 2055 ret_reg = mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2056 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLdiv); 2057 break; 2058 case Instruction::REM_LONG: 2059 case Instruction::REM_LONG_2ADDR: 2060 if (cu->instruction_set == kArm64 || cu->instruction_set == kX86_64) { 2061 mir_to_lir->GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); 2062 return; 2063 } 2064 call_out = true; 2065 check_zero = true; 2066 func_offset = QUICK_ENTRYPOINT_OFFSET(pointer_size, pLmod); 2067 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 2068 ret_reg = (cu->instruction_set == kThumb2) ? mir_to_lir->TargetReg(kArg2, kNotWide).GetReg() : 2069 mir_to_lir->TargetReg(kRet0, kNotWide).GetReg(); 2070 break; 2071 case Instruction::AND_LONG_2ADDR: 2072 case Instruction::AND_LONG: 2073 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2074 cu->instruction_set == kArm64) { 2075 return mir_to_lir->GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 2076 } 2077 first_op = kOpAnd; 2078 second_op = kOpAnd; 2079 break; 2080 case Instruction::OR_LONG: 2081 case Instruction::OR_LONG_2ADDR: 2082 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2083 cu->instruction_set == kArm64) { 2084 mir_to_lir->GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 2085 return; 2086 } 2087 first_op = kOpOr; 2088 second_op = kOpOr; 2089 break; 2090 case Instruction::XOR_LONG: 2091 case Instruction::XOR_LONG_2ADDR: 2092 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64 || 2093 cu->instruction_set == kArm64) { 2094 mir_to_lir->GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 2095 return; 2096 } 2097 first_op = kOpXor; 2098 second_op = kOpXor; 2099 break; 2100 case Instruction::NEG_LONG: { 2101 mir_to_lir->GenNegLong(rl_dest, rl_src2); 2102 return; 2103 } 2104 default: 2105 LOG(FATAL) << "Invalid long arith op"; 2106 } 2107 if (!call_out) { 2108 mir_to_lir->GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 2109 } else { 2110 mir_to_lir->FlushAllRegs(); /* Send everything to home location */ 2111 if (check_zero) { 2112 RegStorage r_tmp1 = mir_to_lir->TargetReg(kArg0, kWide); 2113 RegStorage r_tmp2 = mir_to_lir->TargetReg(kArg2, kWide); 2114 mir_to_lir->LoadValueDirectWideFixed(rl_src2, r_tmp2); 2115 RegStorage r_tgt = mir_to_lir->CallHelperSetup(func_offset); 2116 mir_to_lir->GenDivZeroCheckWide(r_tmp2); 2117 mir_to_lir->LoadValueDirectWideFixed(rl_src1, r_tmp1); 2118 // NOTE: callout here is not a safepoint 2119 mir_to_lir->CallHelper(r_tgt, func_offset, false /* not safepoint */); 2120 } else { 2121 mir_to_lir->CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 2122 } 2123 // Adjust return regs in to handle case of rem returning kArg2/kArg3 2124 if (ret_reg == mir_to_lir->TargetReg(kRet0, kNotWide).GetReg()) 2125 rl_result = mir_to_lir->GetReturnWide(kCoreReg); 2126 else 2127 rl_result = mir_to_lir->GetReturnWideAlt(); 2128 mir_to_lir->StoreValueWide(rl_dest, rl_result); 2129 } 2130} 2131 2132void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 2133 RegLocation rl_src1, RegLocation rl_src2) { 2134 if (cu_->target64) { 2135 GenArithOpLongImpl<8>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2136 } else { 2137 GenArithOpLongImpl<4>(this, cu_, opcode, rl_dest, rl_src1, rl_src2); 2138 } 2139} 2140 2141void Mir2Lir::GenConst(RegLocation rl_dest, int value) { 2142 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2143 LoadConstantNoClobber(rl_result.reg, value); 2144 StoreValue(rl_dest, rl_result); 2145 if (value == 0) { 2146 Workaround7250540(rl_dest, rl_result.reg); 2147 } 2148} 2149 2150template <size_t pointer_size> 2151void Mir2Lir::GenConversionCall(ThreadOffset<pointer_size> func_offset, 2152 RegLocation rl_dest, RegLocation rl_src) { 2153 /* 2154 * Don't optimize the register usage since it calls out to support 2155 * functions 2156 */ 2157 DCHECK_EQ(pointer_size, GetInstructionSetPointerSize(cu_->instruction_set)); 2158 2159 FlushAllRegs(); /* Send everything to home location */ 2160 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 2161 if (rl_dest.wide) { 2162 RegLocation rl_result; 2163 rl_result = GetReturnWide(LocToRegClass(rl_dest)); 2164 StoreValueWide(rl_dest, rl_result); 2165 } else { 2166 RegLocation rl_result; 2167 rl_result = GetReturn(LocToRegClass(rl_dest)); 2168 StoreValue(rl_dest, rl_result); 2169 } 2170} 2171template void Mir2Lir::GenConversionCall(ThreadOffset<4> func_offset, 2172 RegLocation rl_dest, RegLocation rl_src); 2173template void Mir2Lir::GenConversionCall(ThreadOffset<8> func_offset, 2174 RegLocation rl_dest, RegLocation rl_src); 2175 2176class SuspendCheckSlowPath : public Mir2Lir::LIRSlowPath { 2177 public: 2178 SuspendCheckSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont) 2179 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, cont) { 2180 } 2181 2182 void Compile() OVERRIDE { 2183 m2l_->ResetRegPool(); 2184 m2l_->ResetDefTracking(); 2185 GenerateTargetLabel(kPseudoSuspendTarget); 2186 if (cu_->target64) { 2187 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(8, pTestSuspend), true); 2188 } else { 2189 m2l_->CallRuntimeHelper(QUICK_ENTRYPOINT_OFFSET(4, pTestSuspend), true); 2190 } 2191 if (cont_ != nullptr) { 2192 m2l_->OpUnconditionalBranch(cont_); 2193 } 2194 } 2195}; 2196 2197/* Check if we need to check for pending suspend request */ 2198void Mir2Lir::GenSuspendTest(int opt_flags) { 2199 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitSuspendChecks()) { 2200 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2201 return; 2202 } 2203 FlushAllRegs(); 2204 LIR* branch = OpTestSuspend(NULL); 2205 LIR* cont = NewLIR0(kPseudoTargetLabel); 2206 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, cont)); 2207 } else { 2208 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2209 return; 2210 } 2211 FlushAllRegs(); // TODO: needed? 2212 LIR* inst = CheckSuspendUsingLoad(); 2213 MarkSafepointPC(inst); 2214 } 2215} 2216 2217/* Check if we need to check for pending suspend request */ 2218void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 2219 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitSuspendChecks()) { 2220 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2221 OpUnconditionalBranch(target); 2222 return; 2223 } 2224 OpTestSuspend(target); 2225 FlushAllRegs(); 2226 LIR* branch = OpUnconditionalBranch(nullptr); 2227 AddSlowPath(new (arena_) SuspendCheckSlowPath(this, branch, target)); 2228 } else { 2229 // For the implicit suspend check, just perform the trigger 2230 // load and branch to the target. 2231 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2232 OpUnconditionalBranch(target); 2233 return; 2234 } 2235 FlushAllRegs(); 2236 LIR* inst = CheckSuspendUsingLoad(); 2237 MarkSafepointPC(inst); 2238 OpUnconditionalBranch(target); 2239 } 2240} 2241 2242/* Call out to helper assembly routine that will null check obj and then lock it. */ 2243void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2244 FlushAllRegs(); 2245 if (cu_->target64) { 2246 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pLockObject), rl_src, true); 2247 } else { 2248 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pLockObject), rl_src, true); 2249 } 2250} 2251 2252/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2253void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2254 FlushAllRegs(); 2255 if (cu_->target64) { 2256 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject), rl_src, true); 2257 } else { 2258 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject), rl_src, true); 2259 } 2260} 2261 2262/* Generic code for generating a wide constant into a VR. */ 2263void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2264 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2265 LoadConstantWide(rl_result.reg, value); 2266 StoreValueWide(rl_dest, rl_result); 2267} 2268 2269} // namespace art 2270