call_mips.cc revision 984305917bf57b3f8d92965e4715a0370cc5bcfb
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the Mips ISA */ 18 19#include "codegen_mips.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "entrypoints/quick/quick_entrypoints.h" 22#include "gc/accounting/card_table.h" 23#include "mips_lir.h" 24 25namespace art { 26 27bool MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, 28 const InlineMethod& special) { 29 // TODO 30 return false; 31} 32 33/* 34 * The lack of pc-relative loads on Mips presents somewhat of a challenge 35 * for our PIC switch table strategy. To materialize the current location 36 * we'll do a dummy JAL and reference our tables using rRA as the 37 * base register. Note that rRA will be used both as the base to 38 * locate the switch table data and as the reference base for the switch 39 * target offsets stored in the table. We'll use a special pseudo-instruction 40 * to represent the jal and trigger the construction of the 41 * switch table offsets (which will happen after final assembly and all 42 * labels are fixed). 43 * 44 * The test loop will look something like: 45 * 46 * ori r_end, rZERO, #table_size ; size in bytes 47 * jal BaseLabel ; stores "return address" (BaseLabel) in rRA 48 * nop ; opportunistically fill 49 * BaseLabel: 50 * addiu r_base, rRA, <table> - <BaseLabel> ; table relative to BaseLabel 51 addu r_end, r_end, r_base ; end of table 52 * lw r_val, [rSP, v_reg_off] ; Test Value 53 * loop: 54 * beq r_base, r_end, done 55 * lw r_key, 0(r_base) 56 * addu r_base, 8 57 * bne r_val, r_key, loop 58 * lw r_disp, -4(r_base) 59 * addu rRA, r_disp 60 * jr rRA 61 * done: 62 * 63 */ 64void MipsMir2Lir::GenSparseSwitch(MIR* mir, DexOffset table_offset, 65 RegLocation rl_src) { 66 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 67 if (cu_->verbose) { 68 DumpSparseSwitchTable(table); 69 } 70 // Add the table to the list - we'll process it later 71 SwitchTable* tab_rec = 72 static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), kArenaAllocData)); 73 tab_rec->table = table; 74 tab_rec->vaddr = current_dalvik_offset_; 75 int elements = table[1]; 76 tab_rec->targets = 77 static_cast<LIR**>(arena_->Alloc(elements * sizeof(LIR*), kArenaAllocLIR)); 78 switch_tables_.Insert(tab_rec); 79 80 // The table is composed of 8-byte key/disp pairs 81 int byte_size = elements * 8; 82 83 int size_hi = byte_size >> 16; 84 int size_lo = byte_size & 0xffff; 85 86 RegStorage r_end = AllocTemp(); 87 if (size_hi) { 88 NewLIR2(kMipsLui, r_end.GetReg(), size_hi); 89 } 90 // Must prevent code motion for the curr pc pair 91 GenBarrier(); // Scheduling barrier 92 NewLIR0(kMipsCurrPC); // Really a jal to .+8 93 // Now, fill the branch delay slot 94 if (size_hi) { 95 NewLIR3(kMipsOri, r_end.GetReg(), r_end.GetReg(), size_lo); 96 } else { 97 NewLIR3(kMipsOri, r_end.GetReg(), rZERO, size_lo); 98 } 99 GenBarrier(); // Scheduling barrier 100 101 // Construct BaseLabel and set up table base register 102 LIR* base_label = NewLIR0(kPseudoTargetLabel); 103 // Remember base label so offsets can be computed later 104 tab_rec->anchor = base_label; 105 RegStorage r_base = AllocTemp(); 106 NewLIR4(kMipsDelta, r_base.GetReg(), 0, WrapPointer(base_label), WrapPointer(tab_rec)); 107 OpRegRegReg(kOpAdd, r_end, r_end, r_base); 108 109 // Grab switch test value 110 rl_src = LoadValue(rl_src, kCoreReg); 111 112 // Test loop 113 RegStorage r_key = AllocTemp(); 114 LIR* loop_label = NewLIR0(kPseudoTargetLabel); 115 LIR* exit_branch = OpCmpBranch(kCondEq, r_base, r_end, NULL); 116 Load32Disp(r_base, 0, r_key); 117 OpRegImm(kOpAdd, r_base, 8); 118 OpCmpBranch(kCondNe, rl_src.reg, r_key, loop_label); 119 RegStorage r_disp = AllocTemp(); 120 Load32Disp(r_base, -4, r_disp); 121 OpRegRegReg(kOpAdd, rs_rRA, rs_rRA, r_disp); 122 OpReg(kOpBx, rs_rRA); 123 124 // Loop exit 125 LIR* exit_label = NewLIR0(kPseudoTargetLabel); 126 exit_branch->target = exit_label; 127} 128 129/* 130 * Code pattern will look something like: 131 * 132 * lw r_val 133 * jal BaseLabel ; stores "return address" (BaseLabel) in rRA 134 * nop ; opportunistically fill 135 * [subiu r_val, bias] ; Remove bias if low_val != 0 136 * bound check -> done 137 * lw r_disp, [rRA, r_val] 138 * addu rRA, r_disp 139 * jr rRA 140 * done: 141 */ 142void MipsMir2Lir::GenPackedSwitch(MIR* mir, DexOffset table_offset, 143 RegLocation rl_src) { 144 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 145 if (cu_->verbose) { 146 DumpPackedSwitchTable(table); 147 } 148 // Add the table to the list - we'll process it later 149 SwitchTable* tab_rec = 150 static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), kArenaAllocData)); 151 tab_rec->table = table; 152 tab_rec->vaddr = current_dalvik_offset_; 153 int size = table[1]; 154 tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), 155 kArenaAllocLIR)); 156 switch_tables_.Insert(tab_rec); 157 158 // Get the switch value 159 rl_src = LoadValue(rl_src, kCoreReg); 160 161 // Prepare the bias. If too big, handle 1st stage here 162 int low_key = s4FromSwitchData(&table[2]); 163 bool large_bias = false; 164 RegStorage r_key; 165 if (low_key == 0) { 166 r_key = rl_src.reg; 167 } else if ((low_key & 0xffff) != low_key) { 168 r_key = AllocTemp(); 169 LoadConstant(r_key, low_key); 170 large_bias = true; 171 } else { 172 r_key = AllocTemp(); 173 } 174 175 // Must prevent code motion for the curr pc pair 176 GenBarrier(); 177 NewLIR0(kMipsCurrPC); // Really a jal to .+8 178 // Now, fill the branch delay slot with bias strip 179 if (low_key == 0) { 180 NewLIR0(kMipsNop); 181 } else { 182 if (large_bias) { 183 OpRegRegReg(kOpSub, r_key, rl_src.reg, r_key); 184 } else { 185 OpRegRegImm(kOpSub, r_key, rl_src.reg, low_key); 186 } 187 } 188 GenBarrier(); // Scheduling barrier 189 190 // Construct BaseLabel and set up table base register 191 LIR* base_label = NewLIR0(kPseudoTargetLabel); 192 // Remember base label so offsets can be computed later 193 tab_rec->anchor = base_label; 194 195 // Bounds check - if < 0 or >= size continue following switch 196 LIR* branch_over = OpCmpImmBranch(kCondHi, r_key, size-1, NULL); 197 198 // Materialize the table base pointer 199 RegStorage r_base = AllocTemp(); 200 NewLIR4(kMipsDelta, r_base.GetReg(), 0, WrapPointer(base_label), WrapPointer(tab_rec)); 201 202 // Load the displacement from the switch table 203 RegStorage r_disp = AllocTemp(); 204 LoadBaseIndexed(r_base, r_key, r_disp, 2, k32); 205 206 // Add to rAP and go 207 OpRegRegReg(kOpAdd, rs_rRA, rs_rRA, r_disp); 208 OpReg(kOpBx, rs_rRA); 209 210 /* branch_over target here */ 211 LIR* target = NewLIR0(kPseudoTargetLabel); 212 branch_over->target = target; 213} 214 215/* 216 * Array data table format: 217 * ushort ident = 0x0300 magic value 218 * ushort width width of each element in the table 219 * uint size number of elements in the table 220 * ubyte data[size*width] table of data values (may contain a single-byte 221 * padding at the end) 222 * 223 * Total size is 4+(width * size + 1)/2 16-bit code units. 224 */ 225void MipsMir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) { 226 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 227 // Add the table to the list - we'll process it later 228 FillArrayData* tab_rec = 229 reinterpret_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), 230 kArenaAllocData)); 231 tab_rec->table = table; 232 tab_rec->vaddr = current_dalvik_offset_; 233 uint16_t width = tab_rec->table[1]; 234 uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); 235 tab_rec->size = (size * width) + 8; 236 237 fill_array_data_.Insert(tab_rec); 238 239 // Making a call - use explicit registers 240 FlushAllRegs(); /* Everything to home location */ 241 LockCallTemps(); 242 LoadValueDirectFixed(rl_src, rs_rMIPS_ARG0); 243 244 // Must prevent code motion for the curr pc pair 245 GenBarrier(); 246 NewLIR0(kMipsCurrPC); // Really a jal to .+8 247 // Now, fill the branch delay slot with the helper load 248 RegStorage r_tgt = LoadHelper(kQuickHandleFillArrayData); 249 GenBarrier(); // Scheduling barrier 250 251 // Construct BaseLabel and set up table base register 252 LIR* base_label = NewLIR0(kPseudoTargetLabel); 253 254 // Materialize a pointer to the fill data image 255 NewLIR4(kMipsDelta, rMIPS_ARG1, 0, WrapPointer(base_label), WrapPointer(tab_rec)); 256 257 // And go... 258 ClobberCallerSave(); 259 LIR* call_inst = OpReg(kOpBlx, r_tgt); // ( array*, fill_data* ) 260 MarkSafepointPC(call_inst); 261} 262 263void MipsMir2Lir::GenMoveException(RegLocation rl_dest) { 264 int ex_offset = Thread::ExceptionOffset<4>().Int32Value(); 265 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 266 RegStorage reset_reg = AllocTempRef(); 267 LoadRefDisp(rs_rMIPS_SELF, ex_offset, rl_result.reg, kNotVolatile); 268 LoadConstant(reset_reg, 0); 269 StoreRefDisp(rs_rMIPS_SELF, ex_offset, reset_reg, kNotVolatile); 270 FreeTemp(reset_reg); 271 StoreValue(rl_dest, rl_result); 272} 273 274/* 275 * Mark garbage collection card. Skip if the value we're storing is null. 276 */ 277void MipsMir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { 278 RegStorage reg_card_base = AllocTemp(); 279 RegStorage reg_card_no = AllocTemp(); 280 LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); 281 // NOTE: native pointer. 282 LoadWordDisp(rs_rMIPS_SELF, Thread::CardTableOffset<4>().Int32Value(), reg_card_base); 283 OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); 284 StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte); 285 LIR* target = NewLIR0(kPseudoTargetLabel); 286 branch_over->target = target; 287 FreeTemp(reg_card_base); 288 FreeTemp(reg_card_no); 289} 290 291void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { 292 int spill_count = num_core_spills_ + num_fp_spills_; 293 /* 294 * On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live. Let the register 295 * allocation mechanism know so it doesn't try to use any of them when 296 * expanding the frame or flushing. This leaves the utility 297 * code with a single temp: r12. This should be enough. 298 */ 299 LockTemp(rs_rMIPS_ARG0); 300 LockTemp(rs_rMIPS_ARG1); 301 LockTemp(rs_rMIPS_ARG2); 302 LockTemp(rs_rMIPS_ARG3); 303 304 /* 305 * We can safely skip the stack overflow check if we're 306 * a leaf *and* our frame size < fudge factor. 307 */ 308 bool skip_overflow_check = mir_graph_->MethodIsLeaf() && !IsLargeFrame(frame_size_, kMips); 309 NewLIR0(kPseudoMethodEntry); 310 RegStorage check_reg = AllocTemp(); 311 RegStorage new_sp = AllocTemp(); 312 if (!skip_overflow_check) { 313 /* Load stack limit */ 314 Load32Disp(rs_rMIPS_SELF, Thread::StackEndOffset<4>().Int32Value(), check_reg); 315 } 316 /* Spill core callee saves */ 317 SpillCoreRegs(); 318 /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */ 319 DCHECK_EQ(num_fp_spills_, 0); 320 const int frame_sub = frame_size_ - spill_count * 4; 321 if (!skip_overflow_check) { 322 class StackOverflowSlowPath : public LIRSlowPath { 323 public: 324 StackOverflowSlowPath(Mir2Lir* m2l, LIR* branch, size_t sp_displace) 325 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, nullptr), sp_displace_(sp_displace) { 326 } 327 void Compile() OVERRIDE { 328 m2l_->ResetRegPool(); 329 m2l_->ResetDefTracking(); 330 GenerateTargetLabel(kPseudoThrowTarget); 331 // LR is offset 0 since we push in reverse order. 332 m2l_->Load32Disp(rs_rMIPS_SP, 0, rs_rRA); 333 m2l_->OpRegImm(kOpAdd, rs_rMIPS_SP, sp_displace_); 334 m2l_->ClobberCallerSave(); 335 RegStorage r_tgt = m2l_->CallHelperSetup(kQuickThrowStackOverflow); // Doesn't clobber LR. 336 m2l_->CallHelper(r_tgt, kQuickThrowStackOverflow, false /* MarkSafepointPC */, 337 false /* UseLink */); 338 } 339 340 private: 341 const size_t sp_displace_; 342 }; 343 OpRegRegImm(kOpSub, new_sp, rs_rMIPS_SP, frame_sub); 344 LIR* branch = OpCmpBranch(kCondUlt, new_sp, check_reg, nullptr); 345 AddSlowPath(new(arena_)StackOverflowSlowPath(this, branch, spill_count * 4)); 346 // TODO: avoid copy for small frame sizes. 347 OpRegCopy(rs_rMIPS_SP, new_sp); // Establish stack 348 } else { 349 OpRegImm(kOpSub, rs_rMIPS_SP, frame_sub); 350 } 351 352 FlushIns(ArgLocs, rl_method); 353 354 FreeTemp(rs_rMIPS_ARG0); 355 FreeTemp(rs_rMIPS_ARG1); 356 FreeTemp(rs_rMIPS_ARG2); 357 FreeTemp(rs_rMIPS_ARG3); 358} 359 360void MipsMir2Lir::GenExitSequence() { 361 /* 362 * In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't 363 * allocated by the register utilities as temps. 364 */ 365 LockTemp(rs_rMIPS_RET0); 366 LockTemp(rs_rMIPS_RET1); 367 368 NewLIR0(kPseudoMethodExit); 369 UnSpillCoreRegs(); 370 OpReg(kOpBx, rs_rRA); 371} 372 373void MipsMir2Lir::GenSpecialExitSequence() { 374 OpReg(kOpBx, rs_rRA); 375} 376 377} // namespace art 378