codegen_mips.h revision 5030d3ee8c6fe10394912ede107cbc8df63b7b16 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
18#define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
19
20#include "dex/compiler_internals.h"
21#include "mips_lir.h"
22
23namespace art {
24
25class MipsMir2Lir FINAL : public Mir2Lir {
26  public:
27    MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen utilities.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
33    LIR* CheckSuspendUsingLoad() OVERRIDE;
34    RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE;
35    RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE;
36    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37                      OpSize size, VolatileKind is_volatile) OVERRIDE;
38    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39                         OpSize size) OVERRIDE;
40    LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
41                             RegStorage r_dest, OpSize size) OVERRIDE;
42    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
43    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
44    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
45                       OpSize size, VolatileKind is_volatile) OVERRIDE;
46    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
47                          OpSize size) OVERRIDE;
48    LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
49                              RegStorage r_src, OpSize size) OVERRIDE;
50    LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
51    LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
52    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
53
54    // Required for target - register utilities.
55    RegStorage Solo64ToPair64(RegStorage reg);
56    RegStorage TargetReg(SpecialTargetRegister reg);
57    RegStorage GetArgMappingToPhysicalReg(int arg_num);
58    RegLocation GetReturnAlt();
59    RegLocation GetReturnWideAlt();
60    RegLocation LocCReturn();
61    RegLocation LocCReturnRef();
62    RegLocation LocCReturnDouble();
63    RegLocation LocCReturnFloat();
64    RegLocation LocCReturnWide();
65    ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
66    void AdjustSpillMask();
67    void ClobberCallerSave();
68    void FreeCallTemps();
69    void LockCallTemps();
70    void CompilerInitializeRegAlloc();
71
72    // Required for target - miscellaneous.
73    void AssembleLIR();
74    int AssignInsnOffsets();
75    void AssignOffsets();
76    AssemblerStatus AssembleInstructions(CodeOffset start_addr);
77    void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
78    void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
79                                  ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
80    const char* GetTargetInstFmt(int opcode);
81    const char* GetTargetInstName(int opcode);
82    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
83    ResourceMask GetPCUseDefEncoding() const OVERRIDE;
84    uint64_t GetTargetInstFlags(int opcode);
85    size_t GetInsnSize(LIR* lir) OVERRIDE;
86    bool IsUnconditionalBranch(LIR* lir);
87
88    // Get the register class for load/store of a field.
89    RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
90
91    // Required for target - Dalvik-level generators.
92    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
93                           RegLocation rl_src1, RegLocation rl_src2);
94    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
95                     RegLocation rl_index, RegLocation rl_dest, int scale);
96    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
97                     RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
98    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
99                           RegLocation rl_shift);
100    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
101                    RegLocation rl_src2);
102    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
103                    RegLocation rl_src2);
104    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105                    RegLocation rl_src2);
106    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107                          RegLocation rl_src2);
108    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
109                         RegLocation rl_src2);
110    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
111                  RegLocation rl_src2);
112    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
113    bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE;
114    bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE;
115    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
116    bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long);
117    bool GenInlinedSqrt(CallInfo* info);
118    bool GenInlinedPeek(CallInfo* info, OpSize size);
119    bool GenInlinedPoke(CallInfo* info, OpSize size);
120    void GenNotLong(RegLocation rl_dest, RegLocation rl_src);
121    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
122    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
123                   RegLocation rl_src2);
124    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
125                    RegLocation rl_src2);
126    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
127                    RegLocation rl_src2);
128    void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
129                       RegLocation rl_src2, bool is_div);
130    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
131    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
132    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
133    void GenDivZeroCheckWide(RegStorage reg);
134    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
135    void GenExitSequence();
136    void GenSpecialExitSequence();
137    void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
138    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
139    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
140    void GenSelect(BasicBlock* bb, MIR* mir);
141    void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
142                          int32_t true_val, int32_t false_val, RegStorage rs_dest,
143                          int dest_reg_class) OVERRIDE;
144    bool GenMemBarrier(MemBarrierKind barrier_kind);
145    void GenMoveException(RegLocation rl_dest);
146    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
147                                       int first_bit, int second_bit);
148    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
149    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
150    void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
151    void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
152    bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special);
153
154    // Required for target - single operation generators.
155    LIR* OpUnconditionalBranch(LIR* target);
156    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
157    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
158    LIR* OpCondBranch(ConditionCode cc, LIR* target);
159    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
160    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
161    LIR* OpIT(ConditionCode cond, const char* guide);
162    void OpEndIT(LIR* it);
163    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
164    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
165    LIR* OpReg(OpKind op, RegStorage r_dest_src);
166    void OpRegCopy(RegStorage r_dest, RegStorage r_src);
167    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
168    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
169    LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
170    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
171    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
172    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
173    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
174    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
175    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
176    LIR* OpTestSuspend(LIR* target);
177    LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE;
178    LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE;
179    LIR* OpVldm(RegStorage r_base, int count);
180    LIR* OpVstm(RegStorage r_base, int count);
181    void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
182    void OpRegCopyWide(RegStorage dest, RegStorage src);
183    void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE;
184    void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE;
185
186    // TODO: collapse r_dest.
187    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
188                          OpSize size);
189    // TODO: collapse r_src.
190    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
191                           OpSize size);
192    void SpillCoreRegs();
193    void UnSpillCoreRegs();
194    static const MipsEncodingMap EncodingMap[kMipsLast];
195    bool InexpensiveConstantInt(int32_t value);
196    bool InexpensiveConstantFloat(int32_t value);
197    bool InexpensiveConstantLong(int64_t value);
198    bool InexpensiveConstantDouble(int64_t value);
199
200    bool WideGPRsAreAliases() OVERRIDE {
201      return false;  // Wide GPRs are formed by pairing.
202    }
203    bool WideFPRsAreAliases() OVERRIDE {
204      return false;  // Wide FPRs are formed by pairing.
205    }
206
207  private:
208    void ConvertShortToLongBranch(LIR* lir);
209    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
210                          RegLocation rl_src2, bool is_div, bool check_zero);
211    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
212};
213
214}  // namespace art
215
216#endif  // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
217