codegen_mips.h revision 90969af6deb19b1dbe356d62fe68d8f5698d3d8f 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
18#define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
19
20#include "dex/compiler_internals.h"
21#include "mips_lir.h"
22
23namespace art {
24
25class MipsMir2Lir FINAL : public Mir2Lir {
26  public:
27    MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen utilities.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
33    LIR* CheckSuspendUsingLoad() OVERRIDE;
34    RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE;
35    RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE;
36    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37                      OpSize size, VolatileKind is_volatile) OVERRIDE;
38    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39                         OpSize size) OVERRIDE;
40    LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
41                             RegStorage r_dest, OpSize size) OVERRIDE;
42    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
43    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
44    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
45                       OpSize size, VolatileKind is_volatile) OVERRIDE;
46    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
47                          OpSize size) OVERRIDE;
48    LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
49                              RegStorage r_src, OpSize size) OVERRIDE;
50    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
51
52    // Required for target - register utilities.
53    RegStorage Solo64ToPair64(RegStorage reg);
54    RegStorage TargetReg(SpecialTargetRegister reg);
55    RegStorage GetArgMappingToPhysicalReg(int arg_num);
56    RegLocation GetReturnAlt();
57    RegLocation GetReturnWideAlt();
58    RegLocation LocCReturn();
59    RegLocation LocCReturnRef();
60    RegLocation LocCReturnDouble();
61    RegLocation LocCReturnFloat();
62    RegLocation LocCReturnWide();
63    ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
64    void AdjustSpillMask();
65    void ClobberCallerSave();
66    void FreeCallTemps();
67    void LockCallTemps();
68    void CompilerInitializeRegAlloc();
69
70    // Required for target - miscellaneous.
71    void AssembleLIR();
72    int AssignInsnOffsets();
73    void AssignOffsets();
74    AssemblerStatus AssembleInstructions(CodeOffset start_addr);
75    void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
76    void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
77                                  ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
78    const char* GetTargetInstFmt(int opcode);
79    const char* GetTargetInstName(int opcode);
80    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
81    ResourceMask GetPCUseDefEncoding() const OVERRIDE;
82    uint64_t GetTargetInstFlags(int opcode);
83    size_t GetInsnSize(LIR* lir) OVERRIDE;
84    bool IsUnconditionalBranch(LIR* lir);
85
86    // Check support for volatile load/store of a given size.
87    bool SupportsVolatileLoadStore(OpSize size) OVERRIDE;
88    // Get the register class for load/store of a field.
89    RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
90
91    // Required for target - Dalvik-level generators.
92    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
93                           RegLocation rl_src1, RegLocation rl_src2);
94    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
95                     RegLocation rl_index, RegLocation rl_dest, int scale);
96    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
97                     RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
98    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
99                           RegLocation rl_shift);
100    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
101                    RegLocation rl_src2);
102    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
103                    RegLocation rl_src2);
104    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105                    RegLocation rl_src2);
106    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107                          RegLocation rl_src2);
108    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
109                         RegLocation rl_src2);
110    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
111                  RegLocation rl_src2);
112    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
113    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
114    bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long);
115    bool GenInlinedSqrt(CallInfo* info);
116    bool GenInlinedPeek(CallInfo* info, OpSize size);
117    bool GenInlinedPoke(CallInfo* info, OpSize size);
118    void GenNotLong(RegLocation rl_dest, RegLocation rl_src);
119    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
120    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
121                   RegLocation rl_src2);
122    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
123                    RegLocation rl_src2);
124    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
125                    RegLocation rl_src2);
126    void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
127                       RegLocation rl_src2, bool is_div);
128    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
129    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
130    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
131    void GenDivZeroCheckWide(RegStorage reg);
132    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
133    void GenExitSequence();
134    void GenSpecialExitSequence();
135    void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
136    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
137    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
138    void GenSelect(BasicBlock* bb, MIR* mir);
139    void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
140                          int32_t true_val, int32_t false_val, RegStorage rs_dest,
141                          int dest_reg_class) OVERRIDE;
142    bool GenMemBarrier(MemBarrierKind barrier_kind);
143    void GenMoveException(RegLocation rl_dest);
144    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
145                                       int first_bit, int second_bit);
146    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
147    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
148    void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
149    void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
150    bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special);
151
152    // Required for target - single operation generators.
153    LIR* OpUnconditionalBranch(LIR* target);
154    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
155    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
156    LIR* OpCondBranch(ConditionCode cc, LIR* target);
157    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
158    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
159    LIR* OpIT(ConditionCode cond, const char* guide);
160    void OpEndIT(LIR* it);
161    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
162    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
163    LIR* OpReg(OpKind op, RegStorage r_dest_src);
164    void OpRegCopy(RegStorage r_dest, RegStorage r_src);
165    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
166    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
167    LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
168    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
169    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
170    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
171    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
172    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
173    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
174    LIR* OpTestSuspend(LIR* target);
175    LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE;
176    LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE;
177    LIR* OpVldm(RegStorage r_base, int count);
178    LIR* OpVstm(RegStorage r_base, int count);
179    void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
180    void OpRegCopyWide(RegStorage dest, RegStorage src);
181    void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE;
182    void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE;
183
184    // TODO: collapse r_dest.
185    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
186                          OpSize size);
187    // TODO: collapse r_src.
188    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
189                           OpSize size);
190    void SpillCoreRegs();
191    void UnSpillCoreRegs();
192    static const MipsEncodingMap EncodingMap[kMipsLast];
193    bool InexpensiveConstantInt(int32_t value);
194    bool InexpensiveConstantFloat(int32_t value);
195    bool InexpensiveConstantLong(int64_t value);
196    bool InexpensiveConstantDouble(int64_t value);
197
198    bool WideGPRsAreAliases() OVERRIDE {
199      return false;  // Wide GPRs are formed by pairing.
200    }
201    bool WideFPRsAreAliases() OVERRIDE {
202      return false;  // Wide FPRs are formed by pairing.
203    }
204
205  private:
206    void ConvertShortToLongBranch(LIR* lir);
207    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
208                          RegLocation rl_src2, bool is_div, bool check_zero);
209    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
210};
211
212}  // namespace art
213
214#endif  // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
215