mir_to_lir.h revision 2700f7e1edbcd2518f4978e4cd0e05a4149f91b6
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87 88// Common combo register usage patterns. 89#define REG_DEF01 (REG_DEF0 | REG_DEF1) 90#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 91#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 92#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 93#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 94#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 95#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 96#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 97#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 98#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 99#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 100#define REG_USE012 (REG_USE01 | REG_USE2) 101#define REG_USE014 (REG_USE01 | REG_USE4) 102#define REG_USE01 (REG_USE0 | REG_USE1) 103#define REG_USE02 (REG_USE0 | REG_USE2) 104#define REG_USE12 (REG_USE1 | REG_USE2) 105#define REG_USE23 (REG_USE2 | REG_USE3) 106#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 107 108struct BasicBlock; 109struct CallInfo; 110struct CompilationUnit; 111struct InlineMethod; 112struct MIR; 113struct LIR; 114struct RegLocation; 115struct RegisterInfo; 116class DexFileMethodInliner; 117class MIRGraph; 118class Mir2Lir; 119 120typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 121 const MethodReference& target_method, 122 uint32_t method_idx, uintptr_t direct_code, 123 uintptr_t direct_method, InvokeType type); 124 125typedef std::vector<uint8_t> CodeBuffer; 126 127struct UseDefMasks { 128 uint64_t use_mask; // Resource mask for use. 129 uint64_t def_mask; // Resource mask for def. 130}; 131 132struct AssemblyInfo { 133 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 134 uint8_t bytes[16]; // Encoded instruction bytes. 135}; 136 137struct LIR { 138 CodeOffset offset; // Offset of this instruction. 139 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 140 int16_t opcode; 141 LIR* next; 142 LIR* prev; 143 LIR* target; 144 struct { 145 unsigned int alias_info:17; // For Dalvik register disambiguation. 146 bool is_nop:1; // LIR is optimized away. 147 unsigned int size:4; // Note: size of encoded instruction is in bytes. 148 bool use_def_invalid:1; // If true, masks should not be used. 149 unsigned int generation:1; // Used to track visitation state during fixup pass. 150 unsigned int fixup:8; // Fixup kind. 151 } flags; 152 union { 153 UseDefMasks m; // Use & Def masks used during optimization. 154 AssemblyInfo a; // Instruction encoding used during assembly phase. 155 } u; 156 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 157}; 158 159// Target-specific initialization. 160Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 161 ArenaAllocator* const arena); 162Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 163 ArenaAllocator* const arena); 164Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 165 ArenaAllocator* const arena); 166 167// Utility macros to traverse the LIR list. 168#define NEXT_LIR(lir) (lir->next) 169#define PREV_LIR(lir) (lir->prev) 170 171// Defines for alias_info (tracks Dalvik register references). 172#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 173#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 174#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 175#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 176 177// Common resource macros. 178#define ENCODE_CCODE (1ULL << kCCode) 179#define ENCODE_FP_STATUS (1ULL << kFPStatus) 180 181// Abstract memory locations. 182#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 183#define ENCODE_LITERAL (1ULL << kLiteral) 184#define ENCODE_HEAP_REF (1ULL << kHeapRef) 185#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 186 187#define ENCODE_ALL (~0ULL) 188#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 189 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 190 191#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 192#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 193 do { \ 194 low_reg = both_regs & 0xff; \ 195 high_reg = (both_regs >> 8) & 0xff; \ 196 } while (false) 197 198// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 199#define STARTING_DOUBLE_SREG 0x10000 200 201// TODO: replace these macros 202#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 203#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 204#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 205#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 206#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 207 208class Mir2Lir : public Backend { 209 public: 210 /* 211 * Auxiliary information describing the location of data embedded in the Dalvik 212 * byte code stream. 213 */ 214 struct EmbeddedData { 215 CodeOffset offset; // Code offset of data block. 216 const uint16_t* table; // Original dex data. 217 DexOffset vaddr; // Dalvik offset of parent opcode. 218 }; 219 220 struct FillArrayData : EmbeddedData { 221 int32_t size; 222 }; 223 224 struct SwitchTable : EmbeddedData { 225 LIR* anchor; // Reference instruction for relative offsets. 226 LIR** targets; // Array of case targets. 227 }; 228 229 /* Static register use counts */ 230 struct RefCounts { 231 int count; 232 int s_reg; 233 }; 234 235 /* 236 * Data structure tracking the mapping between a Dalvik register (pair) and a 237 * native register (pair). The idea is to reuse the previously loaded value 238 * if possible, otherwise to keep the value in a native register as long as 239 * possible. 240 */ 241 struct RegisterInfo { 242 int reg; // Reg number 243 bool in_use; // Has it been allocated? 244 bool is_temp; // Can allocate as temp? 245 bool pair; // Part of a register pair? 246 int partner; // If pair, other reg of pair. 247 bool live; // Is there an associated SSA name? 248 bool dirty; // If live, is it dirty? 249 int s_reg; // Name of live value. 250 LIR *def_start; // Starting inst in last def sequence. 251 LIR *def_end; // Ending inst in last def sequence. 252 }; 253 254 struct RegisterPool { 255 int num_core_regs; 256 RegisterInfo *core_regs; 257 int next_core_reg; 258 int num_fp_regs; 259 RegisterInfo *FPRegs; 260 int next_fp_reg; 261 }; 262 263 struct PromotionMap { 264 RegLocationType core_location:3; 265 uint8_t core_reg; 266 RegLocationType fp_location:3; 267 uint8_t FpReg; 268 bool first_in_pair; 269 }; 270 271 // 272 // Slow paths. This object is used generate a sequence of code that is executed in the 273 // slow path. For example, resolving a string or class is slow as it will only be executed 274 // once (after that it is resolved and doesn't need to be done again). We want slow paths 275 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 276 // branch over them. 277 // 278 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 279 // the Compile() function that will be called near the end of the code generated by the 280 // method. 281 // 282 // The basic flow for a slow path is: 283 // 284 // CMP reg, #value 285 // BEQ fromfast 286 // cont: 287 // ... 288 // fast path code 289 // ... 290 // more code 291 // ... 292 // RETURN 293 /// 294 // fromfast: 295 // ... 296 // slow path code 297 // ... 298 // B cont 299 // 300 // So you see we need two labels and two branches. The first branch (called fromfast) is 301 // the conditional branch to the slow path code. The second label (called cont) is used 302 // as an unconditional branch target for getting back to the code after the slow path 303 // has completed. 304 // 305 306 class LIRSlowPath { 307 public: 308 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 309 LIR* cont = nullptr) : 310 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 311 } 312 virtual ~LIRSlowPath() {} 313 virtual void Compile() = 0; 314 315 static void* operator new(size_t size, ArenaAllocator* arena) { 316 return arena->Alloc(size, kArenaAllocData); 317 } 318 319 protected: 320 LIR* GenerateTargetLabel(); 321 322 Mir2Lir* const m2l_; 323 const DexOffset current_dex_pc_; 324 LIR* const fromfast_; 325 LIR* const cont_; 326 }; 327 328 virtual ~Mir2Lir() {} 329 330 int32_t s4FromSwitchData(const void* switch_data) { 331 return *reinterpret_cast<const int32_t*>(switch_data); 332 } 333 334 RegisterClass oat_reg_class_by_size(OpSize size) { 335 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 336 size == kSignedByte) ? kCoreReg : kAnyReg; 337 } 338 339 size_t CodeBufferSizeInBytes() { 340 return code_buffer_.size() / sizeof(code_buffer_[0]); 341 } 342 343 bool IsPseudoLirOp(int opcode) { 344 return (opcode < 0); 345 } 346 347 /* 348 * LIR operands are 32-bit integers. Sometimes, (especially for managing 349 * instructions which require PC-relative fixups), we need the operands to carry 350 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 351 * hold that index in the operand array. 352 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 353 * may be worth conditionally-compiling a set of identity functions here. 354 */ 355 uint32_t WrapPointer(void* pointer) { 356 uint32_t res = pointer_storage_.Size(); 357 pointer_storage_.Insert(pointer); 358 return res; 359 } 360 361 void* UnwrapPointer(size_t index) { 362 return pointer_storage_.Get(index); 363 } 364 365 // strdup(), but allocates from the arena. 366 char* ArenaStrdup(const char* str) { 367 size_t len = strlen(str) + 1; 368 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 369 if (res != NULL) { 370 strncpy(res, str, len); 371 } 372 return res; 373 } 374 375 // Shared by all targets - implemented in codegen_util.cc 376 void AppendLIR(LIR* lir); 377 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 378 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 379 380 /** 381 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 382 * to place in a frame. 383 * @return Returns the maximum number of compiler temporaries. 384 */ 385 size_t GetMaxPossibleCompilerTemps() const; 386 387 /** 388 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 389 * @return Returns the size in bytes for space needed for compiler temporary spill region. 390 */ 391 size_t GetNumBytesForCompilerTempSpillRegion(); 392 393 DexOffset GetCurrentDexPc() const { 394 return current_dalvik_offset_; 395 } 396 397 int ComputeFrameSize(); 398 virtual void Materialize(); 399 virtual CompiledMethod* GetCompiledMethod(); 400 void MarkSafepointPC(LIR* inst); 401 void SetupResourceMasks(LIR* lir); 402 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 403 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 404 void SetupRegMask(uint64_t* mask, int reg); 405 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 406 void DumpPromotionMap(); 407 void CodegenDump(); 408 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 409 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 410 LIR* NewLIR0(int opcode); 411 LIR* NewLIR1(int opcode, int dest); 412 LIR* NewLIR2(int opcode, int dest, int src1); 413 LIR* NewLIR2NoDest(int opcode, int src, int info); 414 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 415 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 416 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 417 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 418 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 419 LIR* AddWordData(LIR* *constant_list_p, int value); 420 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 421 void ProcessSwitchTables(); 422 void DumpSparseSwitchTable(const uint16_t* table); 423 void DumpPackedSwitchTable(const uint16_t* table); 424 void MarkBoundary(DexOffset offset, const char* inst_str); 425 void NopLIR(LIR* lir); 426 void UnlinkLIR(LIR* lir); 427 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 428 bool IsInexpensiveConstant(RegLocation rl_src); 429 ConditionCode FlipComparisonOrder(ConditionCode before); 430 ConditionCode NegateComparison(ConditionCode before); 431 virtual void InstallLiteralPools(); 432 void InstallSwitchTables(); 433 void InstallFillArrayData(); 434 bool VerifyCatchEntries(); 435 void CreateMappingTables(); 436 void CreateNativeGcMap(); 437 int AssignLiteralOffset(CodeOffset offset); 438 int AssignSwitchTablesOffset(CodeOffset offset); 439 int AssignFillArrayDataOffset(CodeOffset offset); 440 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 441 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 442 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 443 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 444 RegLocation NarrowRegLoc(RegLocation loc); 445 446 // Shared by all targets - implemented in local_optimizations.cc 447 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 448 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 449 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 450 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 451 452 // Shared by all targets - implemented in ralloc_util.cc 453 int GetSRegHi(int lowSreg); 454 bool oat_live_out(int s_reg); 455 int oatSSASrc(MIR* mir, int num); 456 void SimpleRegAlloc(); 457 void ResetRegPool(); 458 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 459 void DumpRegPool(RegisterInfo* p, int num_regs); 460 void DumpCoreRegPool(); 461 void DumpFpRegPool(); 462 /* Mark a temp register as dead. Does not affect allocation state. */ 463 void Clobber(int reg) { 464 ClobberBody(GetRegInfo(reg)); 465 } 466 void Clobber(RegStorage reg); 467 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 468 void ClobberSReg(int s_reg); 469 int SRegToPMap(int s_reg); 470 void RecordCorePromotion(RegStorage reg, int s_reg); 471 RegStorage AllocPreservedCoreReg(int s_reg); 472 void RecordFpPromotion(RegStorage reg, int s_reg); 473 RegStorage AllocPreservedSingle(int s_reg); 474 RegStorage AllocPreservedDouble(int s_reg); 475 RegStorage AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 476 virtual RegStorage AllocTempDouble(); 477 RegStorage AllocFreeTemp(); 478 RegStorage AllocTemp(); 479 RegStorage AllocTempFloat(); 480 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 481 RegisterInfo* AllocLive(int s_reg, int reg_class); 482 void FreeTemp(int reg); 483 void FreeTemp(RegStorage reg); 484 RegisterInfo* IsLive(int reg); 485 RegisterInfo* IsLive(RegStorage reg); 486 RegisterInfo* IsTemp(int reg); 487 RegisterInfo* IsTemp(RegStorage reg); 488 RegisterInfo* IsPromoted(int reg); 489 RegisterInfo* IsPromoted(RegStorage reg); 490 bool IsDirty(int reg); 491 bool IsDirty(RegStorage reg); 492 void LockTemp(int reg); 493 void LockTemp(RegStorage reg); 494 void ResetDef(int reg); 495 void ResetDef(RegStorage reg); 496 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 497 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 498 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 499 RegLocation WideToNarrow(RegLocation rl); 500 void ResetDefLoc(RegLocation rl); 501 virtual void ResetDefLocWide(RegLocation rl); 502 void ResetDefTracking(); 503 void ClobberAllRegs(); 504 void FlushSpecificReg(RegisterInfo* info); 505 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 506 void FlushAllRegs(); 507 bool RegClassMatches(int reg_class, RegStorage reg); 508 void MarkLive(RegStorage reg, int s_reg); 509 void MarkTemp(int reg); 510 void MarkTemp(RegStorage reg); 511 void UnmarkTemp(int reg); 512 void UnmarkTemp(RegStorage reg); 513 void MarkPair(int low_reg, int high_reg); 514 void MarkClean(RegLocation loc); 515 void MarkDirty(RegLocation loc); 516 void MarkInUse(int reg); 517 void MarkInUse(RegStorage reg); 518 void CopyRegInfo(int new_reg, int old_reg); 519 void CopyRegInfo(RegStorage new_reg, RegStorage old_reg); 520 bool CheckCorePoolSanity(); 521 RegLocation UpdateLoc(RegLocation loc); 522 virtual RegLocation UpdateLocWide(RegLocation loc); 523 RegLocation UpdateRawLoc(RegLocation loc); 524 525 /** 526 * @brief Used to load register location into a typed temporary or pair of temporaries. 527 * @see EvalLoc 528 * @param loc The register location to load from. 529 * @param reg_class Type of register needed. 530 * @param update Whether the liveness information should be updated. 531 * @return Returns the properly typed temporary in physical register pairs. 532 */ 533 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 534 535 /** 536 * @brief Used to load register location into a typed temporary. 537 * @param loc The register location to load from. 538 * @param reg_class Type of register needed. 539 * @param update Whether the liveness information should be updated. 540 * @return Returns the properly typed temporary in physical register. 541 */ 542 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 543 544 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 545 void DumpCounts(const RefCounts* arr, int size, const char* msg); 546 void DoPromotion(); 547 int VRegOffset(int v_reg); 548 int SRegOffset(int s_reg); 549 RegLocation GetReturnWide(bool is_double); 550 RegLocation GetReturn(bool is_float); 551 RegisterInfo* GetRegInfo(int reg); 552 553 // Shared by all targets - implemented in gen_common.cc. 554 void AddIntrinsicLaunchpad(CallInfo* info, LIR* branch, LIR* resume = nullptr); 555 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 556 RegLocation rl_src, RegLocation rl_dest, int lit); 557 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 558 void HandleSuspendLaunchPads(); 559 void HandleThrowLaunchPads(); 560 void HandleSlowPaths(); 561 void GenBarrier(); 562 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 563 void MarkPossibleNullPointerException(int opt_flags); 564 void MarkPossibleStackOverflowException(); 565 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 566 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 567 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 568 LIR* GenRegRegCheck(ConditionCode c_code, RegStorage reg1, RegStorage reg2, ThrowKind kind); 569 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 570 RegLocation rl_src2, LIR* taken, LIR* fall_through); 571 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 572 LIR* taken, LIR* fall_through); 573 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 574 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 575 RegLocation rl_src); 576 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 577 RegLocation rl_src); 578 void GenFilledNewArray(CallInfo* info); 579 void GenSput(MIR* mir, RegLocation rl_src, 580 bool is_long_or_double, bool is_object); 581 void GenSget(MIR* mir, RegLocation rl_dest, 582 bool is_long_or_double, bool is_object); 583 void GenIGet(MIR* mir, int opt_flags, OpSize size, 584 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 585 void GenIPut(MIR* mir, int opt_flags, OpSize size, 586 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 587 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 588 RegLocation rl_src); 589 590 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 591 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 592 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 593 void GenThrow(RegLocation rl_src); 594 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 595 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 596 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 597 RegLocation rl_src1, RegLocation rl_src2); 598 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 599 RegLocation rl_src1, RegLocation rl_shift); 600 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 601 RegLocation rl_src, int lit); 602 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 603 RegLocation rl_src1, RegLocation rl_src2); 604 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 605 RegLocation rl_src); 606 void GenSuspendTest(int opt_flags); 607 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 608 609 // This will be overridden by x86 implementation. 610 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 611 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 612 RegLocation rl_src1, RegLocation rl_src2); 613 614 // Shared by all targets - implemented in gen_invoke.cc. 615 LIR* CallHelper(RegStorage r_tgt, ThreadOffset helper_offset, bool safepoint_pc, 616 bool use_link = true); 617 RegStorage CallHelperSetup(ThreadOffset helper_offset); 618 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 619 void CallRuntimeHelperReg(ThreadOffset helper_offset, RegStorage arg0, bool safepoint_pc); 620 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 621 bool safepoint_pc); 622 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 623 bool safepoint_pc); 624 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 625 RegLocation arg1, bool safepoint_pc); 626 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 627 int arg1, bool safepoint_pc); 628 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, RegStorage arg1, 629 bool safepoint_pc); 630 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, RegStorage arg0, int arg1, 631 bool safepoint_pc); 632 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 633 bool safepoint_pc); 634 void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, RegStorage arg0, bool safepoint_pc); 635 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, RegStorage arg0, 636 RegLocation arg2, bool safepoint_pc); 637 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 638 RegLocation arg0, RegLocation arg1, 639 bool safepoint_pc); 640 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, RegStorage arg0, RegStorage arg1, 641 bool safepoint_pc); 642 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, RegStorage arg0, RegStorage arg1, 643 int arg2, bool safepoint_pc); 644 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 645 RegLocation arg2, bool safepoint_pc); 646 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 647 bool safepoint_pc); 648 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 649 int arg0, RegLocation arg1, RegLocation arg2, 650 bool safepoint_pc); 651 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 652 RegLocation arg0, RegLocation arg1, 653 RegLocation arg2, 654 bool safepoint_pc); 655 void GenInvoke(CallInfo* info); 656 void GenInvokeNoInline(CallInfo* info); 657 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 658 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 659 NextCallInsn next_call_insn, 660 const MethodReference& target_method, 661 uint32_t vtable_idx, 662 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 663 bool skip_this); 664 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 665 NextCallInsn next_call_insn, 666 const MethodReference& target_method, 667 uint32_t vtable_idx, 668 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 669 bool skip_this); 670 671 /** 672 * @brief Used to determine the register location of destination. 673 * @details This is needed during generation of inline intrinsics because it finds destination of return, 674 * either the physical register or the target of move-result. 675 * @param info Information about the invoke. 676 * @return Returns the destination location. 677 */ 678 RegLocation InlineTarget(CallInfo* info); 679 680 /** 681 * @brief Used to determine the wide register location of destination. 682 * @see InlineTarget 683 * @param info Information about the invoke. 684 * @return Returns the destination location. 685 */ 686 RegLocation InlineTargetWide(CallInfo* info); 687 688 bool GenInlinedCharAt(CallInfo* info); 689 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 690 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 691 bool GenInlinedAbsInt(CallInfo* info); 692 bool GenInlinedAbsLong(CallInfo* info); 693 bool GenInlinedAbsFloat(CallInfo* info); 694 bool GenInlinedAbsDouble(CallInfo* info); 695 bool GenInlinedFloatCvt(CallInfo* info); 696 bool GenInlinedDoubleCvt(CallInfo* info); 697 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 698 bool GenInlinedStringCompareTo(CallInfo* info); 699 bool GenInlinedCurrentThread(CallInfo* info); 700 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 701 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 702 bool is_volatile, bool is_ordered); 703 int LoadArgRegs(CallInfo* info, int call_state, 704 NextCallInsn next_call_insn, 705 const MethodReference& target_method, 706 uint32_t vtable_idx, 707 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 708 bool skip_this); 709 710 // Shared by all targets - implemented in gen_loadstore.cc. 711 RegLocation LoadCurrMethod(); 712 void LoadCurrMethodDirect(RegStorage r_tgt); 713 LIR* LoadConstant(RegStorage r_dest, int value); 714 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest); 715 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 716 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 717 void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 718 void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 719 void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 720 void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 721 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src); 722 723 /** 724 * @brief Used to do the final store in the destination as per bytecode semantics. 725 * @param rl_dest The destination dalvik register location. 726 * @param rl_src The source register location. Can be either physical register or dalvik register. 727 */ 728 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 729 730 /** 731 * @brief Used to do the final store in a wide destination as per bytecode semantics. 732 * @see StoreValue 733 * @param rl_dest The destination dalvik register location. 734 * @param rl_src The source register location. Can be either physical register or dalvik register. 735 */ 736 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 737 738 /** 739 * @brief Used to do the final store to a destination as per bytecode semantics. 740 * @see StoreValue 741 * @param rl_dest The destination dalvik register location. 742 * @param rl_src The source register location. It must be kLocPhysReg 743 * 744 * This is used for x86 two operand computations, where we have computed the correct 745 * register value that now needs to be properly registered. This is used to avoid an 746 * extra register copy that would result if StoreValue was called. 747 */ 748 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 749 750 /** 751 * @brief Used to do the final store in a wide destination as per bytecode semantics. 752 * @see StoreValueWide 753 * @param rl_dest The destination dalvik register location. 754 * @param rl_src The source register location. It must be kLocPhysReg 755 * 756 * This is used for x86 two operand computations, where we have computed the correct 757 * register values that now need to be properly registered. This is used to avoid an 758 * extra pair of register copies that would result if StoreValueWide was called. 759 */ 760 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 761 762 // Shared by all targets - implemented in mir_to_lir.cc. 763 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 764 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 765 bool MethodBlockCodeGen(BasicBlock* bb); 766 bool SpecialMIR2LIR(const InlineMethod& special); 767 void MethodMIR2LIR(); 768 769 /* 770 * @brief Load the address of the dex method into the register. 771 * @param target_method The MethodReference of the method to be invoked. 772 * @param type How the method will be invoked. 773 * @param register that will contain the code address. 774 * @note register will be passed to TargetReg to get physical register. 775 */ 776 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 777 SpecialTargetRegister symbolic_reg); 778 779 /* 780 * @brief Load the Method* of a dex method into the register. 781 * @param target_method The MethodReference of the method to be invoked. 782 * @param type How the method will be invoked. 783 * @param register that will contain the code address. 784 * @note register will be passed to TargetReg to get physical register. 785 */ 786 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 787 SpecialTargetRegister symbolic_reg); 788 789 /* 790 * @brief Load the Class* of a Dex Class type into the register. 791 * @param type How the method will be invoked. 792 * @param register that will contain the code address. 793 * @note register will be passed to TargetReg to get physical register. 794 */ 795 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 796 797 // Routines that work for the generic case, but may be overriden by target. 798 /* 799 * @brief Compare memory to immediate, and branch if condition true. 800 * @param cond The condition code that when true will branch to the target. 801 * @param temp_reg A temporary register that can be used if compare to memory is not 802 * supported by the architecture. 803 * @param base_reg The register holding the base address. 804 * @param offset The offset from the base. 805 * @param check_value The immediate to compare to. 806 * @returns The branch instruction that was generated. 807 */ 808 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 809 int offset, int check_value, LIR* target); 810 811 // Required for target - codegen helpers. 812 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 813 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 814 virtual LIR* CheckSuspendUsingLoad() = 0; 815 virtual RegStorage LoadHelper(ThreadOffset offset) = 0; 816 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 817 int s_reg) = 0; 818 virtual LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, 819 int s_reg) = 0; 820 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 821 int scale, OpSize size) = 0; 822 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 823 int displacement, RegStorage r_dest, RegStorage r_dest_hi, 824 OpSize size, int s_reg) = 0; 825 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 826 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 827 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 828 OpSize size) = 0; 829 virtual LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) = 0; 830 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 831 int scale, OpSize size) = 0; 832 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 833 int displacement, RegStorage r_src, RegStorage r_src_hi, 834 OpSize size, int s_reg) = 0; 835 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 836 837 // Required for target - register utilities. 838 virtual bool IsFpReg(int reg) = 0; 839 virtual bool IsFpReg(RegStorage reg) = 0; 840 virtual bool SameRegType(int reg1, int reg2) = 0; 841 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 842 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 843 // TODO: elminate S2d. 844 virtual int S2d(int low_reg, int high_reg) = 0; 845 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 846 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 847 virtual RegLocation GetReturnAlt() = 0; 848 virtual RegLocation GetReturnWideAlt() = 0; 849 virtual RegLocation LocCReturn() = 0; 850 virtual RegLocation LocCReturnDouble() = 0; 851 virtual RegLocation LocCReturnFloat() = 0; 852 virtual RegLocation LocCReturnWide() = 0; 853 // TODO: use to reduce/eliminate xx_FPREG() macro use. 854 virtual uint32_t FpRegMask() = 0; 855 virtual uint64_t GetRegMaskCommon(int reg) = 0; 856 virtual void AdjustSpillMask() = 0; 857 virtual void ClobberCallerSave() = 0; 858 virtual void FlushReg(RegStorage reg) = 0; 859 virtual void FlushRegWide(RegStorage reg) = 0; 860 virtual void FreeCallTemps() = 0; 861 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 862 virtual void LockCallTemps() = 0; 863 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 864 virtual void CompilerInitializeRegAlloc() = 0; 865 866 // Required for target - miscellaneous. 867 virtual void AssembleLIR() = 0; 868 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 869 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 870 virtual const char* GetTargetInstFmt(int opcode) = 0; 871 virtual const char* GetTargetInstName(int opcode) = 0; 872 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 873 virtual uint64_t GetPCUseDefEncoding() = 0; 874 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 875 virtual int GetInsnSize(LIR* lir) = 0; 876 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 877 878 // Required for target - Dalvik-level generators. 879 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 880 RegLocation rl_src1, RegLocation rl_src2) = 0; 881 virtual void GenMulLong(Instruction::Code, 882 RegLocation rl_dest, RegLocation rl_src1, 883 RegLocation rl_src2) = 0; 884 virtual void GenAddLong(Instruction::Code, 885 RegLocation rl_dest, RegLocation rl_src1, 886 RegLocation rl_src2) = 0; 887 virtual void GenAndLong(Instruction::Code, 888 RegLocation rl_dest, RegLocation rl_src1, 889 RegLocation rl_src2) = 0; 890 virtual void GenArithOpDouble(Instruction::Code opcode, 891 RegLocation rl_dest, RegLocation rl_src1, 892 RegLocation rl_src2) = 0; 893 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 894 RegLocation rl_src1, RegLocation rl_src2) = 0; 895 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 896 RegLocation rl_src1, RegLocation rl_src2) = 0; 897 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 898 RegLocation rl_src) = 0; 899 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 900 901 /** 902 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 903 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 904 * that applies on integers. The generated code will write the smallest or largest value 905 * directly into the destination register as specified by the invoke information. 906 * @param info Information about the invoke. 907 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 908 * @return Returns true if successfully generated 909 */ 910 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 911 912 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 913 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 914 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 915 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 916 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 917 RegLocation rl_src2) = 0; 918 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 919 RegLocation rl_src2) = 0; 920 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 921 RegLocation rl_src2) = 0; 922 virtual LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, 923 int offset, ThrowKind kind) = 0; 924 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 925 bool is_div) = 0; 926 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 927 bool is_div) = 0; 928 /* 929 * @brief Generate an integer div or rem operation by a literal. 930 * @param rl_dest Destination Location. 931 * @param rl_src1 Numerator Location. 932 * @param rl_src2 Divisor Location. 933 * @param is_div 'true' if this is a division, 'false' for a remainder. 934 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 935 */ 936 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 937 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 938 /* 939 * @brief Generate an integer div or rem operation by a literal. 940 * @param rl_dest Destination Location. 941 * @param rl_src Numerator Location. 942 * @param lit Divisor. 943 * @param is_div 'true' if this is a division, 'false' for a remainder. 944 */ 945 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 946 bool is_div) = 0; 947 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 948 949 /** 950 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 951 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers. 952 * @param reg_lo The register holding the lower 32-bits. 953 * @param reg_hi The register holding the upper 32-bits. 954 */ 955 virtual void GenDivZeroCheck(RegStorage reg) = 0; 956 957 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 958 virtual void GenExitSequence() = 0; 959 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 960 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 961 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 962 963 /** 964 * @brief Lowers the kMirOpSelect MIR into LIR. 965 * @param bb The basic block in which the MIR is from. 966 * @param mir The MIR whose opcode is kMirOpSelect. 967 */ 968 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 969 970 /** 971 * @brief Used to generate a memory barrier in an architecture specific way. 972 * @details The last generated LIR will be considered for use as barrier. Namely, 973 * if the last LIR can be updated in a way where it will serve the semantics of 974 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 975 * that can keep the semantics. 976 * @param barrier_kind The kind of memory barrier to generate. 977 */ 978 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 979 980 virtual void GenMoveException(RegLocation rl_dest) = 0; 981 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 982 int first_bit, int second_bit) = 0; 983 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 984 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 985 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 986 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 987 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 988 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 989 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 990 RegLocation rl_index, RegLocation rl_src, int scale, 991 bool card_mark) = 0; 992 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 993 RegLocation rl_src1, RegLocation rl_shift) = 0; 994 995 // Required for target - single operation generators. 996 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 997 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 998 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 999 LIR* target) = 0; 1000 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1001 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1002 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1003 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1004 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1005 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1006 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1007 virtual LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1008 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1009 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1010 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1011 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1012 1013 /** 1014 * @brief Used to generate an LIR that does a load from mem to reg. 1015 * @param r_dest The destination physical register. 1016 * @param r_base The base physical register for memory operand. 1017 * @param offset The displacement for memory operand. 1018 * @param move_type Specification on the move desired (size, alignment, register kind). 1019 * @return Returns the generate move LIR. 1020 */ 1021 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1022 MoveType move_type) = 0; 1023 1024 /** 1025 * @brief Used to generate an LIR that does a store from reg to mem. 1026 * @param r_base The base physical register for memory operand. 1027 * @param offset The displacement for memory operand. 1028 * @param r_src The destination physical register. 1029 * @param bytes_to_move The number of bytes to move. 1030 * @param is_aligned Whether the memory location is known to be aligned. 1031 * @return Returns the generate move LIR. 1032 */ 1033 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1034 MoveType move_type) = 0; 1035 1036 /** 1037 * @brief Used for generating a conditional register to register operation. 1038 * @param op The opcode kind. 1039 * @param cc The condition code that when true will perform the opcode. 1040 * @param r_dest The destination physical register. 1041 * @param r_src The source physical register. 1042 * @return Returns the newly created LIR or null in case of creation failure. 1043 */ 1044 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1045 1046 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1047 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1048 RegStorage r_src2) = 0; 1049 virtual LIR* OpTestSuspend(LIR* target) = 0; 1050 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 1051 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1052 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1053 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1054 int offset) = 0; 1055 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1056 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 1057 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1058 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1059 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1060 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1061 1062 // May be optimized by targets. 1063 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1064 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1065 1066 // Temp workaround 1067 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1068 1069 protected: 1070 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1071 1072 CompilationUnit* GetCompilationUnit() { 1073 return cu_; 1074 } 1075 /* 1076 * @brief Returns the index of the lowest set bit in 'x'. 1077 * @param x Value to be examined. 1078 * @returns The bit number of the lowest bit set in the value. 1079 */ 1080 int32_t LowestSetBit(uint64_t x); 1081 /* 1082 * @brief Is this value a power of two? 1083 * @param x Value to be examined. 1084 * @returns 'true' if only 1 bit is set in the value. 1085 */ 1086 bool IsPowerOfTwo(uint64_t x); 1087 /* 1088 * @brief Do these SRs overlap? 1089 * @param rl_op1 One RegLocation 1090 * @param rl_op2 The other RegLocation 1091 * @return 'true' if the VR pairs overlap 1092 * 1093 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1094 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1095 * dex, we'll want to make this case illegal. 1096 */ 1097 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1098 1099 /* 1100 * @brief Force a location (in a register) into a temporary register 1101 * @param loc location of result 1102 * @returns update location 1103 */ 1104 RegLocation ForceTemp(RegLocation loc); 1105 1106 /* 1107 * @brief Force a wide location (in registers) into temporary registers 1108 * @param loc location of result 1109 * @returns update location 1110 */ 1111 RegLocation ForceTempWide(RegLocation loc); 1112 1113 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1114 RegLocation rl_dest, RegLocation rl_src); 1115 1116 void AddSlowPath(LIRSlowPath* slowpath); 1117 1118 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1119 bool type_known_abstract, bool use_declaring_class, 1120 bool can_assume_type_is_in_dex_cache, 1121 uint32_t type_idx, RegLocation rl_dest, 1122 RegLocation rl_src); 1123 /* 1124 * @brief Generate the debug_frame FDE information if possible. 1125 * @returns pointer to vector containg CFE information, or NULL. 1126 */ 1127 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1128 1129 /** 1130 * @brief Used to insert marker that can be used to associate MIR with LIR. 1131 * @details Only inserts marker if verbosity is enabled. 1132 * @param mir The mir that is currently being generated. 1133 */ 1134 void GenPrintLabel(MIR* mir); 1135 1136 /** 1137 * @brief Used to generate return sequence when there is no frame. 1138 * @details Assumes that the return registers have already been populated. 1139 */ 1140 virtual void GenSpecialExitSequence() = 0; 1141 1142 /** 1143 * @brief Used to generate code for special methods that are known to be 1144 * small enough to work in frameless mode. 1145 * @param bb The basic block of the first MIR. 1146 * @param mir The first MIR of the special method. 1147 * @param special Information about the special method. 1148 * @return Returns whether or not this was handled successfully. Returns false 1149 * if caller should punt to normal MIR2LIR conversion. 1150 */ 1151 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1152 1153 private: 1154 void ClobberBody(RegisterInfo* p); 1155 void ResetDefBody(RegisterInfo* p) { 1156 p->def_start = NULL; 1157 p->def_end = NULL; 1158 } 1159 1160 void SetCurrentDexPc(DexOffset dexpc) { 1161 current_dalvik_offset_ = dexpc; 1162 } 1163 1164 /** 1165 * @brief Used to lock register if argument at in_position was passed that way. 1166 * @details Does nothing if the argument is passed via stack. 1167 * @param in_position The argument number whose register to lock. 1168 * @param wide Whether the argument is wide. 1169 */ 1170 void LockArg(int in_position, bool wide = false); 1171 1172 /** 1173 * @brief Used to load VR argument to a physical register. 1174 * @details The load is only done if the argument is not already in physical register. 1175 * LockArg must have been previously called. 1176 * @param in_position The argument number to load. 1177 * @param wide Whether the argument is 64-bit or not. 1178 * @return Returns the register (or register pair) for the loaded argument. 1179 */ 1180 RegStorage LoadArg(int in_position, bool wide = false); 1181 1182 /** 1183 * @brief Used to load a VR argument directly to a specified register location. 1184 * @param in_position The argument number to place in register. 1185 * @param rl_dest The register location where to place argument. 1186 */ 1187 void LoadArgDirect(int in_position, RegLocation rl_dest); 1188 1189 /** 1190 * @brief Used to generate LIR for special getter method. 1191 * @param mir The mir that represents the iget. 1192 * @param special Information about the special getter method. 1193 * @return Returns whether LIR was successfully generated. 1194 */ 1195 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1196 1197 /** 1198 * @brief Used to generate LIR for special setter method. 1199 * @param mir The mir that represents the iput. 1200 * @param special Information about the special setter method. 1201 * @return Returns whether LIR was successfully generated. 1202 */ 1203 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1204 1205 /** 1206 * @brief Used to generate LIR for special return-args method. 1207 * @param mir The mir that represents the return of argument. 1208 * @param special Information about the special return-args method. 1209 * @return Returns whether LIR was successfully generated. 1210 */ 1211 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1212 1213 1214 public: 1215 // TODO: add accessors for these. 1216 LIR* literal_list_; // Constants. 1217 LIR* method_literal_list_; // Method literals requiring patching. 1218 LIR* class_literal_list_; // Class literals requiring patching. 1219 LIR* code_literal_list_; // Code literals requiring patching. 1220 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1221 1222 protected: 1223 CompilationUnit* const cu_; 1224 MIRGraph* const mir_graph_; 1225 GrowableArray<SwitchTable*> switch_tables_; 1226 GrowableArray<FillArrayData*> fill_array_data_; 1227 GrowableArray<LIR*> throw_launchpads_; 1228 GrowableArray<LIR*> suspend_launchpads_; 1229 GrowableArray<RegisterInfo*> tempreg_info_; 1230 GrowableArray<RegisterInfo*> reginfo_map_; 1231 GrowableArray<void*> pointer_storage_; 1232 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1233 CodeOffset data_offset_; // starting offset of literal pool. 1234 size_t total_size_; // header + code size. 1235 LIR* block_label_list_; 1236 PromotionMap* promotion_map_; 1237 /* 1238 * TODO: The code generation utilities don't have a built-in 1239 * mechanism to propagate the original Dalvik opcode address to the 1240 * associated generated instructions. For the trace compiler, this wasn't 1241 * necessary because the interpreter handled all throws and debugging 1242 * requests. For now we'll handle this by placing the Dalvik offset 1243 * in the CompilationUnit struct before codegen for each instruction. 1244 * The low-level LIR creation utilites will pull it from here. Rework this. 1245 */ 1246 DexOffset current_dalvik_offset_; 1247 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1248 RegisterPool* reg_pool_; 1249 /* 1250 * Sanity checking for the register temp tracking. The same ssa 1251 * name should never be associated with one temp register per 1252 * instruction compilation. 1253 */ 1254 int live_sreg_; 1255 CodeBuffer code_buffer_; 1256 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1257 std::vector<uint8_t> encoded_mapping_table_; 1258 std::vector<uint32_t> core_vmap_table_; 1259 std::vector<uint32_t> fp_vmap_table_; 1260 std::vector<uint8_t> native_gc_map_; 1261 int num_core_spills_; 1262 int num_fp_spills_; 1263 int frame_size_; 1264 unsigned int core_spill_mask_; 1265 unsigned int fp_spill_mask_; 1266 LIR* first_lir_insn_; 1267 LIR* last_lir_insn_; 1268 1269 GrowableArray<LIRSlowPath*> slow_paths_; 1270}; // Class Mir2Lir 1271 1272} // namespace art 1273 1274#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1275