mir_to_lir.h revision 3bc8615332b7848dec8c2297a40f7e4d176c0efb
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEFA (1ULL << kRegDefA) 60#define REG_DEFD (1ULL << kRegDefD) 61#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 62#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 63#define REG_DEF_LIST0 (1ULL << kRegDefList0) 64#define REG_DEF_LIST1 (1ULL << kRegDefList1) 65#define REG_DEF_LR (1ULL << kRegDefLR) 66#define REG_DEF_SP (1ULL << kRegDefSP) 67#define REG_USE0 (1ULL << kRegUse0) 68#define REG_USE1 (1ULL << kRegUse1) 69#define REG_USE2 (1ULL << kRegUse2) 70#define REG_USE3 (1ULL << kRegUse3) 71#define REG_USE4 (1ULL << kRegUse4) 72#define REG_USEA (1ULL << kRegUseA) 73#define REG_USEC (1ULL << kRegUseC) 74#define REG_USED (1ULL << kRegUseD) 75#define REG_USEB (1ULL << kRegUseB) 76#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 77#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 78#define REG_USE_LIST0 (1ULL << kRegUseList0) 79#define REG_USE_LIST1 (1ULL << kRegUseList1) 80#define REG_USE_LR (1ULL << kRegUseLR) 81#define REG_USE_PC (1ULL << kRegUsePC) 82#define REG_USE_SP (1ULL << kRegUseSP) 83#define SETS_CCODES (1ULL << kSetsCCodes) 84#define USES_CCODES (1ULL << kUsesCCodes) 85 86// Common combo register usage patterns. 87#define REG_DEF01 (REG_DEF0 | REG_DEF1) 88#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 89#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 90#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 91#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 92#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 93#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 94#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 95#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 96#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 97#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 98#define REG_USE012 (REG_USE01 | REG_USE2) 99#define REG_USE014 (REG_USE01 | REG_USE4) 100#define REG_USE01 (REG_USE0 | REG_USE1) 101#define REG_USE02 (REG_USE0 | REG_USE2) 102#define REG_USE12 (REG_USE1 | REG_USE2) 103#define REG_USE23 (REG_USE2 | REG_USE3) 104#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 105 106struct BasicBlock; 107struct CallInfo; 108struct CompilationUnit; 109struct InlineMethod; 110struct MIR; 111struct LIR; 112struct RegLocation; 113struct RegisterInfo; 114class DexFileMethodInliner; 115class MIRGraph; 116class Mir2Lir; 117 118typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 119 const MethodReference& target_method, 120 uint32_t method_idx, uintptr_t direct_code, 121 uintptr_t direct_method, InvokeType type); 122 123typedef std::vector<uint8_t> CodeBuffer; 124 125struct UseDefMasks { 126 uint64_t use_mask; // Resource mask for use. 127 uint64_t def_mask; // Resource mask for def. 128}; 129 130struct AssemblyInfo { 131 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 132 uint8_t bytes[16]; // Encoded instruction bytes. 133}; 134 135struct LIR { 136 CodeOffset offset; // Offset of this instruction. 137 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 138 int16_t opcode; 139 LIR* next; 140 LIR* prev; 141 LIR* target; 142 struct { 143 unsigned int alias_info:17; // For Dalvik register disambiguation. 144 bool is_nop:1; // LIR is optimized away. 145 unsigned int size:4; // Note: size of encoded instruction is in bytes. 146 bool use_def_invalid:1; // If true, masks should not be used. 147 unsigned int generation:1; // Used to track visitation state during fixup pass. 148 unsigned int fixup:8; // Fixup kind. 149 } flags; 150 union { 151 UseDefMasks m; // Use & Def masks used during optimization. 152 AssemblyInfo a; // Instruction encoding used during assembly phase. 153 } u; 154 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 155}; 156 157// Target-specific initialization. 158Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 159 ArenaAllocator* const arena); 160Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 161 ArenaAllocator* const arena); 162Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 163 ArenaAllocator* const arena); 164 165// Utility macros to traverse the LIR list. 166#define NEXT_LIR(lir) (lir->next) 167#define PREV_LIR(lir) (lir->prev) 168 169// Defines for alias_info (tracks Dalvik register references). 170#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 171#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 172#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 173#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 174 175// Common resource macros. 176#define ENCODE_CCODE (1ULL << kCCode) 177#define ENCODE_FP_STATUS (1ULL << kFPStatus) 178 179// Abstract memory locations. 180#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 181#define ENCODE_LITERAL (1ULL << kLiteral) 182#define ENCODE_HEAP_REF (1ULL << kHeapRef) 183#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 184 185#define ENCODE_ALL (~0ULL) 186#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 187 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 188 189#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 190#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 191 do { \ 192 low_reg = both_regs & 0xff; \ 193 high_reg = (both_regs >> 8) & 0xff; \ 194 } while (false) 195 196// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 197#define STARTING_DOUBLE_SREG 0x10000 198 199// TODO: replace these macros 200#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 201#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 202#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 203#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 204#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 205 206class Mir2Lir : public Backend { 207 public: 208 /* 209 * Auxiliary information describing the location of data embedded in the Dalvik 210 * byte code stream. 211 */ 212 struct EmbeddedData { 213 CodeOffset offset; // Code offset of data block. 214 const uint16_t* table; // Original dex data. 215 DexOffset vaddr; // Dalvik offset of parent opcode. 216 }; 217 218 struct FillArrayData : EmbeddedData { 219 int32_t size; 220 }; 221 222 struct SwitchTable : EmbeddedData { 223 LIR* anchor; // Reference instruction for relative offsets. 224 LIR** targets; // Array of case targets. 225 }; 226 227 /* Static register use counts */ 228 struct RefCounts { 229 int count; 230 int s_reg; 231 }; 232 233 /* 234 * Data structure tracking the mapping between a Dalvik register (pair) and a 235 * native register (pair). The idea is to reuse the previously loaded value 236 * if possible, otherwise to keep the value in a native register as long as 237 * possible. 238 */ 239 struct RegisterInfo { 240 int reg; // Reg number 241 bool in_use; // Has it been allocated? 242 bool is_temp; // Can allocate as temp? 243 bool pair; // Part of a register pair? 244 int partner; // If pair, other reg of pair. 245 bool live; // Is there an associated SSA name? 246 bool dirty; // If live, is it dirty? 247 int s_reg; // Name of live value. 248 LIR *def_start; // Starting inst in last def sequence. 249 LIR *def_end; // Ending inst in last def sequence. 250 }; 251 252 struct RegisterPool { 253 int num_core_regs; 254 RegisterInfo *core_regs; 255 int next_core_reg; 256 int num_fp_regs; 257 RegisterInfo *FPRegs; 258 int next_fp_reg; 259 }; 260 261 struct PromotionMap { 262 RegLocationType core_location:3; 263 uint8_t core_reg; 264 RegLocationType fp_location:3; 265 uint8_t FpReg; 266 bool first_in_pair; 267 }; 268 269 // 270 // Slow paths. This object is used generate a sequence of code that is executed in the 271 // slow path. For example, resolving a string or class is slow as it will only be executed 272 // once (after that it is resolved and doesn't need to be done again). We want slow paths 273 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 274 // branch over them. 275 // 276 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 277 // the Compile() function that will be called near the end of the code generated by the 278 // method. 279 // 280 // The basic flow for a slow path is: 281 // 282 // CMP reg, #value 283 // BEQ fromfast 284 // cont: 285 // ... 286 // fast path code 287 // ... 288 // more code 289 // ... 290 // RETURN 291 /// 292 // fromfast: 293 // ... 294 // slow path code 295 // ... 296 // B cont 297 // 298 // So you see we need two labels and two branches. The first branch (called fromfast) is 299 // the conditional branch to the slow path code. The second label (called cont) is used 300 // as an unconditional branch target for getting back to the code after the slow path 301 // has completed. 302 // 303 304 class LIRSlowPath { 305 public: 306 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 307 LIR* cont = nullptr) : 308 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 309 } 310 virtual ~LIRSlowPath() {} 311 virtual void Compile() = 0; 312 313 static void* operator new(size_t size, ArenaAllocator* arena) { 314 return arena->Alloc(size, kArenaAllocData); 315 } 316 317 protected: 318 LIR* GenerateTargetLabel(); 319 320 Mir2Lir* const m2l_; 321 const DexOffset current_dex_pc_; 322 LIR* const fromfast_; 323 LIR* const cont_; 324 }; 325 326 virtual ~Mir2Lir() {} 327 328 int32_t s4FromSwitchData(const void* switch_data) { 329 return *reinterpret_cast<const int32_t*>(switch_data); 330 } 331 332 RegisterClass oat_reg_class_by_size(OpSize size) { 333 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 334 size == kSignedByte) ? kCoreReg : kAnyReg; 335 } 336 337 size_t CodeBufferSizeInBytes() { 338 return code_buffer_.size() / sizeof(code_buffer_[0]); 339 } 340 341 bool IsPseudoLirOp(int opcode) { 342 return (opcode < 0); 343 } 344 345 /* 346 * LIR operands are 32-bit integers. Sometimes, (especially for managing 347 * instructions which require PC-relative fixups), we need the operands to carry 348 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 349 * hold that index in the operand array. 350 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 351 * may be worth conditionally-compiling a set of identity functions here. 352 */ 353 uint32_t WrapPointer(void* pointer) { 354 uint32_t res = pointer_storage_.Size(); 355 pointer_storage_.Insert(pointer); 356 return res; 357 } 358 359 void* UnwrapPointer(size_t index) { 360 return pointer_storage_.Get(index); 361 } 362 363 // strdup(), but allocates from the arena. 364 char* ArenaStrdup(const char* str) { 365 size_t len = strlen(str) + 1; 366 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 367 if (res != NULL) { 368 strncpy(res, str, len); 369 } 370 return res; 371 } 372 373 // Shared by all targets - implemented in codegen_util.cc 374 void AppendLIR(LIR* lir); 375 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 376 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 377 378 /** 379 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 380 * to place in a frame. 381 * @return Returns the maximum number of compiler temporaries. 382 */ 383 size_t GetMaxPossibleCompilerTemps() const; 384 385 /** 386 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 387 * @return Returns the size in bytes for space needed for compiler temporary spill region. 388 */ 389 size_t GetNumBytesForCompilerTempSpillRegion(); 390 391 DexOffset GetCurrentDexPc() const { 392 return current_dalvik_offset_; 393 } 394 395 int ComputeFrameSize(); 396 virtual void Materialize(); 397 virtual CompiledMethod* GetCompiledMethod(); 398 void MarkSafepointPC(LIR* inst); 399 void SetupResourceMasks(LIR* lir); 400 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 401 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 402 void SetupRegMask(uint64_t* mask, int reg); 403 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 404 void DumpPromotionMap(); 405 void CodegenDump(); 406 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 407 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 408 LIR* NewLIR0(int opcode); 409 LIR* NewLIR1(int opcode, int dest); 410 LIR* NewLIR2(int opcode, int dest, int src1); 411 LIR* NewLIR2NoDest(int opcode, int src, int info); 412 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 413 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 414 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 415 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 416 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 417 LIR* AddWordData(LIR* *constant_list_p, int value); 418 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 419 void ProcessSwitchTables(); 420 void DumpSparseSwitchTable(const uint16_t* table); 421 void DumpPackedSwitchTable(const uint16_t* table); 422 void MarkBoundary(DexOffset offset, const char* inst_str); 423 void NopLIR(LIR* lir); 424 void UnlinkLIR(LIR* lir); 425 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 426 bool IsInexpensiveConstant(RegLocation rl_src); 427 ConditionCode FlipComparisonOrder(ConditionCode before); 428 ConditionCode NegateComparison(ConditionCode before); 429 virtual void InstallLiteralPools(); 430 void InstallSwitchTables(); 431 void InstallFillArrayData(); 432 bool VerifyCatchEntries(); 433 void CreateMappingTables(); 434 void CreateNativeGcMap(); 435 int AssignLiteralOffset(CodeOffset offset); 436 int AssignSwitchTablesOffset(CodeOffset offset); 437 int AssignFillArrayDataOffset(CodeOffset offset); 438 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 439 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 440 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 441 442 // Shared by all targets - implemented in local_optimizations.cc 443 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src); 444 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 445 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 446 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 447 448 // Shared by all targets - implemented in ralloc_util.cc 449 int GetSRegHi(int lowSreg); 450 bool oat_live_out(int s_reg); 451 int oatSSASrc(MIR* mir, int num); 452 void SimpleRegAlloc(); 453 void ResetRegPool(); 454 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 455 void DumpRegPool(RegisterInfo* p, int num_regs); 456 void DumpCoreRegPool(); 457 void DumpFpRegPool(); 458 /* Mark a temp register as dead. Does not affect allocation state. */ 459 void Clobber(int reg) { 460 ClobberBody(GetRegInfo(reg)); 461 } 462 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 463 void ClobberSReg(int s_reg); 464 int SRegToPMap(int s_reg); 465 void RecordCorePromotion(int reg, int s_reg); 466 int AllocPreservedCoreReg(int s_reg); 467 void RecordFpPromotion(int reg, int s_reg); 468 int AllocPreservedSingle(int s_reg); 469 int AllocPreservedDouble(int s_reg); 470 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 471 virtual int AllocTempDouble(); 472 int AllocFreeTemp(); 473 int AllocTemp(); 474 int AllocTempFloat(); 475 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 476 RegisterInfo* AllocLive(int s_reg, int reg_class); 477 void FreeTemp(int reg); 478 RegisterInfo* IsLive(int reg); 479 RegisterInfo* IsTemp(int reg); 480 RegisterInfo* IsPromoted(int reg); 481 bool IsDirty(int reg); 482 void LockTemp(int reg); 483 void ResetDef(int reg); 484 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 485 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 486 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 487 RegLocation WideToNarrow(RegLocation rl); 488 void ResetDefLoc(RegLocation rl); 489 virtual void ResetDefLocWide(RegLocation rl); 490 void ResetDefTracking(); 491 void ClobberAllRegs(); 492 void FlushSpecificReg(RegisterInfo* info); 493 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 494 void FlushAllRegs(); 495 bool RegClassMatches(int reg_class, int reg); 496 void MarkLive(int reg, int s_reg); 497 void MarkTemp(int reg); 498 void UnmarkTemp(int reg); 499 void MarkPair(int low_reg, int high_reg); 500 void MarkClean(RegLocation loc); 501 void MarkDirty(RegLocation loc); 502 void MarkInUse(int reg); 503 void CopyRegInfo(int new_reg, int old_reg); 504 bool CheckCorePoolSanity(); 505 RegLocation UpdateLoc(RegLocation loc); 506 virtual RegLocation UpdateLocWide(RegLocation loc); 507 RegLocation UpdateRawLoc(RegLocation loc); 508 509 /** 510 * @brief Used to load register location into a typed temporary or pair of temporaries. 511 * @see EvalLoc 512 * @param loc The register location to load from. 513 * @param reg_class Type of register needed. 514 * @param update Whether the liveness information should be updated. 515 * @return Returns the properly typed temporary in physical register pairs. 516 */ 517 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 518 519 /** 520 * @brief Used to load register location into a typed temporary. 521 * @param loc The register location to load from. 522 * @param reg_class Type of register needed. 523 * @param update Whether the liveness information should be updated. 524 * @return Returns the properly typed temporary in physical register. 525 */ 526 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 527 528 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 529 void DumpCounts(const RefCounts* arr, int size, const char* msg); 530 void DoPromotion(); 531 int VRegOffset(int v_reg); 532 int SRegOffset(int s_reg); 533 RegLocation GetReturnWide(bool is_double); 534 RegLocation GetReturn(bool is_float); 535 RegisterInfo* GetRegInfo(int reg); 536 537 // Shared by all targets - implemented in gen_common.cc. 538 void AddIntrinsicLaunchpad(CallInfo* info, LIR* branch, LIR* resume = nullptr); 539 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 540 RegLocation rl_src, RegLocation rl_dest, int lit); 541 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 542 void HandleSuspendLaunchPads(); 543 void HandleThrowLaunchPads(); 544 void HandleSlowPaths(); 545 void GenBarrier(); 546 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 547 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val, 548 ThrowKind kind); 549 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags); 550 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 551 ThrowKind kind); 552 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 553 RegLocation rl_src2, LIR* taken, LIR* fall_through); 554 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 555 LIR* taken, LIR* fall_through); 556 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 557 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 558 RegLocation rl_src); 559 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 560 RegLocation rl_src); 561 void GenFilledNewArray(CallInfo* info); 562 void GenSput(MIR* mir, RegLocation rl_src, 563 bool is_long_or_double, bool is_object); 564 void GenSget(MIR* mir, RegLocation rl_dest, 565 bool is_long_or_double, bool is_object); 566 void GenIGet(MIR* mir, int opt_flags, OpSize size, 567 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 568 void GenIPut(MIR* mir, int opt_flags, OpSize size, 569 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 570 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 571 RegLocation rl_src); 572 573 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 574 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 575 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 576 void GenThrow(RegLocation rl_src); 577 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, 578 RegLocation rl_src); 579 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, 580 RegLocation rl_src); 581 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 582 RegLocation rl_src1, RegLocation rl_src2); 583 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 584 RegLocation rl_src1, RegLocation rl_shift); 585 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 586 RegLocation rl_src, int lit); 587 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 588 RegLocation rl_src1, RegLocation rl_src2); 589 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 590 RegLocation rl_src); 591 void GenSuspendTest(int opt_flags); 592 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 593 594 // This will be overridden by x86 implementation. 595 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 596 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 597 RegLocation rl_src1, RegLocation rl_src2); 598 599 // Shared by all targets - implemented in gen_invoke.cc. 600 int CallHelperSetup(ThreadOffset helper_offset); 601 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc); 602 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 603 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 604 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 605 bool safepoint_pc); 606 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 607 bool safepoint_pc); 608 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 609 RegLocation arg1, bool safepoint_pc); 610 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 611 int arg1, bool safepoint_pc); 612 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 613 bool safepoint_pc); 614 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 615 bool safepoint_pc); 616 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 617 bool safepoint_pc); 618 void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 619 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, int arg0, 620 RegLocation arg2, bool safepoint_pc); 621 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 622 RegLocation arg0, RegLocation arg1, 623 bool safepoint_pc); 624 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 625 bool safepoint_pc); 626 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 627 int arg2, bool safepoint_pc); 628 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 629 RegLocation arg2, bool safepoint_pc); 630 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 631 bool safepoint_pc); 632 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 633 int arg0, RegLocation arg1, RegLocation arg2, 634 bool safepoint_pc); 635 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 636 RegLocation arg0, RegLocation arg1, 637 RegLocation arg2, 638 bool safepoint_pc); 639 void GenInvoke(CallInfo* info); 640 void GenInvokeNoInline(CallInfo* info); 641 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 642 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 643 NextCallInsn next_call_insn, 644 const MethodReference& target_method, 645 uint32_t vtable_idx, 646 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 647 bool skip_this); 648 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 649 NextCallInsn next_call_insn, 650 const MethodReference& target_method, 651 uint32_t vtable_idx, 652 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 653 bool skip_this); 654 655 /** 656 * @brief Used to determine the register location of destination. 657 * @details This is needed during generation of inline intrinsics because it finds destination of return, 658 * either the physical register or the target of move-result. 659 * @param info Information about the invoke. 660 * @return Returns the destination location. 661 */ 662 RegLocation InlineTarget(CallInfo* info); 663 664 /** 665 * @brief Used to determine the wide register location of destination. 666 * @see InlineTarget 667 * @param info Information about the invoke. 668 * @return Returns the destination location. 669 */ 670 RegLocation InlineTargetWide(CallInfo* info); 671 672 bool GenInlinedCharAt(CallInfo* info); 673 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 674 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 675 bool GenInlinedAbsInt(CallInfo* info); 676 bool GenInlinedAbsLong(CallInfo* info); 677 bool GenInlinedAbsFloat(CallInfo* info); 678 bool GenInlinedAbsDouble(CallInfo* info); 679 bool GenInlinedFloatCvt(CallInfo* info); 680 bool GenInlinedDoubleCvt(CallInfo* info); 681 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 682 bool GenInlinedStringCompareTo(CallInfo* info); 683 bool GenInlinedCurrentThread(CallInfo* info); 684 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 685 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 686 bool is_volatile, bool is_ordered); 687 int LoadArgRegs(CallInfo* info, int call_state, 688 NextCallInsn next_call_insn, 689 const MethodReference& target_method, 690 uint32_t vtable_idx, 691 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 692 bool skip_this); 693 694 // Shared by all targets - implemented in gen_loadstore.cc. 695 RegLocation LoadCurrMethod(); 696 void LoadCurrMethodDirect(int r_tgt); 697 LIR* LoadConstant(int r_dest, int value); 698 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 699 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 700 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 701 void LoadValueDirect(RegLocation rl_src, int r_dest); 702 void LoadValueDirectFixed(RegLocation rl_src, int r_dest); 703 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi); 704 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi); 705 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 706 707 /** 708 * @brief Used to do the final store in the destination as per bytecode semantics. 709 * @param rl_dest The destination dalvik register location. 710 * @param rl_src The source register location. Can be either physical register or dalvik register. 711 */ 712 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 713 714 /** 715 * @brief Used to do the final store in a wide destination as per bytecode semantics. 716 * @see StoreValue 717 * @param rl_dest The destination dalvik register location. 718 * @param rl_src The source register location. Can be either physical register or dalvik register. 719 */ 720 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 721 722 /** 723 * @brief Used to do the final store to a destination as per bytecode semantics. 724 * @see StoreValue 725 * @param rl_dest The destination dalvik register location. 726 * @param rl_src The source register location. It must be kLocPhysReg 727 * 728 * This is used for x86 two operand computations, where we have computed the correct 729 * register value that now needs to be properly registered. This is used to avoid an 730 * extra register copy that would result if StoreValue was called. 731 */ 732 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 733 734 /** 735 * @brief Used to do the final store in a wide destination as per bytecode semantics. 736 * @see StoreValueWide 737 * @param rl_dest The destination dalvik register location. 738 * @param rl_src The source register location. It must be kLocPhysReg 739 * 740 * This is used for x86 two operand computations, where we have computed the correct 741 * register values that now need to be properly registered. This is used to avoid an 742 * extra pair of register copies that would result if StoreValueWide was called. 743 */ 744 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 745 746 // Shared by all targets - implemented in mir_to_lir.cc. 747 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 748 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 749 bool MethodBlockCodeGen(BasicBlock* bb); 750 bool SpecialMIR2LIR(const InlineMethod& special); 751 void MethodMIR2LIR(); 752 753 /* 754 * @brief Load the address of the dex method into the register. 755 * @param dex_method_index The index of the method to be invoked. 756 * @param type How the method will be invoked. 757 * @param register that will contain the code address. 758 * @note register will be passed to TargetReg to get physical register. 759 */ 760 void LoadCodeAddress(int dex_method_index, InvokeType type, 761 SpecialTargetRegister symbolic_reg); 762 763 /* 764 * @brief Load the Method* of a dex method into the register. 765 * @param dex_method_index The index of the method to be invoked. 766 * @param type How the method will be invoked. 767 * @param register that will contain the code address. 768 * @note register will be passed to TargetReg to get physical register. 769 */ 770 virtual void LoadMethodAddress(int dex_method_index, InvokeType type, 771 SpecialTargetRegister symbolic_reg); 772 773 /* 774 * @brief Load the Class* of a Dex Class type into the register. 775 * @param type How the method will be invoked. 776 * @param register that will contain the code address. 777 * @note register will be passed to TargetReg to get physical register. 778 */ 779 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 780 781 // Routines that work for the generic case, but may be overriden by target. 782 /* 783 * @brief Compare memory to immediate, and branch if condition true. 784 * @param cond The condition code that when true will branch to the target. 785 * @param temp_reg A temporary register that can be used if compare to memory is not 786 * supported by the architecture. 787 * @param base_reg The register holding the base address. 788 * @param offset The offset from the base. 789 * @param check_value The immediate to compare to. 790 * @returns The branch instruction that was generated. 791 */ 792 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg, 793 int offset, int check_value, LIR* target); 794 795 // Required for target - codegen helpers. 796 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 797 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 798 virtual int LoadHelper(ThreadOffset offset) = 0; 799 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 800 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 801 int s_reg) = 0; 802 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 803 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 804 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0; 805 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0; 806 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0; 807 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 808 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 809 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 810 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 811 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 812 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0; 813 814 // Required for target - register utilities. 815 virtual bool IsFpReg(int reg) = 0; 816 virtual bool SameRegType(int reg1, int reg2) = 0; 817 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0; 818 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 819 virtual int S2d(int low_reg, int high_reg) = 0; 820 virtual int TargetReg(SpecialTargetRegister reg) = 0; 821 virtual int GetArgMappingToPhysicalReg(int arg_num) = 0; 822 virtual RegLocation GetReturnAlt() = 0; 823 virtual RegLocation GetReturnWideAlt() = 0; 824 virtual RegLocation LocCReturn() = 0; 825 virtual RegLocation LocCReturnDouble() = 0; 826 virtual RegLocation LocCReturnFloat() = 0; 827 virtual RegLocation LocCReturnWide() = 0; 828 virtual uint32_t FpRegMask() = 0; 829 virtual uint64_t GetRegMaskCommon(int reg) = 0; 830 virtual void AdjustSpillMask() = 0; 831 virtual void ClobberCallerSave() = 0; 832 virtual void FlushReg(int reg) = 0; 833 virtual void FlushRegWide(int reg1, int reg2) = 0; 834 virtual void FreeCallTemps() = 0; 835 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 836 virtual void LockCallTemps() = 0; 837 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 838 virtual void CompilerInitializeRegAlloc() = 0; 839 840 // Required for target - miscellaneous. 841 virtual void AssembleLIR() = 0; 842 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 843 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 844 virtual const char* GetTargetInstFmt(int opcode) = 0; 845 virtual const char* GetTargetInstName(int opcode) = 0; 846 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 847 virtual uint64_t GetPCUseDefEncoding() = 0; 848 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 849 virtual int GetInsnSize(LIR* lir) = 0; 850 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 851 852 // Required for target - Dalvik-level generators. 853 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 854 RegLocation rl_src1, RegLocation rl_src2) = 0; 855 virtual void GenMulLong(Instruction::Code, 856 RegLocation rl_dest, RegLocation rl_src1, 857 RegLocation rl_src2) = 0; 858 virtual void GenAddLong(Instruction::Code, 859 RegLocation rl_dest, RegLocation rl_src1, 860 RegLocation rl_src2) = 0; 861 virtual void GenAndLong(Instruction::Code, 862 RegLocation rl_dest, RegLocation rl_src1, 863 RegLocation rl_src2) = 0; 864 virtual void GenArithOpDouble(Instruction::Code opcode, 865 RegLocation rl_dest, RegLocation rl_src1, 866 RegLocation rl_src2) = 0; 867 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 868 RegLocation rl_src1, RegLocation rl_src2) = 0; 869 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 870 RegLocation rl_src1, RegLocation rl_src2) = 0; 871 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 872 RegLocation rl_src) = 0; 873 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 874 875 /** 876 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 877 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 878 * that applies on integers. The generated code will write the smallest or largest value 879 * directly into the destination register as specified by the invoke information. 880 * @param info Information about the invoke. 881 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 882 * @return Returns true if successfully generated 883 */ 884 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 885 886 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 887 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 888 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 889 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 890 virtual void GenOrLong(Instruction::Code, 891 RegLocation rl_dest, RegLocation rl_src1, 892 RegLocation rl_src2) = 0; 893 virtual void GenSubLong(Instruction::Code, 894 RegLocation rl_dest, RegLocation rl_src1, 895 RegLocation rl_src2) = 0; 896 virtual void GenXorLong(Instruction::Code, 897 RegLocation rl_dest, RegLocation rl_src1, 898 RegLocation rl_src2) = 0; 899 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, 900 int offset, ThrowKind kind) = 0; 901 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, 902 bool is_div) = 0; 903 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, 904 bool is_div) = 0; 905 /* 906 * @brief Generate an integer div or rem operation by a literal. 907 * @param rl_dest Destination Location. 908 * @param rl_src1 Numerator Location. 909 * @param rl_src2 Divisor Location. 910 * @param is_div 'true' if this is a division, 'false' for a remainder. 911 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 912 */ 913 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 914 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 915 /* 916 * @brief Generate an integer div or rem operation by a literal. 917 * @param rl_dest Destination Location. 918 * @param rl_src Numerator Location. 919 * @param lit Divisor. 920 * @param is_div 'true' if this is a division, 'false' for a remainder. 921 */ 922 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, 923 int lit, bool is_div) = 0; 924 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 925 RegLocation rl_src2) = 0; 926 927 /** 928 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 929 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers. 930 * @param reg_lo The register holding the lower 32-bits. 931 * @param reg_hi The register holding the upper 32-bits. 932 */ 933 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0; 934 935 virtual void GenEntrySequence(RegLocation* ArgLocs, 936 RegLocation rl_method) = 0; 937 virtual void GenExitSequence() = 0; 938 virtual void GenFillArrayData(DexOffset table_offset, 939 RegLocation rl_src) = 0; 940 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, 941 bool is_double) = 0; 942 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 943 944 /** 945 * @brief Lowers the kMirOpSelect MIR into LIR. 946 * @param bb The basic block in which the MIR is from. 947 * @param mir The MIR whose opcode is kMirOpSelect. 948 */ 949 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 950 951 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 952 virtual void GenMoveException(RegLocation rl_dest) = 0; 953 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 954 RegLocation rl_result, int lit, int first_bit, 955 int second_bit) = 0; 956 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 957 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 958 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, 959 RegLocation rl_src) = 0; 960 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, 961 RegLocation rl_src) = 0; 962 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 963 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 964 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 965 RegLocation rl_index, RegLocation rl_src, int scale, 966 bool card_mark) = 0; 967 virtual void GenShiftImmOpLong(Instruction::Code opcode, 968 RegLocation rl_dest, RegLocation rl_src1, 969 RegLocation rl_shift) = 0; 970 971 // Required for target - single operation generators. 972 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 973 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target) = 0; 974 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target) = 0; 975 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 976 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) = 0; 977 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 978 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 979 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0; 980 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0; 981 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0; 982 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 983 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0; 984 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0; 985 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0; 986 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0; 987 988 /** 989 * @brief Used to generate an LIR that does a load from mem to reg. 990 * @param r_dest The destination physical register. 991 * @param r_base The base physical register for memory operand. 992 * @param offset The displacement for memory operand. 993 * @param move_type Specification on the move desired (size, alignment, register kind). 994 * @return Returns the generate move LIR. 995 */ 996 virtual LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) = 0; 997 998 /** 999 * @brief Used to generate an LIR that does a store from reg to mem. 1000 * @param r_base The base physical register for memory operand. 1001 * @param offset The displacement for memory operand. 1002 * @param r_src The destination physical register. 1003 * @param bytes_to_move The number of bytes to move. 1004 * @param is_aligned Whether the memory location is known to be aligned. 1005 * @return Returns the generate move LIR. 1006 */ 1007 virtual LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) = 0; 1008 1009 /** 1010 * @brief Used for generating a conditional register to register operation. 1011 * @param op The opcode kind. 1012 * @param cc The condition code that when true will perform the opcode. 1013 * @param r_dest The destination physical register. 1014 * @param r_src The source physical register. 1015 * @return Returns the newly created LIR or null in case of creation failure. 1016 */ 1017 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) = 0; 1018 1019 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0; 1020 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) = 0; 1021 virtual LIR* OpTestSuspend(LIR* target) = 0; 1022 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 1023 virtual LIR* OpVldm(int rBase, int count) = 0; 1024 virtual LIR* OpVstm(int rBase, int count) = 0; 1025 virtual void OpLea(int rBase, int reg1, int reg2, int scale, int offset) = 0; 1026 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi) = 0; 1027 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 1028 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1029 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1030 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1031 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1032 1033 // May be optimized by targets. 1034 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1035 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1036 1037 // Temp workaround 1038 void Workaround7250540(RegLocation rl_dest, int value); 1039 1040 protected: 1041 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1042 1043 CompilationUnit* GetCompilationUnit() { 1044 return cu_; 1045 } 1046 /* 1047 * @brief Returns the index of the lowest set bit in 'x'. 1048 * @param x Value to be examined. 1049 * @returns The bit number of the lowest bit set in the value. 1050 */ 1051 int32_t LowestSetBit(uint64_t x); 1052 /* 1053 * @brief Is this value a power of two? 1054 * @param x Value to be examined. 1055 * @returns 'true' if only 1 bit is set in the value. 1056 */ 1057 bool IsPowerOfTwo(uint64_t x); 1058 /* 1059 * @brief Do these SRs overlap? 1060 * @param rl_op1 One RegLocation 1061 * @param rl_op2 The other RegLocation 1062 * @return 'true' if the VR pairs overlap 1063 * 1064 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1065 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1066 * dex, we'll want to make this case illegal. 1067 */ 1068 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1069 1070 /* 1071 * @brief Force a location (in a register) into a temporary register 1072 * @param loc location of result 1073 * @returns update location 1074 */ 1075 RegLocation ForceTemp(RegLocation loc); 1076 1077 /* 1078 * @brief Force a wide location (in registers) into temporary registers 1079 * @param loc location of result 1080 * @returns update location 1081 */ 1082 RegLocation ForceTempWide(RegLocation loc); 1083 1084 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1085 RegLocation rl_dest, RegLocation rl_src); 1086 1087 void AddSlowPath(LIRSlowPath* slowpath); 1088 1089 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1090 bool type_known_abstract, bool use_declaring_class, 1091 bool can_assume_type_is_in_dex_cache, 1092 uint32_t type_idx, RegLocation rl_dest, 1093 RegLocation rl_src); 1094 /* 1095 * @brief Generate the debug_frame FDE information if possible. 1096 * @returns pointer to vector containg CFE information, or NULL. 1097 */ 1098 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1099 1100 /** 1101 * @brief Used to insert marker that can be used to associate MIR with LIR. 1102 * @details Only inserts marker if verbosity is enabled. 1103 * @param mir The mir that is currently being generated. 1104 */ 1105 void GenPrintLabel(MIR* mir); 1106 1107 /** 1108 * @brief Used to generate return sequence when there is no frame. 1109 * @details Assumes that the return registers have already been populated. 1110 */ 1111 virtual void GenSpecialExitSequence() = 0; 1112 1113 /** 1114 * @brief Used to generate code for special methods that are known to be 1115 * small enough to work in frameless mode. 1116 * @param bb The basic block of the first MIR. 1117 * @param mir The first MIR of the special method. 1118 * @param special Information about the special method. 1119 * @return Returns whether or not this was handled successfully. Returns false 1120 * if caller should punt to normal MIR2LIR conversion. 1121 */ 1122 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1123 1124 private: 1125 void ClobberBody(RegisterInfo* p); 1126 void ResetDefBody(RegisterInfo* p) { 1127 p->def_start = NULL; 1128 p->def_end = NULL; 1129 } 1130 1131 void SetCurrentDexPc(DexOffset dexpc) { 1132 current_dalvik_offset_ = dexpc; 1133 } 1134 1135 /** 1136 * @brief Used to lock register if argument at in_position was passed that way. 1137 * @details Does nothing if the argument is passed via stack. 1138 * @param in_position The argument number whose register to lock. 1139 * @param wide Whether the argument is wide. 1140 */ 1141 void LockArg(int in_position, bool wide = false); 1142 1143 /** 1144 * @brief Used to load VR argument to a physical register. 1145 * @details The load is only done if the argument is not already in physical register. 1146 * LockArg must have been previously called. 1147 * @param in_position The argument number to load. 1148 * @param wide Whether the argument is 64-bit or not. 1149 * @return Returns the register (or register pair) for the loaded argument. 1150 */ 1151 int LoadArg(int in_position, bool wide = false); 1152 1153 /** 1154 * @brief Used to load a VR argument directly to a specified register location. 1155 * @param in_position The argument number to place in register. 1156 * @param rl_dest The register location where to place argument. 1157 */ 1158 void LoadArgDirect(int in_position, RegLocation rl_dest); 1159 1160 /** 1161 * @brief Used to generate LIR for special getter method. 1162 * @param mir The mir that represents the iget. 1163 * @param special Information about the special getter method. 1164 * @return Returns whether LIR was successfully generated. 1165 */ 1166 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1167 1168 /** 1169 * @brief Used to generate LIR for special setter method. 1170 * @param mir The mir that represents the iput. 1171 * @param special Information about the special setter method. 1172 * @return Returns whether LIR was successfully generated. 1173 */ 1174 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1175 1176 /** 1177 * @brief Used to generate LIR for special return-args method. 1178 * @param mir The mir that represents the return of argument. 1179 * @param special Information about the special return-args method. 1180 * @return Returns whether LIR was successfully generated. 1181 */ 1182 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1183 1184 1185 public: 1186 // TODO: add accessors for these. 1187 LIR* literal_list_; // Constants. 1188 LIR* method_literal_list_; // Method literals requiring patching. 1189 LIR* class_literal_list_; // Class literals requiring patching. 1190 LIR* code_literal_list_; // Code literals requiring patching. 1191 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1192 1193 protected: 1194 CompilationUnit* const cu_; 1195 MIRGraph* const mir_graph_; 1196 GrowableArray<SwitchTable*> switch_tables_; 1197 GrowableArray<FillArrayData*> fill_array_data_; 1198 GrowableArray<LIR*> throw_launchpads_; 1199 GrowableArray<LIR*> suspend_launchpads_; 1200 GrowableArray<RegisterInfo*> tempreg_info_; 1201 GrowableArray<RegisterInfo*> reginfo_map_; 1202 GrowableArray<void*> pointer_storage_; 1203 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1204 CodeOffset data_offset_; // starting offset of literal pool. 1205 size_t total_size_; // header + code size. 1206 LIR* block_label_list_; 1207 PromotionMap* promotion_map_; 1208 /* 1209 * TODO: The code generation utilities don't have a built-in 1210 * mechanism to propagate the original Dalvik opcode address to the 1211 * associated generated instructions. For the trace compiler, this wasn't 1212 * necessary because the interpreter handled all throws and debugging 1213 * requests. For now we'll handle this by placing the Dalvik offset 1214 * in the CompilationUnit struct before codegen for each instruction. 1215 * The low-level LIR creation utilites will pull it from here. Rework this. 1216 */ 1217 DexOffset current_dalvik_offset_; 1218 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1219 RegisterPool* reg_pool_; 1220 /* 1221 * Sanity checking for the register temp tracking. The same ssa 1222 * name should never be associated with one temp register per 1223 * instruction compilation. 1224 */ 1225 int live_sreg_; 1226 CodeBuffer code_buffer_; 1227 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1228 std::vector<uint8_t> encoded_mapping_table_; 1229 std::vector<uint32_t> core_vmap_table_; 1230 std::vector<uint32_t> fp_vmap_table_; 1231 std::vector<uint8_t> native_gc_map_; 1232 int num_core_spills_; 1233 int num_fp_spills_; 1234 int frame_size_; 1235 unsigned int core_spill_mask_; 1236 unsigned int fp_spill_mask_; 1237 LIR* first_lir_insn_; 1238 LIR* last_lir_insn_; 1239 1240 GrowableArray<LIRSlowPath*> slow_paths_; 1241}; // Class Mir2Lir 1242 1243} // namespace art 1244 1245#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1246