mir_to_lir.h revision 3bf7c60a86d49bf8c05c5d2ac5ca8e9f80bd9824
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 95#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 96#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 97#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 98#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 99#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 100#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 101#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 102#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 103#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 104#define REG_USE012 (REG_USE01 | REG_USE2) 105#define REG_USE014 (REG_USE01 | REG_USE4) 106#define REG_USE01 (REG_USE0 | REG_USE1) 107#define REG_USE02 (REG_USE0 | REG_USE2) 108#define REG_USE12 (REG_USE1 | REG_USE2) 109#define REG_USE23 (REG_USE2 | REG_USE3) 110#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 111 112// TODO: #includes need a cleanup 113#ifndef INVALID_SREG 114#define INVALID_SREG (-1) 115#endif 116 117struct BasicBlock; 118struct CallInfo; 119struct CompilationUnit; 120struct InlineMethod; 121struct MIR; 122struct LIR; 123struct RegLocation; 124struct RegisterInfo; 125class DexFileMethodInliner; 126class MIRGraph; 127class Mir2Lir; 128 129typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 130 const MethodReference& target_method, 131 uint32_t method_idx, uintptr_t direct_code, 132 uintptr_t direct_method, InvokeType type); 133 134typedef std::vector<uint8_t> CodeBuffer; 135 136struct UseDefMasks { 137 uint64_t use_mask; // Resource mask for use. 138 uint64_t def_mask; // Resource mask for def. 139}; 140 141struct AssemblyInfo { 142 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 143}; 144 145struct LIR { 146 CodeOffset offset; // Offset of this instruction. 147 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 148 int16_t opcode; 149 LIR* next; 150 LIR* prev; 151 LIR* target; 152 struct { 153 unsigned int alias_info:17; // For Dalvik register disambiguation. 154 bool is_nop:1; // LIR is optimized away. 155 unsigned int size:4; // Note: size of encoded instruction is in bytes. 156 bool use_def_invalid:1; // If true, masks should not be used. 157 unsigned int generation:1; // Used to track visitation state during fixup pass. 158 unsigned int fixup:8; // Fixup kind. 159 } flags; 160 union { 161 UseDefMasks m; // Use & Def masks used during optimization. 162 AssemblyInfo a; // Instruction info used during assembly phase. 163 } u; 164 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 165}; 166 167// Target-specific initialization. 168Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 169 ArenaAllocator* const arena); 170Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 171 ArenaAllocator* const arena); 172Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 173 ArenaAllocator* const arena); 174 175// Utility macros to traverse the LIR list. 176#define NEXT_LIR(lir) (lir->next) 177#define PREV_LIR(lir) (lir->prev) 178 179// Defines for alias_info (tracks Dalvik register references). 180#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 181#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 182#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 183#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 184 185// Common resource macros. 186#define ENCODE_CCODE (1ULL << kCCode) 187#define ENCODE_FP_STATUS (1ULL << kFPStatus) 188 189// Abstract memory locations. 190#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 191#define ENCODE_LITERAL (1ULL << kLiteral) 192#define ENCODE_HEAP_REF (1ULL << kHeapRef) 193#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 194 195#define ENCODE_ALL (~0ULL) 196#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 197 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 198 199#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 200#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 201 do { \ 202 low_reg = both_regs & 0xff; \ 203 high_reg = (both_regs >> 8) & 0xff; \ 204 } while (false) 205 206// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 207#define STARTING_DOUBLE_SREG 0x10000 208 209// TODO: replace these macros 210#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 211#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 212#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 213#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 214#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 215 216class Mir2Lir : public Backend { 217 public: 218 /* 219 * Auxiliary information describing the location of data embedded in the Dalvik 220 * byte code stream. 221 */ 222 struct EmbeddedData { 223 CodeOffset offset; // Code offset of data block. 224 const uint16_t* table; // Original dex data. 225 DexOffset vaddr; // Dalvik offset of parent opcode. 226 }; 227 228 struct FillArrayData : EmbeddedData { 229 int32_t size; 230 }; 231 232 struct SwitchTable : EmbeddedData { 233 LIR* anchor; // Reference instruction for relative offsets. 234 LIR** targets; // Array of case targets. 235 }; 236 237 /* Static register use counts */ 238 struct RefCounts { 239 int count; 240 int s_reg; 241 }; 242 243 /* 244 * Data structure tracking the mapping detween a Dalvik value (32 or 64 bits) 245 * and native register storage. The primary purpose is to reuse previuosly 246 * loaded values, if possible, and otherwise to keep the value in register 247 * storage as long as possible. 248 * 249 * NOTE 1: wide_value refers to the width of the Dalvik value contained in 250 * this register (or pair). For example, a 64-bit register containing a 32-bit 251 * Dalvik value would have wide_value==false even though the storage container itself 252 * is wide. Similarly, a 32-bit register containing half of a 64-bit Dalvik value 253 * would have wide_value==true (and additionally would have its partner field set to the 254 * other half whose wide_value field would also be true. 255 * 256 * NOTE 2: In the case of a register pair, you can determine which of the partners 257 * is the low half by looking at the s_reg names. The high s_reg will equal low_sreg + 1. 258 * 259 * NOTE 3: In the case of a 64-bit register holding a Dalvik wide value, wide_value 260 * will be true and partner==self. s_reg refers to the low-order word of the Dalvik 261 * value, and the s_reg of the high word is implied (s_reg + 1). 262 * 263 * NOTE 4: The reg and is_temp fields should always be correct. If is_temp is false no 264 * other fields have meaning. [perhaps not true, wide should work for promoted regs?] 265 * If is_temp==true and live==false, no other fields have 266 * meaning. If is_temp==true and live==true, wide_value, partner, dirty, s_reg, def_start 267 * and def_end describe the relationship between the temp register/register pair and 268 * the Dalvik value[s] described by s_reg/s_reg+1. 269 * 270 * The fields used_storage, master_storage and storage_mask are used to track allocation 271 * in light of potential aliasing. For example, consider Arm's d2, which overlaps s4 & s5. 272 * d2's storage mask would be 0x00000003, the two low-order bits denoting 64 bits of 273 * storage use. For s4, it would be 0x0000001; for s5 0x00000002. These values should not 274 * change once initialized. The "used_storage" field tracks current allocation status. 275 * Although each record contains this field, only the field from the largest member of 276 * an aliased group is used. In our case, it would be d2's. The master_storage pointer 277 * of d2, s4 and s5 would all point to d2's used_storage field. Each bit in a used_storage 278 * represents 32 bits of storage. d2's used_storage would be initialized to 0xfffffffc. 279 * Then, if we wanted to determine whether s4 could be allocated, we would "and" 280 * s4's storage_mask with s4's *master_storage. If the result is zero, s4 is free and 281 * to allocate: *master_storage |= storage_mask. To free, *master_storage &= ~storage_mask. 282 * 283 * For an X86 vector register example, storage_mask would be: 284 * 0x00000001 for 32-bit view of xmm1 285 * 0x00000003 for 64-bit view of xmm1 286 * 0x0000000f for 128-bit view of xmm1 287 * 0x000000ff for 256-bit view of ymm1 // future expansion, if needed 288 * 0x0000ffff for 512-bit view of ymm1 // future expansion, if needed 289 * 0xffffffff for 1024-bit view of ymm1 // future expansion, if needed 290 * 291 * NOTE: the x86 usage is still somewhat in flux. There are competing notions of how 292 * to treat xmm registers: 293 * 1. Treat them all as 128-bits wide, but denote how much data used via bytes field. 294 * o This more closely matches reality, but means you'd need to be able to get 295 * to the associated RegisterInfo struct to figure out how it's being used. 296 * o This is how 64-bit core registers will be used - always 64 bits, but the 297 * "bytes" field will be 4 for 32-bit usage and 8 for 64-bit usage. 298 * 2. View the xmm registers based on contents. 299 * o A single in a xmm2 register would be k32BitVector, while a double in xmm2 would 300 * be a k64BitVector. 301 * o Note that the two uses above would be considered distinct registers (but with 302 * the aliasing mechanism, we could detect interference). 303 * o This is how aliased double and single float registers will be handled on 304 * Arm and MIPS. 305 * Working plan is, for all targets, to follow mechanism 1 for 64-bit core registers, and 306 * mechanism 2 for aliased float registers and x86 vector registers. 307 */ 308 class RegisterInfo { 309 public: 310 RegisterInfo(RegStorage r, uint64_t mask = ENCODE_ALL); 311 ~RegisterInfo() {} 312 static void* operator new(size_t size, ArenaAllocator* arena) { 313 return arena->Alloc(size, kArenaAllocRegAlloc); 314 } 315 316 bool InUse() { return (storage_mask_ & master_->used_storage_) != 0; } 317 void MarkInUse() { master_->used_storage_ |= storage_mask_; } 318 void MarkFree() { master_->used_storage_ &= ~storage_mask_; } 319 RegStorage GetReg() { return reg_; } 320 void SetReg(RegStorage reg) { reg_ = reg; } 321 bool IsTemp() { return is_temp_; } 322 void SetIsTemp(bool val) { is_temp_ = val; } 323 bool IsWide() { return wide_value_; } 324 void SetIsWide(bool val) { wide_value_ = val; } 325 bool IsLive() { return live_; } 326 void SetIsLive(bool val) { live_ = val; } 327 bool IsDirty() { return dirty_; } 328 void SetIsDirty(bool val) { dirty_ = val; } 329 RegStorage Partner() { return partner_; } 330 void SetPartner(RegStorage partner) { partner_ = partner; } 331 int SReg() { return s_reg_; } 332 void SetSReg(int s_reg) { s_reg_ = s_reg; } 333 uint64_t DefUseMask() { return def_use_mask_; } 334 void SetDefUseMask(uint64_t def_use_mask) { def_use_mask_ = def_use_mask; } 335 RegisterInfo* Master() { return master_; } 336 void SetMaster(RegisterInfo* master) { master_ = master; } 337 uint32_t StorageMask() { return storage_mask_; } 338 void SetStorageMask(uint32_t storage_mask) { storage_mask_ = storage_mask; } 339 LIR* DefStart() { return def_start_; } 340 void SetDefStart(LIR* def_start) { def_start_ = def_start; } 341 LIR* DefEnd() { return def_end_; } 342 void SetDefEnd(LIR* def_end) { def_end_ = def_end; } 343 void ResetDefBody() { def_start_ = def_end_ = nullptr; } 344 345 346 private: 347 RegStorage reg_; 348 bool is_temp_; // Can allocate as temp? 349 bool wide_value_; // Holds a Dalvik wide value (either itself, or part of a pair). 350 bool live_; // Is there an associated SSA name? 351 bool dirty_; // If live, is it dirty? 352 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register. 353 int s_reg_; // Name of live value. 354 uint64_t def_use_mask_; // Resources for this element. 355 uint32_t used_storage_; // 1 bit per 4 bytes of storage. Unused by aliases. 356 RegisterInfo* master_; // Pointer to controlling storage mask. 357 uint32_t storage_mask_; // Track allocation of sub-units. 358 LIR *def_start_; // Starting inst in last def sequence. 359 LIR *def_end_; // Ending inst in last def sequence. 360 }; 361 362 class RegisterPool { 363 public: 364 RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, const std::vector<RegStorage>& core_regs, 365 const std::vector<RegStorage>& sp_regs, const std::vector<RegStorage>& dp_regs, 366 const std::vector<RegStorage>& reserved_regs, 367 const std::vector<RegStorage>& core_temps, 368 const std::vector<RegStorage>& sp_temps, 369 const std::vector<RegStorage>& dp_temps); 370 ~RegisterPool() {} 371 static void* operator new(size_t size, ArenaAllocator* arena) { 372 return arena->Alloc(size, kArenaAllocRegAlloc); 373 } 374 void ResetNextTemp() { 375 next_core_reg_ = 0; 376 next_sp_reg_ = 0; 377 next_dp_reg_ = 0; 378 } 379 GrowableArray<RegisterInfo*> core_regs_; 380 int next_core_reg_; 381 GrowableArray<RegisterInfo*> sp_regs_; // Single precision float. 382 int next_sp_reg_; 383 GrowableArray<RegisterInfo*> dp_regs_; // Double precision float. 384 int next_dp_reg_; 385 386 private: 387 Mir2Lir* const m2l_; 388 }; 389 390 struct PromotionMap { 391 RegLocationType core_location:3; 392 uint8_t core_reg; 393 RegLocationType fp_location:3; 394 uint8_t FpReg; 395 bool first_in_pair; 396 }; 397 398 // 399 // Slow paths. This object is used generate a sequence of code that is executed in the 400 // slow path. For example, resolving a string or class is slow as it will only be executed 401 // once (after that it is resolved and doesn't need to be done again). We want slow paths 402 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 403 // branch over them. 404 // 405 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 406 // the Compile() function that will be called near the end of the code generated by the 407 // method. 408 // 409 // The basic flow for a slow path is: 410 // 411 // CMP reg, #value 412 // BEQ fromfast 413 // cont: 414 // ... 415 // fast path code 416 // ... 417 // more code 418 // ... 419 // RETURN 420 /// 421 // fromfast: 422 // ... 423 // slow path code 424 // ... 425 // B cont 426 // 427 // So you see we need two labels and two branches. The first branch (called fromfast) is 428 // the conditional branch to the slow path code. The second label (called cont) is used 429 // as an unconditional branch target for getting back to the code after the slow path 430 // has completed. 431 // 432 433 class LIRSlowPath { 434 public: 435 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 436 LIR* cont = nullptr) : 437 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 438 } 439 virtual ~LIRSlowPath() {} 440 virtual void Compile() = 0; 441 442 static void* operator new(size_t size, ArenaAllocator* arena) { 443 return arena->Alloc(size, kArenaAllocData); 444 } 445 446 protected: 447 LIR* GenerateTargetLabel(int opcode = kPseudoTargetLabel); 448 449 Mir2Lir* const m2l_; 450 const DexOffset current_dex_pc_; 451 LIR* const fromfast_; 452 LIR* const cont_; 453 }; 454 455 virtual ~Mir2Lir() {} 456 457 int32_t s4FromSwitchData(const void* switch_data) { 458 return *reinterpret_cast<const int32_t*>(switch_data); 459 } 460 461 /* 462 * TODO: this is a trace JIT vestige, and its use should be reconsidered. At the time 463 * it was introduced, it was intended to be a quick best guess of type without having to 464 * take the time to do type analysis. Currently, though, we have a much better idea of 465 * the types of Dalvik virtual registers. Instead of using this for a best guess, why not 466 * just use our knowledge of type to select the most appropriate register class? 467 */ 468 RegisterClass RegClassBySize(OpSize size) { 469 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 470 size == kSignedByte) ? kCoreReg : kAnyReg; 471 } 472 473 size_t CodeBufferSizeInBytes() { 474 return code_buffer_.size() / sizeof(code_buffer_[0]); 475 } 476 477 static bool IsPseudoLirOp(int opcode) { 478 return (opcode < 0); 479 } 480 481 /* 482 * LIR operands are 32-bit integers. Sometimes, (especially for managing 483 * instructions which require PC-relative fixups), we need the operands to carry 484 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 485 * hold that index in the operand array. 486 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 487 * may be worth conditionally-compiling a set of identity functions here. 488 */ 489 uint32_t WrapPointer(void* pointer) { 490 uint32_t res = pointer_storage_.Size(); 491 pointer_storage_.Insert(pointer); 492 return res; 493 } 494 495 void* UnwrapPointer(size_t index) { 496 return pointer_storage_.Get(index); 497 } 498 499 // strdup(), but allocates from the arena. 500 char* ArenaStrdup(const char* str) { 501 size_t len = strlen(str) + 1; 502 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 503 if (res != NULL) { 504 strncpy(res, str, len); 505 } 506 return res; 507 } 508 509 // Shared by all targets - implemented in codegen_util.cc 510 void AppendLIR(LIR* lir); 511 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 512 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 513 514 /** 515 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 516 * to place in a frame. 517 * @return Returns the maximum number of compiler temporaries. 518 */ 519 size_t GetMaxPossibleCompilerTemps() const; 520 521 /** 522 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 523 * @return Returns the size in bytes for space needed for compiler temporary spill region. 524 */ 525 size_t GetNumBytesForCompilerTempSpillRegion(); 526 527 DexOffset GetCurrentDexPc() const { 528 return current_dalvik_offset_; 529 } 530 531 int ComputeFrameSize(); 532 virtual void Materialize(); 533 virtual CompiledMethod* GetCompiledMethod(); 534 void MarkSafepointPC(LIR* inst); 535 void SetupResourceMasks(LIR* lir); 536 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 537 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 538 void SetupRegMask(uint64_t* mask, int reg); 539 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 540 void DumpPromotionMap(); 541 void CodegenDump(); 542 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 543 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 544 LIR* NewLIR0(int opcode); 545 LIR* NewLIR1(int opcode, int dest); 546 LIR* NewLIR2(int opcode, int dest, int src1); 547 LIR* NewLIR2NoDest(int opcode, int src, int info); 548 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 549 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 550 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 551 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 552 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 553 LIR* AddWordData(LIR* *constant_list_p, int value); 554 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 555 void ProcessSwitchTables(); 556 void DumpSparseSwitchTable(const uint16_t* table); 557 void DumpPackedSwitchTable(const uint16_t* table); 558 void MarkBoundary(DexOffset offset, const char* inst_str); 559 void NopLIR(LIR* lir); 560 void UnlinkLIR(LIR* lir); 561 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 562 bool IsInexpensiveConstant(RegLocation rl_src); 563 ConditionCode FlipComparisonOrder(ConditionCode before); 564 ConditionCode NegateComparison(ConditionCode before); 565 virtual void InstallLiteralPools(); 566 void InstallSwitchTables(); 567 void InstallFillArrayData(); 568 bool VerifyCatchEntries(); 569 void CreateMappingTables(); 570 void CreateNativeGcMap(); 571 int AssignLiteralOffset(CodeOffset offset); 572 int AssignSwitchTablesOffset(CodeOffset offset); 573 int AssignFillArrayDataOffset(CodeOffset offset); 574 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 575 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 576 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 577 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 578 RegLocation NarrowRegLoc(RegLocation loc); 579 580 // Shared by all targets - implemented in local_optimizations.cc 581 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 582 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 583 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 584 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 585 586 // Shared by all targets - implemented in ralloc_util.cc 587 int GetSRegHi(int lowSreg); 588 bool LiveOut(int s_reg); 589 void SimpleRegAlloc(); 590 void ResetRegPool(); 591 void CompilerInitPool(RegisterInfo* info, RegStorage* regs, int num); 592 void DumpRegPool(GrowableArray<RegisterInfo*>* regs); 593 void DumpCoreRegPool(); 594 void DumpFpRegPool(); 595 void DumpRegPools(); 596 /* Mark a temp register as dead. Does not affect allocation state. */ 597 void Clobber(RegStorage reg); 598 void ClobberSRegBody(GrowableArray<RegisterInfo*>* regs, int s_reg); 599 void ClobberSReg(int s_reg); 600 int SRegToPMap(int s_reg); 601 void RecordCorePromotion(RegStorage reg, int s_reg); 602 RegStorage AllocPreservedCoreReg(int s_reg); 603 void RecordSinglePromotion(RegStorage reg, int s_reg); 604 void RecordDoublePromotion(RegStorage reg, int s_reg); 605 RegStorage AllocPreservedSingle(int s_reg); 606 virtual RegStorage AllocPreservedDouble(int s_reg); 607 RegStorage AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required); 608 RegStorage AllocFreeTemp(); 609 RegStorage AllocTemp(); 610 RegStorage AllocTempSingle(); 611 RegStorage AllocTempDouble(); 612 void FlushReg(RegStorage reg); 613 void FlushRegWide(RegStorage reg); 614 RegStorage AllocLiveReg(int s_reg, int reg_class, bool wide); 615 RegStorage FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg); 616 void FreeTemp(RegStorage reg); 617 bool IsLive(RegStorage reg); 618 bool IsTemp(RegStorage reg); 619 bool IsPromoted(RegStorage reg); 620 bool IsDirty(RegStorage reg); 621 void LockTemp(RegStorage reg); 622 void ResetDef(RegStorage reg); 623 void NullifyRange(RegStorage reg, int s_reg); 624 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 625 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 626 RegLocation WideToNarrow(RegLocation rl); 627 void ResetDefLoc(RegLocation rl); 628 void ResetDefLocWide(RegLocation rl); 629 void ResetDefTracking(); 630 void ClobberAllRegs(); 631 void FlushSpecificReg(RegisterInfo* info); 632 void FlushAllRegs(); 633 bool RegClassMatches(int reg_class, RegStorage reg); 634 void MarkLive(RegLocation loc); 635 void MarkLiveReg(RegStorage reg, int s_reg); 636 void MarkTemp(RegStorage reg); 637 void UnmarkTemp(RegStorage reg); 638 void MarkWide(RegStorage reg); 639 void MarkClean(RegLocation loc); 640 void MarkDirty(RegLocation loc); 641 void MarkInUse(RegStorage reg); 642 bool CheckCorePoolSanity(); 643 RegLocation UpdateLoc(RegLocation loc); 644 RegLocation UpdateLocWide(RegLocation loc); 645 RegLocation UpdateRawLoc(RegLocation loc); 646 647 /** 648 * @brief Used to load register location into a typed temporary or pair of temporaries. 649 * @see EvalLoc 650 * @param loc The register location to load from. 651 * @param reg_class Type of register needed. 652 * @param update Whether the liveness information should be updated. 653 * @return Returns the properly typed temporary in physical register pairs. 654 */ 655 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 656 657 /** 658 * @brief Used to load register location into a typed temporary. 659 * @param loc The register location to load from. 660 * @param reg_class Type of register needed. 661 * @param update Whether the liveness information should be updated. 662 * @return Returns the properly typed temporary in physical register. 663 */ 664 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 665 666 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 667 void DumpCounts(const RefCounts* arr, int size, const char* msg); 668 void DoPromotion(); 669 int VRegOffset(int v_reg); 670 int SRegOffset(int s_reg); 671 RegLocation GetReturnWide(bool is_double); 672 RegLocation GetReturn(bool is_float); 673 RegisterInfo* GetRegInfo(RegStorage reg); 674 675 // Shared by all targets - implemented in gen_common.cc. 676 void AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume = nullptr); 677 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 678 RegLocation rl_src, RegLocation rl_dest, int lit); 679 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 680 void HandleSlowPaths(); 681 void GenBarrier(); 682 void GenDivZeroException(); 683 // c_code holds condition code that's generated from testing divisor against 0. 684 void GenDivZeroCheck(ConditionCode c_code); 685 // reg holds divisor. 686 void GenDivZeroCheck(RegStorage reg); 687 void GenArrayBoundsCheck(RegStorage index, RegStorage length); 688 void GenArrayBoundsCheck(int32_t index, RegStorage length); 689 LIR* GenNullCheck(RegStorage reg); 690 void MarkPossibleNullPointerException(int opt_flags); 691 void MarkPossibleStackOverflowException(); 692 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 693 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 694 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 695 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 696 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 697 RegLocation rl_src2, LIR* taken, LIR* fall_through); 698 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 699 LIR* taken, LIR* fall_through); 700 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 701 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 702 RegLocation rl_src); 703 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 704 RegLocation rl_src); 705 void GenFilledNewArray(CallInfo* info); 706 void GenSput(MIR* mir, RegLocation rl_src, 707 bool is_long_or_double, bool is_object); 708 void GenSget(MIR* mir, RegLocation rl_dest, 709 bool is_long_or_double, bool is_object); 710 void GenIGet(MIR* mir, int opt_flags, OpSize size, 711 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 712 void GenIPut(MIR* mir, int opt_flags, OpSize size, 713 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 714 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 715 RegLocation rl_src); 716 717 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 718 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 719 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 720 void GenThrow(RegLocation rl_src); 721 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 722 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 723 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 724 RegLocation rl_src1, RegLocation rl_src2); 725 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 726 RegLocation rl_src1, RegLocation rl_shift); 727 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 728 RegLocation rl_src, int lit); 729 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 730 RegLocation rl_src1, RegLocation rl_src2); 731 void GenConversionCall(ThreadOffset<4> func_offset, RegLocation rl_dest, 732 RegLocation rl_src); 733 void GenSuspendTest(int opt_flags); 734 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 735 736 // This will be overridden by x86 implementation. 737 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 738 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 739 RegLocation rl_src1, RegLocation rl_src2); 740 741 // Shared by all targets - implemented in gen_invoke.cc. 742 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, bool safepoint_pc, 743 bool use_link = true); 744 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 745 void CallRuntimeHelper(ThreadOffset<4> helper_offset, bool safepoint_pc); 746 void CallRuntimeHelperImm(ThreadOffset<4> helper_offset, int arg0, bool safepoint_pc); 747 void CallRuntimeHelperReg(ThreadOffset<4> helper_offset, RegStorage arg0, bool safepoint_pc); 748 void CallRuntimeHelperRegLocation(ThreadOffset<4> helper_offset, RegLocation arg0, 749 bool safepoint_pc); 750 void CallRuntimeHelperImmImm(ThreadOffset<4> helper_offset, int arg0, int arg1, 751 bool safepoint_pc); 752 void CallRuntimeHelperImmRegLocation(ThreadOffset<4> helper_offset, int arg0, 753 RegLocation arg1, bool safepoint_pc); 754 void CallRuntimeHelperRegLocationImm(ThreadOffset<4> helper_offset, RegLocation arg0, 755 int arg1, bool safepoint_pc); 756 void CallRuntimeHelperImmReg(ThreadOffset<4> helper_offset, int arg0, RegStorage arg1, 757 bool safepoint_pc); 758 void CallRuntimeHelperRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, int arg1, 759 bool safepoint_pc); 760 void CallRuntimeHelperImmMethod(ThreadOffset<4> helper_offset, int arg0, 761 bool safepoint_pc); 762 void CallRuntimeHelperRegMethod(ThreadOffset<4> helper_offset, RegStorage arg0, 763 bool safepoint_pc); 764 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<4> helper_offset, RegStorage arg0, 765 RegLocation arg2, bool safepoint_pc); 766 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<4> helper_offset, 767 RegLocation arg0, RegLocation arg1, 768 bool safepoint_pc); 769 void CallRuntimeHelperRegReg(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 770 bool safepoint_pc); 771 void CallRuntimeHelperRegRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 772 int arg2, bool safepoint_pc); 773 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<4> helper_offset, int arg0, 774 RegLocation arg2, bool safepoint_pc); 775 void CallRuntimeHelperImmMethodImm(ThreadOffset<4> helper_offset, int arg0, int arg2, 776 bool safepoint_pc); 777 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<4> helper_offset, 778 int arg0, RegLocation arg1, RegLocation arg2, 779 bool safepoint_pc); 780 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<4> helper_offset, 781 RegLocation arg0, RegLocation arg1, 782 RegLocation arg2, 783 bool safepoint_pc); 784 void GenInvoke(CallInfo* info); 785 void GenInvokeNoInline(CallInfo* info); 786 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 787 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 788 NextCallInsn next_call_insn, 789 const MethodReference& target_method, 790 uint32_t vtable_idx, 791 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 792 bool skip_this); 793 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 794 NextCallInsn next_call_insn, 795 const MethodReference& target_method, 796 uint32_t vtable_idx, 797 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 798 bool skip_this); 799 800 /** 801 * @brief Used to determine the register location of destination. 802 * @details This is needed during generation of inline intrinsics because it finds destination 803 * of return, 804 * either the physical register or the target of move-result. 805 * @param info Information about the invoke. 806 * @return Returns the destination location. 807 */ 808 RegLocation InlineTarget(CallInfo* info); 809 810 /** 811 * @brief Used to determine the wide register location of destination. 812 * @see InlineTarget 813 * @param info Information about the invoke. 814 * @return Returns the destination location. 815 */ 816 RegLocation InlineTargetWide(CallInfo* info); 817 818 bool GenInlinedCharAt(CallInfo* info); 819 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 820 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 821 bool GenInlinedAbsInt(CallInfo* info); 822 bool GenInlinedAbsLong(CallInfo* info); 823 bool GenInlinedAbsFloat(CallInfo* info); 824 bool GenInlinedAbsDouble(CallInfo* info); 825 bool GenInlinedFloatCvt(CallInfo* info); 826 bool GenInlinedDoubleCvt(CallInfo* info); 827 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 828 bool GenInlinedStringCompareTo(CallInfo* info); 829 bool GenInlinedCurrentThread(CallInfo* info); 830 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 831 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 832 bool is_volatile, bool is_ordered); 833 int LoadArgRegs(CallInfo* info, int call_state, 834 NextCallInsn next_call_insn, 835 const MethodReference& target_method, 836 uint32_t vtable_idx, 837 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 838 bool skip_this); 839 840 // Shared by all targets - implemented in gen_loadstore.cc. 841 RegLocation LoadCurrMethod(); 842 void LoadCurrMethodDirect(RegStorage r_tgt); 843 LIR* LoadConstant(RegStorage r_dest, int value); 844 // Natural word size. 845 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 846 return LoadBaseDisp(r_base, displacement, r_dest, kWord); 847 } 848 // Load 32 bits, regardless of target. 849 LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { 850 return LoadBaseDisp(r_base, displacement, r_dest, k32); 851 } 852 // Load a reference at base + displacement and decompress into register. 853 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 854 return LoadBaseDisp(r_base, displacement, r_dest, kReference); 855 } 856 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 857 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 858 // Load Dalvik value with 64-bit memory storage. 859 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 860 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 861 void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 862 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 863 void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 864 // Load Dalvik value with 64-bit memory storage. 865 void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 866 // Load Dalvik value with 64-bit memory storage. 867 void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 868 // Store an item of natural word size. 869 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { 870 return StoreBaseDisp(r_base, displacement, r_src, kWord); 871 } 872 // Store an uncompressed reference into a compressed 32-bit container. 873 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src) { 874 return StoreBaseDisp(r_base, displacement, r_src, kReference); 875 } 876 // Store 32 bits, regardless of target. 877 LIR* Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) { 878 return StoreBaseDisp(r_base, displacement, r_src, k32); 879 } 880 881 /** 882 * @brief Used to do the final store in the destination as per bytecode semantics. 883 * @param rl_dest The destination dalvik register location. 884 * @param rl_src The source register location. Can be either physical register or dalvik register. 885 */ 886 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 887 888 /** 889 * @brief Used to do the final store in a wide destination as per bytecode semantics. 890 * @see StoreValue 891 * @param rl_dest The destination dalvik register location. 892 * @param rl_src The source register location. Can be either physical register or dalvik 893 * register. 894 */ 895 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 896 897 /** 898 * @brief Used to do the final store to a destination as per bytecode semantics. 899 * @see StoreValue 900 * @param rl_dest The destination dalvik register location. 901 * @param rl_src The source register location. It must be kLocPhysReg 902 * 903 * This is used for x86 two operand computations, where we have computed the correct 904 * register value that now needs to be properly registered. This is used to avoid an 905 * extra register copy that would result if StoreValue was called. 906 */ 907 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 908 909 /** 910 * @brief Used to do the final store in a wide destination as per bytecode semantics. 911 * @see StoreValueWide 912 * @param rl_dest The destination dalvik register location. 913 * @param rl_src The source register location. It must be kLocPhysReg 914 * 915 * This is used for x86 two operand computations, where we have computed the correct 916 * register values that now need to be properly registered. This is used to avoid an 917 * extra pair of register copies that would result if StoreValueWide was called. 918 */ 919 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 920 921 // Shared by all targets - implemented in mir_to_lir.cc. 922 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 923 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 924 bool MethodBlockCodeGen(BasicBlock* bb); 925 bool SpecialMIR2LIR(const InlineMethod& special); 926 void MethodMIR2LIR(); 927 // Update LIR for verbose listings. 928 void UpdateLIROffsets(); 929 930 /* 931 * @brief Load the address of the dex method into the register. 932 * @param target_method The MethodReference of the method to be invoked. 933 * @param type How the method will be invoked. 934 * @param register that will contain the code address. 935 * @note register will be passed to TargetReg to get physical register. 936 */ 937 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 938 SpecialTargetRegister symbolic_reg); 939 940 /* 941 * @brief Load the Method* of a dex method into the register. 942 * @param target_method The MethodReference of the method to be invoked. 943 * @param type How the method will be invoked. 944 * @param register that will contain the code address. 945 * @note register will be passed to TargetReg to get physical register. 946 */ 947 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 948 SpecialTargetRegister symbolic_reg); 949 950 /* 951 * @brief Load the Class* of a Dex Class type into the register. 952 * @param type How the method will be invoked. 953 * @param register that will contain the code address. 954 * @note register will be passed to TargetReg to get physical register. 955 */ 956 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 957 958 // Routines that work for the generic case, but may be overriden by target. 959 /* 960 * @brief Compare memory to immediate, and branch if condition true. 961 * @param cond The condition code that when true will branch to the target. 962 * @param temp_reg A temporary register that can be used if compare to memory is not 963 * supported by the architecture. 964 * @param base_reg The register holding the base address. 965 * @param offset The offset from the base. 966 * @param check_value The immediate to compare to. 967 * @returns The branch instruction that was generated. 968 */ 969 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 970 int offset, int check_value, LIR* target); 971 972 // Required for target - codegen helpers. 973 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 974 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 975 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 976 virtual LIR* CheckSuspendUsingLoad() = 0; 977 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 978 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 979 OpSize size) = 0; 980 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 981 int scale, OpSize size) = 0; 982 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 983 int displacement, RegStorage r_dest, OpSize size) = 0; 984 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 985 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 986 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 987 OpSize size) = 0; 988 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 989 int scale, OpSize size) = 0; 990 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 991 int displacement, RegStorage r_src, OpSize size) = 0; 992 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 993 994 // Required for target - register utilities. 995 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 996 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 997 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 998 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 999 virtual RegLocation GetReturnAlt() = 0; 1000 virtual RegLocation GetReturnWideAlt() = 0; 1001 virtual RegLocation LocCReturn() = 0; 1002 virtual RegLocation LocCReturnDouble() = 0; 1003 virtual RegLocation LocCReturnFloat() = 0; 1004 virtual RegLocation LocCReturnWide() = 0; 1005 virtual uint64_t GetRegMaskCommon(RegStorage reg) = 0; 1006 virtual void AdjustSpillMask() = 0; 1007 virtual void ClobberCallerSave() = 0; 1008 virtual void FreeCallTemps() = 0; 1009 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 1010 virtual void LockCallTemps() = 0; 1011 virtual void MarkPreservedSingle(int v_reg, RegStorage reg) = 0; 1012 virtual void MarkPreservedDouble(int v_reg, RegStorage reg) = 0; 1013 virtual void CompilerInitializeRegAlloc() = 0; 1014 1015 // Required for target - miscellaneous. 1016 virtual void AssembleLIR() = 0; 1017 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 1018 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 1019 virtual const char* GetTargetInstFmt(int opcode) = 0; 1020 virtual const char* GetTargetInstName(int opcode) = 0; 1021 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 1022 virtual uint64_t GetPCUseDefEncoding() = 0; 1023 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 1024 virtual int GetInsnSize(LIR* lir) = 0; 1025 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 1026 1027 // Required for target - Dalvik-level generators. 1028 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1029 RegLocation rl_src1, RegLocation rl_src2) = 0; 1030 virtual void GenMulLong(Instruction::Code, 1031 RegLocation rl_dest, RegLocation rl_src1, 1032 RegLocation rl_src2) = 0; 1033 virtual void GenAddLong(Instruction::Code, 1034 RegLocation rl_dest, RegLocation rl_src1, 1035 RegLocation rl_src2) = 0; 1036 virtual void GenAndLong(Instruction::Code, 1037 RegLocation rl_dest, RegLocation rl_src1, 1038 RegLocation rl_src2) = 0; 1039 virtual void GenArithOpDouble(Instruction::Code opcode, 1040 RegLocation rl_dest, RegLocation rl_src1, 1041 RegLocation rl_src2) = 0; 1042 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 1043 RegLocation rl_src1, RegLocation rl_src2) = 0; 1044 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 1045 RegLocation rl_src1, RegLocation rl_src2) = 0; 1046 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 1047 RegLocation rl_src) = 0; 1048 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 1049 1050 /** 1051 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 1052 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 1053 * that applies on integers. The generated code will write the smallest or largest value 1054 * directly into the destination register as specified by the invoke information. 1055 * @param info Information about the invoke. 1056 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 1057 * @return Returns true if successfully generated 1058 */ 1059 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 1060 1061 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 1062 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 1063 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 1064 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1065 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1066 RegLocation rl_src2) = 0; 1067 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1068 RegLocation rl_src2) = 0; 1069 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1070 RegLocation rl_src2) = 0; 1071 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 1072 bool is_div) = 0; 1073 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 1074 bool is_div) = 0; 1075 /* 1076 * @brief Generate an integer div or rem operation by a literal. 1077 * @param rl_dest Destination Location. 1078 * @param rl_src1 Numerator Location. 1079 * @param rl_src2 Divisor Location. 1080 * @param is_div 'true' if this is a division, 'false' for a remainder. 1081 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 1082 */ 1083 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 1084 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 1085 /* 1086 * @brief Generate an integer div or rem operation by a literal. 1087 * @param rl_dest Destination Location. 1088 * @param rl_src Numerator Location. 1089 * @param lit Divisor. 1090 * @param is_div 'true' if this is a division, 'false' for a remainder. 1091 */ 1092 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 1093 bool is_div) = 0; 1094 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 1095 1096 /** 1097 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 1098 * @details This is used for generating DivideByZero checks when divisor is held in two 1099 * separate registers. 1100 * @param reg The register holding the pair of 32-bit values. 1101 */ 1102 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 1103 1104 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 1105 virtual void GenExitSequence() = 0; 1106 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 1107 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 1108 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 1109 1110 /** 1111 * @brief Lowers the kMirOpSelect MIR into LIR. 1112 * @param bb The basic block in which the MIR is from. 1113 * @param mir The MIR whose opcode is kMirOpSelect. 1114 */ 1115 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 1116 1117 /** 1118 * @brief Used to generate a memory barrier in an architecture specific way. 1119 * @details The last generated LIR will be considered for use as barrier. Namely, 1120 * if the last LIR can be updated in a way where it will serve the semantics of 1121 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 1122 * that can keep the semantics. 1123 * @param barrier_kind The kind of memory barrier to generate. 1124 */ 1125 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 1126 1127 virtual void GenMoveException(RegLocation rl_dest) = 0; 1128 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 1129 int first_bit, int second_bit) = 0; 1130 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 1131 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 1132 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1133 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1134 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1135 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1136 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1137 RegLocation rl_index, RegLocation rl_src, int scale, 1138 bool card_mark) = 0; 1139 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1140 RegLocation rl_src1, RegLocation rl_shift) = 0; 1141 1142 // Required for target - single operation generators. 1143 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1144 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1145 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1146 LIR* target) = 0; 1147 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1148 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1149 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1150 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1151 virtual void OpEndIT(LIR* it) = 0; 1152 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1153 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1154 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1155 virtual void OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1156 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1157 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1158 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1159 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1160 1161 /** 1162 * @brief Used to generate an LIR that does a load from mem to reg. 1163 * @param r_dest The destination physical register. 1164 * @param r_base The base physical register for memory operand. 1165 * @param offset The displacement for memory operand. 1166 * @param move_type Specification on the move desired (size, alignment, register kind). 1167 * @return Returns the generate move LIR. 1168 */ 1169 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1170 MoveType move_type) = 0; 1171 1172 /** 1173 * @brief Used to generate an LIR that does a store from reg to mem. 1174 * @param r_base The base physical register for memory operand. 1175 * @param offset The displacement for memory operand. 1176 * @param r_src The destination physical register. 1177 * @param bytes_to_move The number of bytes to move. 1178 * @param is_aligned Whether the memory location is known to be aligned. 1179 * @return Returns the generate move LIR. 1180 */ 1181 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1182 MoveType move_type) = 0; 1183 1184 /** 1185 * @brief Used for generating a conditional register to register operation. 1186 * @param op The opcode kind. 1187 * @param cc The condition code that when true will perform the opcode. 1188 * @param r_dest The destination physical register. 1189 * @param r_src The source physical register. 1190 * @return Returns the newly created LIR or null in case of creation failure. 1191 */ 1192 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1193 1194 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1195 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1196 RegStorage r_src2) = 0; 1197 virtual LIR* OpTestSuspend(LIR* target) = 0; 1198 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1199 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1200 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1201 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1202 int offset) = 0; 1203 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1204 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1205 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1206 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1207 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1208 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1209 1210 // May be optimized by targets. 1211 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1212 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1213 1214 // Temp workaround 1215 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1216 1217 protected: 1218 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1219 1220 CompilationUnit* GetCompilationUnit() { 1221 return cu_; 1222 } 1223 /* 1224 * @brief Returns the index of the lowest set bit in 'x'. 1225 * @param x Value to be examined. 1226 * @returns The bit number of the lowest bit set in the value. 1227 */ 1228 int32_t LowestSetBit(uint64_t x); 1229 /* 1230 * @brief Is this value a power of two? 1231 * @param x Value to be examined. 1232 * @returns 'true' if only 1 bit is set in the value. 1233 */ 1234 bool IsPowerOfTwo(uint64_t x); 1235 /* 1236 * @brief Do these SRs overlap? 1237 * @param rl_op1 One RegLocation 1238 * @param rl_op2 The other RegLocation 1239 * @return 'true' if the VR pairs overlap 1240 * 1241 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1242 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1243 * dex, we'll want to make this case illegal. 1244 */ 1245 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1246 1247 /* 1248 * @brief Force a location (in a register) into a temporary register 1249 * @param loc location of result 1250 * @returns update location 1251 */ 1252 RegLocation ForceTemp(RegLocation loc); 1253 1254 /* 1255 * @brief Force a wide location (in registers) into temporary registers 1256 * @param loc location of result 1257 * @returns update location 1258 */ 1259 RegLocation ForceTempWide(RegLocation loc); 1260 1261 static constexpr OpSize LoadStoreOpSize(bool wide, bool ref) { 1262 return wide ? k64 : ref ? kReference : k32; 1263 } 1264 1265 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1266 RegLocation rl_dest, RegLocation rl_src); 1267 1268 void AddSlowPath(LIRSlowPath* slowpath); 1269 1270 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1271 bool type_known_abstract, bool use_declaring_class, 1272 bool can_assume_type_is_in_dex_cache, 1273 uint32_t type_idx, RegLocation rl_dest, 1274 RegLocation rl_src); 1275 /* 1276 * @brief Generate the debug_frame FDE information if possible. 1277 * @returns pointer to vector containg CFE information, or NULL. 1278 */ 1279 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1280 1281 /** 1282 * @brief Used to insert marker that can be used to associate MIR with LIR. 1283 * @details Only inserts marker if verbosity is enabled. 1284 * @param mir The mir that is currently being generated. 1285 */ 1286 void GenPrintLabel(MIR* mir); 1287 1288 /** 1289 * @brief Used to generate return sequence when there is no frame. 1290 * @details Assumes that the return registers have already been populated. 1291 */ 1292 virtual void GenSpecialExitSequence() = 0; 1293 1294 /** 1295 * @brief Used to generate code for special methods that are known to be 1296 * small enough to work in frameless mode. 1297 * @param bb The basic block of the first MIR. 1298 * @param mir The first MIR of the special method. 1299 * @param special Information about the special method. 1300 * @return Returns whether or not this was handled successfully. Returns false 1301 * if caller should punt to normal MIR2LIR conversion. 1302 */ 1303 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1304 1305 private: 1306 void ClobberBody(RegisterInfo* p); 1307 void SetCurrentDexPc(DexOffset dexpc) { 1308 current_dalvik_offset_ = dexpc; 1309 } 1310 1311 /** 1312 * @brief Used to lock register if argument at in_position was passed that way. 1313 * @details Does nothing if the argument is passed via stack. 1314 * @param in_position The argument number whose register to lock. 1315 * @param wide Whether the argument is wide. 1316 */ 1317 void LockArg(int in_position, bool wide = false); 1318 1319 /** 1320 * @brief Used to load VR argument to a physical register. 1321 * @details The load is only done if the argument is not already in physical register. 1322 * LockArg must have been previously called. 1323 * @param in_position The argument number to load. 1324 * @param wide Whether the argument is 64-bit or not. 1325 * @return Returns the register (or register pair) for the loaded argument. 1326 */ 1327 RegStorage LoadArg(int in_position, bool wide = false); 1328 1329 /** 1330 * @brief Used to load a VR argument directly to a specified register location. 1331 * @param in_position The argument number to place in register. 1332 * @param rl_dest The register location where to place argument. 1333 */ 1334 void LoadArgDirect(int in_position, RegLocation rl_dest); 1335 1336 /** 1337 * @brief Used to generate LIR for special getter method. 1338 * @param mir The mir that represents the iget. 1339 * @param special Information about the special getter method. 1340 * @return Returns whether LIR was successfully generated. 1341 */ 1342 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1343 1344 /** 1345 * @brief Used to generate LIR for special setter method. 1346 * @param mir The mir that represents the iput. 1347 * @param special Information about the special setter method. 1348 * @return Returns whether LIR was successfully generated. 1349 */ 1350 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1351 1352 /** 1353 * @brief Used to generate LIR for special return-args method. 1354 * @param mir The mir that represents the return of argument. 1355 * @param special Information about the special return-args method. 1356 * @return Returns whether LIR was successfully generated. 1357 */ 1358 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1359 1360 void AddDivZeroCheckSlowPath(LIR* branch); 1361 1362 // Copy arg0 and arg1 to kArg0 and kArg1 safely, possibly using 1363 // kArg2 as temp. 1364 void CopyToArgumentRegs(RegStorage arg0, RegStorage arg1); 1365 1366 public: 1367 // TODO: add accessors for these. 1368 LIR* literal_list_; // Constants. 1369 LIR* method_literal_list_; // Method literals requiring patching. 1370 LIR* class_literal_list_; // Class literals requiring patching. 1371 LIR* code_literal_list_; // Code literals requiring patching. 1372 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1373 1374 protected: 1375 CompilationUnit* const cu_; 1376 MIRGraph* const mir_graph_; 1377 GrowableArray<SwitchTable*> switch_tables_; 1378 GrowableArray<FillArrayData*> fill_array_data_; 1379 GrowableArray<RegisterInfo*> tempreg_info_; 1380 GrowableArray<RegisterInfo*> reginfo_map_; 1381 GrowableArray<void*> pointer_storage_; 1382 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1383 CodeOffset data_offset_; // starting offset of literal pool. 1384 size_t total_size_; // header + code size. 1385 LIR* block_label_list_; 1386 PromotionMap* promotion_map_; 1387 /* 1388 * TODO: The code generation utilities don't have a built-in 1389 * mechanism to propagate the original Dalvik opcode address to the 1390 * associated generated instructions. For the trace compiler, this wasn't 1391 * necessary because the interpreter handled all throws and debugging 1392 * requests. For now we'll handle this by placing the Dalvik offset 1393 * in the CompilationUnit struct before codegen for each instruction. 1394 * The low-level LIR creation utilites will pull it from here. Rework this. 1395 */ 1396 DexOffset current_dalvik_offset_; 1397 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1398 RegisterPool* reg_pool_; 1399 /* 1400 * Sanity checking for the register temp tracking. The same ssa 1401 * name should never be associated with one temp register per 1402 * instruction compilation. 1403 */ 1404 int live_sreg_; 1405 CodeBuffer code_buffer_; 1406 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1407 std::vector<uint8_t> encoded_mapping_table_; 1408 std::vector<uint32_t> core_vmap_table_; 1409 std::vector<uint32_t> fp_vmap_table_; 1410 std::vector<uint8_t> native_gc_map_; 1411 int num_core_spills_; 1412 int num_fp_spills_; 1413 int frame_size_; 1414 unsigned int core_spill_mask_; 1415 unsigned int fp_spill_mask_; 1416 LIR* first_lir_insn_; 1417 LIR* last_lir_insn_; 1418 1419 GrowableArray<LIRSlowPath*> slow_paths_; 1420}; // Class Mir2Lir 1421 1422} // namespace art 1423 1424#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1425