mir_to_lir.h revision 3e5af82ae1a2cd69b7b045ac008ac3b394d17f41
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/backend.h" 25#include "dex/growable_array.h" 26#include "dex/arena_allocator.h" 27#include "driver/compiler_driver.h" 28#include "leb128_encoder.h" 29#include "safe_map.h" 30 31namespace art { 32 33/* 34 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 35 * add type safety (see runtime/offsets.h). 36 */ 37typedef uint32_t DexOffset; // Dex offset in code units. 38typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 39typedef uint32_t CodeOffset; // Native code offset in bytes. 40 41// Set to 1 to measure cost of suspend check. 42#define NO_SUSPEND 0 43 44#define IS_BINARY_OP (1ULL << kIsBinaryOp) 45#define IS_BRANCH (1ULL << kIsBranch) 46#define IS_IT (1ULL << kIsIT) 47#define IS_LOAD (1ULL << kMemLoad) 48#define IS_QUAD_OP (1ULL << kIsQuadOp) 49#define IS_QUIN_OP (1ULL << kIsQuinOp) 50#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 51#define IS_STORE (1ULL << kMemStore) 52#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 53#define IS_UNARY_OP (1ULL << kIsUnaryOp) 54#define NEEDS_FIXUP (1ULL << kPCRelFixup) 55#define NO_OPERAND (1ULL << kNoOperand) 56#define REG_DEF0 (1ULL << kRegDef0) 57#define REG_DEF1 (1ULL << kRegDef1) 58#define REG_DEFA (1ULL << kRegDefA) 59#define REG_DEFD (1ULL << kRegDefD) 60#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 61#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 62#define REG_DEF_LIST0 (1ULL << kRegDefList0) 63#define REG_DEF_LIST1 (1ULL << kRegDefList1) 64#define REG_DEF_LR (1ULL << kRegDefLR) 65#define REG_DEF_SP (1ULL << kRegDefSP) 66#define REG_USE0 (1ULL << kRegUse0) 67#define REG_USE1 (1ULL << kRegUse1) 68#define REG_USE2 (1ULL << kRegUse2) 69#define REG_USE3 (1ULL << kRegUse3) 70#define REG_USE4 (1ULL << kRegUse4) 71#define REG_USEA (1ULL << kRegUseA) 72#define REG_USEC (1ULL << kRegUseC) 73#define REG_USED (1ULL << kRegUseD) 74#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 75#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 76#define REG_USE_LIST0 (1ULL << kRegUseList0) 77#define REG_USE_LIST1 (1ULL << kRegUseList1) 78#define REG_USE_LR (1ULL << kRegUseLR) 79#define REG_USE_PC (1ULL << kRegUsePC) 80#define REG_USE_SP (1ULL << kRegUseSP) 81#define SETS_CCODES (1ULL << kSetsCCodes) 82#define USES_CCODES (1ULL << kUsesCCodes) 83 84// Common combo register usage patterns. 85#define REG_DEF01 (REG_DEF0 | REG_DEF1) 86#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 87#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 88#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 89#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 90#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 91#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 92#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 93#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 94#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 95#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 96#define REG_USE012 (REG_USE01 | REG_USE2) 97#define REG_USE014 (REG_USE01 | REG_USE4) 98#define REG_USE01 (REG_USE0 | REG_USE1) 99#define REG_USE02 (REG_USE0 | REG_USE2) 100#define REG_USE12 (REG_USE1 | REG_USE2) 101#define REG_USE23 (REG_USE2 | REG_USE3) 102#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 103 104struct BasicBlock; 105struct CallInfo; 106struct CompilationUnit; 107struct MIR; 108struct LIR; 109struct RegLocation; 110struct RegisterInfo; 111class DexFileMethodInliner; 112class MIRGraph; 113class Mir2Lir; 114 115typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 116 const MethodReference& target_method, 117 uint32_t method_idx, uintptr_t direct_code, 118 uintptr_t direct_method, InvokeType type); 119 120typedef std::vector<uint8_t> CodeBuffer; 121 122struct UseDefMasks { 123 uint64_t use_mask; // Resource mask for use. 124 uint64_t def_mask; // Resource mask for def. 125}; 126 127struct AssemblyInfo { 128 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 129 uint8_t bytes[16]; // Encoded instruction bytes. 130}; 131 132struct LIR { 133 CodeOffset offset; // Offset of this instruction. 134 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 135 int16_t opcode; 136 LIR* next; 137 LIR* prev; 138 LIR* target; 139 struct { 140 unsigned int alias_info:17; // For Dalvik register disambiguation. 141 bool is_nop:1; // LIR is optimized away. 142 unsigned int size:4; // Note: size of encoded instruction is in bytes. 143 bool use_def_invalid:1; // If true, masks should not be used. 144 unsigned int generation:1; // Used to track visitation state during fixup pass. 145 unsigned int fixup:8; // Fixup kind. 146 } flags; 147 union { 148 UseDefMasks m; // Use & Def masks used during optimization. 149 AssemblyInfo a; // Instruction encoding used during assembly phase. 150 } u; 151 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 152}; 153 154// Target-specific initialization. 155Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 156 ArenaAllocator* const arena); 157Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 158 ArenaAllocator* const arena); 159Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 160 ArenaAllocator* const arena); 161 162// Utility macros to traverse the LIR list. 163#define NEXT_LIR(lir) (lir->next) 164#define PREV_LIR(lir) (lir->prev) 165 166// Defines for alias_info (tracks Dalvik register references). 167#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 168#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 169#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 170#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 171 172// Common resource macros. 173#define ENCODE_CCODE (1ULL << kCCode) 174#define ENCODE_FP_STATUS (1ULL << kFPStatus) 175 176// Abstract memory locations. 177#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 178#define ENCODE_LITERAL (1ULL << kLiteral) 179#define ENCODE_HEAP_REF (1ULL << kHeapRef) 180#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 181 182#define ENCODE_ALL (~0ULL) 183#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 184 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 185 186// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 187#define STARTING_DOUBLE_SREG 0x10000 188 189// TODO: replace these macros 190#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 191#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 192#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 193#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 194#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 195 196class Mir2Lir : public Backend { 197 public: 198 /* 199 * Auxiliary information describing the location of data embedded in the Dalvik 200 * byte code stream. 201 */ 202 struct EmbeddedData { 203 CodeOffset offset; // Code offset of data block. 204 const uint16_t* table; // Original dex data. 205 DexOffset vaddr; // Dalvik offset of parent opcode. 206 }; 207 208 struct FillArrayData : EmbeddedData { 209 int32_t size; 210 }; 211 212 struct SwitchTable : EmbeddedData { 213 LIR* anchor; // Reference instruction for relative offsets. 214 LIR** targets; // Array of case targets. 215 }; 216 217 /* Static register use counts */ 218 struct RefCounts { 219 int count; 220 int s_reg; 221 }; 222 223 /* 224 * Data structure tracking the mapping between a Dalvik register (pair) and a 225 * native register (pair). The idea is to reuse the previously loaded value 226 * if possible, otherwise to keep the value in a native register as long as 227 * possible. 228 */ 229 struct RegisterInfo { 230 int reg; // Reg number 231 bool in_use; // Has it been allocated? 232 bool is_temp; // Can allocate as temp? 233 bool pair; // Part of a register pair? 234 int partner; // If pair, other reg of pair. 235 bool live; // Is there an associated SSA name? 236 bool dirty; // If live, is it dirty? 237 int s_reg; // Name of live value. 238 LIR *def_start; // Starting inst in last def sequence. 239 LIR *def_end; // Ending inst in last def sequence. 240 }; 241 242 struct RegisterPool { 243 int num_core_regs; 244 RegisterInfo *core_regs; 245 int next_core_reg; 246 int num_fp_regs; 247 RegisterInfo *FPRegs; 248 int next_fp_reg; 249 }; 250 251 struct PromotionMap { 252 RegLocationType core_location:3; 253 uint8_t core_reg; 254 RegLocationType fp_location:3; 255 uint8_t FpReg; 256 bool first_in_pair; 257 }; 258 259 virtual ~Mir2Lir() {} 260 261 int32_t s4FromSwitchData(const void* switch_data) { 262 return *reinterpret_cast<const int32_t*>(switch_data); 263 } 264 265 RegisterClass oat_reg_class_by_size(OpSize size) { 266 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 267 size == kSignedByte) ? kCoreReg : kAnyReg; 268 } 269 270 size_t CodeBufferSizeInBytes() { 271 return code_buffer_.size() / sizeof(code_buffer_[0]); 272 } 273 274 bool IsPseudoLirOp(int opcode) { 275 return (opcode < 0); 276 } 277 278 /* 279 * LIR operands are 32-bit integers. Sometimes, (especially for managing 280 * instructions which require PC-relative fixups), we need the operands to carry 281 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 282 * hold that index in the operand array. 283 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 284 * may be worth conditionally-compiling a set of identity functions here. 285 */ 286 uint32_t WrapPointer(void* pointer) { 287 uint32_t res = pointer_storage_.Size(); 288 pointer_storage_.Insert(pointer); 289 return res; 290 } 291 292 void* UnwrapPointer(size_t index) { 293 return pointer_storage_.Get(index); 294 } 295 296 // strdup(), but allocates from the arena. 297 char* ArenaStrdup(const char* str) { 298 size_t len = strlen(str) + 1; 299 char* res = reinterpret_cast<char*>(arena_->Alloc(len, ArenaAllocator::kAllocMisc)); 300 if (res != NULL) { 301 strncpy(res, str, len); 302 } 303 return res; 304 } 305 306 // Shared by all targets - implemented in codegen_util.cc 307 void AppendLIR(LIR* lir); 308 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 309 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 310 311 int ComputeFrameSize(); 312 virtual void Materialize(); 313 virtual CompiledMethod* GetCompiledMethod(); 314 void MarkSafepointPC(LIR* inst); 315 bool FastInstance(uint32_t field_idx, bool is_put, int* field_offset, bool* is_volatile); 316 void SetupResourceMasks(LIR* lir); 317 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 318 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 319 void SetupRegMask(uint64_t* mask, int reg); 320 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 321 void DumpPromotionMap(); 322 void CodegenDump(); 323 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 324 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 325 LIR* NewLIR0(int opcode); 326 LIR* NewLIR1(int opcode, int dest); 327 LIR* NewLIR2(int opcode, int dest, int src1); 328 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 329 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 330 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 331 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 332 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 333 LIR* AddWordData(LIR* *constant_list_p, int value); 334 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 335 void ProcessSwitchTables(); 336 void DumpSparseSwitchTable(const uint16_t* table); 337 void DumpPackedSwitchTable(const uint16_t* table); 338 void MarkBoundary(DexOffset offset, const char* inst_str); 339 void NopLIR(LIR* lir); 340 void UnlinkLIR(LIR* lir); 341 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 342 bool IsInexpensiveConstant(RegLocation rl_src); 343 ConditionCode FlipComparisonOrder(ConditionCode before); 344 void DumpMappingTable(const char* table_name, const char* descriptor, 345 const char* name, const Signature& signature, 346 const std::vector<uint32_t>& v); 347 void InstallLiteralPools(); 348 void InstallSwitchTables(); 349 void InstallFillArrayData(); 350 bool VerifyCatchEntries(); 351 void CreateMappingTables(); 352 void CreateNativeGcMap(); 353 int AssignLiteralOffset(CodeOffset offset); 354 int AssignSwitchTablesOffset(CodeOffset offset); 355 int AssignFillArrayDataOffset(CodeOffset offset); 356 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 357 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 358 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 359 360 // Shared by all targets - implemented in local_optimizations.cc 361 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src); 362 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 363 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 364 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 365 366 // Shared by all targets - implemented in ralloc_util.cc 367 int GetSRegHi(int lowSreg); 368 bool oat_live_out(int s_reg); 369 int oatSSASrc(MIR* mir, int num); 370 void SimpleRegAlloc(); 371 void ResetRegPool(); 372 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 373 void DumpRegPool(RegisterInfo* p, int num_regs); 374 void DumpCoreRegPool(); 375 void DumpFpRegPool(); 376 /* Mark a temp register as dead. Does not affect allocation state. */ 377 void Clobber(int reg) { 378 ClobberBody(GetRegInfo(reg)); 379 } 380 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 381 void ClobberSReg(int s_reg); 382 int SRegToPMap(int s_reg); 383 void RecordCorePromotion(int reg, int s_reg); 384 int AllocPreservedCoreReg(int s_reg); 385 void RecordFpPromotion(int reg, int s_reg); 386 int AllocPreservedSingle(int s_reg); 387 int AllocPreservedDouble(int s_reg); 388 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 389 int AllocTempDouble(); 390 int AllocFreeTemp(); 391 int AllocTemp(); 392 int AllocTempFloat(); 393 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 394 RegisterInfo* AllocLive(int s_reg, int reg_class); 395 void FreeTemp(int reg); 396 RegisterInfo* IsLive(int reg); 397 RegisterInfo* IsTemp(int reg); 398 RegisterInfo* IsPromoted(int reg); 399 bool IsDirty(int reg); 400 void LockTemp(int reg); 401 void ResetDef(int reg); 402 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 403 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 404 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 405 RegLocation WideToNarrow(RegLocation rl); 406 void ResetDefLoc(RegLocation rl); 407 void ResetDefLocWide(RegLocation rl); 408 void ResetDefTracking(); 409 void ClobberAllRegs(); 410 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 411 void FlushAllRegs(); 412 bool RegClassMatches(int reg_class, int reg); 413 void MarkLive(int reg, int s_reg); 414 void MarkTemp(int reg); 415 void UnmarkTemp(int reg); 416 void MarkPair(int low_reg, int high_reg); 417 void MarkClean(RegLocation loc); 418 void MarkDirty(RegLocation loc); 419 void MarkInUse(int reg); 420 void CopyRegInfo(int new_reg, int old_reg); 421 bool CheckCorePoolSanity(); 422 RegLocation UpdateLoc(RegLocation loc); 423 RegLocation UpdateLocWide(RegLocation loc); 424 RegLocation UpdateRawLoc(RegLocation loc); 425 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 426 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 427 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 428 void DumpCounts(const RefCounts* arr, int size, const char* msg); 429 void DoPromotion(); 430 int VRegOffset(int v_reg); 431 int SRegOffset(int s_reg); 432 RegLocation GetReturnWide(bool is_double); 433 RegLocation GetReturn(bool is_float); 434 RegisterInfo* GetRegInfo(int reg); 435 436 // Shared by all targets - implemented in gen_common.cc. 437 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 438 RegLocation rl_src, RegLocation rl_dest, int lit); 439 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 440 void HandleSuspendLaunchPads(); 441 void HandleIntrinsicLaunchPads(); 442 void HandleThrowLaunchPads(); 443 void GenBarrier(); 444 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 445 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val, 446 ThrowKind kind); 447 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags); 448 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 449 ThrowKind kind); 450 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 451 RegLocation rl_src2, LIR* taken, LIR* fall_through); 452 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 453 LIR* taken, LIR* fall_through); 454 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 455 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 456 RegLocation rl_src); 457 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 458 RegLocation rl_src); 459 void GenFilledNewArray(CallInfo* info); 460 void GenSput(uint32_t field_idx, RegLocation rl_src, 461 bool is_long_or_double, bool is_object); 462 void GenSget(uint32_t field_idx, RegLocation rl_dest, 463 bool is_long_or_double, bool is_object); 464 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size, 465 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 466 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size, 467 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 468 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 469 RegLocation rl_src); 470 471 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 472 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 473 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 474 void GenThrow(RegLocation rl_src); 475 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, 476 RegLocation rl_src); 477 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, 478 RegLocation rl_src); 479 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 480 RegLocation rl_src1, RegLocation rl_src2); 481 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 482 RegLocation rl_src1, RegLocation rl_shift); 483 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 484 RegLocation rl_src1, RegLocation rl_src2); 485 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 486 RegLocation rl_src, int lit); 487 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 488 RegLocation rl_src1, RegLocation rl_src2); 489 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 490 RegLocation rl_src); 491 void GenSuspendTest(int opt_flags); 492 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 493 494 // Shared by all targets - implemented in gen_invoke.cc. 495 int CallHelperSetup(ThreadOffset helper_offset); 496 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc); 497 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 498 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 499 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 500 bool safepoint_pc); 501 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 502 bool safepoint_pc); 503 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 504 RegLocation arg1, bool safepoint_pc); 505 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 506 int arg1, bool safepoint_pc); 507 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 508 bool safepoint_pc); 509 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 510 bool safepoint_pc); 511 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 512 bool safepoint_pc); 513 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 514 RegLocation arg0, RegLocation arg1, 515 bool safepoint_pc); 516 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 517 bool safepoint_pc); 518 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 519 int arg2, bool safepoint_pc); 520 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 521 RegLocation arg2, bool safepoint_pc); 522 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 523 bool safepoint_pc); 524 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 525 int arg0, RegLocation arg1, RegLocation arg2, 526 bool safepoint_pc); 527 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 528 RegLocation arg0, RegLocation arg1, 529 RegLocation arg2, 530 bool safepoint_pc); 531 void GenInvoke(CallInfo* info); 532 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 533 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 534 NextCallInsn next_call_insn, 535 const MethodReference& target_method, 536 uint32_t vtable_idx, 537 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 538 bool skip_this); 539 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 540 NextCallInsn next_call_insn, 541 const MethodReference& target_method, 542 uint32_t vtable_idx, 543 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 544 bool skip_this); 545 RegLocation InlineTarget(CallInfo* info); 546 RegLocation InlineTargetWide(CallInfo* info); 547 548 bool GenInlinedCharAt(CallInfo* info); 549 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 550 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 551 bool GenInlinedAbsInt(CallInfo* info); 552 bool GenInlinedAbsLong(CallInfo* info); 553 bool GenInlinedFloatCvt(CallInfo* info); 554 bool GenInlinedDoubleCvt(CallInfo* info); 555 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 556 bool GenInlinedStringCompareTo(CallInfo* info); 557 bool GenInlinedCurrentThread(CallInfo* info); 558 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 559 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 560 bool is_volatile, bool is_ordered); 561 int LoadArgRegs(CallInfo* info, int call_state, 562 NextCallInsn next_call_insn, 563 const MethodReference& target_method, 564 uint32_t vtable_idx, 565 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 566 bool skip_this); 567 568 // Shared by all targets - implemented in gen_loadstore.cc. 569 RegLocation LoadCurrMethod(); 570 void LoadCurrMethodDirect(int r_tgt); 571 LIR* LoadConstant(int r_dest, int value); 572 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 573 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 574 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 575 void LoadValueDirect(RegLocation rl_src, int r_dest); 576 void LoadValueDirectFixed(RegLocation rl_src, int r_dest); 577 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi); 578 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi); 579 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 580 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 581 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 582 583 // Shared by all targets - implemented in mir_to_lir.cc. 584 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 585 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 586 bool MethodBlockCodeGen(BasicBlock* bb); 587 void SpecialMIR2LIR(SpecialCaseHandler special_case); 588 void MethodMIR2LIR(); 589 590 591 592 // Required for target - codegen helpers. 593 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 594 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 595 virtual int LoadHelper(ThreadOffset offset) = 0; 596 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 597 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 598 int s_reg) = 0; 599 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 600 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 601 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0; 602 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0; 603 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0; 604 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 605 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 606 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 607 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 608 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 609 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0; 610 611 // Required for target - register utilities. 612 virtual bool IsFpReg(int reg) = 0; 613 virtual bool SameRegType(int reg1, int reg2) = 0; 614 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0; 615 virtual int AllocTypedTempPair(bool fp_hint, int reg_class) = 0; 616 virtual int S2d(int low_reg, int high_reg) = 0; 617 virtual int TargetReg(SpecialTargetRegister reg) = 0; 618 virtual RegLocation GetReturnAlt() = 0; 619 virtual RegLocation GetReturnWideAlt() = 0; 620 virtual RegLocation LocCReturn() = 0; 621 virtual RegLocation LocCReturnDouble() = 0; 622 virtual RegLocation LocCReturnFloat() = 0; 623 virtual RegLocation LocCReturnWide() = 0; 624 virtual uint32_t FpRegMask() = 0; 625 virtual uint64_t GetRegMaskCommon(int reg) = 0; 626 virtual void AdjustSpillMask() = 0; 627 virtual void ClobberCalleeSave() = 0; 628 virtual void FlushReg(int reg) = 0; 629 virtual void FlushRegWide(int reg1, int reg2) = 0; 630 virtual void FreeCallTemps() = 0; 631 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 632 virtual void LockCallTemps() = 0; 633 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 634 virtual void CompilerInitializeRegAlloc() = 0; 635 636 // Required for target - miscellaneous. 637 virtual void AssembleLIR() = 0; 638 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 639 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 640 virtual const char* GetTargetInstFmt(int opcode) = 0; 641 virtual const char* GetTargetInstName(int opcode) = 0; 642 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 643 virtual uint64_t GetPCUseDefEncoding() = 0; 644 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 645 virtual int GetInsnSize(LIR* lir) = 0; 646 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 647 648 // Required for target - Dalvik-level generators. 649 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 650 RegLocation rl_src1, RegLocation rl_src2) = 0; 651 virtual void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, 652 RegLocation rl_src2) = 0; 653 virtual void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, 654 RegLocation rl_src2) = 0; 655 virtual void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, 656 RegLocation rl_src2) = 0; 657 virtual void GenArithOpDouble(Instruction::Code opcode, 658 RegLocation rl_dest, RegLocation rl_src1, 659 RegLocation rl_src2) = 0; 660 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 661 RegLocation rl_src1, RegLocation rl_src2) = 0; 662 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 663 RegLocation rl_src1, RegLocation rl_src2) = 0; 664 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 665 RegLocation rl_src) = 0; 666 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 667 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 668 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 669 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 670 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 671 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 672 virtual void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, 673 RegLocation rl_src2) = 0; 674 virtual void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, 675 RegLocation rl_src2) = 0; 676 virtual void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, 677 RegLocation rl_src2) = 0; 678 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, 679 int offset, ThrowKind kind) = 0; 680 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, 681 bool is_div) = 0; 682 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, 683 bool is_div) = 0; 684 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 685 RegLocation rl_src2) = 0; 686 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0; 687 virtual void GenEntrySequence(RegLocation* ArgLocs, 688 RegLocation rl_method) = 0; 689 virtual void GenExitSequence() = 0; 690 virtual void GenFillArrayData(DexOffset table_offset, 691 RegLocation rl_src) = 0; 692 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, 693 bool is_double) = 0; 694 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 695 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 696 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 697 virtual void GenMoveException(RegLocation rl_dest) = 0; 698 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 699 RegLocation rl_result, int lit, int first_bit, 700 int second_bit) = 0; 701 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 702 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 703 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, 704 RegLocation rl_src) = 0; 705 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, 706 RegLocation rl_src) = 0; 707 virtual void GenSpecialCase(BasicBlock* bb, MIR* mir, 708 SpecialCaseHandler special_case) = 0; 709 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 710 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 711 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 712 RegLocation rl_index, RegLocation rl_src, int scale, 713 bool card_mark) = 0; 714 virtual void GenShiftImmOpLong(Instruction::Code opcode, 715 RegLocation rl_dest, RegLocation rl_src1, 716 RegLocation rl_shift) = 0; 717 718 // Required for target - single operation generators. 719 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 720 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target) = 0; 721 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target) = 0; 722 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 723 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) = 0; 724 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 725 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 726 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0; 727 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0; 728 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0; 729 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 730 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0; 731 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0; 732 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0; 733 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0; 734 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0; 735 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) = 0; 736 virtual LIR* OpTestSuspend(LIR* target) = 0; 737 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 738 virtual LIR* OpVldm(int rBase, int count) = 0; 739 virtual LIR* OpVstm(int rBase, int count) = 0; 740 virtual void OpLea(int rBase, int reg1, int reg2, int scale, int offset) = 0; 741 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi) = 0; 742 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 743 virtual bool InexpensiveConstantInt(int32_t value) = 0; 744 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 745 virtual bool InexpensiveConstantLong(int64_t value) = 0; 746 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 747 748 // May be optimized by targets. 749 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 750 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 751 752 // Temp workaround 753 void Workaround7250540(RegLocation rl_dest, int value); 754 755 protected: 756 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 757 758 CompilationUnit* GetCompilationUnit() { 759 return cu_; 760 } 761 762 private: 763 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 764 RegLocation rl_src); 765 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 766 bool type_known_abstract, bool use_declaring_class, 767 bool can_assume_type_is_in_dex_cache, 768 uint32_t type_idx, RegLocation rl_dest, 769 RegLocation rl_src); 770 771 void ClobberBody(RegisterInfo* p); 772 void ResetDefBody(RegisterInfo* p) { 773 p->def_start = NULL; 774 p->def_end = NULL; 775 } 776 777 public: 778 // TODO: add accessors for these. 779 LIR* literal_list_; // Constants. 780 LIR* method_literal_list_; // Method literals requiring patching. 781 LIR* code_literal_list_; // Code literals requiring patching. 782 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 783 784 protected: 785 CompilationUnit* const cu_; 786 MIRGraph* const mir_graph_; 787 GrowableArray<SwitchTable*> switch_tables_; 788 GrowableArray<FillArrayData*> fill_array_data_; 789 GrowableArray<LIR*> throw_launchpads_; 790 GrowableArray<LIR*> suspend_launchpads_; 791 GrowableArray<LIR*> intrinsic_launchpads_; 792 GrowableArray<RegisterInfo*> tempreg_info_; 793 GrowableArray<RegisterInfo*> reginfo_map_; 794 GrowableArray<void*> pointer_storage_; 795 /* 796 * Holds mapping from native PC to dex PC for safepoints where we may deoptimize. 797 * Native PC is on the return address of the safepointed operation. Dex PC is for 798 * the instruction being executed at the safepoint. 799 */ 800 std::vector<uint32_t> pc2dex_mapping_table_; 801 /* 802 * Holds mapping from Dex PC to native PC for catch entry points. Native PC and Dex PC 803 * immediately preceed the instruction. 804 */ 805 std::vector<uint32_t> dex2pc_mapping_table_; 806 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 807 CodeOffset data_offset_; // starting offset of literal pool. 808 size_t total_size_; // header + code size. 809 LIR* block_label_list_; 810 PromotionMap* promotion_map_; 811 /* 812 * TODO: The code generation utilities don't have a built-in 813 * mechanism to propagate the original Dalvik opcode address to the 814 * associated generated instructions. For the trace compiler, this wasn't 815 * necessary because the interpreter handled all throws and debugging 816 * requests. For now we'll handle this by placing the Dalvik offset 817 * in the CompilationUnit struct before codegen for each instruction. 818 * The low-level LIR creation utilites will pull it from here. Rework this. 819 */ 820 DexOffset current_dalvik_offset_; 821 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 822 RegisterPool* reg_pool_; 823 /* 824 * Sanity checking for the register temp tracking. The same ssa 825 * name should never be associated with one temp register per 826 * instruction compilation. 827 */ 828 int live_sreg_; 829 CodeBuffer code_buffer_; 830 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 831 UnsignedLeb128EncodingVector encoded_mapping_table_; 832 std::vector<uint32_t> core_vmap_table_; 833 std::vector<uint32_t> fp_vmap_table_; 834 std::vector<uint8_t> native_gc_map_; 835 int num_core_spills_; 836 int num_fp_spills_; 837 int frame_size_; 838 unsigned int core_spill_mask_; 839 unsigned int fp_spill_mask_; 840 LIR* first_lir_insn_; 841 LIR* last_lir_insn_; 842 // Lazily retrieved method inliner for intrinsics. 843 const DexFileMethodInliner* inliner_; 844}; // Class Mir2Lir 845 846} // namespace art 847 848#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 849