mir_to_lir.h revision 6607d97166984ce578817269f9775c15b9044190
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/backend.h" 25#include "dex/growable_array.h" 26#include "dex/arena_allocator.h" 27#include "driver/compiler_driver.h" 28#include "leb128_encoder.h" 29#include "safe_map.h" 30 31namespace art { 32 33/* 34 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 35 * add type safety (see runtime/offsets.h). 36 */ 37typedef uint32_t DexOffset; // Dex offset in code units. 38typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 39typedef uint32_t CodeOffset; // Native code offset in bytes. 40 41// Set to 1 to measure cost of suspend check. 42#define NO_SUSPEND 0 43 44#define IS_BINARY_OP (1ULL << kIsBinaryOp) 45#define IS_BRANCH (1ULL << kIsBranch) 46#define IS_IT (1ULL << kIsIT) 47#define IS_LOAD (1ULL << kMemLoad) 48#define IS_QUAD_OP (1ULL << kIsQuadOp) 49#define IS_QUIN_OP (1ULL << kIsQuinOp) 50#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 51#define IS_STORE (1ULL << kMemStore) 52#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 53#define IS_UNARY_OP (1ULL << kIsUnaryOp) 54#define NEEDS_FIXUP (1ULL << kPCRelFixup) 55#define NO_OPERAND (1ULL << kNoOperand) 56#define REG_DEF0 (1ULL << kRegDef0) 57#define REG_DEF1 (1ULL << kRegDef1) 58#define REG_DEFA (1ULL << kRegDefA) 59#define REG_DEFD (1ULL << kRegDefD) 60#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 61#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 62#define REG_DEF_LIST0 (1ULL << kRegDefList0) 63#define REG_DEF_LIST1 (1ULL << kRegDefList1) 64#define REG_DEF_LR (1ULL << kRegDefLR) 65#define REG_DEF_SP (1ULL << kRegDefSP) 66#define REG_USE0 (1ULL << kRegUse0) 67#define REG_USE1 (1ULL << kRegUse1) 68#define REG_USE2 (1ULL << kRegUse2) 69#define REG_USE3 (1ULL << kRegUse3) 70#define REG_USE4 (1ULL << kRegUse4) 71#define REG_USEA (1ULL << kRegUseA) 72#define REG_USEC (1ULL << kRegUseC) 73#define REG_USED (1ULL << kRegUseD) 74#define REG_USEB (1ULL << kRegUseB) 75#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 76#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 77#define REG_USE_LIST0 (1ULL << kRegUseList0) 78#define REG_USE_LIST1 (1ULL << kRegUseList1) 79#define REG_USE_LR (1ULL << kRegUseLR) 80#define REG_USE_PC (1ULL << kRegUsePC) 81#define REG_USE_SP (1ULL << kRegUseSP) 82#define SETS_CCODES (1ULL << kSetsCCodes) 83#define USES_CCODES (1ULL << kUsesCCodes) 84 85// Common combo register usage patterns. 86#define REG_DEF01 (REG_DEF0 | REG_DEF1) 87#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 88#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 89#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 90#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 91#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 92#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 93#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 94#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 95#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 96#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 97#define REG_USE012 (REG_USE01 | REG_USE2) 98#define REG_USE014 (REG_USE01 | REG_USE4) 99#define REG_USE01 (REG_USE0 | REG_USE1) 100#define REG_USE02 (REG_USE0 | REG_USE2) 101#define REG_USE12 (REG_USE1 | REG_USE2) 102#define REG_USE23 (REG_USE2 | REG_USE3) 103#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 104 105struct BasicBlock; 106struct CallInfo; 107struct CompilationUnit; 108struct InlineMethod; 109struct MIR; 110struct LIR; 111struct RegLocation; 112struct RegisterInfo; 113class DexFileMethodInliner; 114class MIRGraph; 115class Mir2Lir; 116 117typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 118 const MethodReference& target_method, 119 uint32_t method_idx, uintptr_t direct_code, 120 uintptr_t direct_method, InvokeType type); 121 122typedef std::vector<uint8_t> CodeBuffer; 123 124struct UseDefMasks { 125 uint64_t use_mask; // Resource mask for use. 126 uint64_t def_mask; // Resource mask for def. 127}; 128 129struct AssemblyInfo { 130 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 131 uint8_t bytes[16]; // Encoded instruction bytes. 132}; 133 134struct LIR { 135 CodeOffset offset; // Offset of this instruction. 136 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 137 int16_t opcode; 138 LIR* next; 139 LIR* prev; 140 LIR* target; 141 struct { 142 unsigned int alias_info:17; // For Dalvik register disambiguation. 143 bool is_nop:1; // LIR is optimized away. 144 unsigned int size:4; // Note: size of encoded instruction is in bytes. 145 bool use_def_invalid:1; // If true, masks should not be used. 146 unsigned int generation:1; // Used to track visitation state during fixup pass. 147 unsigned int fixup:8; // Fixup kind. 148 } flags; 149 union { 150 UseDefMasks m; // Use & Def masks used during optimization. 151 AssemblyInfo a; // Instruction encoding used during assembly phase. 152 } u; 153 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 154}; 155 156// Target-specific initialization. 157Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 158 ArenaAllocator* const arena); 159Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 160 ArenaAllocator* const arena); 161Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 162 ArenaAllocator* const arena); 163 164// Utility macros to traverse the LIR list. 165#define NEXT_LIR(lir) (lir->next) 166#define PREV_LIR(lir) (lir->prev) 167 168// Defines for alias_info (tracks Dalvik register references). 169#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 170#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 171#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 172#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 173 174// Common resource macros. 175#define ENCODE_CCODE (1ULL << kCCode) 176#define ENCODE_FP_STATUS (1ULL << kFPStatus) 177 178// Abstract memory locations. 179#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 180#define ENCODE_LITERAL (1ULL << kLiteral) 181#define ENCODE_HEAP_REF (1ULL << kHeapRef) 182#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 183 184#define ENCODE_ALL (~0ULL) 185#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 186 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 187 188// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 189#define STARTING_DOUBLE_SREG 0x10000 190 191// TODO: replace these macros 192#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 193#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 194#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 195#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 196#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 197 198class Mir2Lir : public Backend { 199 public: 200 /* 201 * Auxiliary information describing the location of data embedded in the Dalvik 202 * byte code stream. 203 */ 204 struct EmbeddedData { 205 CodeOffset offset; // Code offset of data block. 206 const uint16_t* table; // Original dex data. 207 DexOffset vaddr; // Dalvik offset of parent opcode. 208 }; 209 210 struct FillArrayData : EmbeddedData { 211 int32_t size; 212 }; 213 214 struct SwitchTable : EmbeddedData { 215 LIR* anchor; // Reference instruction for relative offsets. 216 LIR** targets; // Array of case targets. 217 }; 218 219 /* Static register use counts */ 220 struct RefCounts { 221 int count; 222 int s_reg; 223 }; 224 225 /* 226 * Data structure tracking the mapping between a Dalvik register (pair) and a 227 * native register (pair). The idea is to reuse the previously loaded value 228 * if possible, otherwise to keep the value in a native register as long as 229 * possible. 230 */ 231 struct RegisterInfo { 232 int reg; // Reg number 233 bool in_use; // Has it been allocated? 234 bool is_temp; // Can allocate as temp? 235 bool pair; // Part of a register pair? 236 int partner; // If pair, other reg of pair. 237 bool live; // Is there an associated SSA name? 238 bool dirty; // If live, is it dirty? 239 int s_reg; // Name of live value. 240 LIR *def_start; // Starting inst in last def sequence. 241 LIR *def_end; // Ending inst in last def sequence. 242 }; 243 244 struct RegisterPool { 245 int num_core_regs; 246 RegisterInfo *core_regs; 247 int next_core_reg; 248 int num_fp_regs; 249 RegisterInfo *FPRegs; 250 int next_fp_reg; 251 }; 252 253 struct PromotionMap { 254 RegLocationType core_location:3; 255 uint8_t core_reg; 256 RegLocationType fp_location:3; 257 uint8_t FpReg; 258 bool first_in_pair; 259 }; 260 261 // 262 // Slow paths. This object is used generate a sequence of code that is executed in the 263 // slow path. For example, resolving a string or class is slow as it will only be executed 264 // once (after that it is resolved and doesn't need to be done again). We want slow paths 265 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 266 // branch over them. 267 // 268 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 269 // the Compile() function that will be called near the end of the code generated by the 270 // method. 271 // 272 // The basic flow for a slow path is: 273 // 274 // CMP reg, #value 275 // BEQ fromfast 276 // cont: 277 // ... 278 // fast path code 279 // ... 280 // more code 281 // ... 282 // RETURN 283 /// 284 // fromfast: 285 // ... 286 // slow path code 287 // ... 288 // B cont 289 // 290 // So you see we need two labels and two branches. The first branch (called fromfast) is 291 // the conditional branch to the slow path code. The second label (called cont) is used 292 // as an unconditional branch target for getting back to the code after the slow path 293 // has completed. 294 // 295 296 class LIRSlowPath { 297 public: 298 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 299 LIR* cont = nullptr) : 300 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 301 } 302 virtual ~LIRSlowPath() {} 303 virtual void Compile() = 0; 304 305 static void* operator new(size_t size, ArenaAllocator* arena) { 306 return arena->Alloc(size, ArenaAllocator::kAllocData); 307 } 308 309 protected: 310 LIR* GenerateTargetLabel(); 311 312 Mir2Lir* const m2l_; 313 const DexOffset current_dex_pc_; 314 LIR* const fromfast_; 315 LIR* const cont_; 316 }; 317 318 virtual ~Mir2Lir() {} 319 320 int32_t s4FromSwitchData(const void* switch_data) { 321 return *reinterpret_cast<const int32_t*>(switch_data); 322 } 323 324 RegisterClass oat_reg_class_by_size(OpSize size) { 325 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 326 size == kSignedByte) ? kCoreReg : kAnyReg; 327 } 328 329 size_t CodeBufferSizeInBytes() { 330 return code_buffer_.size() / sizeof(code_buffer_[0]); 331 } 332 333 bool IsPseudoLirOp(int opcode) { 334 return (opcode < 0); 335 } 336 337 /* 338 * LIR operands are 32-bit integers. Sometimes, (especially for managing 339 * instructions which require PC-relative fixups), we need the operands to carry 340 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 341 * hold that index in the operand array. 342 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 343 * may be worth conditionally-compiling a set of identity functions here. 344 */ 345 uint32_t WrapPointer(void* pointer) { 346 uint32_t res = pointer_storage_.Size(); 347 pointer_storage_.Insert(pointer); 348 return res; 349 } 350 351 void* UnwrapPointer(size_t index) { 352 return pointer_storage_.Get(index); 353 } 354 355 // strdup(), but allocates from the arena. 356 char* ArenaStrdup(const char* str) { 357 size_t len = strlen(str) + 1; 358 char* res = reinterpret_cast<char*>(arena_->Alloc(len, ArenaAllocator::kAllocMisc)); 359 if (res != NULL) { 360 strncpy(res, str, len); 361 } 362 return res; 363 } 364 365 // Shared by all targets - implemented in codegen_util.cc 366 void AppendLIR(LIR* lir); 367 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 368 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 369 370 /** 371 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 372 * to place in a frame. 373 * @return Returns the maximum number of compiler temporaries. 374 */ 375 size_t GetMaxPossibleCompilerTemps() const; 376 377 /** 378 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 379 * @return Returns the size in bytes for space needed for compiler temporary spill region. 380 */ 381 size_t GetNumBytesForCompilerTempSpillRegion(); 382 383 DexOffset GetCurrentDexPc() const { 384 return current_dalvik_offset_; 385 } 386 387 int ComputeFrameSize(); 388 virtual void Materialize(); 389 virtual CompiledMethod* GetCompiledMethod(); 390 void MarkSafepointPC(LIR* inst); 391 bool FastInstance(uint32_t field_idx, bool is_put, int* field_offset, bool* is_volatile); 392 void SetupResourceMasks(LIR* lir); 393 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 394 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 395 void SetupRegMask(uint64_t* mask, int reg); 396 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 397 void DumpPromotionMap(); 398 void CodegenDump(); 399 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 400 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 401 LIR* NewLIR0(int opcode); 402 LIR* NewLIR1(int opcode, int dest); 403 LIR* NewLIR2(int opcode, int dest, int src1); 404 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 405 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 406 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 407 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 408 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 409 LIR* AddWordData(LIR* *constant_list_p, int value); 410 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 411 void ProcessSwitchTables(); 412 void DumpSparseSwitchTable(const uint16_t* table); 413 void DumpPackedSwitchTable(const uint16_t* table); 414 void MarkBoundary(DexOffset offset, const char* inst_str); 415 void NopLIR(LIR* lir); 416 void UnlinkLIR(LIR* lir); 417 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 418 bool IsInexpensiveConstant(RegLocation rl_src); 419 ConditionCode FlipComparisonOrder(ConditionCode before); 420 void InstallLiteralPools(); 421 void InstallSwitchTables(); 422 void InstallFillArrayData(); 423 bool VerifyCatchEntries(); 424 void CreateMappingTables(); 425 void CreateNativeGcMap(); 426 int AssignLiteralOffset(CodeOffset offset); 427 int AssignSwitchTablesOffset(CodeOffset offset); 428 int AssignFillArrayDataOffset(CodeOffset offset); 429 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 430 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 431 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 432 433 // Shared by all targets - implemented in local_optimizations.cc 434 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src); 435 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 436 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 437 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 438 439 // Shared by all targets - implemented in ralloc_util.cc 440 int GetSRegHi(int lowSreg); 441 bool oat_live_out(int s_reg); 442 int oatSSASrc(MIR* mir, int num); 443 void SimpleRegAlloc(); 444 void ResetRegPool(); 445 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 446 void DumpRegPool(RegisterInfo* p, int num_regs); 447 void DumpCoreRegPool(); 448 void DumpFpRegPool(); 449 /* Mark a temp register as dead. Does not affect allocation state. */ 450 void Clobber(int reg) { 451 ClobberBody(GetRegInfo(reg)); 452 } 453 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 454 void ClobberSReg(int s_reg); 455 int SRegToPMap(int s_reg); 456 void RecordCorePromotion(int reg, int s_reg); 457 int AllocPreservedCoreReg(int s_reg); 458 void RecordFpPromotion(int reg, int s_reg); 459 int AllocPreservedSingle(int s_reg); 460 int AllocPreservedDouble(int s_reg); 461 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 462 virtual int AllocTempDouble(); 463 int AllocFreeTemp(); 464 int AllocTemp(); 465 int AllocTempFloat(); 466 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 467 RegisterInfo* AllocLive(int s_reg, int reg_class); 468 void FreeTemp(int reg); 469 RegisterInfo* IsLive(int reg); 470 RegisterInfo* IsTemp(int reg); 471 RegisterInfo* IsPromoted(int reg); 472 bool IsDirty(int reg); 473 void LockTemp(int reg); 474 void ResetDef(int reg); 475 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 476 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 477 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 478 RegLocation WideToNarrow(RegLocation rl); 479 void ResetDefLoc(RegLocation rl); 480 virtual void ResetDefLocWide(RegLocation rl); 481 void ResetDefTracking(); 482 void ClobberAllRegs(); 483 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 484 void FlushAllRegs(); 485 bool RegClassMatches(int reg_class, int reg); 486 void MarkLive(int reg, int s_reg); 487 void MarkTemp(int reg); 488 void UnmarkTemp(int reg); 489 void MarkPair(int low_reg, int high_reg); 490 void MarkClean(RegLocation loc); 491 void MarkDirty(RegLocation loc); 492 void MarkInUse(int reg); 493 void CopyRegInfo(int new_reg, int old_reg); 494 bool CheckCorePoolSanity(); 495 RegLocation UpdateLoc(RegLocation loc); 496 virtual RegLocation UpdateLocWide(RegLocation loc); 497 RegLocation UpdateRawLoc(RegLocation loc); 498 499 /** 500 * @brief Used to load register location into a typed temporary or pair of temporaries. 501 * @see EvalLoc 502 * @param loc The register location to load from. 503 * @param reg_class Type of register needed. 504 * @param update Whether the liveness information should be updated. 505 * @return Returns the properly typed temporary in physical register pairs. 506 */ 507 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 508 509 /** 510 * @brief Used to load register location into a typed temporary. 511 * @param loc The register location to load from. 512 * @param reg_class Type of register needed. 513 * @param update Whether the liveness information should be updated. 514 * @return Returns the properly typed temporary in physical register. 515 */ 516 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 517 518 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 519 void DumpCounts(const RefCounts* arr, int size, const char* msg); 520 void DoPromotion(); 521 int VRegOffset(int v_reg); 522 int SRegOffset(int s_reg); 523 RegLocation GetReturnWide(bool is_double); 524 RegLocation GetReturn(bool is_float); 525 RegisterInfo* GetRegInfo(int reg); 526 527 // Shared by all targets - implemented in gen_common.cc. 528 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 529 RegLocation rl_src, RegLocation rl_dest, int lit); 530 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 531 void HandleSuspendLaunchPads(); 532 void HandleIntrinsicLaunchPads(); 533 void HandleThrowLaunchPads(); 534 void HandleSlowPaths(); 535 void GenBarrier(); 536 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 537 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val, 538 ThrowKind kind); 539 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags); 540 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 541 ThrowKind kind); 542 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 543 RegLocation rl_src2, LIR* taken, LIR* fall_through); 544 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 545 LIR* taken, LIR* fall_through); 546 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 547 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 548 RegLocation rl_src); 549 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 550 RegLocation rl_src); 551 void GenFilledNewArray(CallInfo* info); 552 void GenSput(uint32_t field_idx, RegLocation rl_src, 553 bool is_long_or_double, bool is_object); 554 void GenSget(uint32_t field_idx, RegLocation rl_dest, 555 bool is_long_or_double, bool is_object); 556 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size, 557 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 558 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size, 559 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 560 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 561 RegLocation rl_src); 562 563 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 564 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 565 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 566 void GenThrow(RegLocation rl_src); 567 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, 568 RegLocation rl_src); 569 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, 570 RegLocation rl_src); 571 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 572 RegLocation rl_src1, RegLocation rl_src2); 573 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 574 RegLocation rl_src1, RegLocation rl_shift); 575 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 576 RegLocation rl_src, int lit); 577 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 578 RegLocation rl_src1, RegLocation rl_src2); 579 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 580 RegLocation rl_src); 581 void GenSuspendTest(int opt_flags); 582 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 583 584 // This will be overridden by x86 implementation. 585 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 586 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 587 RegLocation rl_src1, RegLocation rl_src2); 588 589 // Shared by all targets - implemented in gen_invoke.cc. 590 int CallHelperSetup(ThreadOffset helper_offset); 591 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc); 592 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 593 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 594 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 595 bool safepoint_pc); 596 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 597 bool safepoint_pc); 598 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 599 RegLocation arg1, bool safepoint_pc); 600 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 601 int arg1, bool safepoint_pc); 602 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 603 bool safepoint_pc); 604 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 605 bool safepoint_pc); 606 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 607 bool safepoint_pc); 608 void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 609 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, int arg0, 610 RegLocation arg2, bool safepoint_pc); 611 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 612 RegLocation arg0, RegLocation arg1, 613 bool safepoint_pc); 614 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 615 bool safepoint_pc); 616 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 617 int arg2, bool safepoint_pc); 618 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 619 RegLocation arg2, bool safepoint_pc); 620 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 621 bool safepoint_pc); 622 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 623 int arg0, RegLocation arg1, RegLocation arg2, 624 bool safepoint_pc); 625 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 626 RegLocation arg0, RegLocation arg1, 627 RegLocation arg2, 628 bool safepoint_pc); 629 void GenInvoke(CallInfo* info); 630 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 631 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 632 NextCallInsn next_call_insn, 633 const MethodReference& target_method, 634 uint32_t vtable_idx, 635 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 636 bool skip_this); 637 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 638 NextCallInsn next_call_insn, 639 const MethodReference& target_method, 640 uint32_t vtable_idx, 641 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 642 bool skip_this); 643 644 /** 645 * @brief Used to determine the register location of destination. 646 * @details This is needed during generation of inline intrinsics because it finds destination of return, 647 * either the physical register or the target of move-result. 648 * @param info Information about the invoke. 649 * @return Returns the destination location. 650 */ 651 RegLocation InlineTarget(CallInfo* info); 652 653 /** 654 * @brief Used to determine the wide register location of destination. 655 * @see InlineTarget 656 * @param info Information about the invoke. 657 * @return Returns the destination location. 658 */ 659 RegLocation InlineTargetWide(CallInfo* info); 660 661 bool GenInlinedCharAt(CallInfo* info); 662 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 663 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 664 bool GenInlinedAbsInt(CallInfo* info); 665 bool GenInlinedAbsLong(CallInfo* info); 666 bool GenInlinedFloatCvt(CallInfo* info); 667 bool GenInlinedDoubleCvt(CallInfo* info); 668 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 669 bool GenInlinedStringCompareTo(CallInfo* info); 670 bool GenInlinedCurrentThread(CallInfo* info); 671 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 672 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 673 bool is_volatile, bool is_ordered); 674 int LoadArgRegs(CallInfo* info, int call_state, 675 NextCallInsn next_call_insn, 676 const MethodReference& target_method, 677 uint32_t vtable_idx, 678 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 679 bool skip_this); 680 681 // Shared by all targets - implemented in gen_loadstore.cc. 682 RegLocation LoadCurrMethod(); 683 void LoadCurrMethodDirect(int r_tgt); 684 LIR* LoadConstant(int r_dest, int value); 685 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 686 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 687 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 688 void LoadValueDirect(RegLocation rl_src, int r_dest); 689 void LoadValueDirectFixed(RegLocation rl_src, int r_dest); 690 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi); 691 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi); 692 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 693 694 /** 695 * @brief Used to do the final store in the destination as per bytecode semantics. 696 * @param rl_dest The destination dalvik register location. 697 * @param rl_src The source register location. Can be either physical register or dalvik register. 698 */ 699 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 700 701 /** 702 * @brief Used to do the final store in a wide destination as per bytecode semantics. 703 * @see StoreValue 704 * @param rl_dest The destination dalvik register location. 705 * @param rl_src The source register location. Can be either physical register or dalvik register. 706 */ 707 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 708 709 /** 710 * @brief Used to do the final store to a destination as per bytecode semantics. 711 * @see StoreValue 712 * @param rl_dest The destination dalvik register location. 713 * @param rl_src The source register location. It must be kLocPhysReg 714 * 715 * This is used for x86 two operand computations, where we have computed the correct 716 * register value that now needs to be properly registered. This is used to avoid an 717 * extra register copy that would result if StoreValue was called. 718 */ 719 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 720 721 /** 722 * @brief Used to do the final store in a wide destination as per bytecode semantics. 723 * @see StoreValueWide 724 * @param rl_dest The destination dalvik register location. 725 * @param rl_src The source register location. It must be kLocPhysReg 726 * 727 * This is used for x86 two operand computations, where we have computed the correct 728 * register values that now need to be properly registered. This is used to avoid an 729 * extra pair of register copies that would result if StoreValueWide was called. 730 */ 731 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 732 733 // Shared by all targets - implemented in mir_to_lir.cc. 734 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 735 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 736 bool MethodBlockCodeGen(BasicBlock* bb); 737 void SpecialMIR2LIR(const InlineMethod& special); 738 void MethodMIR2LIR(); 739 740 // Routines that work for the generic case, but may be overriden by target. 741 /* 742 * @brief Compare memory to immediate, and branch if condition true. 743 * @param cond The condition code that when true will branch to the target. 744 * @param temp_reg A temporary register that can be used if compare to memory is not 745 * supported by the architecture. 746 * @param base_reg The register holding the base address. 747 * @param offset The offset from the base. 748 * @param check_value The immediate to compare to. 749 * @returns The branch instruction that was generated. 750 */ 751 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg, 752 int offset, int check_value, LIR* target); 753 754 // Required for target - codegen helpers. 755 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 756 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 757 virtual int LoadHelper(ThreadOffset offset) = 0; 758 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 759 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 760 int s_reg) = 0; 761 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 762 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 763 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0; 764 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0; 765 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0; 766 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 767 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 768 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 769 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 770 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 771 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0; 772 773 // Required for target - register utilities. 774 virtual bool IsFpReg(int reg) = 0; 775 virtual bool SameRegType(int reg1, int reg2) = 0; 776 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0; 777 virtual int AllocTypedTempPair(bool fp_hint, int reg_class) = 0; 778 virtual int S2d(int low_reg, int high_reg) = 0; 779 virtual int TargetReg(SpecialTargetRegister reg) = 0; 780 virtual RegLocation GetReturnAlt() = 0; 781 virtual RegLocation GetReturnWideAlt() = 0; 782 virtual RegLocation LocCReturn() = 0; 783 virtual RegLocation LocCReturnDouble() = 0; 784 virtual RegLocation LocCReturnFloat() = 0; 785 virtual RegLocation LocCReturnWide() = 0; 786 virtual uint32_t FpRegMask() = 0; 787 virtual uint64_t GetRegMaskCommon(int reg) = 0; 788 virtual void AdjustSpillMask() = 0; 789 virtual void ClobberCallerSave() = 0; 790 virtual void FlushReg(int reg) = 0; 791 virtual void FlushRegWide(int reg1, int reg2) = 0; 792 virtual void FreeCallTemps() = 0; 793 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 794 virtual void LockCallTemps() = 0; 795 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 796 virtual void CompilerInitializeRegAlloc() = 0; 797 798 // Required for target - miscellaneous. 799 virtual void AssembleLIR() = 0; 800 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 801 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 802 virtual const char* GetTargetInstFmt(int opcode) = 0; 803 virtual const char* GetTargetInstName(int opcode) = 0; 804 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 805 virtual uint64_t GetPCUseDefEncoding() = 0; 806 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 807 virtual int GetInsnSize(LIR* lir) = 0; 808 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 809 810 // Required for target - Dalvik-level generators. 811 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 812 RegLocation rl_src1, RegLocation rl_src2) = 0; 813 virtual void GenMulLong(Instruction::Code, 814 RegLocation rl_dest, RegLocation rl_src1, 815 RegLocation rl_src2) = 0; 816 virtual void GenAddLong(Instruction::Code, 817 RegLocation rl_dest, RegLocation rl_src1, 818 RegLocation rl_src2) = 0; 819 virtual void GenAndLong(Instruction::Code, 820 RegLocation rl_dest, RegLocation rl_src1, 821 RegLocation rl_src2) = 0; 822 virtual void GenArithOpDouble(Instruction::Code opcode, 823 RegLocation rl_dest, RegLocation rl_src1, 824 RegLocation rl_src2) = 0; 825 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 826 RegLocation rl_src1, RegLocation rl_src2) = 0; 827 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 828 RegLocation rl_src1, RegLocation rl_src2) = 0; 829 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 830 RegLocation rl_src) = 0; 831 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 832 833 /** 834 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 835 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 836 * that applies on integers. The generated code will write the smallest or largest value 837 * directly into the destination register as specified by the invoke information. 838 * @param info Information about the invoke. 839 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 840 * @return Returns true if successfully generated 841 */ 842 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 843 844 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 845 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 846 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 847 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 848 virtual void GenOrLong(Instruction::Code, 849 RegLocation rl_dest, RegLocation rl_src1, 850 RegLocation rl_src2) = 0; 851 virtual void GenSubLong(Instruction::Code, 852 RegLocation rl_dest, RegLocation rl_src1, 853 RegLocation rl_src2) = 0; 854 virtual void GenXorLong(Instruction::Code, 855 RegLocation rl_dest, RegLocation rl_src1, 856 RegLocation rl_src2) = 0; 857 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, 858 int offset, ThrowKind kind) = 0; 859 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, 860 bool is_div) = 0; 861 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, 862 bool is_div) = 0; 863 /* 864 * @brief Generate an integer div or rem operation by a literal. 865 * @param rl_dest Destination Location. 866 * @param rl_src1 Numerator Location. 867 * @param rl_src2 Divisor Location. 868 * @param is_div 'true' if this is a division, 'false' for a remainder. 869 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 870 */ 871 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 872 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 873 /* 874 * @brief Generate an integer div or rem operation by a literal. 875 * @param rl_dest Destination Location. 876 * @param rl_src Numerator Location. 877 * @param lit Divisor. 878 * @param is_div 'true' if this is a division, 'false' for a remainder. 879 */ 880 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, 881 int lit, bool is_div) = 0; 882 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 883 RegLocation rl_src2) = 0; 884 885 /** 886 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 887 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers. 888 * @param reg_lo The register holding the lower 32-bits. 889 * @param reg_hi The register holding the upper 32-bits. 890 */ 891 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0; 892 893 virtual void GenEntrySequence(RegLocation* ArgLocs, 894 RegLocation rl_method) = 0; 895 virtual void GenExitSequence() = 0; 896 virtual void GenFillArrayData(DexOffset table_offset, 897 RegLocation rl_src) = 0; 898 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, 899 bool is_double) = 0; 900 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 901 902 /** 903 * @brief Lowers the kMirOpSelect MIR into LIR. 904 * @param bb The basic block in which the MIR is from. 905 * @param mir The MIR whose opcode is kMirOpSelect. 906 */ 907 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 908 909 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 910 virtual void GenMoveException(RegLocation rl_dest) = 0; 911 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 912 RegLocation rl_result, int lit, int first_bit, 913 int second_bit) = 0; 914 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 915 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 916 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, 917 RegLocation rl_src) = 0; 918 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, 919 RegLocation rl_src) = 0; 920 virtual void GenSpecialCase(BasicBlock* bb, MIR* mir, 921 const InlineMethod& special) = 0; 922 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 923 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 924 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 925 RegLocation rl_index, RegLocation rl_src, int scale, 926 bool card_mark) = 0; 927 virtual void GenShiftImmOpLong(Instruction::Code opcode, 928 RegLocation rl_dest, RegLocation rl_src1, 929 RegLocation rl_shift) = 0; 930 931 // Required for target - single operation generators. 932 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 933 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target) = 0; 934 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target) = 0; 935 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 936 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) = 0; 937 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 938 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 939 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0; 940 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0; 941 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0; 942 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 943 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0; 944 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0; 945 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0; 946 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0; 947 948 /** 949 * @brief Used to generate an LIR that does a load from mem to reg. 950 * @param r_dest The destination physical register. 951 * @param r_base The base physical register for memory operand. 952 * @param offset The displacement for memory operand. 953 * @param move_type Specification on the move desired (size, alignment, register kind). 954 * @return Returns the generate move LIR. 955 */ 956 virtual LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) = 0; 957 958 /** 959 * @brief Used to generate an LIR that does a store from reg to mem. 960 * @param r_base The base physical register for memory operand. 961 * @param offset The displacement for memory operand. 962 * @param r_src The destination physical register. 963 * @param bytes_to_move The number of bytes to move. 964 * @param is_aligned Whether the memory location is known to be aligned. 965 * @return Returns the generate move LIR. 966 */ 967 virtual LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) = 0; 968 969 /** 970 * @brief Used for generating a conditional register to register operation. 971 * @param op The opcode kind. 972 * @param cc The condition code that when true will perform the opcode. 973 * @param r_dest The destination physical register. 974 * @param r_src The source physical register. 975 * @return Returns the newly created LIR or null in case of creation failure. 976 */ 977 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) = 0; 978 979 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0; 980 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) = 0; 981 virtual LIR* OpTestSuspend(LIR* target) = 0; 982 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 983 virtual LIR* OpVldm(int rBase, int count) = 0; 984 virtual LIR* OpVstm(int rBase, int count) = 0; 985 virtual void OpLea(int rBase, int reg1, int reg2, int scale, int offset) = 0; 986 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi) = 0; 987 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 988 virtual bool InexpensiveConstantInt(int32_t value) = 0; 989 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 990 virtual bool InexpensiveConstantLong(int64_t value) = 0; 991 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 992 993 // May be optimized by targets. 994 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 995 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 996 997 // Temp workaround 998 void Workaround7250540(RegLocation rl_dest, int value); 999 1000 protected: 1001 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1002 1003 CompilationUnit* GetCompilationUnit() { 1004 return cu_; 1005 } 1006 /* 1007 * @brief Returns the index of the lowest set bit in 'x'. 1008 * @param x Value to be examined. 1009 * @returns The bit number of the lowest bit set in the value. 1010 */ 1011 int32_t LowestSetBit(uint64_t x); 1012 /* 1013 * @brief Is this value a power of two? 1014 * @param x Value to be examined. 1015 * @returns 'true' if only 1 bit is set in the value. 1016 */ 1017 bool IsPowerOfTwo(uint64_t x); 1018 /* 1019 * @brief Do these SRs overlap? 1020 * @param rl_op1 One RegLocation 1021 * @param rl_op2 The other RegLocation 1022 * @return 'true' if the VR pairs overlap 1023 * 1024 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1025 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1026 * dex, we'll want to make this case illegal. 1027 */ 1028 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1029 1030 /* 1031 * @brief Force a location (in a register) into a temporary register 1032 * @param loc location of result 1033 * @returns update location 1034 */ 1035 RegLocation ForceTemp(RegLocation loc); 1036 1037 /* 1038 * @brief Force a wide location (in registers) into temporary registers 1039 * @param loc location of result 1040 * @returns update location 1041 */ 1042 RegLocation ForceTempWide(RegLocation loc); 1043 1044 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1045 RegLocation rl_dest, RegLocation rl_src); 1046 1047 void AddSlowPath(LIRSlowPath* slowpath); 1048 1049 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1050 bool type_known_abstract, bool use_declaring_class, 1051 bool can_assume_type_is_in_dex_cache, 1052 uint32_t type_idx, RegLocation rl_dest, 1053 RegLocation rl_src); 1054 1055 private: 1056 void ClobberBody(RegisterInfo* p); 1057 void ResetDefBody(RegisterInfo* p) { 1058 p->def_start = NULL; 1059 p->def_end = NULL; 1060 } 1061 1062 void SetCurrentDexPc(DexOffset dexpc) { 1063 current_dalvik_offset_ = dexpc; 1064 } 1065 1066 1067 public: 1068 // TODO: add accessors for these. 1069 LIR* literal_list_; // Constants. 1070 LIR* method_literal_list_; // Method literals requiring patching. 1071 LIR* class_literal_list_; // Class literals requiring patching. 1072 LIR* code_literal_list_; // Code literals requiring patching. 1073 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1074 1075 protected: 1076 CompilationUnit* const cu_; 1077 MIRGraph* const mir_graph_; 1078 GrowableArray<SwitchTable*> switch_tables_; 1079 GrowableArray<FillArrayData*> fill_array_data_; 1080 GrowableArray<LIR*> throw_launchpads_; 1081 GrowableArray<LIR*> suspend_launchpads_; 1082 GrowableArray<LIR*> intrinsic_launchpads_; 1083 GrowableArray<RegisterInfo*> tempreg_info_; 1084 GrowableArray<RegisterInfo*> reginfo_map_; 1085 GrowableArray<void*> pointer_storage_; 1086 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1087 CodeOffset data_offset_; // starting offset of literal pool. 1088 size_t total_size_; // header + code size. 1089 LIR* block_label_list_; 1090 PromotionMap* promotion_map_; 1091 /* 1092 * TODO: The code generation utilities don't have a built-in 1093 * mechanism to propagate the original Dalvik opcode address to the 1094 * associated generated instructions. For the trace compiler, this wasn't 1095 * necessary because the interpreter handled all throws and debugging 1096 * requests. For now we'll handle this by placing the Dalvik offset 1097 * in the CompilationUnit struct before codegen for each instruction. 1098 * The low-level LIR creation utilites will pull it from here. Rework this. 1099 */ 1100 DexOffset current_dalvik_offset_; 1101 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1102 RegisterPool* reg_pool_; 1103 /* 1104 * Sanity checking for the register temp tracking. The same ssa 1105 * name should never be associated with one temp register per 1106 * instruction compilation. 1107 */ 1108 int live_sreg_; 1109 CodeBuffer code_buffer_; 1110 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1111 std::vector<uint8_t> encoded_mapping_table_; 1112 std::vector<uint32_t> core_vmap_table_; 1113 std::vector<uint32_t> fp_vmap_table_; 1114 std::vector<uint8_t> native_gc_map_; 1115 int num_core_spills_; 1116 int num_fp_spills_; 1117 int frame_size_; 1118 unsigned int core_spill_mask_; 1119 unsigned int fp_spill_mask_; 1120 LIR* first_lir_insn_; 1121 LIR* last_lir_insn_; 1122 1123 GrowableArray<LIRSlowPath*> slow_paths_; 1124}; // Class Mir2Lir 1125 1126} // namespace art 1127 1128#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1129