mir_to_lir.h revision 68a5fefa90f03fdf5a238ac85c9439c6b03eae96
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/backend.h" 25#include "driver/compiler_driver.h" 26#include "leb128_encoder.h" 27#include "safe_map.h" 28#include "utils/arena_allocator.h" 29#include "utils/growable_array.h" 30 31namespace art { 32 33/* 34 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 35 * add type safety (see runtime/offsets.h). 36 */ 37typedef uint32_t DexOffset; // Dex offset in code units. 38typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 39typedef uint32_t CodeOffset; // Native code offset in bytes. 40 41// Set to 1 to measure cost of suspend check. 42#define NO_SUSPEND 0 43 44#define IS_BINARY_OP (1ULL << kIsBinaryOp) 45#define IS_BRANCH (1ULL << kIsBranch) 46#define IS_IT (1ULL << kIsIT) 47#define IS_LOAD (1ULL << kMemLoad) 48#define IS_QUAD_OP (1ULL << kIsQuadOp) 49#define IS_QUIN_OP (1ULL << kIsQuinOp) 50#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 51#define IS_STORE (1ULL << kMemStore) 52#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 53#define IS_UNARY_OP (1ULL << kIsUnaryOp) 54#define NEEDS_FIXUP (1ULL << kPCRelFixup) 55#define NO_OPERAND (1ULL << kNoOperand) 56#define REG_DEF0 (1ULL << kRegDef0) 57#define REG_DEF1 (1ULL << kRegDef1) 58#define REG_DEFA (1ULL << kRegDefA) 59#define REG_DEFD (1ULL << kRegDefD) 60#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 61#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 62#define REG_DEF_LIST0 (1ULL << kRegDefList0) 63#define REG_DEF_LIST1 (1ULL << kRegDefList1) 64#define REG_DEF_LR (1ULL << kRegDefLR) 65#define REG_DEF_SP (1ULL << kRegDefSP) 66#define REG_USE0 (1ULL << kRegUse0) 67#define REG_USE1 (1ULL << kRegUse1) 68#define REG_USE2 (1ULL << kRegUse2) 69#define REG_USE3 (1ULL << kRegUse3) 70#define REG_USE4 (1ULL << kRegUse4) 71#define REG_USEA (1ULL << kRegUseA) 72#define REG_USEC (1ULL << kRegUseC) 73#define REG_USED (1ULL << kRegUseD) 74#define REG_USEB (1ULL << kRegUseB) 75#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 76#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 77#define REG_USE_LIST0 (1ULL << kRegUseList0) 78#define REG_USE_LIST1 (1ULL << kRegUseList1) 79#define REG_USE_LR (1ULL << kRegUseLR) 80#define REG_USE_PC (1ULL << kRegUsePC) 81#define REG_USE_SP (1ULL << kRegUseSP) 82#define SETS_CCODES (1ULL << kSetsCCodes) 83#define USES_CCODES (1ULL << kUsesCCodes) 84 85// Common combo register usage patterns. 86#define REG_DEF01 (REG_DEF0 | REG_DEF1) 87#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 88#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 89#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 90#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 91#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 92#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 93#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 94#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 95#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 96#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 97#define REG_USE012 (REG_USE01 | REG_USE2) 98#define REG_USE014 (REG_USE01 | REG_USE4) 99#define REG_USE01 (REG_USE0 | REG_USE1) 100#define REG_USE02 (REG_USE0 | REG_USE2) 101#define REG_USE12 (REG_USE1 | REG_USE2) 102#define REG_USE23 (REG_USE2 | REG_USE3) 103#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 104 105struct BasicBlock; 106struct CallInfo; 107struct CompilationUnit; 108struct InlineMethod; 109struct MIR; 110struct LIR; 111struct RegLocation; 112struct RegisterInfo; 113class DexFileMethodInliner; 114class MIRGraph; 115class Mir2Lir; 116 117typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 118 const MethodReference& target_method, 119 uint32_t method_idx, uintptr_t direct_code, 120 uintptr_t direct_method, InvokeType type); 121 122typedef std::vector<uint8_t> CodeBuffer; 123 124struct UseDefMasks { 125 uint64_t use_mask; // Resource mask for use. 126 uint64_t def_mask; // Resource mask for def. 127}; 128 129struct AssemblyInfo { 130 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 131 uint8_t bytes[16]; // Encoded instruction bytes. 132}; 133 134struct LIR { 135 CodeOffset offset; // Offset of this instruction. 136 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 137 int16_t opcode; 138 LIR* next; 139 LIR* prev; 140 LIR* target; 141 struct { 142 unsigned int alias_info:17; // For Dalvik register disambiguation. 143 bool is_nop:1; // LIR is optimized away. 144 unsigned int size:4; // Note: size of encoded instruction is in bytes. 145 bool use_def_invalid:1; // If true, masks should not be used. 146 unsigned int generation:1; // Used to track visitation state during fixup pass. 147 unsigned int fixup:8; // Fixup kind. 148 } flags; 149 union { 150 UseDefMasks m; // Use & Def masks used during optimization. 151 AssemblyInfo a; // Instruction encoding used during assembly phase. 152 } u; 153 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 154}; 155 156// Target-specific initialization. 157Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 158 ArenaAllocator* const arena); 159Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 160 ArenaAllocator* const arena); 161Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 162 ArenaAllocator* const arena); 163 164// Utility macros to traverse the LIR list. 165#define NEXT_LIR(lir) (lir->next) 166#define PREV_LIR(lir) (lir->prev) 167 168// Defines for alias_info (tracks Dalvik register references). 169#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 170#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 171#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 172#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 173 174// Common resource macros. 175#define ENCODE_CCODE (1ULL << kCCode) 176#define ENCODE_FP_STATUS (1ULL << kFPStatus) 177 178// Abstract memory locations. 179#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 180#define ENCODE_LITERAL (1ULL << kLiteral) 181#define ENCODE_HEAP_REF (1ULL << kHeapRef) 182#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 183 184#define ENCODE_ALL (~0ULL) 185#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 186 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 187 188#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 189#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 190 do { \ 191 low_reg = both_regs & 0xff; \ 192 high_reg = (both_regs >> 8) & 0xff; \ 193 } while (false) 194 195// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 196#define STARTING_DOUBLE_SREG 0x10000 197 198// TODO: replace these macros 199#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 200#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 201#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 202#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 203#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 204 205class Mir2Lir : public Backend { 206 public: 207 /* 208 * Auxiliary information describing the location of data embedded in the Dalvik 209 * byte code stream. 210 */ 211 struct EmbeddedData { 212 CodeOffset offset; // Code offset of data block. 213 const uint16_t* table; // Original dex data. 214 DexOffset vaddr; // Dalvik offset of parent opcode. 215 }; 216 217 struct FillArrayData : EmbeddedData { 218 int32_t size; 219 }; 220 221 struct SwitchTable : EmbeddedData { 222 LIR* anchor; // Reference instruction for relative offsets. 223 LIR** targets; // Array of case targets. 224 }; 225 226 /* Static register use counts */ 227 struct RefCounts { 228 int count; 229 int s_reg; 230 }; 231 232 /* 233 * Data structure tracking the mapping between a Dalvik register (pair) and a 234 * native register (pair). The idea is to reuse the previously loaded value 235 * if possible, otherwise to keep the value in a native register as long as 236 * possible. 237 */ 238 struct RegisterInfo { 239 int reg; // Reg number 240 bool in_use; // Has it been allocated? 241 bool is_temp; // Can allocate as temp? 242 bool pair; // Part of a register pair? 243 int partner; // If pair, other reg of pair. 244 bool live; // Is there an associated SSA name? 245 bool dirty; // If live, is it dirty? 246 int s_reg; // Name of live value. 247 LIR *def_start; // Starting inst in last def sequence. 248 LIR *def_end; // Ending inst in last def sequence. 249 }; 250 251 struct RegisterPool { 252 int num_core_regs; 253 RegisterInfo *core_regs; 254 int next_core_reg; 255 int num_fp_regs; 256 RegisterInfo *FPRegs; 257 int next_fp_reg; 258 }; 259 260 struct PromotionMap { 261 RegLocationType core_location:3; 262 uint8_t core_reg; 263 RegLocationType fp_location:3; 264 uint8_t FpReg; 265 bool first_in_pair; 266 }; 267 268 // 269 // Slow paths. This object is used generate a sequence of code that is executed in the 270 // slow path. For example, resolving a string or class is slow as it will only be executed 271 // once (after that it is resolved and doesn't need to be done again). We want slow paths 272 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 273 // branch over them. 274 // 275 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 276 // the Compile() function that will be called near the end of the code generated by the 277 // method. 278 // 279 // The basic flow for a slow path is: 280 // 281 // CMP reg, #value 282 // BEQ fromfast 283 // cont: 284 // ... 285 // fast path code 286 // ... 287 // more code 288 // ... 289 // RETURN 290 /// 291 // fromfast: 292 // ... 293 // slow path code 294 // ... 295 // B cont 296 // 297 // So you see we need two labels and two branches. The first branch (called fromfast) is 298 // the conditional branch to the slow path code. The second label (called cont) is used 299 // as an unconditional branch target for getting back to the code after the slow path 300 // has completed. 301 // 302 303 class LIRSlowPath { 304 public: 305 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 306 LIR* cont = nullptr) : 307 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 308 } 309 virtual ~LIRSlowPath() {} 310 virtual void Compile() = 0; 311 312 static void* operator new(size_t size, ArenaAllocator* arena) { 313 return arena->Alloc(size, ArenaAllocator::kAllocData); 314 } 315 316 protected: 317 LIR* GenerateTargetLabel(); 318 319 Mir2Lir* const m2l_; 320 const DexOffset current_dex_pc_; 321 LIR* const fromfast_; 322 LIR* const cont_; 323 }; 324 325 virtual ~Mir2Lir() {} 326 327 int32_t s4FromSwitchData(const void* switch_data) { 328 return *reinterpret_cast<const int32_t*>(switch_data); 329 } 330 331 RegisterClass oat_reg_class_by_size(OpSize size) { 332 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 333 size == kSignedByte) ? kCoreReg : kAnyReg; 334 } 335 336 size_t CodeBufferSizeInBytes() { 337 return code_buffer_.size() / sizeof(code_buffer_[0]); 338 } 339 340 bool IsPseudoLirOp(int opcode) { 341 return (opcode < 0); 342 } 343 344 /* 345 * LIR operands are 32-bit integers. Sometimes, (especially for managing 346 * instructions which require PC-relative fixups), we need the operands to carry 347 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 348 * hold that index in the operand array. 349 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 350 * may be worth conditionally-compiling a set of identity functions here. 351 */ 352 uint32_t WrapPointer(void* pointer) { 353 uint32_t res = pointer_storage_.Size(); 354 pointer_storage_.Insert(pointer); 355 return res; 356 } 357 358 void* UnwrapPointer(size_t index) { 359 return pointer_storage_.Get(index); 360 } 361 362 // strdup(), but allocates from the arena. 363 char* ArenaStrdup(const char* str) { 364 size_t len = strlen(str) + 1; 365 char* res = reinterpret_cast<char*>(arena_->Alloc(len, ArenaAllocator::kAllocMisc)); 366 if (res != NULL) { 367 strncpy(res, str, len); 368 } 369 return res; 370 } 371 372 // Shared by all targets - implemented in codegen_util.cc 373 void AppendLIR(LIR* lir); 374 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 375 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 376 377 /** 378 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 379 * to place in a frame. 380 * @return Returns the maximum number of compiler temporaries. 381 */ 382 size_t GetMaxPossibleCompilerTemps() const; 383 384 /** 385 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 386 * @return Returns the size in bytes for space needed for compiler temporary spill region. 387 */ 388 size_t GetNumBytesForCompilerTempSpillRegion(); 389 390 DexOffset GetCurrentDexPc() const { 391 return current_dalvik_offset_; 392 } 393 394 int ComputeFrameSize(); 395 virtual void Materialize(); 396 virtual CompiledMethod* GetCompiledMethod(); 397 void MarkSafepointPC(LIR* inst); 398 bool FastInstance(uint32_t field_idx, bool is_put, int* field_offset, bool* is_volatile); 399 void SetupResourceMasks(LIR* lir); 400 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 401 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 402 void SetupRegMask(uint64_t* mask, int reg); 403 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 404 void DumpPromotionMap(); 405 void CodegenDump(); 406 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 407 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 408 LIR* NewLIR0(int opcode); 409 LIR* NewLIR1(int opcode, int dest); 410 LIR* NewLIR2(int opcode, int dest, int src1); 411 LIR* NewLIR2NoDest(int opcode, int src, int info); 412 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 413 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 414 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 415 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 416 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 417 LIR* AddWordData(LIR* *constant_list_p, int value); 418 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 419 void ProcessSwitchTables(); 420 void DumpSparseSwitchTable(const uint16_t* table); 421 void DumpPackedSwitchTable(const uint16_t* table); 422 void MarkBoundary(DexOffset offset, const char* inst_str); 423 void NopLIR(LIR* lir); 424 void UnlinkLIR(LIR* lir); 425 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 426 bool IsInexpensiveConstant(RegLocation rl_src); 427 ConditionCode FlipComparisonOrder(ConditionCode before); 428 virtual void InstallLiteralPools(); 429 void InstallSwitchTables(); 430 void InstallFillArrayData(); 431 bool VerifyCatchEntries(); 432 void CreateMappingTables(); 433 void CreateNativeGcMap(); 434 int AssignLiteralOffset(CodeOffset offset); 435 int AssignSwitchTablesOffset(CodeOffset offset); 436 int AssignFillArrayDataOffset(CodeOffset offset); 437 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 438 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 439 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 440 441 // Shared by all targets - implemented in local_optimizations.cc 442 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src); 443 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 444 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 445 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 446 447 // Shared by all targets - implemented in ralloc_util.cc 448 int GetSRegHi(int lowSreg); 449 bool oat_live_out(int s_reg); 450 int oatSSASrc(MIR* mir, int num); 451 void SimpleRegAlloc(); 452 void ResetRegPool(); 453 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 454 void DumpRegPool(RegisterInfo* p, int num_regs); 455 void DumpCoreRegPool(); 456 void DumpFpRegPool(); 457 /* Mark a temp register as dead. Does not affect allocation state. */ 458 void Clobber(int reg) { 459 ClobberBody(GetRegInfo(reg)); 460 } 461 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 462 void ClobberSReg(int s_reg); 463 int SRegToPMap(int s_reg); 464 void RecordCorePromotion(int reg, int s_reg); 465 int AllocPreservedCoreReg(int s_reg); 466 void RecordFpPromotion(int reg, int s_reg); 467 int AllocPreservedSingle(int s_reg); 468 int AllocPreservedDouble(int s_reg); 469 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 470 virtual int AllocTempDouble(); 471 int AllocFreeTemp(); 472 int AllocTemp(); 473 int AllocTempFloat(); 474 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 475 RegisterInfo* AllocLive(int s_reg, int reg_class); 476 void FreeTemp(int reg); 477 RegisterInfo* IsLive(int reg); 478 RegisterInfo* IsTemp(int reg); 479 RegisterInfo* IsPromoted(int reg); 480 bool IsDirty(int reg); 481 void LockTemp(int reg); 482 void ResetDef(int reg); 483 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 484 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 485 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 486 RegLocation WideToNarrow(RegLocation rl); 487 void ResetDefLoc(RegLocation rl); 488 virtual void ResetDefLocWide(RegLocation rl); 489 void ResetDefTracking(); 490 void ClobberAllRegs(); 491 void FlushSpecificReg(RegisterInfo* info); 492 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 493 void FlushAllRegs(); 494 bool RegClassMatches(int reg_class, int reg); 495 void MarkLive(int reg, int s_reg); 496 void MarkTemp(int reg); 497 void UnmarkTemp(int reg); 498 void MarkPair(int low_reg, int high_reg); 499 void MarkClean(RegLocation loc); 500 void MarkDirty(RegLocation loc); 501 void MarkInUse(int reg); 502 void CopyRegInfo(int new_reg, int old_reg); 503 bool CheckCorePoolSanity(); 504 RegLocation UpdateLoc(RegLocation loc); 505 virtual RegLocation UpdateLocWide(RegLocation loc); 506 RegLocation UpdateRawLoc(RegLocation loc); 507 508 /** 509 * @brief Used to load register location into a typed temporary or pair of temporaries. 510 * @see EvalLoc 511 * @param loc The register location to load from. 512 * @param reg_class Type of register needed. 513 * @param update Whether the liveness information should be updated. 514 * @return Returns the properly typed temporary in physical register pairs. 515 */ 516 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 517 518 /** 519 * @brief Used to load register location into a typed temporary. 520 * @param loc The register location to load from. 521 * @param reg_class Type of register needed. 522 * @param update Whether the liveness information should be updated. 523 * @return Returns the properly typed temporary in physical register. 524 */ 525 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 526 527 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 528 void DumpCounts(const RefCounts* arr, int size, const char* msg); 529 void DoPromotion(); 530 int VRegOffset(int v_reg); 531 int SRegOffset(int s_reg); 532 RegLocation GetReturnWide(bool is_double); 533 RegLocation GetReturn(bool is_float); 534 RegisterInfo* GetRegInfo(int reg); 535 536 // Shared by all targets - implemented in gen_common.cc. 537 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 538 RegLocation rl_src, RegLocation rl_dest, int lit); 539 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 540 void HandleSuspendLaunchPads(); 541 void HandleIntrinsicLaunchPads(); 542 void HandleThrowLaunchPads(); 543 void HandleSlowPaths(); 544 void GenBarrier(); 545 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 546 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val, 547 ThrowKind kind); 548 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags); 549 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 550 ThrowKind kind); 551 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 552 RegLocation rl_src2, LIR* taken, LIR* fall_through); 553 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 554 LIR* taken, LIR* fall_through); 555 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 556 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 557 RegLocation rl_src); 558 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 559 RegLocation rl_src); 560 void GenFilledNewArray(CallInfo* info); 561 void GenSput(uint32_t field_idx, RegLocation rl_src, 562 bool is_long_or_double, bool is_object); 563 void GenSget(uint32_t field_idx, RegLocation rl_dest, 564 bool is_long_or_double, bool is_object); 565 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size, 566 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 567 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size, 568 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 569 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 570 RegLocation rl_src); 571 572 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 573 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 574 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 575 void GenThrow(RegLocation rl_src); 576 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, 577 RegLocation rl_src); 578 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, 579 RegLocation rl_src); 580 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 581 RegLocation rl_src1, RegLocation rl_src2); 582 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 583 RegLocation rl_src1, RegLocation rl_shift); 584 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 585 RegLocation rl_src, int lit); 586 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 587 RegLocation rl_src1, RegLocation rl_src2); 588 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 589 RegLocation rl_src); 590 void GenSuspendTest(int opt_flags); 591 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 592 593 // This will be overridden by x86 implementation. 594 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 595 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 596 RegLocation rl_src1, RegLocation rl_src2); 597 598 // Shared by all targets - implemented in gen_invoke.cc. 599 int CallHelperSetup(ThreadOffset helper_offset); 600 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc); 601 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 602 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 603 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 604 bool safepoint_pc); 605 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 606 bool safepoint_pc); 607 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 608 RegLocation arg1, bool safepoint_pc); 609 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 610 int arg1, bool safepoint_pc); 611 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 612 bool safepoint_pc); 613 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 614 bool safepoint_pc); 615 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 616 bool safepoint_pc); 617 void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 618 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, int arg0, 619 RegLocation arg2, bool safepoint_pc); 620 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 621 RegLocation arg0, RegLocation arg1, 622 bool safepoint_pc); 623 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 624 bool safepoint_pc); 625 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 626 int arg2, bool safepoint_pc); 627 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 628 RegLocation arg2, bool safepoint_pc); 629 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 630 bool safepoint_pc); 631 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 632 int arg0, RegLocation arg1, RegLocation arg2, 633 bool safepoint_pc); 634 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 635 RegLocation arg0, RegLocation arg1, 636 RegLocation arg2, 637 bool safepoint_pc); 638 void GenInvoke(CallInfo* info); 639 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 640 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 641 NextCallInsn next_call_insn, 642 const MethodReference& target_method, 643 uint32_t vtable_idx, 644 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 645 bool skip_this); 646 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 647 NextCallInsn next_call_insn, 648 const MethodReference& target_method, 649 uint32_t vtable_idx, 650 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 651 bool skip_this); 652 653 /** 654 * @brief Used to determine the register location of destination. 655 * @details This is needed during generation of inline intrinsics because it finds destination of return, 656 * either the physical register or the target of move-result. 657 * @param info Information about the invoke. 658 * @return Returns the destination location. 659 */ 660 RegLocation InlineTarget(CallInfo* info); 661 662 /** 663 * @brief Used to determine the wide register location of destination. 664 * @see InlineTarget 665 * @param info Information about the invoke. 666 * @return Returns the destination location. 667 */ 668 RegLocation InlineTargetWide(CallInfo* info); 669 670 bool GenInlinedCharAt(CallInfo* info); 671 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 672 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 673 bool GenInlinedAbsInt(CallInfo* info); 674 bool GenInlinedAbsLong(CallInfo* info); 675 bool GenInlinedAbsFloat(CallInfo* info); 676 bool GenInlinedAbsDouble(CallInfo* info); 677 bool GenInlinedFloatCvt(CallInfo* info); 678 bool GenInlinedDoubleCvt(CallInfo* info); 679 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 680 bool GenInlinedStringCompareTo(CallInfo* info); 681 bool GenInlinedCurrentThread(CallInfo* info); 682 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 683 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 684 bool is_volatile, bool is_ordered); 685 int LoadArgRegs(CallInfo* info, int call_state, 686 NextCallInsn next_call_insn, 687 const MethodReference& target_method, 688 uint32_t vtable_idx, 689 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 690 bool skip_this); 691 692 // Shared by all targets - implemented in gen_loadstore.cc. 693 RegLocation LoadCurrMethod(); 694 void LoadCurrMethodDirect(int r_tgt); 695 LIR* LoadConstant(int r_dest, int value); 696 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 697 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 698 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 699 void LoadValueDirect(RegLocation rl_src, int r_dest); 700 void LoadValueDirectFixed(RegLocation rl_src, int r_dest); 701 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi); 702 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi); 703 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 704 705 /** 706 * @brief Used to do the final store in the destination as per bytecode semantics. 707 * @param rl_dest The destination dalvik register location. 708 * @param rl_src The source register location. Can be either physical register or dalvik register. 709 */ 710 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 711 712 /** 713 * @brief Used to do the final store in a wide destination as per bytecode semantics. 714 * @see StoreValue 715 * @param rl_dest The destination dalvik register location. 716 * @param rl_src The source register location. Can be either physical register or dalvik register. 717 */ 718 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 719 720 /** 721 * @brief Used to do the final store to a destination as per bytecode semantics. 722 * @see StoreValue 723 * @param rl_dest The destination dalvik register location. 724 * @param rl_src The source register location. It must be kLocPhysReg 725 * 726 * This is used for x86 two operand computations, where we have computed the correct 727 * register value that now needs to be properly registered. This is used to avoid an 728 * extra register copy that would result if StoreValue was called. 729 */ 730 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 731 732 /** 733 * @brief Used to do the final store in a wide destination as per bytecode semantics. 734 * @see StoreValueWide 735 * @param rl_dest The destination dalvik register location. 736 * @param rl_src The source register location. It must be kLocPhysReg 737 * 738 * This is used for x86 two operand computations, where we have computed the correct 739 * register values that now need to be properly registered. This is used to avoid an 740 * extra pair of register copies that would result if StoreValueWide was called. 741 */ 742 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 743 744 // Shared by all targets - implemented in mir_to_lir.cc. 745 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 746 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 747 bool MethodBlockCodeGen(BasicBlock* bb); 748 bool SpecialMIR2LIR(const InlineMethod& special); 749 void MethodMIR2LIR(); 750 751 /* 752 * @brief Load the address of the dex method into the register. 753 * @param dex_method_index The index of the method to be invoked. 754 * @param type How the method will be invoked. 755 * @param register that will contain the code address. 756 * @note register will be passed to TargetReg to get physical register. 757 */ 758 void LoadCodeAddress(int dex_method_index, InvokeType type, 759 SpecialTargetRegister symbolic_reg); 760 761 /* 762 * @brief Load the Method* of a dex method into the register. 763 * @param dex_method_index The index of the method to be invoked. 764 * @param type How the method will be invoked. 765 * @param register that will contain the code address. 766 * @note register will be passed to TargetReg to get physical register. 767 */ 768 virtual void LoadMethodAddress(int dex_method_index, InvokeType type, 769 SpecialTargetRegister symbolic_reg); 770 771 /* 772 * @brief Load the Class* of a Dex Class type into the register. 773 * @param type How the method will be invoked. 774 * @param register that will contain the code address. 775 * @note register will be passed to TargetReg to get physical register. 776 */ 777 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 778 779 // Routines that work for the generic case, but may be overriden by target. 780 /* 781 * @brief Compare memory to immediate, and branch if condition true. 782 * @param cond The condition code that when true will branch to the target. 783 * @param temp_reg A temporary register that can be used if compare to memory is not 784 * supported by the architecture. 785 * @param base_reg The register holding the base address. 786 * @param offset The offset from the base. 787 * @param check_value The immediate to compare to. 788 * @returns The branch instruction that was generated. 789 */ 790 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg, 791 int offset, int check_value, LIR* target); 792 793 // Required for target - codegen helpers. 794 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 795 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 796 virtual int LoadHelper(ThreadOffset offset) = 0; 797 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 798 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 799 int s_reg) = 0; 800 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 801 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 802 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0; 803 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0; 804 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0; 805 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 806 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 807 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 808 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 809 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 810 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0; 811 812 // Required for target - register utilities. 813 virtual bool IsFpReg(int reg) = 0; 814 virtual bool SameRegType(int reg1, int reg2) = 0; 815 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0; 816 virtual int AllocTypedTempPair(bool fp_hint, int reg_class) = 0; 817 virtual int S2d(int low_reg, int high_reg) = 0; 818 virtual int TargetReg(SpecialTargetRegister reg) = 0; 819 virtual int GetArgMappingToPhysicalReg(int arg_num) = 0; 820 virtual RegLocation GetReturnAlt() = 0; 821 virtual RegLocation GetReturnWideAlt() = 0; 822 virtual RegLocation LocCReturn() = 0; 823 virtual RegLocation LocCReturnDouble() = 0; 824 virtual RegLocation LocCReturnFloat() = 0; 825 virtual RegLocation LocCReturnWide() = 0; 826 virtual uint32_t FpRegMask() = 0; 827 virtual uint64_t GetRegMaskCommon(int reg) = 0; 828 virtual void AdjustSpillMask() = 0; 829 virtual void ClobberCallerSave() = 0; 830 virtual void FlushReg(int reg) = 0; 831 virtual void FlushRegWide(int reg1, int reg2) = 0; 832 virtual void FreeCallTemps() = 0; 833 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 834 virtual void LockCallTemps() = 0; 835 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 836 virtual void CompilerInitializeRegAlloc() = 0; 837 838 // Required for target - miscellaneous. 839 virtual void AssembleLIR() = 0; 840 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 841 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 842 virtual const char* GetTargetInstFmt(int opcode) = 0; 843 virtual const char* GetTargetInstName(int opcode) = 0; 844 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 845 virtual uint64_t GetPCUseDefEncoding() = 0; 846 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 847 virtual int GetInsnSize(LIR* lir) = 0; 848 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 849 850 // Required for target - Dalvik-level generators. 851 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 852 RegLocation rl_src1, RegLocation rl_src2) = 0; 853 virtual void GenMulLong(Instruction::Code, 854 RegLocation rl_dest, RegLocation rl_src1, 855 RegLocation rl_src2) = 0; 856 virtual void GenAddLong(Instruction::Code, 857 RegLocation rl_dest, RegLocation rl_src1, 858 RegLocation rl_src2) = 0; 859 virtual void GenAndLong(Instruction::Code, 860 RegLocation rl_dest, RegLocation rl_src1, 861 RegLocation rl_src2) = 0; 862 virtual void GenArithOpDouble(Instruction::Code opcode, 863 RegLocation rl_dest, RegLocation rl_src1, 864 RegLocation rl_src2) = 0; 865 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 866 RegLocation rl_src1, RegLocation rl_src2) = 0; 867 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 868 RegLocation rl_src1, RegLocation rl_src2) = 0; 869 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 870 RegLocation rl_src) = 0; 871 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 872 873 /** 874 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 875 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 876 * that applies on integers. The generated code will write the smallest or largest value 877 * directly into the destination register as specified by the invoke information. 878 * @param info Information about the invoke. 879 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 880 * @return Returns true if successfully generated 881 */ 882 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 883 884 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 885 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 886 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 887 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 888 virtual void GenOrLong(Instruction::Code, 889 RegLocation rl_dest, RegLocation rl_src1, 890 RegLocation rl_src2) = 0; 891 virtual void GenSubLong(Instruction::Code, 892 RegLocation rl_dest, RegLocation rl_src1, 893 RegLocation rl_src2) = 0; 894 virtual void GenXorLong(Instruction::Code, 895 RegLocation rl_dest, RegLocation rl_src1, 896 RegLocation rl_src2) = 0; 897 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, 898 int offset, ThrowKind kind) = 0; 899 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, 900 bool is_div) = 0; 901 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, 902 bool is_div) = 0; 903 /* 904 * @brief Generate an integer div or rem operation by a literal. 905 * @param rl_dest Destination Location. 906 * @param rl_src1 Numerator Location. 907 * @param rl_src2 Divisor Location. 908 * @param is_div 'true' if this is a division, 'false' for a remainder. 909 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 910 */ 911 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 912 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 913 /* 914 * @brief Generate an integer div or rem operation by a literal. 915 * @param rl_dest Destination Location. 916 * @param rl_src Numerator Location. 917 * @param lit Divisor. 918 * @param is_div 'true' if this is a division, 'false' for a remainder. 919 */ 920 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, 921 int lit, bool is_div) = 0; 922 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 923 RegLocation rl_src2) = 0; 924 925 /** 926 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 927 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers. 928 * @param reg_lo The register holding the lower 32-bits. 929 * @param reg_hi The register holding the upper 32-bits. 930 */ 931 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0; 932 933 virtual void GenEntrySequence(RegLocation* ArgLocs, 934 RegLocation rl_method) = 0; 935 virtual void GenExitSequence() = 0; 936 virtual void GenFillArrayData(DexOffset table_offset, 937 RegLocation rl_src) = 0; 938 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, 939 bool is_double) = 0; 940 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 941 942 /** 943 * @brief Lowers the kMirOpSelect MIR into LIR. 944 * @param bb The basic block in which the MIR is from. 945 * @param mir The MIR whose opcode is kMirOpSelect. 946 */ 947 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 948 949 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 950 virtual void GenMoveException(RegLocation rl_dest) = 0; 951 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 952 RegLocation rl_result, int lit, int first_bit, 953 int second_bit) = 0; 954 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 955 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 956 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, 957 RegLocation rl_src) = 0; 958 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, 959 RegLocation rl_src) = 0; 960 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 961 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 962 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 963 RegLocation rl_index, RegLocation rl_src, int scale, 964 bool card_mark) = 0; 965 virtual void GenShiftImmOpLong(Instruction::Code opcode, 966 RegLocation rl_dest, RegLocation rl_src1, 967 RegLocation rl_shift) = 0; 968 969 // Required for target - single operation generators. 970 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 971 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target) = 0; 972 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target) = 0; 973 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 974 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) = 0; 975 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 976 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 977 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0; 978 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0; 979 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0; 980 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 981 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0; 982 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0; 983 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0; 984 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0; 985 986 /** 987 * @brief Used to generate an LIR that does a load from mem to reg. 988 * @param r_dest The destination physical register. 989 * @param r_base The base physical register for memory operand. 990 * @param offset The displacement for memory operand. 991 * @param move_type Specification on the move desired (size, alignment, register kind). 992 * @return Returns the generate move LIR. 993 */ 994 virtual LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) = 0; 995 996 /** 997 * @brief Used to generate an LIR that does a store from reg to mem. 998 * @param r_base The base physical register for memory operand. 999 * @param offset The displacement for memory operand. 1000 * @param r_src The destination physical register. 1001 * @param bytes_to_move The number of bytes to move. 1002 * @param is_aligned Whether the memory location is known to be aligned. 1003 * @return Returns the generate move LIR. 1004 */ 1005 virtual LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) = 0; 1006 1007 /** 1008 * @brief Used for generating a conditional register to register operation. 1009 * @param op The opcode kind. 1010 * @param cc The condition code that when true will perform the opcode. 1011 * @param r_dest The destination physical register. 1012 * @param r_src The source physical register. 1013 * @return Returns the newly created LIR or null in case of creation failure. 1014 */ 1015 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) = 0; 1016 1017 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0; 1018 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) = 0; 1019 virtual LIR* OpTestSuspend(LIR* target) = 0; 1020 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 1021 virtual LIR* OpVldm(int rBase, int count) = 0; 1022 virtual LIR* OpVstm(int rBase, int count) = 0; 1023 virtual void OpLea(int rBase, int reg1, int reg2, int scale, int offset) = 0; 1024 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi) = 0; 1025 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 1026 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1027 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1028 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1029 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1030 1031 // May be optimized by targets. 1032 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1033 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1034 1035 // Temp workaround 1036 void Workaround7250540(RegLocation rl_dest, int value); 1037 1038 protected: 1039 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1040 1041 CompilationUnit* GetCompilationUnit() { 1042 return cu_; 1043 } 1044 /* 1045 * @brief Returns the index of the lowest set bit in 'x'. 1046 * @param x Value to be examined. 1047 * @returns The bit number of the lowest bit set in the value. 1048 */ 1049 int32_t LowestSetBit(uint64_t x); 1050 /* 1051 * @brief Is this value a power of two? 1052 * @param x Value to be examined. 1053 * @returns 'true' if only 1 bit is set in the value. 1054 */ 1055 bool IsPowerOfTwo(uint64_t x); 1056 /* 1057 * @brief Do these SRs overlap? 1058 * @param rl_op1 One RegLocation 1059 * @param rl_op2 The other RegLocation 1060 * @return 'true' if the VR pairs overlap 1061 * 1062 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1063 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1064 * dex, we'll want to make this case illegal. 1065 */ 1066 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1067 1068 /* 1069 * @brief Force a location (in a register) into a temporary register 1070 * @param loc location of result 1071 * @returns update location 1072 */ 1073 RegLocation ForceTemp(RegLocation loc); 1074 1075 /* 1076 * @brief Force a wide location (in registers) into temporary registers 1077 * @param loc location of result 1078 * @returns update location 1079 */ 1080 RegLocation ForceTempWide(RegLocation loc); 1081 1082 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1083 RegLocation rl_dest, RegLocation rl_src); 1084 1085 void AddSlowPath(LIRSlowPath* slowpath); 1086 1087 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1088 bool type_known_abstract, bool use_declaring_class, 1089 bool can_assume_type_is_in_dex_cache, 1090 uint32_t type_idx, RegLocation rl_dest, 1091 RegLocation rl_src); 1092 1093 /** 1094 * @brief Used to insert marker that can be used to associate MIR with LIR. 1095 * @details Only inserts marker if verbosity is enabled. 1096 * @param mir The mir that is currently being generated. 1097 */ 1098 void GenPrintLabel(MIR* mir); 1099 1100 /** 1101 * @brief Used to generate return sequence when there is no frame. 1102 * @details Assumes that the return registers have already been populated. 1103 */ 1104 virtual void GenSpecialExitSequence() = 0; 1105 1106 /** 1107 * @brief Used to generate code for special methods that are known to be 1108 * small enough to work in frameless mode. 1109 * @param bb The basic block of the first MIR. 1110 * @param mir The first MIR of the special method. 1111 * @param special Information about the special method. 1112 * @return Returns whether or not this was handled successfully. Returns false 1113 * if caller should punt to normal MIR2LIR conversion. 1114 */ 1115 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1116 1117 private: 1118 void ClobberBody(RegisterInfo* p); 1119 void ResetDefBody(RegisterInfo* p) { 1120 p->def_start = NULL; 1121 p->def_end = NULL; 1122 } 1123 1124 void SetCurrentDexPc(DexOffset dexpc) { 1125 current_dalvik_offset_ = dexpc; 1126 } 1127 1128 /** 1129 * @brief Used to lock register if argument at in_position was passed that way. 1130 * @details Does nothing if the argument is passed via stack. 1131 * @param in_position The argument number whose register to lock. 1132 * @param wide Whether the argument is wide. 1133 */ 1134 void LockArg(int in_position, bool wide = false); 1135 1136 /** 1137 * @brief Used to load VR argument to a physical register. 1138 * @details The load is only done if the argument is not already in physical register. 1139 * LockArg must have been previously called. 1140 * @param in_position The argument number to load. 1141 * @param wide Whether the argument is 64-bit or not. 1142 * @return Returns the register (or register pair) for the loaded argument. 1143 */ 1144 int LoadArg(int in_position, bool wide = false); 1145 1146 /** 1147 * @brief Used to load a VR argument directly to a specified register location. 1148 * @param in_position The argument number to place in register. 1149 * @param rl_dest The register location where to place argument. 1150 */ 1151 void LoadArgDirect(int in_position, RegLocation rl_dest); 1152 1153 /** 1154 * @brief Used to generate LIR for special getter method. 1155 * @param mir The mir that represents the iget. 1156 * @param special Information about the special getter method. 1157 * @return Returns whether LIR was successfully generated. 1158 */ 1159 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1160 1161 /** 1162 * @brief Used to generate LIR for special setter method. 1163 * @param mir The mir that represents the iput. 1164 * @param special Information about the special setter method. 1165 * @return Returns whether LIR was successfully generated. 1166 */ 1167 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1168 1169 /** 1170 * @brief Used to generate LIR for special return-args method. 1171 * @param mir The mir that represents the return of argument. 1172 * @param special Information about the special return-args method. 1173 * @return Returns whether LIR was successfully generated. 1174 */ 1175 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1176 1177 1178 public: 1179 // TODO: add accessors for these. 1180 LIR* literal_list_; // Constants. 1181 LIR* method_literal_list_; // Method literals requiring patching. 1182 LIR* class_literal_list_; // Class literals requiring patching. 1183 LIR* code_literal_list_; // Code literals requiring patching. 1184 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1185 1186 protected: 1187 CompilationUnit* const cu_; 1188 MIRGraph* const mir_graph_; 1189 GrowableArray<SwitchTable*> switch_tables_; 1190 GrowableArray<FillArrayData*> fill_array_data_; 1191 GrowableArray<LIR*> throw_launchpads_; 1192 GrowableArray<LIR*> suspend_launchpads_; 1193 GrowableArray<LIR*> intrinsic_launchpads_; 1194 GrowableArray<RegisterInfo*> tempreg_info_; 1195 GrowableArray<RegisterInfo*> reginfo_map_; 1196 GrowableArray<void*> pointer_storage_; 1197 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1198 CodeOffset data_offset_; // starting offset of literal pool. 1199 size_t total_size_; // header + code size. 1200 LIR* block_label_list_; 1201 PromotionMap* promotion_map_; 1202 /* 1203 * TODO: The code generation utilities don't have a built-in 1204 * mechanism to propagate the original Dalvik opcode address to the 1205 * associated generated instructions. For the trace compiler, this wasn't 1206 * necessary because the interpreter handled all throws and debugging 1207 * requests. For now we'll handle this by placing the Dalvik offset 1208 * in the CompilationUnit struct before codegen for each instruction. 1209 * The low-level LIR creation utilites will pull it from here. Rework this. 1210 */ 1211 DexOffset current_dalvik_offset_; 1212 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1213 RegisterPool* reg_pool_; 1214 /* 1215 * Sanity checking for the register temp tracking. The same ssa 1216 * name should never be associated with one temp register per 1217 * instruction compilation. 1218 */ 1219 int live_sreg_; 1220 CodeBuffer code_buffer_; 1221 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1222 std::vector<uint8_t> encoded_mapping_table_; 1223 std::vector<uint32_t> core_vmap_table_; 1224 std::vector<uint32_t> fp_vmap_table_; 1225 std::vector<uint8_t> native_gc_map_; 1226 int num_core_spills_; 1227 int num_fp_spills_; 1228 int frame_size_; 1229 unsigned int core_spill_mask_; 1230 unsigned int fp_spill_mask_; 1231 LIR* first_lir_insn_; 1232 LIR* last_lir_insn_; 1233 1234 GrowableArray<LIRSlowPath*> slow_paths_; 1235}; // Class Mir2Lir 1236 1237} // namespace art 1238 1239#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1240