mir_to_lir.h revision 7ea6f79bbddd69d5db86a8656a31aaaf64ae2582
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_location.h" 25#include "dex/reg_storage.h" 26#include "dex/backend.h" 27#include "dex/quick/resource_mask.h" 28#include "driver/compiler_driver.h" 29#include "instruction_set.h" 30#include "leb128.h" 31#include "safe_map.h" 32#include "utils/array_ref.h" 33#include "utils/arena_allocator.h" 34#include "utils/growable_array.h" 35 36namespace art { 37 38/* 39 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 40 * add type safety (see runtime/offsets.h). 41 */ 42typedef uint32_t DexOffset; // Dex offset in code units. 43typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 44typedef uint32_t CodeOffset; // Native code offset in bytes. 45 46// Set to 1 to measure cost of suspend check. 47#define NO_SUSPEND 0 48 49#define IS_BINARY_OP (1ULL << kIsBinaryOp) 50#define IS_BRANCH (1ULL << kIsBranch) 51#define IS_IT (1ULL << kIsIT) 52#define IS_LOAD (1ULL << kMemLoad) 53#define IS_QUAD_OP (1ULL << kIsQuadOp) 54#define IS_QUIN_OP (1ULL << kIsQuinOp) 55#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 56#define IS_STORE (1ULL << kMemStore) 57#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 58#define IS_UNARY_OP (1ULL << kIsUnaryOp) 59#define NEEDS_FIXUP (1ULL << kPCRelFixup) 60#define NO_OPERAND (1ULL << kNoOperand) 61#define REG_DEF0 (1ULL << kRegDef0) 62#define REG_DEF1 (1ULL << kRegDef1) 63#define REG_DEF2 (1ULL << kRegDef2) 64#define REG_DEFA (1ULL << kRegDefA) 65#define REG_DEFD (1ULL << kRegDefD) 66#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 67#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 68#define REG_DEF_LIST0 (1ULL << kRegDefList0) 69#define REG_DEF_LIST1 (1ULL << kRegDefList1) 70#define REG_DEF_LR (1ULL << kRegDefLR) 71#define REG_DEF_SP (1ULL << kRegDefSP) 72#define REG_USE0 (1ULL << kRegUse0) 73#define REG_USE1 (1ULL << kRegUse1) 74#define REG_USE2 (1ULL << kRegUse2) 75#define REG_USE3 (1ULL << kRegUse3) 76#define REG_USE4 (1ULL << kRegUse4) 77#define REG_USEA (1ULL << kRegUseA) 78#define REG_USEC (1ULL << kRegUseC) 79#define REG_USED (1ULL << kRegUseD) 80#define REG_USEB (1ULL << kRegUseB) 81#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 82#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 83#define REG_USE_LIST0 (1ULL << kRegUseList0) 84#define REG_USE_LIST1 (1ULL << kRegUseList1) 85#define REG_USE_LR (1ULL << kRegUseLR) 86#define REG_USE_PC (1ULL << kRegUsePC) 87#define REG_USE_SP (1ULL << kRegUseSP) 88#define SETS_CCODES (1ULL << kSetsCCodes) 89#define USES_CCODES (1ULL << kUsesCCodes) 90#define USE_FP_STACK (1ULL << kUseFpStack) 91#define REG_USE_LO (1ULL << kUseLo) 92#define REG_USE_HI (1ULL << kUseHi) 93#define REG_DEF_LO (1ULL << kDefLo) 94#define REG_DEF_HI (1ULL << kDefHi) 95 96// Common combo register usage patterns. 97#define REG_DEF01 (REG_DEF0 | REG_DEF1) 98#define REG_DEF012 (REG_DEF0 | REG_DEF1 | REG_DEF2) 99#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 100#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 101#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 102#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 103#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 104#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 105#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 106#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 107#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 108#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 109#define REG_USE012 (REG_USE01 | REG_USE2) 110#define REG_USE014 (REG_USE01 | REG_USE4) 111#define REG_USE01 (REG_USE0 | REG_USE1) 112#define REG_USE02 (REG_USE0 | REG_USE2) 113#define REG_USE12 (REG_USE1 | REG_USE2) 114#define REG_USE23 (REG_USE2 | REG_USE3) 115#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 116 117// TODO: #includes need a cleanup 118#ifndef INVALID_SREG 119#define INVALID_SREG (-1) 120#endif 121 122struct BasicBlock; 123struct CallInfo; 124struct CompilationUnit; 125struct InlineMethod; 126struct MIR; 127struct LIR; 128struct RegisterInfo; 129class DexFileMethodInliner; 130class MIRGraph; 131class Mir2Lir; 132 133typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 134 const MethodReference& target_method, 135 uint32_t method_idx, uintptr_t direct_code, 136 uintptr_t direct_method, InvokeType type); 137 138typedef std::vector<uint8_t> CodeBuffer; 139 140struct UseDefMasks { 141 const ResourceMask* use_mask; // Resource mask for use. 142 const ResourceMask* def_mask; // Resource mask for def. 143}; 144 145struct AssemblyInfo { 146 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 147}; 148 149struct LIR { 150 CodeOffset offset; // Offset of this instruction. 151 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 152 int16_t opcode; 153 LIR* next; 154 LIR* prev; 155 LIR* target; 156 struct { 157 unsigned int alias_info:17; // For Dalvik register disambiguation. 158 bool is_nop:1; // LIR is optimized away. 159 unsigned int size:4; // Note: size of encoded instruction is in bytes. 160 bool use_def_invalid:1; // If true, masks should not be used. 161 unsigned int generation:1; // Used to track visitation state during fixup pass. 162 unsigned int fixup:8; // Fixup kind. 163 } flags; 164 union { 165 UseDefMasks m; // Use & Def masks used during optimization. 166 AssemblyInfo a; // Instruction info used during assembly phase. 167 } u; 168 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 169}; 170 171// Target-specific initialization. 172Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 173 ArenaAllocator* const arena); 174Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 175 ArenaAllocator* const arena); 176Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 177 ArenaAllocator* const arena); 178Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 179 ArenaAllocator* const arena); 180 181// Utility macros to traverse the LIR list. 182#define NEXT_LIR(lir) (lir->next) 183#define PREV_LIR(lir) (lir->prev) 184 185// Defines for alias_info (tracks Dalvik register references). 186#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 187#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 188#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 189#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 190 191#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 192#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 193 do { \ 194 low_reg = both_regs & 0xff; \ 195 high_reg = (both_regs >> 8) & 0xff; \ 196 } while (false) 197 198// Mask to denote sreg as the start of a 64-bit item. Must not interfere with low 16 bits. 199#define STARTING_WIDE_SREG 0x10000 200 201// TODO: replace these macros 202#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 203#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 204#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 205#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 206#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 207 208// Size of a frame that we definitely consider large. Anything larger than this should 209// definitely get a stack overflow check. 210static constexpr size_t kLargeFrameSize = 2 * KB; 211 212// Size of a frame that should be small. Anything leaf method smaller than this should run 213// without a stack overflow check. 214// The constant is from experience with frameworks code. 215static constexpr size_t kSmallFrameSize = 1 * KB; 216 217class Mir2Lir : public Backend { 218 public: 219 static constexpr bool kFailOnSizeError = true && kIsDebugBuild; 220 static constexpr bool kReportSizeError = true && kIsDebugBuild; 221 222 // Determine whether a frame is small or large, used in the decision on whether to elide a 223 // stack overflow check on method entry. 224 // 225 // A frame is considered large when it's either above kLargeFrameSize, or a quarter of the 226 // overflow-usable stack space. 227 static bool IsLargeFrame(size_t size, InstructionSet isa) { 228 return size >= kLargeFrameSize || size >= GetStackOverflowReservedBytes(isa) / 4; 229 } 230 231 /* 232 * Auxiliary information describing the location of data embedded in the Dalvik 233 * byte code stream. 234 */ 235 struct EmbeddedData { 236 CodeOffset offset; // Code offset of data block. 237 const uint16_t* table; // Original dex data. 238 DexOffset vaddr; // Dalvik offset of parent opcode. 239 }; 240 241 struct FillArrayData : EmbeddedData { 242 int32_t size; 243 }; 244 245 struct SwitchTable : EmbeddedData { 246 LIR* anchor; // Reference instruction for relative offsets. 247 LIR** targets; // Array of case targets. 248 }; 249 250 /* Static register use counts */ 251 struct RefCounts { 252 int count; 253 int s_reg; 254 }; 255 256 /* 257 * Data structure tracking the mapping detween a Dalvik value (32 or 64 bits) 258 * and native register storage. The primary purpose is to reuse previuosly 259 * loaded values, if possible, and otherwise to keep the value in register 260 * storage as long as possible. 261 * 262 * NOTE 1: wide_value refers to the width of the Dalvik value contained in 263 * this register (or pair). For example, a 64-bit register containing a 32-bit 264 * Dalvik value would have wide_value==false even though the storage container itself 265 * is wide. Similarly, a 32-bit register containing half of a 64-bit Dalvik value 266 * would have wide_value==true (and additionally would have its partner field set to the 267 * other half whose wide_value field would also be true. 268 * 269 * NOTE 2: In the case of a register pair, you can determine which of the partners 270 * is the low half by looking at the s_reg names. The high s_reg will equal low_sreg + 1. 271 * 272 * NOTE 3: In the case of a 64-bit register holding a Dalvik wide value, wide_value 273 * will be true and partner==self. s_reg refers to the low-order word of the Dalvik 274 * value, and the s_reg of the high word is implied (s_reg + 1). 275 * 276 * NOTE 4: The reg and is_temp fields should always be correct. If is_temp is false no 277 * other fields have meaning. [perhaps not true, wide should work for promoted regs?] 278 * If is_temp==true and live==false, no other fields have 279 * meaning. If is_temp==true and live==true, wide_value, partner, dirty, s_reg, def_start 280 * and def_end describe the relationship between the temp register/register pair and 281 * the Dalvik value[s] described by s_reg/s_reg+1. 282 * 283 * The fields used_storage, master_storage and storage_mask are used to track allocation 284 * in light of potential aliasing. For example, consider Arm's d2, which overlaps s4 & s5. 285 * d2's storage mask would be 0x00000003, the two low-order bits denoting 64 bits of 286 * storage use. For s4, it would be 0x0000001; for s5 0x00000002. These values should not 287 * change once initialized. The "used_storage" field tracks current allocation status. 288 * Although each record contains this field, only the field from the largest member of 289 * an aliased group is used. In our case, it would be d2's. The master_storage pointer 290 * of d2, s4 and s5 would all point to d2's used_storage field. Each bit in a used_storage 291 * represents 32 bits of storage. d2's used_storage would be initialized to 0xfffffffc. 292 * Then, if we wanted to determine whether s4 could be allocated, we would "and" 293 * s4's storage_mask with s4's *master_storage. If the result is zero, s4 is free and 294 * to allocate: *master_storage |= storage_mask. To free, *master_storage &= ~storage_mask. 295 * 296 * For an X86 vector register example, storage_mask would be: 297 * 0x00000001 for 32-bit view of xmm1 298 * 0x00000003 for 64-bit view of xmm1 299 * 0x0000000f for 128-bit view of xmm1 300 * 0x000000ff for 256-bit view of ymm1 // future expansion, if needed 301 * 0x0000ffff for 512-bit view of ymm1 // future expansion, if needed 302 * 0xffffffff for 1024-bit view of ymm1 // future expansion, if needed 303 * 304 * The "liveness" of a register is handled in a similar way. The liveness_ storage is 305 * held in the widest member of an aliased set. Note, though, that for a temp register to 306 * reused as live, it must both be marked live and the associated SReg() must match the 307 * desired s_reg. This gets a little complicated when dealing with aliased registers. All 308 * members of an aliased set will share the same liveness flags, but each will individually 309 * maintain s_reg_. In this way we can know that at least one member of an 310 * aliased set is live, but will only fully match on the appropriate alias view. For example, 311 * if Arm d1 is live as a double and has s_reg_ set to Dalvik v8 (which also implies v9 312 * because it is wide), its aliases s2 and s3 will show as live, but will have 313 * s_reg_ == INVALID_SREG. An attempt to later AllocLiveReg() of v9 with a single-precision 314 * view will fail because although s3's liveness bit is set, its s_reg_ will not match v9. 315 * This will cause all members of the aliased set to be clobbered and AllocLiveReg() will 316 * report that v9 is currently not live as a single (which is what we want). 317 * 318 * NOTE: the x86 usage is still somewhat in flux. There are competing notions of how 319 * to treat xmm registers: 320 * 1. Treat them all as 128-bits wide, but denote how much data used via bytes field. 321 * o This more closely matches reality, but means you'd need to be able to get 322 * to the associated RegisterInfo struct to figure out how it's being used. 323 * o This is how 64-bit core registers will be used - always 64 bits, but the 324 * "bytes" field will be 4 for 32-bit usage and 8 for 64-bit usage. 325 * 2. View the xmm registers based on contents. 326 * o A single in a xmm2 register would be k32BitVector, while a double in xmm2 would 327 * be a k64BitVector. 328 * o Note that the two uses above would be considered distinct registers (but with 329 * the aliasing mechanism, we could detect interference). 330 * o This is how aliased double and single float registers will be handled on 331 * Arm and MIPS. 332 * Working plan is, for all targets, to follow mechanism 1 for 64-bit core registers, and 333 * mechanism 2 for aliased float registers and x86 vector registers. 334 */ 335 class RegisterInfo { 336 public: 337 RegisterInfo(RegStorage r, const ResourceMask& mask = kEncodeAll); 338 ~RegisterInfo() {} 339 static void* operator new(size_t size, ArenaAllocator* arena) { 340 return arena->Alloc(size, kArenaAllocRegAlloc); 341 } 342 343 static const uint32_t k32SoloStorageMask = 0x00000001; 344 static const uint32_t kLowSingleStorageMask = 0x00000001; 345 static const uint32_t kHighSingleStorageMask = 0x00000002; 346 static const uint32_t k64SoloStorageMask = 0x00000003; 347 static const uint32_t k128SoloStorageMask = 0x0000000f; 348 static const uint32_t k256SoloStorageMask = 0x000000ff; 349 static const uint32_t k512SoloStorageMask = 0x0000ffff; 350 static const uint32_t k1024SoloStorageMask = 0xffffffff; 351 352 bool InUse() { return (storage_mask_ & master_->used_storage_) != 0; } 353 void MarkInUse() { master_->used_storage_ |= storage_mask_; } 354 void MarkFree() { master_->used_storage_ &= ~storage_mask_; } 355 // No part of the containing storage is live in this view. 356 bool IsDead() { return (master_->liveness_ & storage_mask_) == 0; } 357 // Liveness of this view matches. Note: not equivalent to !IsDead(). 358 bool IsLive() { return (master_->liveness_ & storage_mask_) == storage_mask_; } 359 void MarkLive(int s_reg) { 360 // TODO: Anything useful to assert here? 361 s_reg_ = s_reg; 362 master_->liveness_ |= storage_mask_; 363 } 364 void MarkDead() { 365 if (SReg() != INVALID_SREG) { 366 s_reg_ = INVALID_SREG; 367 master_->liveness_ &= ~storage_mask_; 368 ResetDefBody(); 369 } 370 } 371 RegStorage GetReg() { return reg_; } 372 void SetReg(RegStorage reg) { reg_ = reg; } 373 bool IsTemp() { return is_temp_; } 374 void SetIsTemp(bool val) { is_temp_ = val; } 375 bool IsWide() { return wide_value_; } 376 void SetIsWide(bool val) { 377 wide_value_ = val; 378 if (!val) { 379 // If not wide, reset partner to self. 380 SetPartner(GetReg()); 381 } 382 } 383 bool IsDirty() { return dirty_; } 384 void SetIsDirty(bool val) { dirty_ = val; } 385 RegStorage Partner() { return partner_; } 386 void SetPartner(RegStorage partner) { partner_ = partner; } 387 int SReg() { return (!IsTemp() || IsLive()) ? s_reg_ : INVALID_SREG; } 388 const ResourceMask& DefUseMask() { return def_use_mask_; } 389 void SetDefUseMask(const ResourceMask& def_use_mask) { def_use_mask_ = def_use_mask; } 390 RegisterInfo* Master() { return master_; } 391 void SetMaster(RegisterInfo* master) { 392 master_ = master; 393 if (master != this) { 394 master_->aliased_ = true; 395 DCHECK(alias_chain_ == nullptr); 396 alias_chain_ = master_->alias_chain_; 397 master_->alias_chain_ = this; 398 } 399 } 400 bool IsAliased() { return aliased_; } 401 RegisterInfo* GetAliasChain() { return alias_chain_; } 402 uint32_t StorageMask() { return storage_mask_; } 403 void SetStorageMask(uint32_t storage_mask) { storage_mask_ = storage_mask; } 404 LIR* DefStart() { return def_start_; } 405 void SetDefStart(LIR* def_start) { def_start_ = def_start; } 406 LIR* DefEnd() { return def_end_; } 407 void SetDefEnd(LIR* def_end) { def_end_ = def_end; } 408 void ResetDefBody() { def_start_ = def_end_ = nullptr; } 409 // Find member of aliased set matching storage_used; return nullptr if none. 410 RegisterInfo* FindMatchingView(uint32_t storage_used) { 411 RegisterInfo* res = Master(); 412 for (; res != nullptr; res = res->GetAliasChain()) { 413 if (res->StorageMask() == storage_used) 414 break; 415 } 416 return res; 417 } 418 419 private: 420 RegStorage reg_; 421 bool is_temp_; // Can allocate as temp? 422 bool wide_value_; // Holds a Dalvik wide value (either itself, or part of a pair). 423 bool dirty_; // If live, is it dirty? 424 bool aliased_; // Is this the master for other aliased RegisterInfo's? 425 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register. 426 int s_reg_; // Name of live value. 427 ResourceMask def_use_mask_; // Resources for this element. 428 uint32_t used_storage_; // 1 bit per 4 bytes of storage. Unused by aliases. 429 uint32_t liveness_; // 1 bit per 4 bytes of storage. Unused by aliases. 430 RegisterInfo* master_; // Pointer to controlling storage mask. 431 uint32_t storage_mask_; // Track allocation of sub-units. 432 LIR *def_start_; // Starting inst in last def sequence. 433 LIR *def_end_; // Ending inst in last def sequence. 434 RegisterInfo* alias_chain_; // Chain of aliased registers. 435 }; 436 437 class RegisterPool { 438 public: 439 RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, 440 const ArrayRef<const RegStorage>& core_regs, 441 const ArrayRef<const RegStorage>& core64_regs, 442 const ArrayRef<const RegStorage>& sp_regs, 443 const ArrayRef<const RegStorage>& dp_regs, 444 const ArrayRef<const RegStorage>& reserved_regs, 445 const ArrayRef<const RegStorage>& reserved64_regs, 446 const ArrayRef<const RegStorage>& core_temps, 447 const ArrayRef<const RegStorage>& core64_temps, 448 const ArrayRef<const RegStorage>& sp_temps, 449 const ArrayRef<const RegStorage>& dp_temps); 450 ~RegisterPool() {} 451 static void* operator new(size_t size, ArenaAllocator* arena) { 452 return arena->Alloc(size, kArenaAllocRegAlloc); 453 } 454 void ResetNextTemp() { 455 next_core_reg_ = 0; 456 next_sp_reg_ = 0; 457 next_dp_reg_ = 0; 458 } 459 GrowableArray<RegisterInfo*> core_regs_; 460 int next_core_reg_; 461 GrowableArray<RegisterInfo*> core64_regs_; 462 int next_core64_reg_; 463 GrowableArray<RegisterInfo*> sp_regs_; // Single precision float. 464 int next_sp_reg_; 465 GrowableArray<RegisterInfo*> dp_regs_; // Double precision float. 466 int next_dp_reg_; 467 GrowableArray<RegisterInfo*>* ref_regs_; // Points to core_regs_ or core64_regs_ 468 int* next_ref_reg_; 469 470 private: 471 Mir2Lir* const m2l_; 472 }; 473 474 struct PromotionMap { 475 RegLocationType core_location:3; 476 uint8_t core_reg; 477 RegLocationType fp_location:3; 478 uint8_t fp_reg; 479 bool first_in_pair; 480 }; 481 482 // 483 // Slow paths. This object is used generate a sequence of code that is executed in the 484 // slow path. For example, resolving a string or class is slow as it will only be executed 485 // once (after that it is resolved and doesn't need to be done again). We want slow paths 486 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 487 // branch over them. 488 // 489 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 490 // the Compile() function that will be called near the end of the code generated by the 491 // method. 492 // 493 // The basic flow for a slow path is: 494 // 495 // CMP reg, #value 496 // BEQ fromfast 497 // cont: 498 // ... 499 // fast path code 500 // ... 501 // more code 502 // ... 503 // RETURN 504 /// 505 // fromfast: 506 // ... 507 // slow path code 508 // ... 509 // B cont 510 // 511 // So you see we need two labels and two branches. The first branch (called fromfast) is 512 // the conditional branch to the slow path code. The second label (called cont) is used 513 // as an unconditional branch target for getting back to the code after the slow path 514 // has completed. 515 // 516 517 class LIRSlowPath { 518 public: 519 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 520 LIR* cont = nullptr) : 521 m2l_(m2l), cu_(m2l->cu_), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 522 m2l->StartSlowPath(this); 523 } 524 virtual ~LIRSlowPath() {} 525 virtual void Compile() = 0; 526 527 static void* operator new(size_t size, ArenaAllocator* arena) { 528 return arena->Alloc(size, kArenaAllocData); 529 } 530 531 LIR *GetContinuationLabel() { 532 return cont_; 533 } 534 535 LIR *GetFromFast() { 536 return fromfast_; 537 } 538 539 protected: 540 LIR* GenerateTargetLabel(int opcode = kPseudoTargetLabel); 541 542 Mir2Lir* const m2l_; 543 CompilationUnit* const cu_; 544 const DexOffset current_dex_pc_; 545 LIR* const fromfast_; 546 LIR* const cont_; 547 }; 548 549 // Helper class for changing mem_ref_type_ until the end of current scope. See mem_ref_type_. 550 class ScopedMemRefType { 551 public: 552 ScopedMemRefType(Mir2Lir* m2l, ResourceMask::ResourceBit new_mem_ref_type) 553 : m2l_(m2l), 554 old_mem_ref_type_(m2l->mem_ref_type_) { 555 m2l_->mem_ref_type_ = new_mem_ref_type; 556 } 557 558 ~ScopedMemRefType() { 559 m2l_->mem_ref_type_ = old_mem_ref_type_; 560 } 561 562 private: 563 Mir2Lir* const m2l_; 564 ResourceMask::ResourceBit old_mem_ref_type_; 565 566 DISALLOW_COPY_AND_ASSIGN(ScopedMemRefType); 567 }; 568 569 virtual ~Mir2Lir() {} 570 571 int32_t s4FromSwitchData(const void* switch_data) { 572 return *reinterpret_cast<const int32_t*>(switch_data); 573 } 574 575 /* 576 * TODO: this is a trace JIT vestige, and its use should be reconsidered. At the time 577 * it was introduced, it was intended to be a quick best guess of type without having to 578 * take the time to do type analysis. Currently, though, we have a much better idea of 579 * the types of Dalvik virtual registers. Instead of using this for a best guess, why not 580 * just use our knowledge of type to select the most appropriate register class? 581 */ 582 RegisterClass RegClassBySize(OpSize size) { 583 if (size == kReference) { 584 return kRefReg; 585 } else { 586 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 587 size == kSignedByte) ? kCoreReg : kAnyReg; 588 } 589 } 590 591 size_t CodeBufferSizeInBytes() { 592 return code_buffer_.size() / sizeof(code_buffer_[0]); 593 } 594 595 static bool IsPseudoLirOp(int opcode) { 596 return (opcode < 0); 597 } 598 599 /* 600 * LIR operands are 32-bit integers. Sometimes, (especially for managing 601 * instructions which require PC-relative fixups), we need the operands to carry 602 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 603 * hold that index in the operand array. 604 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 605 * may be worth conditionally-compiling a set of identity functions here. 606 */ 607 uint32_t WrapPointer(void* pointer) { 608 uint32_t res = pointer_storage_.Size(); 609 pointer_storage_.Insert(pointer); 610 return res; 611 } 612 613 void* UnwrapPointer(size_t index) { 614 return pointer_storage_.Get(index); 615 } 616 617 // strdup(), but allocates from the arena. 618 char* ArenaStrdup(const char* str) { 619 size_t len = strlen(str) + 1; 620 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 621 if (res != NULL) { 622 strncpy(res, str, len); 623 } 624 return res; 625 } 626 627 // Shared by all targets - implemented in codegen_util.cc 628 void AppendLIR(LIR* lir); 629 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 630 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 631 632 /** 633 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 634 * to place in a frame. 635 * @return Returns the maximum number of compiler temporaries. 636 */ 637 size_t GetMaxPossibleCompilerTemps() const; 638 639 /** 640 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 641 * @return Returns the size in bytes for space needed for compiler temporary spill region. 642 */ 643 size_t GetNumBytesForCompilerTempSpillRegion(); 644 645 DexOffset GetCurrentDexPc() const { 646 return current_dalvik_offset_; 647 } 648 649 RegisterClass ShortyToRegClass(char shorty_type); 650 RegisterClass LocToRegClass(RegLocation loc); 651 int ComputeFrameSize(); 652 virtual void Materialize(); 653 virtual CompiledMethod* GetCompiledMethod(); 654 void MarkSafepointPC(LIR* inst); 655 void MarkSafepointPCAfter(LIR* after); 656 void SetupResourceMasks(LIR* lir); 657 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 658 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 659 void SetupRegMask(ResourceMask* mask, int reg); 660 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 661 void DumpPromotionMap(); 662 void CodegenDump(); 663 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 664 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 665 LIR* NewLIR0(int opcode); 666 LIR* NewLIR1(int opcode, int dest); 667 LIR* NewLIR2(int opcode, int dest, int src1); 668 LIR* NewLIR2NoDest(int opcode, int src, int info); 669 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 670 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 671 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 672 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 673 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 674 LIR* ScanLiteralPoolMethod(LIR* data_target, const MethodReference& method); 675 LIR* AddWordData(LIR* *constant_list_p, int value); 676 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 677 void ProcessSwitchTables(); 678 void DumpSparseSwitchTable(const uint16_t* table); 679 void DumpPackedSwitchTable(const uint16_t* table); 680 void MarkBoundary(DexOffset offset, const char* inst_str); 681 void NopLIR(LIR* lir); 682 void UnlinkLIR(LIR* lir); 683 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 684 bool IsInexpensiveConstant(RegLocation rl_src); 685 ConditionCode FlipComparisonOrder(ConditionCode before); 686 ConditionCode NegateComparison(ConditionCode before); 687 virtual void InstallLiteralPools(); 688 void InstallSwitchTables(); 689 void InstallFillArrayData(); 690 bool VerifyCatchEntries(); 691 void CreateMappingTables(); 692 void CreateNativeGcMap(); 693 int AssignLiteralOffset(CodeOffset offset); 694 int AssignSwitchTablesOffset(CodeOffset offset); 695 int AssignFillArrayDataOffset(CodeOffset offset); 696 virtual LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 697 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 698 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 699 700 virtual void StartSlowPath(LIRSlowPath* slowpath) {} 701 virtual void BeginInvoke(CallInfo* info) {} 702 virtual void EndInvoke(CallInfo* info) {} 703 704 705 // Handle bookkeeping to convert a wide RegLocation to a narrow RegLocation. No code generated. 706 virtual RegLocation NarrowRegLoc(RegLocation loc); 707 708 // Shared by all targets - implemented in local_optimizations.cc 709 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 710 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 711 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 712 virtual void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 713 714 // Shared by all targets - implemented in ralloc_util.cc 715 int GetSRegHi(int lowSreg); 716 bool LiveOut(int s_reg); 717 void SimpleRegAlloc(); 718 void ResetRegPool(); 719 void CompilerInitPool(RegisterInfo* info, RegStorage* regs, int num); 720 void DumpRegPool(GrowableArray<RegisterInfo*>* regs); 721 void DumpCoreRegPool(); 722 void DumpFpRegPool(); 723 void DumpRegPools(); 724 /* Mark a temp register as dead. Does not affect allocation state. */ 725 void Clobber(RegStorage reg); 726 void ClobberSReg(int s_reg); 727 void ClobberAliases(RegisterInfo* info, uint32_t clobber_mask); 728 int SRegToPMap(int s_reg); 729 void RecordCorePromotion(RegStorage reg, int s_reg); 730 RegStorage AllocPreservedCoreReg(int s_reg); 731 void RecordFpPromotion(RegStorage reg, int s_reg); 732 RegStorage AllocPreservedFpReg(int s_reg); 733 virtual RegStorage AllocPreservedSingle(int s_reg); 734 virtual RegStorage AllocPreservedDouble(int s_reg); 735 RegStorage AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required); 736 virtual RegStorage AllocFreeTemp(); 737 virtual RegStorage AllocTemp(); 738 virtual RegStorage AllocTempWide(); 739 virtual RegStorage AllocTempRef(); 740 virtual RegStorage AllocTempSingle(); 741 virtual RegStorage AllocTempDouble(); 742 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class); 743 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); 744 void FlushReg(RegStorage reg); 745 void FlushRegWide(RegStorage reg); 746 RegStorage AllocLiveReg(int s_reg, int reg_class, bool wide); 747 RegStorage FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg); 748 virtual void FreeTemp(RegStorage reg); 749 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 750 virtual bool IsLive(RegStorage reg); 751 virtual bool IsTemp(RegStorage reg); 752 bool IsPromoted(RegStorage reg); 753 bool IsDirty(RegStorage reg); 754 virtual void LockTemp(RegStorage reg); 755 void ResetDef(RegStorage reg); 756 void NullifyRange(RegStorage reg, int s_reg); 757 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 758 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 759 void ResetDefLoc(RegLocation rl); 760 void ResetDefLocWide(RegLocation rl); 761 void ResetDefTracking(); 762 void ClobberAllTemps(); 763 void FlushSpecificReg(RegisterInfo* info); 764 void FlushAllRegs(); 765 bool RegClassMatches(int reg_class, RegStorage reg); 766 void MarkLive(RegLocation loc); 767 void MarkTemp(RegStorage reg); 768 void UnmarkTemp(RegStorage reg); 769 void MarkWide(RegStorage reg); 770 void MarkNarrow(RegStorage reg); 771 void MarkClean(RegLocation loc); 772 void MarkDirty(RegLocation loc); 773 void MarkInUse(RegStorage reg); 774 bool CheckCorePoolSanity(); 775 virtual RegLocation UpdateLoc(RegLocation loc); 776 virtual RegLocation UpdateLocWide(RegLocation loc); 777 RegLocation UpdateRawLoc(RegLocation loc); 778 779 /** 780 * @brief Used to prepare a register location to receive a wide value. 781 * @see EvalLoc 782 * @param loc the location where the value will be stored. 783 * @param reg_class Type of register needed. 784 * @param update Whether the liveness information should be updated. 785 * @return Returns the properly typed temporary in physical register pairs. 786 */ 787 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 788 789 /** 790 * @brief Used to prepare a register location to receive a value. 791 * @param loc the location where the value will be stored. 792 * @param reg_class Type of register needed. 793 * @param update Whether the liveness information should be updated. 794 * @return Returns the properly typed temporary in physical register. 795 */ 796 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 797 798 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 799 void DumpCounts(const RefCounts* arr, int size, const char* msg); 800 void DoPromotion(); 801 int VRegOffset(int v_reg); 802 int SRegOffset(int s_reg); 803 RegLocation GetReturnWide(RegisterClass reg_class); 804 RegLocation GetReturn(RegisterClass reg_class); 805 RegisterInfo* GetRegInfo(RegStorage reg); 806 807 // Shared by all targets - implemented in gen_common.cc. 808 void AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume = nullptr); 809 virtual bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 810 RegLocation rl_src, RegLocation rl_dest, int lit); 811 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 812 virtual void HandleSlowPaths(); 813 void GenBarrier(); 814 void GenDivZeroException(); 815 // c_code holds condition code that's generated from testing divisor against 0. 816 void GenDivZeroCheck(ConditionCode c_code); 817 // reg holds divisor. 818 void GenDivZeroCheck(RegStorage reg); 819 void GenArrayBoundsCheck(RegStorage index, RegStorage length); 820 void GenArrayBoundsCheck(int32_t index, RegStorage length); 821 LIR* GenNullCheck(RegStorage reg); 822 void MarkPossibleNullPointerException(int opt_flags); 823 void MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after); 824 void MarkPossibleStackOverflowException(); 825 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 826 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 827 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 828 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 829 virtual void GenImplicitNullCheck(RegStorage reg, int opt_flags); 830 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 831 RegLocation rl_src2, LIR* taken, LIR* fall_through); 832 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 833 LIR* taken, LIR* fall_through); 834 virtual void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 835 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 836 RegLocation rl_src); 837 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 838 RegLocation rl_src); 839 void GenFilledNewArray(CallInfo* info); 840 void GenSput(MIR* mir, RegLocation rl_src, 841 bool is_long_or_double, bool is_object); 842 void GenSget(MIR* mir, RegLocation rl_dest, 843 bool is_long_or_double, bool is_object); 844 void GenIGet(MIR* mir, int opt_flags, OpSize size, 845 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 846 void GenIPut(MIR* mir, int opt_flags, OpSize size, 847 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 848 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 849 RegLocation rl_src); 850 851 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 852 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 853 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 854 void GenThrow(RegLocation rl_src); 855 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 856 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 857 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 858 RegLocation rl_src1, RegLocation rl_src2); 859 virtual void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 860 RegLocation rl_src1, RegLocation rl_shift); 861 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 862 RegLocation rl_src, int lit); 863 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 864 RegLocation rl_src1, RegLocation rl_src2); 865 template <size_t pointer_size> 866 void GenConversionCall(ThreadOffset<pointer_size> func_offset, RegLocation rl_dest, 867 RegLocation rl_src); 868 virtual void GenSuspendTest(int opt_flags); 869 virtual void GenSuspendTestAndBranch(int opt_flags, LIR* target); 870 871 // This will be overridden by x86 implementation. 872 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 873 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 874 RegLocation rl_src1, RegLocation rl_src2); 875 876 // Shared by all targets - implemented in gen_invoke.cc. 877 template <size_t pointer_size> 878 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<pointer_size> helper_offset, bool safepoint_pc, 879 bool use_link = true); 880 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 881 RegStorage CallHelperSetup(ThreadOffset<8> helper_offset); 882 template <size_t pointer_size> 883 void CallRuntimeHelper(ThreadOffset<pointer_size> helper_offset, bool safepoint_pc); 884 template <size_t pointer_size> 885 void CallRuntimeHelperImm(ThreadOffset<pointer_size> helper_offset, int arg0, bool safepoint_pc); 886 template <size_t pointer_size> 887 void CallRuntimeHelperReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, bool safepoint_pc); 888 template <size_t pointer_size> 889 void CallRuntimeHelperRegLocation(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 890 bool safepoint_pc); 891 template <size_t pointer_size> 892 void CallRuntimeHelperImmImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg1, 893 bool safepoint_pc); 894 template <size_t pointer_size> 895 void CallRuntimeHelperImmRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 896 RegLocation arg1, bool safepoint_pc); 897 template <size_t pointer_size> 898 void CallRuntimeHelperRegLocationImm(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 899 int arg1, bool safepoint_pc); 900 template <size_t pointer_size> 901 void CallRuntimeHelperImmReg(ThreadOffset<pointer_size> helper_offset, int arg0, RegStorage arg1, 902 bool safepoint_pc); 903 template <size_t pointer_size> 904 void CallRuntimeHelperRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, int arg1, 905 bool safepoint_pc); 906 template <size_t pointer_size> 907 void CallRuntimeHelperImmMethod(ThreadOffset<pointer_size> helper_offset, int arg0, 908 bool safepoint_pc); 909 template <size_t pointer_size> 910 void CallRuntimeHelperRegMethod(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 911 bool safepoint_pc); 912 template <size_t pointer_size> 913 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<pointer_size> helper_offset, 914 RegStorage arg0, RegLocation arg2, bool safepoint_pc); 915 template <size_t pointer_size> 916 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 917 RegLocation arg0, RegLocation arg1, 918 bool safepoint_pc); 919 template <size_t pointer_size> 920 void CallRuntimeHelperRegReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 921 RegStorage arg1, bool safepoint_pc); 922 template <size_t pointer_size> 923 void CallRuntimeHelperRegRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 924 RegStorage arg1, int arg2, bool safepoint_pc); 925 template <size_t pointer_size> 926 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 927 RegLocation arg2, bool safepoint_pc); 928 template <size_t pointer_size> 929 void CallRuntimeHelperImmMethodImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg2, 930 bool safepoint_pc); 931 template <size_t pointer_size> 932 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 933 int arg0, RegLocation arg1, RegLocation arg2, 934 bool safepoint_pc); 935 template <size_t pointer_size> 936 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 937 RegLocation arg0, RegLocation arg1, 938 RegLocation arg2, 939 bool safepoint_pc); 940 void GenInvoke(CallInfo* info); 941 void GenInvokeNoInline(CallInfo* info); 942 virtual void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 943 virtual int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 944 NextCallInsn next_call_insn, 945 const MethodReference& target_method, 946 uint32_t vtable_idx, 947 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 948 bool skip_this); 949 virtual int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 950 NextCallInsn next_call_insn, 951 const MethodReference& target_method, 952 uint32_t vtable_idx, 953 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 954 bool skip_this); 955 956 /** 957 * @brief Used to determine the register location of destination. 958 * @details This is needed during generation of inline intrinsics because it finds destination 959 * of return, 960 * either the physical register or the target of move-result. 961 * @param info Information about the invoke. 962 * @return Returns the destination location. 963 */ 964 RegLocation InlineTarget(CallInfo* info); 965 966 /** 967 * @brief Used to determine the wide register location of destination. 968 * @see InlineTarget 969 * @param info Information about the invoke. 970 * @return Returns the destination location. 971 */ 972 RegLocation InlineTargetWide(CallInfo* info); 973 974 bool GenInlinedGet(CallInfo* info); 975 bool GenInlinedCharAt(CallInfo* info); 976 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 977 virtual bool GenInlinedReverseBits(CallInfo* info, OpSize size); 978 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 979 bool GenInlinedAbsInt(CallInfo* info); 980 virtual bool GenInlinedAbsLong(CallInfo* info); 981 virtual bool GenInlinedAbsFloat(CallInfo* info); 982 virtual bool GenInlinedAbsDouble(CallInfo* info); 983 bool GenInlinedFloatCvt(CallInfo* info); 984 bool GenInlinedDoubleCvt(CallInfo* info); 985 virtual bool GenInlinedArrayCopyCharArray(CallInfo* info); 986 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 987 bool GenInlinedStringCompareTo(CallInfo* info); 988 bool GenInlinedCurrentThread(CallInfo* info); 989 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 990 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 991 bool is_volatile, bool is_ordered); 992 virtual int LoadArgRegs(CallInfo* info, int call_state, 993 NextCallInsn next_call_insn, 994 const MethodReference& target_method, 995 uint32_t vtable_idx, 996 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 997 bool skip_this); 998 999 // Shared by all targets - implemented in gen_loadstore.cc. 1000 RegLocation LoadCurrMethod(); 1001 void LoadCurrMethodDirect(RegStorage r_tgt); 1002 virtual LIR* LoadConstant(RegStorage r_dest, int value); 1003 // Natural word size. 1004 virtual LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 1005 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile); 1006 } 1007 // Load 32 bits, regardless of target. 1008 virtual LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { 1009 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile); 1010 } 1011 // Load a reference at base + displacement and decompress into register. 1012 virtual LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, 1013 VolatileKind is_volatile) { 1014 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile); 1015 } 1016 // Load a reference at base + index and decompress into register. 1017 virtual LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 1018 int scale) { 1019 return LoadBaseIndexed(r_base, r_index, r_dest, scale, kReference); 1020 } 1021 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 1022 virtual RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 1023 // Same as above, but derive the target register class from the location record. 1024 virtual RegLocation LoadValue(RegLocation rl_src); 1025 // Load Dalvik value with 64-bit memory storage. 1026 virtual RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 1027 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 1028 virtual void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 1029 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 1030 virtual void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 1031 // Load Dalvik value with 64-bit memory storage. 1032 virtual void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 1033 // Load Dalvik value with 64-bit memory storage. 1034 virtual void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 1035 // Store an item of natural word size. 1036 virtual LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { 1037 return StoreBaseDisp(r_base, displacement, r_src, kWord, kNotVolatile); 1038 } 1039 // Store an uncompressed reference into a compressed 32-bit container. 1040 virtual LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, 1041 VolatileKind is_volatile) { 1042 return StoreBaseDisp(r_base, displacement, r_src, kReference, is_volatile); 1043 } 1044 // Store an uncompressed reference into a compressed 32-bit container by index. 1045 virtual LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 1046 int scale) { 1047 return StoreBaseIndexed(r_base, r_index, r_src, scale, kReference); 1048 } 1049 // Store 32 bits, regardless of target. 1050 virtual LIR* Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) { 1051 return StoreBaseDisp(r_base, displacement, r_src, k32, kNotVolatile); 1052 } 1053 1054 /** 1055 * @brief Used to do the final store in the destination as per bytecode semantics. 1056 * @param rl_dest The destination dalvik register location. 1057 * @param rl_src The source register location. Can be either physical register or dalvik register. 1058 */ 1059 virtual void StoreValue(RegLocation rl_dest, RegLocation rl_src); 1060 1061 /** 1062 * @brief Used to do the final store in a wide destination as per bytecode semantics. 1063 * @see StoreValue 1064 * @param rl_dest The destination dalvik register location. 1065 * @param rl_src The source register location. Can be either physical register or dalvik 1066 * register. 1067 */ 1068 virtual void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 1069 1070 /** 1071 * @brief Used to do the final store to a destination as per bytecode semantics. 1072 * @see StoreValue 1073 * @param rl_dest The destination dalvik register location. 1074 * @param rl_src The source register location. It must be kLocPhysReg 1075 * 1076 * This is used for x86 two operand computations, where we have computed the correct 1077 * register value that now needs to be properly registered. This is used to avoid an 1078 * extra register copy that would result if StoreValue was called. 1079 */ 1080 virtual void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 1081 1082 /** 1083 * @brief Used to do the final store in a wide destination as per bytecode semantics. 1084 * @see StoreValueWide 1085 * @param rl_dest The destination dalvik register location. 1086 * @param rl_src The source register location. It must be kLocPhysReg 1087 * 1088 * This is used for x86 two operand computations, where we have computed the correct 1089 * register values that now need to be properly registered. This is used to avoid an 1090 * extra pair of register copies that would result if StoreValueWide was called. 1091 */ 1092 virtual void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 1093 1094 // Shared by all targets - implemented in mir_to_lir.cc. 1095 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 1096 virtual void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1097 bool MethodBlockCodeGen(BasicBlock* bb); 1098 bool SpecialMIR2LIR(const InlineMethod& special); 1099 virtual void MethodMIR2LIR(); 1100 // Update LIR for verbose listings. 1101 void UpdateLIROffsets(); 1102 1103 /* 1104 * @brief Load the address of the dex method into the register. 1105 * @param target_method The MethodReference of the method to be invoked. 1106 * @param type How the method will be invoked. 1107 * @param register that will contain the code address. 1108 * @note register will be passed to TargetReg to get physical register. 1109 */ 1110 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 1111 SpecialTargetRegister symbolic_reg); 1112 1113 /* 1114 * @brief Load the Method* of a dex method into the register. 1115 * @param target_method The MethodReference of the method to be invoked. 1116 * @param type How the method will be invoked. 1117 * @param register that will contain the code address. 1118 * @note register will be passed to TargetReg to get physical register. 1119 */ 1120 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 1121 SpecialTargetRegister symbolic_reg); 1122 1123 /* 1124 * @brief Load the Class* of a Dex Class type into the register. 1125 * @param type How the method will be invoked. 1126 * @param register that will contain the code address. 1127 * @note register will be passed to TargetReg to get physical register. 1128 */ 1129 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 1130 1131 // Routines that work for the generic case, but may be overriden by target. 1132 /* 1133 * @brief Compare memory to immediate, and branch if condition true. 1134 * @param cond The condition code that when true will branch to the target. 1135 * @param temp_reg A temporary register that can be used if compare to memory is not 1136 * supported by the architecture. 1137 * @param base_reg The register holding the base address. 1138 * @param offset The offset from the base. 1139 * @param check_value The immediate to compare to. 1140 * @param target branch target (or nullptr) 1141 * @param compare output for getting LIR for comparison (or nullptr) 1142 * @returns The branch instruction that was generated. 1143 */ 1144 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 1145 int offset, int check_value, LIR* target, LIR** compare); 1146 1147 // Required for target - codegen helpers. 1148 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1149 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1150 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1151 virtual LIR* CheckSuspendUsingLoad() = 0; 1152 1153 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 1154 virtual RegStorage LoadHelper(ThreadOffset<8> offset) = 0; 1155 1156 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 1157 OpSize size, VolatileKind is_volatile) = 0; 1158 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 1159 int scale, OpSize size) = 0; 1160 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1161 int displacement, RegStorage r_dest, OpSize size) = 0; 1162 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 1163 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 1164 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 1165 OpSize size, VolatileKind is_volatile) = 0; 1166 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 1167 int scale, OpSize size) = 0; 1168 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1169 int displacement, RegStorage r_src, OpSize size) = 0; 1170 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 1171 1172 // Required for target - register utilities. 1173 1174 bool IsSameReg(RegStorage reg1, RegStorage reg2) { 1175 RegisterInfo* info1 = GetRegInfo(reg1); 1176 RegisterInfo* info2 = GetRegInfo(reg2); 1177 return (info1->Master() == info2->Master() && 1178 (info1->StorageMask() & info2->StorageMask()) != 0); 1179 } 1180 1181 /** 1182 * @brief Portable way of getting special registers from the backend. 1183 * @param reg Enumeration describing the purpose of the register. 1184 * @return Return the #RegStorage corresponding to the given purpose @p reg. 1185 * @note This function is currently allowed to return any suitable view of the registers 1186 * (e.g. this could be 64-bit solo or 32-bit solo for 64-bit backends). 1187 */ 1188 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 1189 1190 /** 1191 * @brief Portable way of getting special registers from the backend. 1192 * @param reg Enumeration describing the purpose of the register. 1193 * @param wide_kind What kind of view of the special register is required. 1194 * @return Return the #RegStorage corresponding to the given purpose @p reg. 1195 * 1196 * @note For 32b system, wide (kWide) views only make sense for the argument registers and the 1197 * return. In that case, this function should return a pair where the first component of 1198 * the result will be the indicated special register. 1199 */ 1200 virtual RegStorage TargetReg(SpecialTargetRegister reg, WideKind wide_kind) { 1201 if (wide_kind == kWide) { 1202 DCHECK((kArg0 <= reg && reg < kArg7) || (kFArg0 <= reg && reg < kFArg7) || (kRet0 == reg)); 1203 COMPILE_ASSERT((kArg1 == kArg0 + 1) && (kArg2 == kArg1 + 1) && (kArg3 == kArg2 + 1) && 1204 (kArg4 == kArg3 + 1) && (kArg5 == kArg4 + 1) && (kArg6 == kArg5 + 1) && 1205 (kArg7 == kArg6 + 1), kargs_range_unexpected); 1206 COMPILE_ASSERT((kFArg1 == kFArg0 + 1) && (kFArg2 == kFArg1 + 1) && (kFArg3 == kFArg2 + 1) && 1207 (kFArg4 == kFArg3 + 1) && (kFArg5 == kFArg4 + 1) && (kFArg6 == kFArg5 + 1) && 1208 (kFArg7 == kFArg6 + 1), kfargs_range_unexpected); 1209 COMPILE_ASSERT(kRet1 == kRet0 + 1, kret_range_unexpected); 1210 return RegStorage::MakeRegPair(TargetReg(reg), 1211 TargetReg(static_cast<SpecialTargetRegister>(reg + 1))); 1212 } else { 1213 return TargetReg(reg); 1214 } 1215 } 1216 1217 /** 1218 * @brief Portable way of getting a special register for storing a pointer. 1219 * @see TargetReg() 1220 */ 1221 virtual RegStorage TargetPtrReg(SpecialTargetRegister reg) { 1222 return TargetReg(reg); 1223 } 1224 1225 // Get a reg storage corresponding to the wide & ref flags of the reg location. 1226 virtual RegStorage TargetReg(SpecialTargetRegister reg, RegLocation loc) { 1227 if (loc.ref) { 1228 return TargetReg(reg, kRef); 1229 } else { 1230 return TargetReg(reg, loc.wide ? kWide : kNotWide); 1231 } 1232 } 1233 1234 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 1235 virtual RegLocation GetReturnAlt() = 0; 1236 virtual RegLocation GetReturnWideAlt() = 0; 1237 virtual RegLocation LocCReturn() = 0; 1238 virtual RegLocation LocCReturnRef() = 0; 1239 virtual RegLocation LocCReturnDouble() = 0; 1240 virtual RegLocation LocCReturnFloat() = 0; 1241 virtual RegLocation LocCReturnWide() = 0; 1242 virtual ResourceMask GetRegMaskCommon(const RegStorage& reg) const = 0; 1243 virtual void AdjustSpillMask() = 0; 1244 virtual void ClobberCallerSave() = 0; 1245 virtual void FreeCallTemps() = 0; 1246 virtual void LockCallTemps() = 0; 1247 virtual void CompilerInitializeRegAlloc() = 0; 1248 1249 // Required for target - miscellaneous. 1250 virtual void AssembleLIR() = 0; 1251 virtual void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) = 0; 1252 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 1253 ResourceMask* use_mask, ResourceMask* def_mask) = 0; 1254 virtual const char* GetTargetInstFmt(int opcode) = 0; 1255 virtual const char* GetTargetInstName(int opcode) = 0; 1256 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 1257 1258 // Note: This may return kEncodeNone on architectures that do not expose a PC. The caller must 1259 // take care of this. 1260 virtual ResourceMask GetPCUseDefEncoding() const = 0; 1261 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 1262 virtual size_t GetInsnSize(LIR* lir) = 0; 1263 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 1264 1265 // Get the register class for load/store of a field. 1266 virtual RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) = 0; 1267 1268 // Required for target - Dalvik-level generators. 1269 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1270 RegLocation rl_src1, RegLocation rl_src2) = 0; 1271 virtual void GenMulLong(Instruction::Code, 1272 RegLocation rl_dest, RegLocation rl_src1, 1273 RegLocation rl_src2) = 0; 1274 virtual void GenAddLong(Instruction::Code, 1275 RegLocation rl_dest, RegLocation rl_src1, 1276 RegLocation rl_src2) = 0; 1277 virtual void GenAndLong(Instruction::Code, 1278 RegLocation rl_dest, RegLocation rl_src1, 1279 RegLocation rl_src2) = 0; 1280 virtual void GenArithOpDouble(Instruction::Code opcode, 1281 RegLocation rl_dest, RegLocation rl_src1, 1282 RegLocation rl_src2) = 0; 1283 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 1284 RegLocation rl_src1, RegLocation rl_src2) = 0; 1285 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 1286 RegLocation rl_src1, RegLocation rl_src2) = 0; 1287 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 1288 RegLocation rl_src) = 0; 1289 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 1290 1291 /** 1292 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 1293 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 1294 * that applies on integers. The generated code will write the smallest or largest value 1295 * directly into the destination register as specified by the invoke information. 1296 * @param info Information about the invoke. 1297 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 1298 * @param is_long If true the value value is Long. Otherwise the value is Int. 1299 * @return Returns true if successfully generated 1300 */ 1301 virtual bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) = 0; 1302 virtual bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double); 1303 1304 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 1305 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 1306 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 1307 virtual void GenNotLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1308 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1309 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1310 RegLocation rl_src2) = 0; 1311 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1312 RegLocation rl_src2) = 0; 1313 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1314 RegLocation rl_src2) = 0; 1315 virtual void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1316 RegLocation rl_src2, bool is_div) = 0; 1317 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 1318 bool is_div) = 0; 1319 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 1320 bool is_div) = 0; 1321 /* 1322 * @brief Generate an integer div or rem operation by a literal. 1323 * @param rl_dest Destination Location. 1324 * @param rl_src1 Numerator Location. 1325 * @param rl_src2 Divisor Location. 1326 * @param is_div 'true' if this is a division, 'false' for a remainder. 1327 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 1328 */ 1329 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 1330 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 1331 /* 1332 * @brief Generate an integer div or rem operation by a literal. 1333 * @param rl_dest Destination Location. 1334 * @param rl_src Numerator Location. 1335 * @param lit Divisor. 1336 * @param is_div 'true' if this is a division, 'false' for a remainder. 1337 */ 1338 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 1339 bool is_div) = 0; 1340 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 1341 1342 /** 1343 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 1344 * @details This is used for generating DivideByZero checks when divisor is held in two 1345 * separate registers. 1346 * @param reg The register holding the pair of 32-bit values. 1347 */ 1348 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 1349 1350 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 1351 virtual void GenExitSequence() = 0; 1352 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 1353 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 1354 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 1355 1356 /* 1357 * @brief Handle Machine Specific MIR Extended opcodes. 1358 * @param bb The basic block in which the MIR is from. 1359 * @param mir The MIR whose opcode is not standard extended MIR. 1360 * @note Base class implementation will abort for unknown opcodes. 1361 */ 1362 virtual void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1363 1364 /** 1365 * @brief Lowers the kMirOpSelect MIR into LIR. 1366 * @param bb The basic block in which the MIR is from. 1367 * @param mir The MIR whose opcode is kMirOpSelect. 1368 */ 1369 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 1370 1371 /** 1372 * @brief Generates code to select one of the given constants depending on the given opcode. 1373 * @note Will neither call EvalLoc nor StoreValue for rl_dest. 1374 */ 1375 virtual void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 1376 int32_t true_val, int32_t false_val, RegStorage rs_dest, 1377 int dest_reg_class) = 0; 1378 1379 /** 1380 * @brief Used to generate a memory barrier in an architecture specific way. 1381 * @details The last generated LIR will be considered for use as barrier. Namely, 1382 * if the last LIR can be updated in a way where it will serve the semantics of 1383 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 1384 * that can keep the semantics. 1385 * @param barrier_kind The kind of memory barrier to generate. 1386 * @return whether a new instruction was generated. 1387 */ 1388 virtual bool GenMemBarrier(MemBarrierKind barrier_kind) = 0; 1389 1390 virtual void GenMoveException(RegLocation rl_dest) = 0; 1391 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 1392 int first_bit, int second_bit) = 0; 1393 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 1394 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 1395 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1396 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1397 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1398 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1399 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1400 RegLocation rl_index, RegLocation rl_src, int scale, 1401 bool card_mark) = 0; 1402 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1403 RegLocation rl_src1, RegLocation rl_shift) = 0; 1404 1405 // Required for target - single operation generators. 1406 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1407 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1408 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1409 LIR* target) = 0; 1410 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1411 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1412 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1413 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1414 virtual void OpEndIT(LIR* it) = 0; 1415 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1416 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1417 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1418 virtual void OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1419 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1420 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1421 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1422 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1423 1424 /** 1425 * @brief Used to generate an LIR that does a load from mem to reg. 1426 * @param r_dest The destination physical register. 1427 * @param r_base The base physical register for memory operand. 1428 * @param offset The displacement for memory operand. 1429 * @param move_type Specification on the move desired (size, alignment, register kind). 1430 * @return Returns the generate move LIR. 1431 */ 1432 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1433 MoveType move_type) = 0; 1434 1435 /** 1436 * @brief Used to generate an LIR that does a store from reg to mem. 1437 * @param r_base The base physical register for memory operand. 1438 * @param offset The displacement for memory operand. 1439 * @param r_src The destination physical register. 1440 * @param bytes_to_move The number of bytes to move. 1441 * @param is_aligned Whether the memory location is known to be aligned. 1442 * @return Returns the generate move LIR. 1443 */ 1444 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1445 MoveType move_type) = 0; 1446 1447 /** 1448 * @brief Used for generating a conditional register to register operation. 1449 * @param op The opcode kind. 1450 * @param cc The condition code that when true will perform the opcode. 1451 * @param r_dest The destination physical register. 1452 * @param r_src The source physical register. 1453 * @return Returns the newly created LIR or null in case of creation failure. 1454 */ 1455 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1456 1457 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1458 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1459 RegStorage r_src2) = 0; 1460 virtual LIR* OpTestSuspend(LIR* target) = 0; 1461 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1462 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) = 0; 1463 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1464 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1465 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1466 int offset) = 0; 1467 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1468 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1469 virtual void OpTlsCmp(ThreadOffset<8> offset, int val) = 0; 1470 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1471 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1472 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1473 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1474 1475 // May be optimized by targets. 1476 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1477 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1478 1479 // Temp workaround 1480 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1481 1482 protected: 1483 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1484 1485 CompilationUnit* GetCompilationUnit() { 1486 return cu_; 1487 } 1488 /* 1489 * @brief Returns the index of the lowest set bit in 'x'. 1490 * @param x Value to be examined. 1491 * @returns The bit number of the lowest bit set in the value. 1492 */ 1493 int32_t LowestSetBit(uint64_t x); 1494 /* 1495 * @brief Is this value a power of two? 1496 * @param x Value to be examined. 1497 * @returns 'true' if only 1 bit is set in the value. 1498 */ 1499 bool IsPowerOfTwo(uint64_t x); 1500 /* 1501 * @brief Do these SRs overlap? 1502 * @param rl_op1 One RegLocation 1503 * @param rl_op2 The other RegLocation 1504 * @return 'true' if the VR pairs overlap 1505 * 1506 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1507 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1508 * dex, we'll want to make this case illegal. 1509 */ 1510 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1511 1512 /* 1513 * @brief Force a location (in a register) into a temporary register 1514 * @param loc location of result 1515 * @returns update location 1516 */ 1517 virtual RegLocation ForceTemp(RegLocation loc); 1518 1519 /* 1520 * @brief Force a wide location (in registers) into temporary registers 1521 * @param loc location of result 1522 * @returns update location 1523 */ 1524 virtual RegLocation ForceTempWide(RegLocation loc); 1525 1526 static constexpr OpSize LoadStoreOpSize(bool wide, bool ref) { 1527 return wide ? k64 : ref ? kReference : k32; 1528 } 1529 1530 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1531 RegLocation rl_dest, RegLocation rl_src); 1532 1533 void AddSlowPath(LIRSlowPath* slowpath); 1534 1535 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1536 bool type_known_abstract, bool use_declaring_class, 1537 bool can_assume_type_is_in_dex_cache, 1538 uint32_t type_idx, RegLocation rl_dest, 1539 RegLocation rl_src); 1540 /* 1541 * @brief Generate the debug_frame FDE information if possible. 1542 * @returns pointer to vector containg CFE information, or NULL. 1543 */ 1544 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1545 1546 /** 1547 * @brief Used to insert marker that can be used to associate MIR with LIR. 1548 * @details Only inserts marker if verbosity is enabled. 1549 * @param mir The mir that is currently being generated. 1550 */ 1551 void GenPrintLabel(MIR* mir); 1552 1553 /** 1554 * @brief Used to generate return sequence when there is no frame. 1555 * @details Assumes that the return registers have already been populated. 1556 */ 1557 virtual void GenSpecialExitSequence() = 0; 1558 1559 /** 1560 * @brief Used to generate code for special methods that are known to be 1561 * small enough to work in frameless mode. 1562 * @param bb The basic block of the first MIR. 1563 * @param mir The first MIR of the special method. 1564 * @param special Information about the special method. 1565 * @return Returns whether or not this was handled successfully. Returns false 1566 * if caller should punt to normal MIR2LIR conversion. 1567 */ 1568 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1569 1570 protected: 1571 void ClobberBody(RegisterInfo* p); 1572 void SetCurrentDexPc(DexOffset dexpc) { 1573 current_dalvik_offset_ = dexpc; 1574 } 1575 1576 /** 1577 * @brief Used to lock register if argument at in_position was passed that way. 1578 * @details Does nothing if the argument is passed via stack. 1579 * @param in_position The argument number whose register to lock. 1580 * @param wide Whether the argument is wide. 1581 */ 1582 void LockArg(int in_position, bool wide = false); 1583 1584 /** 1585 * @brief Used to load VR argument to a physical register. 1586 * @details The load is only done if the argument is not already in physical register. 1587 * LockArg must have been previously called. 1588 * @param in_position The argument number to load. 1589 * @param wide Whether the argument is 64-bit or not. 1590 * @return Returns the register (or register pair) for the loaded argument. 1591 */ 1592 RegStorage LoadArg(int in_position, RegisterClass reg_class, bool wide = false); 1593 1594 /** 1595 * @brief Used to load a VR argument directly to a specified register location. 1596 * @param in_position The argument number to place in register. 1597 * @param rl_dest The register location where to place argument. 1598 */ 1599 void LoadArgDirect(int in_position, RegLocation rl_dest); 1600 1601 /** 1602 * @brief Used to generate LIR for special getter method. 1603 * @param mir The mir that represents the iget. 1604 * @param special Information about the special getter method. 1605 * @return Returns whether LIR was successfully generated. 1606 */ 1607 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1608 1609 /** 1610 * @brief Used to generate LIR for special setter method. 1611 * @param mir The mir that represents the iput. 1612 * @param special Information about the special setter method. 1613 * @return Returns whether LIR was successfully generated. 1614 */ 1615 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1616 1617 /** 1618 * @brief Used to generate LIR for special return-args method. 1619 * @param mir The mir that represents the return of argument. 1620 * @param special Information about the special return-args method. 1621 * @return Returns whether LIR was successfully generated. 1622 */ 1623 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1624 1625 void AddDivZeroCheckSlowPath(LIR* branch); 1626 1627 // Copy arg0 and arg1 to kArg0 and kArg1 safely, possibly using 1628 // kArg2 as temp. 1629 virtual void CopyToArgumentRegs(RegStorage arg0, RegStorage arg1); 1630 1631 /** 1632 * @brief Load Constant into RegLocation 1633 * @param rl_dest Destination RegLocation 1634 * @param value Constant value 1635 */ 1636 virtual void GenConst(RegLocation rl_dest, int value); 1637 1638 /** 1639 * Returns true iff wide GPRs are just different views on the same physical register. 1640 */ 1641 virtual bool WideGPRsAreAliases() = 0; 1642 1643 /** 1644 * Returns true iff wide FPRs are just different views on the same physical register. 1645 */ 1646 virtual bool WideFPRsAreAliases() = 0; 1647 1648 1649 enum class WidenessCheck { // private 1650 kIgnoreWide, 1651 kCheckWide, 1652 kCheckNotWide 1653 }; 1654 1655 enum class RefCheck { // private 1656 kIgnoreRef, 1657 kCheckRef, 1658 kCheckNotRef 1659 }; 1660 1661 enum class FPCheck { // private 1662 kIgnoreFP, 1663 kCheckFP, 1664 kCheckNotFP 1665 }; 1666 1667 /** 1668 * Check whether a reg storage seems well-formed, that is, if a reg storage is valid, 1669 * that it has the expected form for the flags. 1670 * A flag value of 0 means ignore. A flag value of -1 means false. A flag value of 1 means true. 1671 */ 1672 void CheckRegStorageImpl(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp, bool fail, 1673 bool report) 1674 const; 1675 1676 /** 1677 * Check whether a reg location seems well-formed, that is, if a reg storage is encoded, 1678 * that it has the expected size. 1679 */ 1680 void CheckRegLocationImpl(RegLocation rl, bool fail, bool report) const; 1681 1682 // See CheckRegStorageImpl. Will print or fail depending on kFailOnSizeError and 1683 // kReportSizeError. 1684 void CheckRegStorage(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp) const; 1685 // See CheckRegLocationImpl. 1686 void CheckRegLocation(RegLocation rl) const; 1687 1688 public: 1689 // TODO: add accessors for these. 1690 LIR* literal_list_; // Constants. 1691 LIR* method_literal_list_; // Method literals requiring patching. 1692 LIR* class_literal_list_; // Class literals requiring patching. 1693 LIR* code_literal_list_; // Code literals requiring patching. 1694 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1695 1696 protected: 1697 CompilationUnit* const cu_; 1698 MIRGraph* const mir_graph_; 1699 GrowableArray<SwitchTable*> switch_tables_; 1700 GrowableArray<FillArrayData*> fill_array_data_; 1701 GrowableArray<RegisterInfo*> tempreg_info_; 1702 GrowableArray<RegisterInfo*> reginfo_map_; 1703 GrowableArray<void*> pointer_storage_; 1704 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1705 CodeOffset data_offset_; // starting offset of literal pool. 1706 size_t total_size_; // header + code size. 1707 LIR* block_label_list_; 1708 PromotionMap* promotion_map_; 1709 /* 1710 * TODO: The code generation utilities don't have a built-in 1711 * mechanism to propagate the original Dalvik opcode address to the 1712 * associated generated instructions. For the trace compiler, this wasn't 1713 * necessary because the interpreter handled all throws and debugging 1714 * requests. For now we'll handle this by placing the Dalvik offset 1715 * in the CompilationUnit struct before codegen for each instruction. 1716 * The low-level LIR creation utilites will pull it from here. Rework this. 1717 */ 1718 DexOffset current_dalvik_offset_; 1719 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1720 RegisterPool* reg_pool_; 1721 /* 1722 * Sanity checking for the register temp tracking. The same ssa 1723 * name should never be associated with one temp register per 1724 * instruction compilation. 1725 */ 1726 int live_sreg_; 1727 CodeBuffer code_buffer_; 1728 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1729 std::vector<uint8_t> encoded_mapping_table_; 1730 std::vector<uint32_t> core_vmap_table_; 1731 std::vector<uint32_t> fp_vmap_table_; 1732 std::vector<uint8_t> native_gc_map_; 1733 int num_core_spills_; 1734 int num_fp_spills_; 1735 int frame_size_; 1736 unsigned int core_spill_mask_; 1737 unsigned int fp_spill_mask_; 1738 LIR* first_lir_insn_; 1739 LIR* last_lir_insn_; 1740 1741 GrowableArray<LIRSlowPath*> slow_paths_; 1742 1743 // The memory reference type for new LIRs. 1744 // NOTE: Passing this as an explicit parameter by all functions that directly or indirectly 1745 // invoke RawLIR() would clutter the code and reduce the readability. 1746 ResourceMask::ResourceBit mem_ref_type_; 1747 1748 // Each resource mask now takes 16-bytes, so having both use/def masks directly in a LIR 1749 // would consume 32 bytes per LIR. Instead, the LIR now holds only pointers to the masks 1750 // (i.e. 8 bytes on 32-bit arch, 16 bytes on 64-bit arch) and we use ResourceMaskCache 1751 // to deduplicate the masks. 1752 ResourceMaskCache mask_cache_; 1753}; // Class Mir2Lir 1754 1755} // namespace art 1756 1757#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1758