mir_to_lir.h revision 7fff544c38f0dec3a213236bb785c3ca13d21a0f
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 95#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 96#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 97#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 98#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 99#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 100#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 101#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 102#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 103#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 104#define REG_USE012 (REG_USE01 | REG_USE2) 105#define REG_USE014 (REG_USE01 | REG_USE4) 106#define REG_USE01 (REG_USE0 | REG_USE1) 107#define REG_USE02 (REG_USE0 | REG_USE2) 108#define REG_USE12 (REG_USE1 | REG_USE2) 109#define REG_USE23 (REG_USE2 | REG_USE3) 110#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 111 112struct BasicBlock; 113struct CallInfo; 114struct CompilationUnit; 115struct InlineMethod; 116struct MIR; 117struct LIR; 118struct RegLocation; 119struct RegisterInfo; 120class DexFileMethodInliner; 121class MIRGraph; 122class Mir2Lir; 123 124typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 125 const MethodReference& target_method, 126 uint32_t method_idx, uintptr_t direct_code, 127 uintptr_t direct_method, InvokeType type); 128 129typedef std::vector<uint8_t> CodeBuffer; 130 131struct UseDefMasks { 132 uint64_t use_mask; // Resource mask for use. 133 uint64_t def_mask; // Resource mask for def. 134}; 135 136struct AssemblyInfo { 137 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 138}; 139 140struct LIR { 141 CodeOffset offset; // Offset of this instruction. 142 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 143 int16_t opcode; 144 LIR* next; 145 LIR* prev; 146 LIR* target; 147 struct { 148 unsigned int alias_info:17; // For Dalvik register disambiguation. 149 bool is_nop:1; // LIR is optimized away. 150 unsigned int size:4; // Note: size of encoded instruction is in bytes. 151 bool use_def_invalid:1; // If true, masks should not be used. 152 unsigned int generation:1; // Used to track visitation state during fixup pass. 153 unsigned int fixup:8; // Fixup kind. 154 } flags; 155 union { 156 UseDefMasks m; // Use & Def masks used during optimization. 157 AssemblyInfo a; // Instruction info used during assembly phase. 158 } u; 159 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 160}; 161 162// Target-specific initialization. 163Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 164 ArenaAllocator* const arena); 165Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 166 ArenaAllocator* const arena); 167Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 168 ArenaAllocator* const arena); 169 170// Utility macros to traverse the LIR list. 171#define NEXT_LIR(lir) (lir->next) 172#define PREV_LIR(lir) (lir->prev) 173 174// Defines for alias_info (tracks Dalvik register references). 175#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 176#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 177#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 178#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 179 180// Common resource macros. 181#define ENCODE_CCODE (1ULL << kCCode) 182#define ENCODE_FP_STATUS (1ULL << kFPStatus) 183 184// Abstract memory locations. 185#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 186#define ENCODE_LITERAL (1ULL << kLiteral) 187#define ENCODE_HEAP_REF (1ULL << kHeapRef) 188#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 189 190#define ENCODE_ALL (~0ULL) 191#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 192 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 193 194#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 195#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 196 do { \ 197 low_reg = both_regs & 0xff; \ 198 high_reg = (both_regs >> 8) & 0xff; \ 199 } while (false) 200 201// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 202#define STARTING_DOUBLE_SREG 0x10000 203 204// TODO: replace these macros 205#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 206#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 207#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 208#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 209#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 210 211class Mir2Lir : public Backend { 212 public: 213 /* 214 * Auxiliary information describing the location of data embedded in the Dalvik 215 * byte code stream. 216 */ 217 struct EmbeddedData { 218 CodeOffset offset; // Code offset of data block. 219 const uint16_t* table; // Original dex data. 220 DexOffset vaddr; // Dalvik offset of parent opcode. 221 }; 222 223 struct FillArrayData : EmbeddedData { 224 int32_t size; 225 }; 226 227 struct SwitchTable : EmbeddedData { 228 LIR* anchor; // Reference instruction for relative offsets. 229 LIR** targets; // Array of case targets. 230 }; 231 232 /* Static register use counts */ 233 struct RefCounts { 234 int count; 235 int s_reg; 236 }; 237 238 /* 239 * Data structure tracking the mapping between a Dalvik register (pair) and a 240 * native register (pair). The idea is to reuse the previously loaded value 241 * if possible, otherwise to keep the value in a native register as long as 242 * possible. 243 */ 244 struct RegisterInfo { 245 int reg; // Reg number 246 bool in_use; // Has it been allocated? 247 bool is_temp; // Can allocate as temp? 248 bool pair; // Part of a register pair? 249 int partner; // If pair, other reg of pair. 250 bool live; // Is there an associated SSA name? 251 bool dirty; // If live, is it dirty? 252 int s_reg; // Name of live value. 253 LIR *def_start; // Starting inst in last def sequence. 254 LIR *def_end; // Ending inst in last def sequence. 255 }; 256 257 struct RegisterPool { 258 int num_core_regs; 259 RegisterInfo *core_regs; 260 int next_core_reg; 261 int num_fp_regs; 262 RegisterInfo *FPRegs; 263 int next_fp_reg; 264 }; 265 266 struct PromotionMap { 267 RegLocationType core_location:3; 268 uint8_t core_reg; 269 RegLocationType fp_location:3; 270 uint8_t FpReg; 271 bool first_in_pair; 272 }; 273 274 // 275 // Slow paths. This object is used generate a sequence of code that is executed in the 276 // slow path. For example, resolving a string or class is slow as it will only be executed 277 // once (after that it is resolved and doesn't need to be done again). We want slow paths 278 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 279 // branch over them. 280 // 281 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 282 // the Compile() function that will be called near the end of the code generated by the 283 // method. 284 // 285 // The basic flow for a slow path is: 286 // 287 // CMP reg, #value 288 // BEQ fromfast 289 // cont: 290 // ... 291 // fast path code 292 // ... 293 // more code 294 // ... 295 // RETURN 296 /// 297 // fromfast: 298 // ... 299 // slow path code 300 // ... 301 // B cont 302 // 303 // So you see we need two labels and two branches. The first branch (called fromfast) is 304 // the conditional branch to the slow path code. The second label (called cont) is used 305 // as an unconditional branch target for getting back to the code after the slow path 306 // has completed. 307 // 308 309 class LIRSlowPath { 310 public: 311 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 312 LIR* cont = nullptr) : 313 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 314 } 315 virtual ~LIRSlowPath() {} 316 virtual void Compile() = 0; 317 318 static void* operator new(size_t size, ArenaAllocator* arena) { 319 return arena->Alloc(size, kArenaAllocData); 320 } 321 322 protected: 323 LIR* GenerateTargetLabel(); 324 325 Mir2Lir* const m2l_; 326 const DexOffset current_dex_pc_; 327 LIR* const fromfast_; 328 LIR* const cont_; 329 }; 330 331 virtual ~Mir2Lir() {} 332 333 int32_t s4FromSwitchData(const void* switch_data) { 334 return *reinterpret_cast<const int32_t*>(switch_data); 335 } 336 337 RegisterClass oat_reg_class_by_size(OpSize size) { 338 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 339 size == kSignedByte) ? kCoreReg : kAnyReg; 340 } 341 342 size_t CodeBufferSizeInBytes() { 343 return code_buffer_.size() / sizeof(code_buffer_[0]); 344 } 345 346 static bool IsPseudoLirOp(int opcode) { 347 return (opcode < 0); 348 } 349 350 /* 351 * LIR operands are 32-bit integers. Sometimes, (especially for managing 352 * instructions which require PC-relative fixups), we need the operands to carry 353 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 354 * hold that index in the operand array. 355 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 356 * may be worth conditionally-compiling a set of identity functions here. 357 */ 358 uint32_t WrapPointer(void* pointer) { 359 uint32_t res = pointer_storage_.Size(); 360 pointer_storage_.Insert(pointer); 361 return res; 362 } 363 364 void* UnwrapPointer(size_t index) { 365 return pointer_storage_.Get(index); 366 } 367 368 // strdup(), but allocates from the arena. 369 char* ArenaStrdup(const char* str) { 370 size_t len = strlen(str) + 1; 371 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 372 if (res != NULL) { 373 strncpy(res, str, len); 374 } 375 return res; 376 } 377 378 // Shared by all targets - implemented in codegen_util.cc 379 void AppendLIR(LIR* lir); 380 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 381 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 382 383 /** 384 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 385 * to place in a frame. 386 * @return Returns the maximum number of compiler temporaries. 387 */ 388 size_t GetMaxPossibleCompilerTemps() const; 389 390 /** 391 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 392 * @return Returns the size in bytes for space needed for compiler temporary spill region. 393 */ 394 size_t GetNumBytesForCompilerTempSpillRegion(); 395 396 DexOffset GetCurrentDexPc() const { 397 return current_dalvik_offset_; 398 } 399 400 int ComputeFrameSize(); 401 virtual void Materialize(); 402 virtual CompiledMethod* GetCompiledMethod(); 403 void MarkSafepointPC(LIR* inst); 404 void SetupResourceMasks(LIR* lir); 405 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 406 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 407 void SetupRegMask(uint64_t* mask, int reg); 408 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 409 void DumpPromotionMap(); 410 void CodegenDump(); 411 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 412 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 413 LIR* NewLIR0(int opcode); 414 LIR* NewLIR1(int opcode, int dest); 415 LIR* NewLIR2(int opcode, int dest, int src1); 416 LIR* NewLIR2NoDest(int opcode, int src, int info); 417 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 418 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 419 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 420 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 421 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 422 LIR* AddWordData(LIR* *constant_list_p, int value); 423 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 424 void ProcessSwitchTables(); 425 void DumpSparseSwitchTable(const uint16_t* table); 426 void DumpPackedSwitchTable(const uint16_t* table); 427 void MarkBoundary(DexOffset offset, const char* inst_str); 428 void NopLIR(LIR* lir); 429 void UnlinkLIR(LIR* lir); 430 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 431 bool IsInexpensiveConstant(RegLocation rl_src); 432 ConditionCode FlipComparisonOrder(ConditionCode before); 433 ConditionCode NegateComparison(ConditionCode before); 434 virtual void InstallLiteralPools(); 435 void InstallSwitchTables(); 436 void InstallFillArrayData(); 437 bool VerifyCatchEntries(); 438 void CreateMappingTables(); 439 void CreateNativeGcMap(); 440 int AssignLiteralOffset(CodeOffset offset); 441 int AssignSwitchTablesOffset(CodeOffset offset); 442 int AssignFillArrayDataOffset(CodeOffset offset); 443 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 444 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 445 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 446 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 447 RegLocation NarrowRegLoc(RegLocation loc); 448 449 // Shared by all targets - implemented in local_optimizations.cc 450 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 451 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 452 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 453 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 454 455 // Shared by all targets - implemented in ralloc_util.cc 456 int GetSRegHi(int lowSreg); 457 bool oat_live_out(int s_reg); 458 int oatSSASrc(MIR* mir, int num); 459 void SimpleRegAlloc(); 460 void ResetRegPool(); 461 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 462 void DumpRegPool(RegisterInfo* p, int num_regs); 463 void DumpCoreRegPool(); 464 void DumpFpRegPool(); 465 /* Mark a temp register as dead. Does not affect allocation state. */ 466 void Clobber(int reg) { 467 ClobberBody(GetRegInfo(reg)); 468 } 469 void Clobber(RegStorage reg); 470 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 471 void ClobberSReg(int s_reg); 472 int SRegToPMap(int s_reg); 473 void RecordCorePromotion(RegStorage reg, int s_reg); 474 RegStorage AllocPreservedCoreReg(int s_reg); 475 void RecordFpPromotion(RegStorage reg, int s_reg); 476 RegStorage AllocPreservedSingle(int s_reg); 477 RegStorage AllocPreservedDouble(int s_reg); 478 RegStorage AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 479 virtual RegStorage AllocTempDouble(); 480 RegStorage AllocFreeTemp(); 481 RegStorage AllocTemp(); 482 RegStorage AllocTempFloat(); 483 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 484 RegisterInfo* AllocLive(int s_reg, int reg_class); 485 void FreeTemp(int reg); 486 void FreeTemp(RegStorage reg); 487 RegisterInfo* IsLive(int reg); 488 bool IsLive(RegStorage reg); 489 RegisterInfo* IsTemp(int reg); 490 bool IsTemp(RegStorage reg); 491 RegisterInfo* IsPromoted(int reg); 492 bool IsPromoted(RegStorage reg); 493 bool IsDirty(int reg); 494 bool IsDirty(RegStorage reg); 495 void LockTemp(int reg); 496 void LockTemp(RegStorage reg); 497 void ResetDef(int reg); 498 void ResetDef(RegStorage reg); 499 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 500 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 501 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 502 RegLocation WideToNarrow(RegLocation rl); 503 void ResetDefLoc(RegLocation rl); 504 virtual void ResetDefLocWide(RegLocation rl); 505 void ResetDefTracking(); 506 void ClobberAllRegs(); 507 void FlushSpecificReg(RegisterInfo* info); 508 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 509 void FlushAllRegs(); 510 bool RegClassMatches(int reg_class, RegStorage reg); 511 void MarkLive(RegStorage reg, int s_reg); 512 void MarkTemp(int reg); 513 void MarkTemp(RegStorage reg); 514 void UnmarkTemp(int reg); 515 void UnmarkTemp(RegStorage reg); 516 void MarkPair(int low_reg, int high_reg); 517 void MarkClean(RegLocation loc); 518 void MarkDirty(RegLocation loc); 519 void MarkInUse(int reg); 520 void MarkInUse(RegStorage reg); 521 void CopyRegInfo(int new_reg, int old_reg); 522 void CopyRegInfo(RegStorage new_reg, RegStorage old_reg); 523 bool CheckCorePoolSanity(); 524 RegLocation UpdateLoc(RegLocation loc); 525 virtual RegLocation UpdateLocWide(RegLocation loc); 526 RegLocation UpdateRawLoc(RegLocation loc); 527 528 /** 529 * @brief Used to load register location into a typed temporary or pair of temporaries. 530 * @see EvalLoc 531 * @param loc The register location to load from. 532 * @param reg_class Type of register needed. 533 * @param update Whether the liveness information should be updated. 534 * @return Returns the properly typed temporary in physical register pairs. 535 */ 536 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 537 538 /** 539 * @brief Used to load register location into a typed temporary. 540 * @param loc The register location to load from. 541 * @param reg_class Type of register needed. 542 * @param update Whether the liveness information should be updated. 543 * @return Returns the properly typed temporary in physical register. 544 */ 545 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 546 547 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 548 void DumpCounts(const RefCounts* arr, int size, const char* msg); 549 void DoPromotion(); 550 int VRegOffset(int v_reg); 551 int SRegOffset(int s_reg); 552 RegLocation GetReturnWide(bool is_double); 553 RegLocation GetReturn(bool is_float); 554 RegisterInfo* GetRegInfo(int reg); 555 556 // Shared by all targets - implemented in gen_common.cc. 557 void AddIntrinsicLaunchpad(CallInfo* info, LIR* branch, LIR* resume = nullptr); 558 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 559 RegLocation rl_src, RegLocation rl_dest, int lit); 560 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 561 void HandleSuspendLaunchPads(); 562 void HandleThrowLaunchPads(); 563 void HandleSlowPaths(); 564 void GenBarrier(); 565 void GenDivZeroException(); 566 // c_code holds condition code that's generated from testing divisor against 0. 567 void GenDivZeroCheck(ConditionCode c_code); 568 // reg holds divisor. 569 void GenDivZeroCheck(RegStorage reg); 570 LIR* GenNullCheck(RegStorage reg); 571 void MarkPossibleNullPointerException(int opt_flags); 572 void MarkPossibleStackOverflowException(); 573 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 574 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 575 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 576 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 577 LIR* GenRegRegCheck(ConditionCode c_code, RegStorage reg1, RegStorage reg2, ThrowKind kind); 578 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 579 RegLocation rl_src2, LIR* taken, LIR* fall_through); 580 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 581 LIR* taken, LIR* fall_through); 582 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 583 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 584 RegLocation rl_src); 585 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 586 RegLocation rl_src); 587 void GenFilledNewArray(CallInfo* info); 588 void GenSput(MIR* mir, RegLocation rl_src, 589 bool is_long_or_double, bool is_object); 590 void GenSget(MIR* mir, RegLocation rl_dest, 591 bool is_long_or_double, bool is_object); 592 void GenIGet(MIR* mir, int opt_flags, OpSize size, 593 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 594 void GenIPut(MIR* mir, int opt_flags, OpSize size, 595 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 596 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 597 RegLocation rl_src); 598 599 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 600 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 601 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 602 void GenThrow(RegLocation rl_src); 603 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 604 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 605 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 606 RegLocation rl_src1, RegLocation rl_src2); 607 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 608 RegLocation rl_src1, RegLocation rl_shift); 609 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 610 RegLocation rl_src, int lit); 611 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 612 RegLocation rl_src1, RegLocation rl_src2); 613 void GenConversionCall(ThreadOffset<4> func_offset, RegLocation rl_dest, 614 RegLocation rl_src); 615 void GenSuspendTest(int opt_flags); 616 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 617 618 // This will be overridden by x86 implementation. 619 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 620 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 621 RegLocation rl_src1, RegLocation rl_src2); 622 623 // Shared by all targets - implemented in gen_invoke.cc. 624 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, bool safepoint_pc, 625 bool use_link = true); 626 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 627 void CallRuntimeHelper(ThreadOffset<4> helper_offset, bool safepoint_pc); 628 void CallRuntimeHelperImm(ThreadOffset<4> helper_offset, int arg0, bool safepoint_pc); 629 void CallRuntimeHelperReg(ThreadOffset<4> helper_offset, RegStorage arg0, bool safepoint_pc); 630 void CallRuntimeHelperRegLocation(ThreadOffset<4> helper_offset, RegLocation arg0, 631 bool safepoint_pc); 632 void CallRuntimeHelperImmImm(ThreadOffset<4> helper_offset, int arg0, int arg1, 633 bool safepoint_pc); 634 void CallRuntimeHelperImmRegLocation(ThreadOffset<4> helper_offset, int arg0, 635 RegLocation arg1, bool safepoint_pc); 636 void CallRuntimeHelperRegLocationImm(ThreadOffset<4> helper_offset, RegLocation arg0, 637 int arg1, bool safepoint_pc); 638 void CallRuntimeHelperImmReg(ThreadOffset<4> helper_offset, int arg0, RegStorage arg1, 639 bool safepoint_pc); 640 void CallRuntimeHelperRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, int arg1, 641 bool safepoint_pc); 642 void CallRuntimeHelperImmMethod(ThreadOffset<4> helper_offset, int arg0, 643 bool safepoint_pc); 644 void CallRuntimeHelperRegMethod(ThreadOffset<4> helper_offset, RegStorage arg0, 645 bool safepoint_pc); 646 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<4> helper_offset, RegStorage arg0, 647 RegLocation arg2, bool safepoint_pc); 648 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<4> helper_offset, 649 RegLocation arg0, RegLocation arg1, 650 bool safepoint_pc); 651 void CallRuntimeHelperRegReg(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 652 bool safepoint_pc); 653 void CallRuntimeHelperRegRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 654 int arg2, bool safepoint_pc); 655 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<4> helper_offset, int arg0, 656 RegLocation arg2, bool safepoint_pc); 657 void CallRuntimeHelperImmMethodImm(ThreadOffset<4> helper_offset, int arg0, int arg2, 658 bool safepoint_pc); 659 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<4> helper_offset, 660 int arg0, RegLocation arg1, RegLocation arg2, 661 bool safepoint_pc); 662 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<4> helper_offset, 663 RegLocation arg0, RegLocation arg1, 664 RegLocation arg2, 665 bool safepoint_pc); 666 void GenInvoke(CallInfo* info); 667 void GenInvokeNoInline(CallInfo* info); 668 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 669 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 670 NextCallInsn next_call_insn, 671 const MethodReference& target_method, 672 uint32_t vtable_idx, 673 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 674 bool skip_this); 675 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 676 NextCallInsn next_call_insn, 677 const MethodReference& target_method, 678 uint32_t vtable_idx, 679 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 680 bool skip_this); 681 682 /** 683 * @brief Used to determine the register location of destination. 684 * @details This is needed during generation of inline intrinsics because it finds destination 685 * of return, 686 * either the physical register or the target of move-result. 687 * @param info Information about the invoke. 688 * @return Returns the destination location. 689 */ 690 RegLocation InlineTarget(CallInfo* info); 691 692 /** 693 * @brief Used to determine the wide register location of destination. 694 * @see InlineTarget 695 * @param info Information about the invoke. 696 * @return Returns the destination location. 697 */ 698 RegLocation InlineTargetWide(CallInfo* info); 699 700 bool GenInlinedCharAt(CallInfo* info); 701 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 702 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 703 bool GenInlinedAbsInt(CallInfo* info); 704 bool GenInlinedAbsLong(CallInfo* info); 705 bool GenInlinedAbsFloat(CallInfo* info); 706 bool GenInlinedAbsDouble(CallInfo* info); 707 bool GenInlinedFloatCvt(CallInfo* info); 708 bool GenInlinedDoubleCvt(CallInfo* info); 709 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 710 bool GenInlinedStringCompareTo(CallInfo* info); 711 bool GenInlinedCurrentThread(CallInfo* info); 712 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 713 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 714 bool is_volatile, bool is_ordered); 715 int LoadArgRegs(CallInfo* info, int call_state, 716 NextCallInsn next_call_insn, 717 const MethodReference& target_method, 718 uint32_t vtable_idx, 719 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 720 bool skip_this); 721 722 // Shared by all targets - implemented in gen_loadstore.cc. 723 RegLocation LoadCurrMethod(); 724 void LoadCurrMethodDirect(RegStorage r_tgt); 725 LIR* LoadConstant(RegStorage r_dest, int value); 726 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest); 727 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 728 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 729 void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 730 void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 731 void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 732 void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 733 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src); 734 735 /** 736 * @brief Used to do the final store in the destination as per bytecode semantics. 737 * @param rl_dest The destination dalvik register location. 738 * @param rl_src The source register location. Can be either physical register or dalvik register. 739 */ 740 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 741 742 /** 743 * @brief Used to do the final store in a wide destination as per bytecode semantics. 744 * @see StoreValue 745 * @param rl_dest The destination dalvik register location. 746 * @param rl_src The source register location. Can be either physical register or dalvik 747 * register. 748 */ 749 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 750 751 /** 752 * @brief Used to do the final store to a destination as per bytecode semantics. 753 * @see StoreValue 754 * @param rl_dest The destination dalvik register location. 755 * @param rl_src The source register location. It must be kLocPhysReg 756 * 757 * This is used for x86 two operand computations, where we have computed the correct 758 * register value that now needs to be properly registered. This is used to avoid an 759 * extra register copy that would result if StoreValue was called. 760 */ 761 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 762 763 /** 764 * @brief Used to do the final store in a wide destination as per bytecode semantics. 765 * @see StoreValueWide 766 * @param rl_dest The destination dalvik register location. 767 * @param rl_src The source register location. It must be kLocPhysReg 768 * 769 * This is used for x86 two operand computations, where we have computed the correct 770 * register values that now need to be properly registered. This is used to avoid an 771 * extra pair of register copies that would result if StoreValueWide was called. 772 */ 773 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 774 775 // Shared by all targets - implemented in mir_to_lir.cc. 776 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 777 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 778 bool MethodBlockCodeGen(BasicBlock* bb); 779 bool SpecialMIR2LIR(const InlineMethod& special); 780 void MethodMIR2LIR(); 781 782 /* 783 * @brief Load the address of the dex method into the register. 784 * @param target_method The MethodReference of the method to be invoked. 785 * @param type How the method will be invoked. 786 * @param register that will contain the code address. 787 * @note register will be passed to TargetReg to get physical register. 788 */ 789 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 790 SpecialTargetRegister symbolic_reg); 791 792 /* 793 * @brief Load the Method* of a dex method into the register. 794 * @param target_method The MethodReference of the method to be invoked. 795 * @param type How the method will be invoked. 796 * @param register that will contain the code address. 797 * @note register will be passed to TargetReg to get physical register. 798 */ 799 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 800 SpecialTargetRegister symbolic_reg); 801 802 /* 803 * @brief Load the Class* of a Dex Class type into the register. 804 * @param type How the method will be invoked. 805 * @param register that will contain the code address. 806 * @note register will be passed to TargetReg to get physical register. 807 */ 808 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 809 810 // Routines that work for the generic case, but may be overriden by target. 811 /* 812 * @brief Compare memory to immediate, and branch if condition true. 813 * @param cond The condition code that when true will branch to the target. 814 * @param temp_reg A temporary register that can be used if compare to memory is not 815 * supported by the architecture. 816 * @param base_reg The register holding the base address. 817 * @param offset The offset from the base. 818 * @param check_value The immediate to compare to. 819 * @returns The branch instruction that was generated. 820 */ 821 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 822 int offset, int check_value, LIR* target); 823 824 // Required for target - codegen helpers. 825 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 826 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 827 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 828 virtual LIR* CheckSuspendUsingLoad() = 0; 829 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 830 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 831 int s_reg) = 0; 832 virtual LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, 833 int s_reg) = 0; 834 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 835 int scale, OpSize size) = 0; 836 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 837 int displacement, RegStorage r_dest, RegStorage r_dest_hi, 838 OpSize size, int s_reg) = 0; 839 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 840 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 841 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 842 OpSize size) = 0; 843 virtual LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) = 0; 844 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 845 int scale, OpSize size) = 0; 846 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 847 int displacement, RegStorage r_src, RegStorage r_src_hi, 848 OpSize size, int s_reg) = 0; 849 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 850 851 // Required for target - register utilities. 852 virtual bool IsFpReg(int reg) = 0; 853 virtual bool IsFpReg(RegStorage reg) = 0; 854 virtual bool SameRegType(int reg1, int reg2) = 0; 855 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 856 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 857 // TODO: elminate S2d. 858 virtual int S2d(int low_reg, int high_reg) = 0; 859 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 860 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 861 virtual RegLocation GetReturnAlt() = 0; 862 virtual RegLocation GetReturnWideAlt() = 0; 863 virtual RegLocation LocCReturn() = 0; 864 virtual RegLocation LocCReturnDouble() = 0; 865 virtual RegLocation LocCReturnFloat() = 0; 866 virtual RegLocation LocCReturnWide() = 0; 867 // TODO: use to reduce/eliminate xx_FPREG() macro use. 868 virtual uint32_t FpRegMask() = 0; 869 virtual uint64_t GetRegMaskCommon(int reg) = 0; 870 virtual void AdjustSpillMask() = 0; 871 virtual void ClobberCallerSave() = 0; 872 virtual void FlushReg(RegStorage reg) = 0; 873 virtual void FlushRegWide(RegStorage reg) = 0; 874 virtual void FreeCallTemps() = 0; 875 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 876 virtual void LockCallTemps() = 0; 877 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 878 virtual void CompilerInitializeRegAlloc() = 0; 879 880 // Required for target - miscellaneous. 881 virtual void AssembleLIR() = 0; 882 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 883 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 884 virtual const char* GetTargetInstFmt(int opcode) = 0; 885 virtual const char* GetTargetInstName(int opcode) = 0; 886 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 887 virtual uint64_t GetPCUseDefEncoding() = 0; 888 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 889 virtual int GetInsnSize(LIR* lir) = 0; 890 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 891 892 // Required for target - Dalvik-level generators. 893 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 894 RegLocation rl_src1, RegLocation rl_src2) = 0; 895 virtual void GenMulLong(Instruction::Code, 896 RegLocation rl_dest, RegLocation rl_src1, 897 RegLocation rl_src2) = 0; 898 virtual void GenAddLong(Instruction::Code, 899 RegLocation rl_dest, RegLocation rl_src1, 900 RegLocation rl_src2) = 0; 901 virtual void GenAndLong(Instruction::Code, 902 RegLocation rl_dest, RegLocation rl_src1, 903 RegLocation rl_src2) = 0; 904 virtual void GenArithOpDouble(Instruction::Code opcode, 905 RegLocation rl_dest, RegLocation rl_src1, 906 RegLocation rl_src2) = 0; 907 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 908 RegLocation rl_src1, RegLocation rl_src2) = 0; 909 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 910 RegLocation rl_src1, RegLocation rl_src2) = 0; 911 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 912 RegLocation rl_src) = 0; 913 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 914 915 /** 916 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 917 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 918 * that applies on integers. The generated code will write the smallest or largest value 919 * directly into the destination register as specified by the invoke information. 920 * @param info Information about the invoke. 921 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 922 * @return Returns true if successfully generated 923 */ 924 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 925 926 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 927 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 928 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 929 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 930 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 931 RegLocation rl_src2) = 0; 932 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 933 RegLocation rl_src2) = 0; 934 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 935 RegLocation rl_src2) = 0; 936 virtual LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, 937 int offset, ThrowKind kind) = 0; 938 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 939 bool is_div) = 0; 940 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 941 bool is_div) = 0; 942 /* 943 * @brief Generate an integer div or rem operation by a literal. 944 * @param rl_dest Destination Location. 945 * @param rl_src1 Numerator Location. 946 * @param rl_src2 Divisor Location. 947 * @param is_div 'true' if this is a division, 'false' for a remainder. 948 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 949 */ 950 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 951 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 952 /* 953 * @brief Generate an integer div or rem operation by a literal. 954 * @param rl_dest Destination Location. 955 * @param rl_src Numerator Location. 956 * @param lit Divisor. 957 * @param is_div 'true' if this is a division, 'false' for a remainder. 958 */ 959 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 960 bool is_div) = 0; 961 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 962 963 /** 964 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 965 * @details This is used for generating DivideByZero checks when divisor is held in two 966 * separate registers. 967 * @param reg The register holding the pair of 32-bit values. 968 */ 969 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 970 971 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 972 virtual void GenExitSequence() = 0; 973 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 974 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 975 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 976 977 /** 978 * @brief Lowers the kMirOpSelect MIR into LIR. 979 * @param bb The basic block in which the MIR is from. 980 * @param mir The MIR whose opcode is kMirOpSelect. 981 */ 982 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 983 984 /** 985 * @brief Used to generate a memory barrier in an architecture specific way. 986 * @details The last generated LIR will be considered for use as barrier. Namely, 987 * if the last LIR can be updated in a way where it will serve the semantics of 988 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 989 * that can keep the semantics. 990 * @param barrier_kind The kind of memory barrier to generate. 991 */ 992 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 993 994 virtual void GenMoveException(RegLocation rl_dest) = 0; 995 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 996 int first_bit, int second_bit) = 0; 997 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 998 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 999 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1000 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1001 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1002 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1003 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1004 RegLocation rl_index, RegLocation rl_src, int scale, 1005 bool card_mark) = 0; 1006 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1007 RegLocation rl_src1, RegLocation rl_shift) = 0; 1008 1009 // Required for target - single operation generators. 1010 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1011 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1012 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1013 LIR* target) = 0; 1014 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1015 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1016 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1017 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1018 virtual void OpEndIT(LIR* it) = 0; 1019 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1020 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1021 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1022 virtual LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1023 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1024 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1025 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1026 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1027 1028 /** 1029 * @brief Used to generate an LIR that does a load from mem to reg. 1030 * @param r_dest The destination physical register. 1031 * @param r_base The base physical register for memory operand. 1032 * @param offset The displacement for memory operand. 1033 * @param move_type Specification on the move desired (size, alignment, register kind). 1034 * @return Returns the generate move LIR. 1035 */ 1036 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1037 MoveType move_type) = 0; 1038 1039 /** 1040 * @brief Used to generate an LIR that does a store from reg to mem. 1041 * @param r_base The base physical register for memory operand. 1042 * @param offset The displacement for memory operand. 1043 * @param r_src The destination physical register. 1044 * @param bytes_to_move The number of bytes to move. 1045 * @param is_aligned Whether the memory location is known to be aligned. 1046 * @return Returns the generate move LIR. 1047 */ 1048 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1049 MoveType move_type) = 0; 1050 1051 /** 1052 * @brief Used for generating a conditional register to register operation. 1053 * @param op The opcode kind. 1054 * @param cc The condition code that when true will perform the opcode. 1055 * @param r_dest The destination physical register. 1056 * @param r_src The source physical register. 1057 * @return Returns the newly created LIR or null in case of creation failure. 1058 */ 1059 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1060 1061 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1062 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1063 RegStorage r_src2) = 0; 1064 virtual LIR* OpTestSuspend(LIR* target) = 0; 1065 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1066 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1067 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1068 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1069 int offset) = 0; 1070 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1071 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1072 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1073 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1074 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1075 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1076 1077 // May be optimized by targets. 1078 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1079 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1080 1081 // Temp workaround 1082 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1083 1084 protected: 1085 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1086 1087 CompilationUnit* GetCompilationUnit() { 1088 return cu_; 1089 } 1090 /* 1091 * @brief Returns the index of the lowest set bit in 'x'. 1092 * @param x Value to be examined. 1093 * @returns The bit number of the lowest bit set in the value. 1094 */ 1095 int32_t LowestSetBit(uint64_t x); 1096 /* 1097 * @brief Is this value a power of two? 1098 * @param x Value to be examined. 1099 * @returns 'true' if only 1 bit is set in the value. 1100 */ 1101 bool IsPowerOfTwo(uint64_t x); 1102 /* 1103 * @brief Do these SRs overlap? 1104 * @param rl_op1 One RegLocation 1105 * @param rl_op2 The other RegLocation 1106 * @return 'true' if the VR pairs overlap 1107 * 1108 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1109 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1110 * dex, we'll want to make this case illegal. 1111 */ 1112 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1113 1114 /* 1115 * @brief Force a location (in a register) into a temporary register 1116 * @param loc location of result 1117 * @returns update location 1118 */ 1119 RegLocation ForceTemp(RegLocation loc); 1120 1121 /* 1122 * @brief Force a wide location (in registers) into temporary registers 1123 * @param loc location of result 1124 * @returns update location 1125 */ 1126 RegLocation ForceTempWide(RegLocation loc); 1127 1128 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1129 RegLocation rl_dest, RegLocation rl_src); 1130 1131 void AddSlowPath(LIRSlowPath* slowpath); 1132 1133 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1134 bool type_known_abstract, bool use_declaring_class, 1135 bool can_assume_type_is_in_dex_cache, 1136 uint32_t type_idx, RegLocation rl_dest, 1137 RegLocation rl_src); 1138 /* 1139 * @brief Generate the debug_frame FDE information if possible. 1140 * @returns pointer to vector containg CFE information, or NULL. 1141 */ 1142 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1143 1144 /** 1145 * @brief Used to insert marker that can be used to associate MIR with LIR. 1146 * @details Only inserts marker if verbosity is enabled. 1147 * @param mir The mir that is currently being generated. 1148 */ 1149 void GenPrintLabel(MIR* mir); 1150 1151 /** 1152 * @brief Used to generate return sequence when there is no frame. 1153 * @details Assumes that the return registers have already been populated. 1154 */ 1155 virtual void GenSpecialExitSequence() = 0; 1156 1157 /** 1158 * @brief Used to generate code for special methods that are known to be 1159 * small enough to work in frameless mode. 1160 * @param bb The basic block of the first MIR. 1161 * @param mir The first MIR of the special method. 1162 * @param special Information about the special method. 1163 * @return Returns whether or not this was handled successfully. Returns false 1164 * if caller should punt to normal MIR2LIR conversion. 1165 */ 1166 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1167 1168 private: 1169 void ClobberBody(RegisterInfo* p); 1170 void ResetDefBody(RegisterInfo* p) { 1171 p->def_start = NULL; 1172 p->def_end = NULL; 1173 } 1174 1175 void SetCurrentDexPc(DexOffset dexpc) { 1176 current_dalvik_offset_ = dexpc; 1177 } 1178 1179 /** 1180 * @brief Used to lock register if argument at in_position was passed that way. 1181 * @details Does nothing if the argument is passed via stack. 1182 * @param in_position The argument number whose register to lock. 1183 * @param wide Whether the argument is wide. 1184 */ 1185 void LockArg(int in_position, bool wide = false); 1186 1187 /** 1188 * @brief Used to load VR argument to a physical register. 1189 * @details The load is only done if the argument is not already in physical register. 1190 * LockArg must have been previously called. 1191 * @param in_position The argument number to load. 1192 * @param wide Whether the argument is 64-bit or not. 1193 * @return Returns the register (or register pair) for the loaded argument. 1194 */ 1195 RegStorage LoadArg(int in_position, bool wide = false); 1196 1197 /** 1198 * @brief Used to load a VR argument directly to a specified register location. 1199 * @param in_position The argument number to place in register. 1200 * @param rl_dest The register location where to place argument. 1201 */ 1202 void LoadArgDirect(int in_position, RegLocation rl_dest); 1203 1204 /** 1205 * @brief Used to generate LIR for special getter method. 1206 * @param mir The mir that represents the iget. 1207 * @param special Information about the special getter method. 1208 * @return Returns whether LIR was successfully generated. 1209 */ 1210 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1211 1212 /** 1213 * @brief Used to generate LIR for special setter method. 1214 * @param mir The mir that represents the iput. 1215 * @param special Information about the special setter method. 1216 * @return Returns whether LIR was successfully generated. 1217 */ 1218 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1219 1220 /** 1221 * @brief Used to generate LIR for special return-args method. 1222 * @param mir The mir that represents the return of argument. 1223 * @param special Information about the special return-args method. 1224 * @return Returns whether LIR was successfully generated. 1225 */ 1226 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1227 1228 void AddDivZeroCheckSlowPath(LIR* branch); 1229 1230 public: 1231 // TODO: add accessors for these. 1232 LIR* literal_list_; // Constants. 1233 LIR* method_literal_list_; // Method literals requiring patching. 1234 LIR* class_literal_list_; // Class literals requiring patching. 1235 LIR* code_literal_list_; // Code literals requiring patching. 1236 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1237 1238 protected: 1239 CompilationUnit* const cu_; 1240 MIRGraph* const mir_graph_; 1241 GrowableArray<SwitchTable*> switch_tables_; 1242 GrowableArray<FillArrayData*> fill_array_data_; 1243 GrowableArray<LIR*> throw_launchpads_; 1244 GrowableArray<LIR*> suspend_launchpads_; 1245 GrowableArray<RegisterInfo*> tempreg_info_; 1246 GrowableArray<RegisterInfo*> reginfo_map_; 1247 GrowableArray<void*> pointer_storage_; 1248 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1249 CodeOffset data_offset_; // starting offset of literal pool. 1250 size_t total_size_; // header + code size. 1251 LIR* block_label_list_; 1252 PromotionMap* promotion_map_; 1253 /* 1254 * TODO: The code generation utilities don't have a built-in 1255 * mechanism to propagate the original Dalvik opcode address to the 1256 * associated generated instructions. For the trace compiler, this wasn't 1257 * necessary because the interpreter handled all throws and debugging 1258 * requests. For now we'll handle this by placing the Dalvik offset 1259 * in the CompilationUnit struct before codegen for each instruction. 1260 * The low-level LIR creation utilites will pull it from here. Rework this. 1261 */ 1262 DexOffset current_dalvik_offset_; 1263 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1264 RegisterPool* reg_pool_; 1265 /* 1266 * Sanity checking for the register temp tracking. The same ssa 1267 * name should never be associated with one temp register per 1268 * instruction compilation. 1269 */ 1270 int live_sreg_; 1271 CodeBuffer code_buffer_; 1272 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1273 std::vector<uint8_t> encoded_mapping_table_; 1274 std::vector<uint32_t> core_vmap_table_; 1275 std::vector<uint32_t> fp_vmap_table_; 1276 std::vector<uint8_t> native_gc_map_; 1277 int num_core_spills_; 1278 int num_fp_spills_; 1279 int frame_size_; 1280 unsigned int core_spill_mask_; 1281 unsigned int fp_spill_mask_; 1282 LIR* first_lir_insn_; 1283 LIR* last_lir_insn_; 1284 1285 GrowableArray<LIRSlowPath*> slow_paths_; 1286}; // Class Mir2Lir 1287 1288} // namespace art 1289 1290#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1291