mir_to_lir.h revision 9da5c1013215176f2a4dbe7a804be899e12d5f68
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 95#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 96#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 97#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 98#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 99#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 100#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 101#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 102#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 103#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 104#define REG_USE012 (REG_USE01 | REG_USE2) 105#define REG_USE014 (REG_USE01 | REG_USE4) 106#define REG_USE01 (REG_USE0 | REG_USE1) 107#define REG_USE02 (REG_USE0 | REG_USE2) 108#define REG_USE12 (REG_USE1 | REG_USE2) 109#define REG_USE23 (REG_USE2 | REG_USE3) 110#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 111 112struct BasicBlock; 113struct CallInfo; 114struct CompilationUnit; 115struct InlineMethod; 116struct MIR; 117struct LIR; 118struct RegLocation; 119struct RegisterInfo; 120class DexFileMethodInliner; 121class MIRGraph; 122class Mir2Lir; 123 124typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 125 const MethodReference& target_method, 126 uint32_t method_idx, uintptr_t direct_code, 127 uintptr_t direct_method, InvokeType type); 128 129typedef std::vector<uint8_t> CodeBuffer; 130 131struct UseDefMasks { 132 uint64_t use_mask; // Resource mask for use. 133 uint64_t def_mask; // Resource mask for def. 134}; 135 136struct AssemblyInfo { 137 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 138 uint8_t bytes[16]; // Encoded instruction bytes. 139}; 140 141struct LIR { 142 CodeOffset offset; // Offset of this instruction. 143 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 144 int16_t opcode; 145 LIR* next; 146 LIR* prev; 147 LIR* target; 148 struct { 149 unsigned int alias_info:17; // For Dalvik register disambiguation. 150 bool is_nop:1; // LIR is optimized away. 151 unsigned int size:4; // Note: size of encoded instruction is in bytes. 152 bool use_def_invalid:1; // If true, masks should not be used. 153 unsigned int generation:1; // Used to track visitation state during fixup pass. 154 unsigned int fixup:8; // Fixup kind. 155 } flags; 156 union { 157 UseDefMasks m; // Use & Def masks used during optimization. 158 AssemblyInfo a; // Instruction encoding used during assembly phase. 159 } u; 160 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 161}; 162 163// Target-specific initialization. 164Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 165 ArenaAllocator* const arena); 166Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 167 ArenaAllocator* const arena); 168Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 169 ArenaAllocator* const arena); 170 171// Utility macros to traverse the LIR list. 172#define NEXT_LIR(lir) (lir->next) 173#define PREV_LIR(lir) (lir->prev) 174 175// Defines for alias_info (tracks Dalvik register references). 176#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 177#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 178#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 179#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 180 181// Common resource macros. 182#define ENCODE_CCODE (1ULL << kCCode) 183#define ENCODE_FP_STATUS (1ULL << kFPStatus) 184 185// Abstract memory locations. 186#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 187#define ENCODE_LITERAL (1ULL << kLiteral) 188#define ENCODE_HEAP_REF (1ULL << kHeapRef) 189#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 190 191#define ENCODE_ALL (~0ULL) 192#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 193 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 194 195#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 196#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 197 do { \ 198 low_reg = both_regs & 0xff; \ 199 high_reg = (both_regs >> 8) & 0xff; \ 200 } while (false) 201 202// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 203#define STARTING_DOUBLE_SREG 0x10000 204 205// TODO: replace these macros 206#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 207#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 208#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 209#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 210#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 211 212class Mir2Lir : public Backend { 213 public: 214 /* 215 * Auxiliary information describing the location of data embedded in the Dalvik 216 * byte code stream. 217 */ 218 struct EmbeddedData { 219 CodeOffset offset; // Code offset of data block. 220 const uint16_t* table; // Original dex data. 221 DexOffset vaddr; // Dalvik offset of parent opcode. 222 }; 223 224 struct FillArrayData : EmbeddedData { 225 int32_t size; 226 }; 227 228 struct SwitchTable : EmbeddedData { 229 LIR* anchor; // Reference instruction for relative offsets. 230 LIR** targets; // Array of case targets. 231 }; 232 233 /* Static register use counts */ 234 struct RefCounts { 235 int count; 236 int s_reg; 237 }; 238 239 /* 240 * Data structure tracking the mapping between a Dalvik register (pair) and a 241 * native register (pair). The idea is to reuse the previously loaded value 242 * if possible, otherwise to keep the value in a native register as long as 243 * possible. 244 */ 245 struct RegisterInfo { 246 int reg; // Reg number 247 bool in_use; // Has it been allocated? 248 bool is_temp; // Can allocate as temp? 249 bool pair; // Part of a register pair? 250 int partner; // If pair, other reg of pair. 251 bool live; // Is there an associated SSA name? 252 bool dirty; // If live, is it dirty? 253 int s_reg; // Name of live value. 254 LIR *def_start; // Starting inst in last def sequence. 255 LIR *def_end; // Ending inst in last def sequence. 256 }; 257 258 struct RegisterPool { 259 int num_core_regs; 260 RegisterInfo *core_regs; 261 int next_core_reg; 262 int num_fp_regs; 263 RegisterInfo *FPRegs; 264 int next_fp_reg; 265 }; 266 267 struct PromotionMap { 268 RegLocationType core_location:3; 269 uint8_t core_reg; 270 RegLocationType fp_location:3; 271 uint8_t FpReg; 272 bool first_in_pair; 273 }; 274 275 // 276 // Slow paths. This object is used generate a sequence of code that is executed in the 277 // slow path. For example, resolving a string or class is slow as it will only be executed 278 // once (after that it is resolved and doesn't need to be done again). We want slow paths 279 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 280 // branch over them. 281 // 282 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 283 // the Compile() function that will be called near the end of the code generated by the 284 // method. 285 // 286 // The basic flow for a slow path is: 287 // 288 // CMP reg, #value 289 // BEQ fromfast 290 // cont: 291 // ... 292 // fast path code 293 // ... 294 // more code 295 // ... 296 // RETURN 297 /// 298 // fromfast: 299 // ... 300 // slow path code 301 // ... 302 // B cont 303 // 304 // So you see we need two labels and two branches. The first branch (called fromfast) is 305 // the conditional branch to the slow path code. The second label (called cont) is used 306 // as an unconditional branch target for getting back to the code after the slow path 307 // has completed. 308 // 309 310 class LIRSlowPath { 311 public: 312 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 313 LIR* cont = nullptr) : 314 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 315 } 316 virtual ~LIRSlowPath() {} 317 virtual void Compile() = 0; 318 319 static void* operator new(size_t size, ArenaAllocator* arena) { 320 return arena->Alloc(size, kArenaAllocData); 321 } 322 323 protected: 324 LIR* GenerateTargetLabel(); 325 326 Mir2Lir* const m2l_; 327 const DexOffset current_dex_pc_; 328 LIR* const fromfast_; 329 LIR* const cont_; 330 }; 331 332 virtual ~Mir2Lir() {} 333 334 int32_t s4FromSwitchData(const void* switch_data) { 335 return *reinterpret_cast<const int32_t*>(switch_data); 336 } 337 338 RegisterClass oat_reg_class_by_size(OpSize size) { 339 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 340 size == kSignedByte) ? kCoreReg : kAnyReg; 341 } 342 343 size_t CodeBufferSizeInBytes() { 344 return code_buffer_.size() / sizeof(code_buffer_[0]); 345 } 346 347 bool IsPseudoLirOp(int opcode) { 348 return (opcode < 0); 349 } 350 351 /* 352 * LIR operands are 32-bit integers. Sometimes, (especially for managing 353 * instructions which require PC-relative fixups), we need the operands to carry 354 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 355 * hold that index in the operand array. 356 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 357 * may be worth conditionally-compiling a set of identity functions here. 358 */ 359 uint32_t WrapPointer(void* pointer) { 360 uint32_t res = pointer_storage_.Size(); 361 pointer_storage_.Insert(pointer); 362 return res; 363 } 364 365 void* UnwrapPointer(size_t index) { 366 return pointer_storage_.Get(index); 367 } 368 369 // strdup(), but allocates from the arena. 370 char* ArenaStrdup(const char* str) { 371 size_t len = strlen(str) + 1; 372 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 373 if (res != NULL) { 374 strncpy(res, str, len); 375 } 376 return res; 377 } 378 379 // Shared by all targets - implemented in codegen_util.cc 380 void AppendLIR(LIR* lir); 381 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 382 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 383 384 /** 385 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 386 * to place in a frame. 387 * @return Returns the maximum number of compiler temporaries. 388 */ 389 size_t GetMaxPossibleCompilerTemps() const; 390 391 /** 392 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 393 * @return Returns the size in bytes for space needed for compiler temporary spill region. 394 */ 395 size_t GetNumBytesForCompilerTempSpillRegion(); 396 397 DexOffset GetCurrentDexPc() const { 398 return current_dalvik_offset_; 399 } 400 401 int ComputeFrameSize(); 402 virtual void Materialize(); 403 virtual CompiledMethod* GetCompiledMethod(); 404 void MarkSafepointPC(LIR* inst); 405 void SetupResourceMasks(LIR* lir); 406 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 407 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 408 void SetupRegMask(uint64_t* mask, int reg); 409 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 410 void DumpPromotionMap(); 411 void CodegenDump(); 412 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 413 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 414 LIR* NewLIR0(int opcode); 415 LIR* NewLIR1(int opcode, int dest); 416 LIR* NewLIR2(int opcode, int dest, int src1); 417 LIR* NewLIR2NoDest(int opcode, int src, int info); 418 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 419 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 420 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 421 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 422 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 423 LIR* AddWordData(LIR* *constant_list_p, int value); 424 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 425 void ProcessSwitchTables(); 426 void DumpSparseSwitchTable(const uint16_t* table); 427 void DumpPackedSwitchTable(const uint16_t* table); 428 void MarkBoundary(DexOffset offset, const char* inst_str); 429 void NopLIR(LIR* lir); 430 void UnlinkLIR(LIR* lir); 431 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 432 bool IsInexpensiveConstant(RegLocation rl_src); 433 ConditionCode FlipComparisonOrder(ConditionCode before); 434 ConditionCode NegateComparison(ConditionCode before); 435 virtual void InstallLiteralPools(); 436 void InstallSwitchTables(); 437 void InstallFillArrayData(); 438 bool VerifyCatchEntries(); 439 void CreateMappingTables(); 440 void CreateNativeGcMap(); 441 int AssignLiteralOffset(CodeOffset offset); 442 int AssignSwitchTablesOffset(CodeOffset offset); 443 int AssignFillArrayDataOffset(CodeOffset offset); 444 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 445 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 446 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 447 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 448 RegLocation NarrowRegLoc(RegLocation loc); 449 450 // Shared by all targets - implemented in local_optimizations.cc 451 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 452 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 453 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 454 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 455 456 // Shared by all targets - implemented in ralloc_util.cc 457 int GetSRegHi(int lowSreg); 458 bool oat_live_out(int s_reg); 459 int oatSSASrc(MIR* mir, int num); 460 void SimpleRegAlloc(); 461 void ResetRegPool(); 462 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 463 void DumpRegPool(RegisterInfo* p, int num_regs); 464 void DumpCoreRegPool(); 465 void DumpFpRegPool(); 466 /* Mark a temp register as dead. Does not affect allocation state. */ 467 void Clobber(int reg) { 468 ClobberBody(GetRegInfo(reg)); 469 } 470 void Clobber(RegStorage reg); 471 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 472 void ClobberSReg(int s_reg); 473 int SRegToPMap(int s_reg); 474 void RecordCorePromotion(RegStorage reg, int s_reg); 475 RegStorage AllocPreservedCoreReg(int s_reg); 476 void RecordFpPromotion(RegStorage reg, int s_reg); 477 RegStorage AllocPreservedSingle(int s_reg); 478 RegStorage AllocPreservedDouble(int s_reg); 479 RegStorage AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 480 virtual RegStorage AllocTempDouble(); 481 RegStorage AllocFreeTemp(); 482 RegStorage AllocTemp(); 483 RegStorage AllocTempFloat(); 484 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 485 RegisterInfo* AllocLive(int s_reg, int reg_class); 486 void FreeTemp(int reg); 487 void FreeTemp(RegStorage reg); 488 RegisterInfo* IsLive(int reg); 489 bool IsLive(RegStorage reg); 490 RegisterInfo* IsTemp(int reg); 491 bool IsTemp(RegStorage reg); 492 RegisterInfo* IsPromoted(int reg); 493 bool IsPromoted(RegStorage reg); 494 bool IsDirty(int reg); 495 bool IsDirty(RegStorage reg); 496 void LockTemp(int reg); 497 void LockTemp(RegStorage reg); 498 void ResetDef(int reg); 499 void ResetDef(RegStorage reg); 500 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 501 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 502 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 503 RegLocation WideToNarrow(RegLocation rl); 504 void ResetDefLoc(RegLocation rl); 505 virtual void ResetDefLocWide(RegLocation rl); 506 void ResetDefTracking(); 507 void ClobberAllRegs(); 508 void FlushSpecificReg(RegisterInfo* info); 509 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 510 void FlushAllRegs(); 511 bool RegClassMatches(int reg_class, RegStorage reg); 512 void MarkLive(RegStorage reg, int s_reg); 513 void MarkTemp(int reg); 514 void MarkTemp(RegStorage reg); 515 void UnmarkTemp(int reg); 516 void UnmarkTemp(RegStorage reg); 517 void MarkPair(int low_reg, int high_reg); 518 void MarkClean(RegLocation loc); 519 void MarkDirty(RegLocation loc); 520 void MarkInUse(int reg); 521 void MarkInUse(RegStorage reg); 522 void CopyRegInfo(int new_reg, int old_reg); 523 void CopyRegInfo(RegStorage new_reg, RegStorage old_reg); 524 bool CheckCorePoolSanity(); 525 RegLocation UpdateLoc(RegLocation loc); 526 virtual RegLocation UpdateLocWide(RegLocation loc); 527 RegLocation UpdateRawLoc(RegLocation loc); 528 529 /** 530 * @brief Used to load register location into a typed temporary or pair of temporaries. 531 * @see EvalLoc 532 * @param loc The register location to load from. 533 * @param reg_class Type of register needed. 534 * @param update Whether the liveness information should be updated. 535 * @return Returns the properly typed temporary in physical register pairs. 536 */ 537 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 538 539 /** 540 * @brief Used to load register location into a typed temporary. 541 * @param loc The register location to load from. 542 * @param reg_class Type of register needed. 543 * @param update Whether the liveness information should be updated. 544 * @return Returns the properly typed temporary in physical register. 545 */ 546 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 547 548 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 549 void DumpCounts(const RefCounts* arr, int size, const char* msg); 550 void DoPromotion(); 551 int VRegOffset(int v_reg); 552 int SRegOffset(int s_reg); 553 RegLocation GetReturnWide(bool is_double); 554 RegLocation GetReturn(bool is_float); 555 RegisterInfo* GetRegInfo(int reg); 556 557 // Shared by all targets - implemented in gen_common.cc. 558 void AddIntrinsicLaunchpad(CallInfo* info, LIR* branch, LIR* resume = nullptr); 559 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 560 RegLocation rl_src, RegLocation rl_dest, int lit); 561 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 562 void HandleSuspendLaunchPads(); 563 void HandleThrowLaunchPads(); 564 void HandleSlowPaths(); 565 void GenBarrier(); 566 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 567 void MarkPossibleNullPointerException(int opt_flags); 568 void MarkPossibleStackOverflowException(); 569 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 570 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 571 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 572 LIR* GenRegRegCheck(ConditionCode c_code, RegStorage reg1, RegStorage reg2, ThrowKind kind); 573 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 574 RegLocation rl_src2, LIR* taken, LIR* fall_through); 575 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 576 LIR* taken, LIR* fall_through); 577 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 578 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 579 RegLocation rl_src); 580 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 581 RegLocation rl_src); 582 void GenFilledNewArray(CallInfo* info); 583 void GenSput(MIR* mir, RegLocation rl_src, 584 bool is_long_or_double, bool is_object); 585 void GenSget(MIR* mir, RegLocation rl_dest, 586 bool is_long_or_double, bool is_object); 587 void GenIGet(MIR* mir, int opt_flags, OpSize size, 588 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 589 void GenIPut(MIR* mir, int opt_flags, OpSize size, 590 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 591 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 592 RegLocation rl_src); 593 594 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 595 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 596 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 597 void GenThrow(RegLocation rl_src); 598 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 599 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 600 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 601 RegLocation rl_src1, RegLocation rl_src2); 602 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 603 RegLocation rl_src1, RegLocation rl_shift); 604 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 605 RegLocation rl_src, int lit); 606 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 607 RegLocation rl_src1, RegLocation rl_src2); 608 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 609 RegLocation rl_src); 610 void GenSuspendTest(int opt_flags); 611 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 612 613 // This will be overridden by x86 implementation. 614 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 615 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 616 RegLocation rl_src1, RegLocation rl_src2); 617 618 // Shared by all targets - implemented in gen_invoke.cc. 619 LIR* CallHelper(RegStorage r_tgt, ThreadOffset helper_offset, bool safepoint_pc, 620 bool use_link = true); 621 RegStorage CallHelperSetup(ThreadOffset helper_offset); 622 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 623 void CallRuntimeHelperReg(ThreadOffset helper_offset, RegStorage arg0, bool safepoint_pc); 624 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 625 bool safepoint_pc); 626 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 627 bool safepoint_pc); 628 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 629 RegLocation arg1, bool safepoint_pc); 630 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 631 int arg1, bool safepoint_pc); 632 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, RegStorage arg1, 633 bool safepoint_pc); 634 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, RegStorage arg0, int arg1, 635 bool safepoint_pc); 636 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 637 bool safepoint_pc); 638 void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, RegStorage arg0, bool safepoint_pc); 639 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, RegStorage arg0, 640 RegLocation arg2, bool safepoint_pc); 641 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 642 RegLocation arg0, RegLocation arg1, 643 bool safepoint_pc); 644 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, RegStorage arg0, RegStorage arg1, 645 bool safepoint_pc); 646 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, RegStorage arg0, RegStorage arg1, 647 int arg2, bool safepoint_pc); 648 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 649 RegLocation arg2, bool safepoint_pc); 650 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 651 bool safepoint_pc); 652 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 653 int arg0, RegLocation arg1, RegLocation arg2, 654 bool safepoint_pc); 655 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 656 RegLocation arg0, RegLocation arg1, 657 RegLocation arg2, 658 bool safepoint_pc); 659 void GenInvoke(CallInfo* info); 660 void GenInvokeNoInline(CallInfo* info); 661 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 662 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 663 NextCallInsn next_call_insn, 664 const MethodReference& target_method, 665 uint32_t vtable_idx, 666 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 667 bool skip_this); 668 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 669 NextCallInsn next_call_insn, 670 const MethodReference& target_method, 671 uint32_t vtable_idx, 672 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 673 bool skip_this); 674 675 /** 676 * @brief Used to determine the register location of destination. 677 * @details This is needed during generation of inline intrinsics because it finds destination of return, 678 * either the physical register or the target of move-result. 679 * @param info Information about the invoke. 680 * @return Returns the destination location. 681 */ 682 RegLocation InlineTarget(CallInfo* info); 683 684 /** 685 * @brief Used to determine the wide register location of destination. 686 * @see InlineTarget 687 * @param info Information about the invoke. 688 * @return Returns the destination location. 689 */ 690 RegLocation InlineTargetWide(CallInfo* info); 691 692 bool GenInlinedCharAt(CallInfo* info); 693 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 694 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 695 bool GenInlinedAbsInt(CallInfo* info); 696 bool GenInlinedAbsLong(CallInfo* info); 697 bool GenInlinedAbsFloat(CallInfo* info); 698 bool GenInlinedAbsDouble(CallInfo* info); 699 bool GenInlinedFloatCvt(CallInfo* info); 700 bool GenInlinedDoubleCvt(CallInfo* info); 701 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 702 bool GenInlinedStringCompareTo(CallInfo* info); 703 bool GenInlinedCurrentThread(CallInfo* info); 704 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 705 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 706 bool is_volatile, bool is_ordered); 707 int LoadArgRegs(CallInfo* info, int call_state, 708 NextCallInsn next_call_insn, 709 const MethodReference& target_method, 710 uint32_t vtable_idx, 711 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 712 bool skip_this); 713 714 // Shared by all targets - implemented in gen_loadstore.cc. 715 RegLocation LoadCurrMethod(); 716 void LoadCurrMethodDirect(RegStorage r_tgt); 717 LIR* LoadConstant(RegStorage r_dest, int value); 718 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest); 719 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 720 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 721 void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 722 void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 723 void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 724 void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 725 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src); 726 727 /** 728 * @brief Used to do the final store in the destination as per bytecode semantics. 729 * @param rl_dest The destination dalvik register location. 730 * @param rl_src The source register location. Can be either physical register or dalvik register. 731 */ 732 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 733 734 /** 735 * @brief Used to do the final store in a wide destination as per bytecode semantics. 736 * @see StoreValue 737 * @param rl_dest The destination dalvik register location. 738 * @param rl_src The source register location. Can be either physical register or dalvik register. 739 */ 740 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 741 742 /** 743 * @brief Used to do the final store to a destination as per bytecode semantics. 744 * @see StoreValue 745 * @param rl_dest The destination dalvik register location. 746 * @param rl_src The source register location. It must be kLocPhysReg 747 * 748 * This is used for x86 two operand computations, where we have computed the correct 749 * register value that now needs to be properly registered. This is used to avoid an 750 * extra register copy that would result if StoreValue was called. 751 */ 752 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 753 754 /** 755 * @brief Used to do the final store in a wide destination as per bytecode semantics. 756 * @see StoreValueWide 757 * @param rl_dest The destination dalvik register location. 758 * @param rl_src The source register location. It must be kLocPhysReg 759 * 760 * This is used for x86 two operand computations, where we have computed the correct 761 * register values that now need to be properly registered. This is used to avoid an 762 * extra pair of register copies that would result if StoreValueWide was called. 763 */ 764 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 765 766 // Shared by all targets - implemented in mir_to_lir.cc. 767 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 768 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 769 bool MethodBlockCodeGen(BasicBlock* bb); 770 bool SpecialMIR2LIR(const InlineMethod& special); 771 void MethodMIR2LIR(); 772 773 /* 774 * @brief Load the address of the dex method into the register. 775 * @param target_method The MethodReference of the method to be invoked. 776 * @param type How the method will be invoked. 777 * @param register that will contain the code address. 778 * @note register will be passed to TargetReg to get physical register. 779 */ 780 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 781 SpecialTargetRegister symbolic_reg); 782 783 /* 784 * @brief Load the Method* of a dex method into the register. 785 * @param target_method The MethodReference of the method to be invoked. 786 * @param type How the method will be invoked. 787 * @param register that will contain the code address. 788 * @note register will be passed to TargetReg to get physical register. 789 */ 790 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 791 SpecialTargetRegister symbolic_reg); 792 793 /* 794 * @brief Load the Class* of a Dex Class type into the register. 795 * @param type How the method will be invoked. 796 * @param register that will contain the code address. 797 * @note register will be passed to TargetReg to get physical register. 798 */ 799 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 800 801 // Routines that work for the generic case, but may be overriden by target. 802 /* 803 * @brief Compare memory to immediate, and branch if condition true. 804 * @param cond The condition code that when true will branch to the target. 805 * @param temp_reg A temporary register that can be used if compare to memory is not 806 * supported by the architecture. 807 * @param base_reg The register holding the base address. 808 * @param offset The offset from the base. 809 * @param check_value The immediate to compare to. 810 * @returns The branch instruction that was generated. 811 */ 812 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 813 int offset, int check_value, LIR* target); 814 815 // Required for target - codegen helpers. 816 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 817 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 818 virtual LIR* CheckSuspendUsingLoad() = 0; 819 virtual RegStorage LoadHelper(ThreadOffset offset) = 0; 820 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 821 int s_reg) = 0; 822 virtual LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, 823 int s_reg) = 0; 824 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 825 int scale, OpSize size) = 0; 826 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 827 int displacement, RegStorage r_dest, RegStorage r_dest_hi, 828 OpSize size, int s_reg) = 0; 829 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 830 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 831 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 832 OpSize size) = 0; 833 virtual LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) = 0; 834 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 835 int scale, OpSize size) = 0; 836 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 837 int displacement, RegStorage r_src, RegStorage r_src_hi, 838 OpSize size, int s_reg) = 0; 839 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 840 841 // Required for target - register utilities. 842 virtual bool IsFpReg(int reg) = 0; 843 virtual bool IsFpReg(RegStorage reg) = 0; 844 virtual bool SameRegType(int reg1, int reg2) = 0; 845 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 846 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 847 // TODO: elminate S2d. 848 virtual int S2d(int low_reg, int high_reg) = 0; 849 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 850 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 851 virtual RegLocation GetReturnAlt() = 0; 852 virtual RegLocation GetReturnWideAlt() = 0; 853 virtual RegLocation LocCReturn() = 0; 854 virtual RegLocation LocCReturnDouble() = 0; 855 virtual RegLocation LocCReturnFloat() = 0; 856 virtual RegLocation LocCReturnWide() = 0; 857 // TODO: use to reduce/eliminate xx_FPREG() macro use. 858 virtual uint32_t FpRegMask() = 0; 859 virtual uint64_t GetRegMaskCommon(int reg) = 0; 860 virtual void AdjustSpillMask() = 0; 861 virtual void ClobberCallerSave() = 0; 862 virtual void FlushReg(RegStorage reg) = 0; 863 virtual void FlushRegWide(RegStorage reg) = 0; 864 virtual void FreeCallTemps() = 0; 865 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 866 virtual void LockCallTemps() = 0; 867 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 868 virtual void CompilerInitializeRegAlloc() = 0; 869 870 // Required for target - miscellaneous. 871 virtual void AssembleLIR() = 0; 872 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 873 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 874 virtual const char* GetTargetInstFmt(int opcode) = 0; 875 virtual const char* GetTargetInstName(int opcode) = 0; 876 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 877 virtual uint64_t GetPCUseDefEncoding() = 0; 878 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 879 virtual int GetInsnSize(LIR* lir) = 0; 880 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 881 882 // Required for target - Dalvik-level generators. 883 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 884 RegLocation rl_src1, RegLocation rl_src2) = 0; 885 virtual void GenMulLong(Instruction::Code, 886 RegLocation rl_dest, RegLocation rl_src1, 887 RegLocation rl_src2) = 0; 888 virtual void GenAddLong(Instruction::Code, 889 RegLocation rl_dest, RegLocation rl_src1, 890 RegLocation rl_src2) = 0; 891 virtual void GenAndLong(Instruction::Code, 892 RegLocation rl_dest, RegLocation rl_src1, 893 RegLocation rl_src2) = 0; 894 virtual void GenArithOpDouble(Instruction::Code opcode, 895 RegLocation rl_dest, RegLocation rl_src1, 896 RegLocation rl_src2) = 0; 897 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 898 RegLocation rl_src1, RegLocation rl_src2) = 0; 899 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 900 RegLocation rl_src1, RegLocation rl_src2) = 0; 901 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 902 RegLocation rl_src) = 0; 903 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 904 905 /** 906 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 907 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 908 * that applies on integers. The generated code will write the smallest or largest value 909 * directly into the destination register as specified by the invoke information. 910 * @param info Information about the invoke. 911 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 912 * @return Returns true if successfully generated 913 */ 914 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 915 916 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 917 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 918 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 919 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 920 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 921 RegLocation rl_src2) = 0; 922 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 923 RegLocation rl_src2) = 0; 924 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 925 RegLocation rl_src2) = 0; 926 virtual LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, 927 int offset, ThrowKind kind) = 0; 928 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 929 bool is_div) = 0; 930 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 931 bool is_div) = 0; 932 /* 933 * @brief Generate an integer div or rem operation by a literal. 934 * @param rl_dest Destination Location. 935 * @param rl_src1 Numerator Location. 936 * @param rl_src2 Divisor Location. 937 * @param is_div 'true' if this is a division, 'false' for a remainder. 938 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 939 */ 940 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 941 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 942 /* 943 * @brief Generate an integer div or rem operation by a literal. 944 * @param rl_dest Destination Location. 945 * @param rl_src Numerator Location. 946 * @param lit Divisor. 947 * @param is_div 'true' if this is a division, 'false' for a remainder. 948 */ 949 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 950 bool is_div) = 0; 951 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 952 953 /** 954 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 955 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers. 956 * @param reg_lo The register holding the lower 32-bits. 957 * @param reg_hi The register holding the upper 32-bits. 958 */ 959 virtual void GenDivZeroCheck(RegStorage reg) = 0; 960 961 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 962 virtual void GenExitSequence() = 0; 963 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 964 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 965 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 966 967 /** 968 * @brief Lowers the kMirOpSelect MIR into LIR. 969 * @param bb The basic block in which the MIR is from. 970 * @param mir The MIR whose opcode is kMirOpSelect. 971 */ 972 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 973 974 /** 975 * @brief Used to generate a memory barrier in an architecture specific way. 976 * @details The last generated LIR will be considered for use as barrier. Namely, 977 * if the last LIR can be updated in a way where it will serve the semantics of 978 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 979 * that can keep the semantics. 980 * @param barrier_kind The kind of memory barrier to generate. 981 */ 982 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 983 984 virtual void GenMoveException(RegLocation rl_dest) = 0; 985 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 986 int first_bit, int second_bit) = 0; 987 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 988 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 989 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 990 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 991 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 992 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 993 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 994 RegLocation rl_index, RegLocation rl_src, int scale, 995 bool card_mark) = 0; 996 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 997 RegLocation rl_src1, RegLocation rl_shift) = 0; 998 999 // Required for target - single operation generators. 1000 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1001 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1002 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1003 LIR* target) = 0; 1004 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1005 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1006 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1007 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1008 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1009 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1010 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1011 virtual LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1012 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1013 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1014 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1015 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1016 1017 /** 1018 * @brief Used to generate an LIR that does a load from mem to reg. 1019 * @param r_dest The destination physical register. 1020 * @param r_base The base physical register for memory operand. 1021 * @param offset The displacement for memory operand. 1022 * @param move_type Specification on the move desired (size, alignment, register kind). 1023 * @return Returns the generate move LIR. 1024 */ 1025 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1026 MoveType move_type) = 0; 1027 1028 /** 1029 * @brief Used to generate an LIR that does a store from reg to mem. 1030 * @param r_base The base physical register for memory operand. 1031 * @param offset The displacement for memory operand. 1032 * @param r_src The destination physical register. 1033 * @param bytes_to_move The number of bytes to move. 1034 * @param is_aligned Whether the memory location is known to be aligned. 1035 * @return Returns the generate move LIR. 1036 */ 1037 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1038 MoveType move_type) = 0; 1039 1040 /** 1041 * @brief Used for generating a conditional register to register operation. 1042 * @param op The opcode kind. 1043 * @param cc The condition code that when true will perform the opcode. 1044 * @param r_dest The destination physical register. 1045 * @param r_src The source physical register. 1046 * @return Returns the newly created LIR or null in case of creation failure. 1047 */ 1048 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1049 1050 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1051 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1052 RegStorage r_src2) = 0; 1053 virtual LIR* OpTestSuspend(LIR* target) = 0; 1054 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 1055 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1056 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1057 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1058 int offset) = 0; 1059 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1060 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 1061 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1062 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1063 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1064 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1065 1066 // May be optimized by targets. 1067 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1068 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1069 1070 // Temp workaround 1071 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1072 1073 protected: 1074 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1075 1076 CompilationUnit* GetCompilationUnit() { 1077 return cu_; 1078 } 1079 /* 1080 * @brief Returns the index of the lowest set bit in 'x'. 1081 * @param x Value to be examined. 1082 * @returns The bit number of the lowest bit set in the value. 1083 */ 1084 int32_t LowestSetBit(uint64_t x); 1085 /* 1086 * @brief Is this value a power of two? 1087 * @param x Value to be examined. 1088 * @returns 'true' if only 1 bit is set in the value. 1089 */ 1090 bool IsPowerOfTwo(uint64_t x); 1091 /* 1092 * @brief Do these SRs overlap? 1093 * @param rl_op1 One RegLocation 1094 * @param rl_op2 The other RegLocation 1095 * @return 'true' if the VR pairs overlap 1096 * 1097 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1098 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1099 * dex, we'll want to make this case illegal. 1100 */ 1101 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1102 1103 /* 1104 * @brief Force a location (in a register) into a temporary register 1105 * @param loc location of result 1106 * @returns update location 1107 */ 1108 RegLocation ForceTemp(RegLocation loc); 1109 1110 /* 1111 * @brief Force a wide location (in registers) into temporary registers 1112 * @param loc location of result 1113 * @returns update location 1114 */ 1115 RegLocation ForceTempWide(RegLocation loc); 1116 1117 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1118 RegLocation rl_dest, RegLocation rl_src); 1119 1120 void AddSlowPath(LIRSlowPath* slowpath); 1121 1122 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1123 bool type_known_abstract, bool use_declaring_class, 1124 bool can_assume_type_is_in_dex_cache, 1125 uint32_t type_idx, RegLocation rl_dest, 1126 RegLocation rl_src); 1127 /* 1128 * @brief Generate the debug_frame FDE information if possible. 1129 * @returns pointer to vector containg CFE information, or NULL. 1130 */ 1131 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1132 1133 /** 1134 * @brief Used to insert marker that can be used to associate MIR with LIR. 1135 * @details Only inserts marker if verbosity is enabled. 1136 * @param mir The mir that is currently being generated. 1137 */ 1138 void GenPrintLabel(MIR* mir); 1139 1140 /** 1141 * @brief Used to generate return sequence when there is no frame. 1142 * @details Assumes that the return registers have already been populated. 1143 */ 1144 virtual void GenSpecialExitSequence() = 0; 1145 1146 /** 1147 * @brief Used to generate code for special methods that are known to be 1148 * small enough to work in frameless mode. 1149 * @param bb The basic block of the first MIR. 1150 * @param mir The first MIR of the special method. 1151 * @param special Information about the special method. 1152 * @return Returns whether or not this was handled successfully. Returns false 1153 * if caller should punt to normal MIR2LIR conversion. 1154 */ 1155 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1156 1157 private: 1158 void ClobberBody(RegisterInfo* p); 1159 void ResetDefBody(RegisterInfo* p) { 1160 p->def_start = NULL; 1161 p->def_end = NULL; 1162 } 1163 1164 void SetCurrentDexPc(DexOffset dexpc) { 1165 current_dalvik_offset_ = dexpc; 1166 } 1167 1168 /** 1169 * @brief Used to lock register if argument at in_position was passed that way. 1170 * @details Does nothing if the argument is passed via stack. 1171 * @param in_position The argument number whose register to lock. 1172 * @param wide Whether the argument is wide. 1173 */ 1174 void LockArg(int in_position, bool wide = false); 1175 1176 /** 1177 * @brief Used to load VR argument to a physical register. 1178 * @details The load is only done if the argument is not already in physical register. 1179 * LockArg must have been previously called. 1180 * @param in_position The argument number to load. 1181 * @param wide Whether the argument is 64-bit or not. 1182 * @return Returns the register (or register pair) for the loaded argument. 1183 */ 1184 RegStorage LoadArg(int in_position, bool wide = false); 1185 1186 /** 1187 * @brief Used to load a VR argument directly to a specified register location. 1188 * @param in_position The argument number to place in register. 1189 * @param rl_dest The register location where to place argument. 1190 */ 1191 void LoadArgDirect(int in_position, RegLocation rl_dest); 1192 1193 /** 1194 * @brief Used to generate LIR for special getter method. 1195 * @param mir The mir that represents the iget. 1196 * @param special Information about the special getter method. 1197 * @return Returns whether LIR was successfully generated. 1198 */ 1199 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1200 1201 /** 1202 * @brief Used to generate LIR for special setter method. 1203 * @param mir The mir that represents the iput. 1204 * @param special Information about the special setter method. 1205 * @return Returns whether LIR was successfully generated. 1206 */ 1207 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1208 1209 /** 1210 * @brief Used to generate LIR for special return-args method. 1211 * @param mir The mir that represents the return of argument. 1212 * @param special Information about the special return-args method. 1213 * @return Returns whether LIR was successfully generated. 1214 */ 1215 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1216 1217 1218 public: 1219 // TODO: add accessors for these. 1220 LIR* literal_list_; // Constants. 1221 LIR* method_literal_list_; // Method literals requiring patching. 1222 LIR* class_literal_list_; // Class literals requiring patching. 1223 LIR* code_literal_list_; // Code literals requiring patching. 1224 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1225 1226 protected: 1227 CompilationUnit* const cu_; 1228 MIRGraph* const mir_graph_; 1229 GrowableArray<SwitchTable*> switch_tables_; 1230 GrowableArray<FillArrayData*> fill_array_data_; 1231 GrowableArray<LIR*> throw_launchpads_; 1232 GrowableArray<LIR*> suspend_launchpads_; 1233 GrowableArray<RegisterInfo*> tempreg_info_; 1234 GrowableArray<RegisterInfo*> reginfo_map_; 1235 GrowableArray<void*> pointer_storage_; 1236 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1237 CodeOffset data_offset_; // starting offset of literal pool. 1238 size_t total_size_; // header + code size. 1239 LIR* block_label_list_; 1240 PromotionMap* promotion_map_; 1241 /* 1242 * TODO: The code generation utilities don't have a built-in 1243 * mechanism to propagate the original Dalvik opcode address to the 1244 * associated generated instructions. For the trace compiler, this wasn't 1245 * necessary because the interpreter handled all throws and debugging 1246 * requests. For now we'll handle this by placing the Dalvik offset 1247 * in the CompilationUnit struct before codegen for each instruction. 1248 * The low-level LIR creation utilites will pull it from here. Rework this. 1249 */ 1250 DexOffset current_dalvik_offset_; 1251 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1252 RegisterPool* reg_pool_; 1253 /* 1254 * Sanity checking for the register temp tracking. The same ssa 1255 * name should never be associated with one temp register per 1256 * instruction compilation. 1257 */ 1258 int live_sreg_; 1259 CodeBuffer code_buffer_; 1260 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1261 std::vector<uint8_t> encoded_mapping_table_; 1262 std::vector<uint32_t> core_vmap_table_; 1263 std::vector<uint32_t> fp_vmap_table_; 1264 std::vector<uint8_t> native_gc_map_; 1265 int num_core_spills_; 1266 int num_fp_spills_; 1267 int frame_size_; 1268 unsigned int core_spill_mask_; 1269 unsigned int fp_spill_mask_; 1270 LIR* first_lir_insn_; 1271 LIR* last_lir_insn_; 1272 1273 GrowableArray<LIRSlowPath*> slow_paths_; 1274}; // Class Mir2Lir 1275 1276} // namespace art 1277 1278#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1279