mir_to_lir.h revision a0cd2d701f29e0bc6275f1b13c0edfd4ec391879
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF012 (REG_DEF0 | REG_DEF1 | REG_DEF2) 95#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 96#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 97#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 98#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 99#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 100#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 101#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 102#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 103#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 104#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 105#define REG_USE012 (REG_USE01 | REG_USE2) 106#define REG_USE014 (REG_USE01 | REG_USE4) 107#define REG_USE01 (REG_USE0 | REG_USE1) 108#define REG_USE02 (REG_USE0 | REG_USE2) 109#define REG_USE12 (REG_USE1 | REG_USE2) 110#define REG_USE23 (REG_USE2 | REG_USE3) 111#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 112 113// TODO: #includes need a cleanup 114#ifndef INVALID_SREG 115#define INVALID_SREG (-1) 116#endif 117 118struct BasicBlock; 119struct CallInfo; 120struct CompilationUnit; 121struct InlineMethod; 122struct MIR; 123struct LIR; 124struct RegLocation; 125struct RegisterInfo; 126class DexFileMethodInliner; 127class MIRGraph; 128class Mir2Lir; 129 130typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 131 const MethodReference& target_method, 132 uint32_t method_idx, uintptr_t direct_code, 133 uintptr_t direct_method, InvokeType type); 134 135typedef std::vector<uint8_t> CodeBuffer; 136 137struct UseDefMasks { 138 uint64_t use_mask; // Resource mask for use. 139 uint64_t def_mask; // Resource mask for def. 140}; 141 142struct AssemblyInfo { 143 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 144}; 145 146struct LIR { 147 CodeOffset offset; // Offset of this instruction. 148 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 149 int16_t opcode; 150 LIR* next; 151 LIR* prev; 152 LIR* target; 153 struct { 154 unsigned int alias_info:17; // For Dalvik register disambiguation. 155 bool is_nop:1; // LIR is optimized away. 156 unsigned int size:4; // Note: size of encoded instruction is in bytes. 157 bool use_def_invalid:1; // If true, masks should not be used. 158 unsigned int generation:1; // Used to track visitation state during fixup pass. 159 unsigned int fixup:8; // Fixup kind. 160 } flags; 161 union { 162 UseDefMasks m; // Use & Def masks used during optimization. 163 AssemblyInfo a; // Instruction info used during assembly phase. 164 } u; 165 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 166}; 167 168// Target-specific initialization. 169Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 170 ArenaAllocator* const arena); 171Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 172 ArenaAllocator* const arena); 173Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 174 ArenaAllocator* const arena); 175Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 176 ArenaAllocator* const arena); 177Mir2Lir* X86_64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 178 ArenaAllocator* const arena); 179 180// Utility macros to traverse the LIR list. 181#define NEXT_LIR(lir) (lir->next) 182#define PREV_LIR(lir) (lir->prev) 183 184// Defines for alias_info (tracks Dalvik register references). 185#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 186#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 187#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 188#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 189 190// Common resource macros. 191#define ENCODE_CCODE (1ULL << kCCode) 192#define ENCODE_FP_STATUS (1ULL << kFPStatus) 193 194// Abstract memory locations. 195#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 196#define ENCODE_LITERAL (1ULL << kLiteral) 197#define ENCODE_HEAP_REF (1ULL << kHeapRef) 198#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 199 200#define ENCODE_ALL (~0ULL) 201#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 202 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 203 204#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 205#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 206 do { \ 207 low_reg = both_regs & 0xff; \ 208 high_reg = (both_regs >> 8) & 0xff; \ 209 } while (false) 210 211// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 212#define STARTING_DOUBLE_SREG 0x10000 213 214// TODO: replace these macros 215#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 216#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 217#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 218#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 219#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 220 221class Mir2Lir : public Backend { 222 public: 223 /* 224 * Auxiliary information describing the location of data embedded in the Dalvik 225 * byte code stream. 226 */ 227 struct EmbeddedData { 228 CodeOffset offset; // Code offset of data block. 229 const uint16_t* table; // Original dex data. 230 DexOffset vaddr; // Dalvik offset of parent opcode. 231 }; 232 233 struct FillArrayData : EmbeddedData { 234 int32_t size; 235 }; 236 237 struct SwitchTable : EmbeddedData { 238 LIR* anchor; // Reference instruction for relative offsets. 239 LIR** targets; // Array of case targets. 240 }; 241 242 /* Static register use counts */ 243 struct RefCounts { 244 int count; 245 int s_reg; 246 }; 247 248 /* 249 * Data structure tracking the mapping detween a Dalvik value (32 or 64 bits) 250 * and native register storage. The primary purpose is to reuse previuosly 251 * loaded values, if possible, and otherwise to keep the value in register 252 * storage as long as possible. 253 * 254 * NOTE 1: wide_value refers to the width of the Dalvik value contained in 255 * this register (or pair). For example, a 64-bit register containing a 32-bit 256 * Dalvik value would have wide_value==false even though the storage container itself 257 * is wide. Similarly, a 32-bit register containing half of a 64-bit Dalvik value 258 * would have wide_value==true (and additionally would have its partner field set to the 259 * other half whose wide_value field would also be true. 260 * 261 * NOTE 2: In the case of a register pair, you can determine which of the partners 262 * is the low half by looking at the s_reg names. The high s_reg will equal low_sreg + 1. 263 * 264 * NOTE 3: In the case of a 64-bit register holding a Dalvik wide value, wide_value 265 * will be true and partner==self. s_reg refers to the low-order word of the Dalvik 266 * value, and the s_reg of the high word is implied (s_reg + 1). 267 * 268 * NOTE 4: The reg and is_temp fields should always be correct. If is_temp is false no 269 * other fields have meaning. [perhaps not true, wide should work for promoted regs?] 270 * If is_temp==true and live==false, no other fields have 271 * meaning. If is_temp==true and live==true, wide_value, partner, dirty, s_reg, def_start 272 * and def_end describe the relationship between the temp register/register pair and 273 * the Dalvik value[s] described by s_reg/s_reg+1. 274 * 275 * The fields used_storage, master_storage and storage_mask are used to track allocation 276 * in light of potential aliasing. For example, consider Arm's d2, which overlaps s4 & s5. 277 * d2's storage mask would be 0x00000003, the two low-order bits denoting 64 bits of 278 * storage use. For s4, it would be 0x0000001; for s5 0x00000002. These values should not 279 * change once initialized. The "used_storage" field tracks current allocation status. 280 * Although each record contains this field, only the field from the largest member of 281 * an aliased group is used. In our case, it would be d2's. The master_storage pointer 282 * of d2, s4 and s5 would all point to d2's used_storage field. Each bit in a used_storage 283 * represents 32 bits of storage. d2's used_storage would be initialized to 0xfffffffc. 284 * Then, if we wanted to determine whether s4 could be allocated, we would "and" 285 * s4's storage_mask with s4's *master_storage. If the result is zero, s4 is free and 286 * to allocate: *master_storage |= storage_mask. To free, *master_storage &= ~storage_mask. 287 * 288 * For an X86 vector register example, storage_mask would be: 289 * 0x00000001 for 32-bit view of xmm1 290 * 0x00000003 for 64-bit view of xmm1 291 * 0x0000000f for 128-bit view of xmm1 292 * 0x000000ff for 256-bit view of ymm1 // future expansion, if needed 293 * 0x0000ffff for 512-bit view of ymm1 // future expansion, if needed 294 * 0xffffffff for 1024-bit view of ymm1 // future expansion, if needed 295 * 296 * The "liveness" of a register is handled in a similar way. The liveness_ storage is 297 * held in the widest member of an aliased set. Note, though, that for a temp register to 298 * reused as live, it must both be marked live and the associated SReg() must match the 299 * desired s_reg. This gets a little complicated when dealing with aliased registers. All 300 * members of an aliased set will share the same liveness flags, but each will individually 301 * maintain s_reg_. In this way we can know that at least one member of an 302 * aliased set is live, but will only fully match on the appropriate alias view. For example, 303 * if Arm d1 is live as a double and has s_reg_ set to Dalvik v8 (which also implies v9 304 * because it is wide), its aliases s2 and s3 will show as live, but will have 305 * s_reg_ == INVALID_SREG. An attempt to later AllocLiveReg() of v9 with a single-precision 306 * view will fail because although s3's liveness bit is set, its s_reg_ will not match v9. 307 * This will cause all members of the aliased set to be clobbered and AllocLiveReg() will 308 * report that v9 is currently not live as a single (which is what we want). 309 * 310 * NOTE: the x86 usage is still somewhat in flux. There are competing notions of how 311 * to treat xmm registers: 312 * 1. Treat them all as 128-bits wide, but denote how much data used via bytes field. 313 * o This more closely matches reality, but means you'd need to be able to get 314 * to the associated RegisterInfo struct to figure out how it's being used. 315 * o This is how 64-bit core registers will be used - always 64 bits, but the 316 * "bytes" field will be 4 for 32-bit usage and 8 for 64-bit usage. 317 * 2. View the xmm registers based on contents. 318 * o A single in a xmm2 register would be k32BitVector, while a double in xmm2 would 319 * be a k64BitVector. 320 * o Note that the two uses above would be considered distinct registers (but with 321 * the aliasing mechanism, we could detect interference). 322 * o This is how aliased double and single float registers will be handled on 323 * Arm and MIPS. 324 * Working plan is, for all targets, to follow mechanism 1 for 64-bit core registers, and 325 * mechanism 2 for aliased float registers and x86 vector registers. 326 */ 327 class RegisterInfo { 328 public: 329 RegisterInfo(RegStorage r, uint64_t mask = ENCODE_ALL); 330 ~RegisterInfo() {} 331 static void* operator new(size_t size, ArenaAllocator* arena) { 332 return arena->Alloc(size, kArenaAllocRegAlloc); 333 } 334 335 static const uint32_t k32SoloStorageMask = 0x00000001; 336 static const uint32_t kLowSingleStorageMask = 0x00000001; 337 static const uint32_t kHighSingleStorageMask = 0x00000002; 338 static const uint32_t k64SoloStorageMask = 0x00000003; 339 static const uint32_t k128SoloStorageMask = 0x0000000f; 340 static const uint32_t k256SoloStorageMask = 0x000000ff; 341 static const uint32_t k512SoloStorageMask = 0x0000ffff; 342 static const uint32_t k1024SoloStorageMask = 0xffffffff; 343 344 bool InUse() { return (storage_mask_ & master_->used_storage_) != 0; } 345 void MarkInUse() { master_->used_storage_ |= storage_mask_; } 346 void MarkFree() { master_->used_storage_ &= ~storage_mask_; } 347 // No part of the containing storage is live in this view. 348 bool IsDead() { return (master_->liveness_ & storage_mask_) == 0; } 349 // Liveness of this view matches. Note: not equivalent to !IsDead(). 350 bool IsLive() { return (master_->liveness_ & storage_mask_) == storage_mask_; } 351 void MarkLive(int s_reg) { 352 // TODO: Anything useful to assert here? 353 s_reg_ = s_reg; 354 master_->liveness_ |= storage_mask_; 355 } 356 void MarkDead() { 357 if (SReg() != INVALID_SREG) { 358 s_reg_ = INVALID_SREG; 359 master_->liveness_ &= ~storage_mask_; 360 ResetDefBody(); 361 } 362 } 363 RegStorage GetReg() { return reg_; } 364 void SetReg(RegStorage reg) { reg_ = reg; } 365 bool IsTemp() { return is_temp_; } 366 void SetIsTemp(bool val) { is_temp_ = val; } 367 bool IsWide() { return wide_value_; } 368 void SetIsWide(bool val) { 369 wide_value_ = val; 370 if (!val) { 371 // If not wide, reset partner to self. 372 SetPartner(GetReg()); 373 } 374 } 375 bool IsDirty() { return dirty_; } 376 void SetIsDirty(bool val) { dirty_ = val; } 377 RegStorage Partner() { return partner_; } 378 void SetPartner(RegStorage partner) { partner_ = partner; } 379 int SReg() { return (!IsTemp() || IsLive()) ? s_reg_ : INVALID_SREG; } 380 uint64_t DefUseMask() { return def_use_mask_; } 381 void SetDefUseMask(uint64_t def_use_mask) { def_use_mask_ = def_use_mask; } 382 RegisterInfo* Master() { return master_; } 383 void SetMaster(RegisterInfo* master) { 384 master_ = master; 385 if (master != this) { 386 master_->aliased_ = true; 387 DCHECK(alias_chain_ == nullptr); 388 alias_chain_ = master_->alias_chain_; 389 master_->alias_chain_ = this; 390 } 391 } 392 bool IsAliased() { return aliased_; } 393 RegisterInfo* GetAliasChain() { return alias_chain_; } 394 uint32_t StorageMask() { return storage_mask_; } 395 void SetStorageMask(uint32_t storage_mask) { storage_mask_ = storage_mask; } 396 LIR* DefStart() { return def_start_; } 397 void SetDefStart(LIR* def_start) { def_start_ = def_start; } 398 LIR* DefEnd() { return def_end_; } 399 void SetDefEnd(LIR* def_end) { def_end_ = def_end; } 400 void ResetDefBody() { def_start_ = def_end_ = nullptr; } 401 // Find member of aliased set matching storage_used; return nullptr if none. 402 RegisterInfo* FindMatchingView(uint32_t storage_used) { 403 RegisterInfo* res = Master(); 404 for (; res != nullptr; res = res->GetAliasChain()) { 405 if (res->StorageMask() == storage_used) 406 break; 407 } 408 return res; 409 } 410 411 private: 412 RegStorage reg_; 413 bool is_temp_; // Can allocate as temp? 414 bool wide_value_; // Holds a Dalvik wide value (either itself, or part of a pair). 415 bool dirty_; // If live, is it dirty? 416 bool aliased_; // Is this the master for other aliased RegisterInfo's? 417 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register. 418 int s_reg_; // Name of live value. 419 uint64_t def_use_mask_; // Resources for this element. 420 uint32_t used_storage_; // 1 bit per 4 bytes of storage. Unused by aliases. 421 uint32_t liveness_; // 1 bit per 4 bytes of storage. Unused by aliases. 422 RegisterInfo* master_; // Pointer to controlling storage mask. 423 uint32_t storage_mask_; // Track allocation of sub-units. 424 LIR *def_start_; // Starting inst in last def sequence. 425 LIR *def_end_; // Ending inst in last def sequence. 426 RegisterInfo* alias_chain_; // Chain of aliased registers. 427 }; 428 429 class RegisterPool { 430 public: 431 RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, 432 const std::vector<RegStorage>& core_regs, 433 const std::vector<RegStorage>& core64_regs, 434 const std::vector<RegStorage>& sp_regs, 435 const std::vector<RegStorage>& dp_regs, 436 const std::vector<RegStorage>& reserved_regs, 437 const std::vector<RegStorage>& reserved64_regs, 438 const std::vector<RegStorage>& core_temps, 439 const std::vector<RegStorage>& core64_temps, 440 const std::vector<RegStorage>& sp_temps, 441 const std::vector<RegStorage>& dp_temps); 442 ~RegisterPool() {} 443 static void* operator new(size_t size, ArenaAllocator* arena) { 444 return arena->Alloc(size, kArenaAllocRegAlloc); 445 } 446 void ResetNextTemp() { 447 next_core_reg_ = 0; 448 next_sp_reg_ = 0; 449 next_dp_reg_ = 0; 450 } 451 GrowableArray<RegisterInfo*> core_regs_; 452 int next_core_reg_; 453 GrowableArray<RegisterInfo*> core64_regs_; 454 int next_core64_reg_; 455 GrowableArray<RegisterInfo*> sp_regs_; // Single precision float. 456 int next_sp_reg_; 457 GrowableArray<RegisterInfo*> dp_regs_; // Double precision float. 458 int next_dp_reg_; 459 GrowableArray<RegisterInfo*>* ref_regs_; // Points to core_regs_ or core64_regs_ 460 int* next_ref_reg_; 461 462 private: 463 Mir2Lir* const m2l_; 464 }; 465 466 struct PromotionMap { 467 RegLocationType core_location:3; 468 uint8_t core_reg; 469 RegLocationType fp_location:3; 470 uint8_t FpReg; 471 bool first_in_pair; 472 }; 473 474 // 475 // Slow paths. This object is used generate a sequence of code that is executed in the 476 // slow path. For example, resolving a string or class is slow as it will only be executed 477 // once (after that it is resolved and doesn't need to be done again). We want slow paths 478 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 479 // branch over them. 480 // 481 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 482 // the Compile() function that will be called near the end of the code generated by the 483 // method. 484 // 485 // The basic flow for a slow path is: 486 // 487 // CMP reg, #value 488 // BEQ fromfast 489 // cont: 490 // ... 491 // fast path code 492 // ... 493 // more code 494 // ... 495 // RETURN 496 /// 497 // fromfast: 498 // ... 499 // slow path code 500 // ... 501 // B cont 502 // 503 // So you see we need two labels and two branches. The first branch (called fromfast) is 504 // the conditional branch to the slow path code. The second label (called cont) is used 505 // as an unconditional branch target for getting back to the code after the slow path 506 // has completed. 507 // 508 509 class LIRSlowPath { 510 public: 511 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 512 LIR* cont = nullptr) : 513 m2l_(m2l), cu_(m2l->cu_), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 514 m2l->StartSlowPath(cont); 515 } 516 virtual ~LIRSlowPath() {} 517 virtual void Compile() = 0; 518 519 static void* operator new(size_t size, ArenaAllocator* arena) { 520 return arena->Alloc(size, kArenaAllocData); 521 } 522 523 LIR *GetContinuationLabel() { 524 return cont_; 525 } 526 527 LIR *GetFromFast() { 528 return fromfast_; 529 } 530 531 protected: 532 LIR* GenerateTargetLabel(int opcode = kPseudoTargetLabel); 533 534 Mir2Lir* const m2l_; 535 CompilationUnit* const cu_; 536 const DexOffset current_dex_pc_; 537 LIR* const fromfast_; 538 LIR* const cont_; 539 }; 540 541 virtual ~Mir2Lir() {} 542 543 int32_t s4FromSwitchData(const void* switch_data) { 544 return *reinterpret_cast<const int32_t*>(switch_data); 545 } 546 547 /* 548 * TODO: this is a trace JIT vestige, and its use should be reconsidered. At the time 549 * it was introduced, it was intended to be a quick best guess of type without having to 550 * take the time to do type analysis. Currently, though, we have a much better idea of 551 * the types of Dalvik virtual registers. Instead of using this for a best guess, why not 552 * just use our knowledge of type to select the most appropriate register class? 553 */ 554 RegisterClass RegClassBySize(OpSize size) { 555 if (size == kReference) { 556 return kRefReg; 557 } else { 558 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 559 size == kSignedByte) ? kCoreReg : kAnyReg; 560 } 561 } 562 563 size_t CodeBufferSizeInBytes() { 564 return code_buffer_.size() / sizeof(code_buffer_[0]); 565 } 566 567 static bool IsPseudoLirOp(int opcode) { 568 return (opcode < 0); 569 } 570 571 /* 572 * LIR operands are 32-bit integers. Sometimes, (especially for managing 573 * instructions which require PC-relative fixups), we need the operands to carry 574 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 575 * hold that index in the operand array. 576 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 577 * may be worth conditionally-compiling a set of identity functions here. 578 */ 579 uint32_t WrapPointer(void* pointer) { 580 uint32_t res = pointer_storage_.Size(); 581 pointer_storage_.Insert(pointer); 582 return res; 583 } 584 585 void* UnwrapPointer(size_t index) { 586 return pointer_storage_.Get(index); 587 } 588 589 // strdup(), but allocates from the arena. 590 char* ArenaStrdup(const char* str) { 591 size_t len = strlen(str) + 1; 592 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 593 if (res != NULL) { 594 strncpy(res, str, len); 595 } 596 return res; 597 } 598 599 // Shared by all targets - implemented in codegen_util.cc 600 void AppendLIR(LIR* lir); 601 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 602 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 603 604 /** 605 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 606 * to place in a frame. 607 * @return Returns the maximum number of compiler temporaries. 608 */ 609 size_t GetMaxPossibleCompilerTemps() const; 610 611 /** 612 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 613 * @return Returns the size in bytes for space needed for compiler temporary spill region. 614 */ 615 size_t GetNumBytesForCompilerTempSpillRegion(); 616 617 DexOffset GetCurrentDexPc() const { 618 return current_dalvik_offset_; 619 } 620 621 RegisterClass ShortyToRegClass(char shorty_type); 622 RegisterClass LocToRegClass(RegLocation loc); 623 int ComputeFrameSize(); 624 virtual void Materialize(); 625 virtual CompiledMethod* GetCompiledMethod(); 626 void MarkSafepointPC(LIR* inst); 627 void SetupResourceMasks(LIR* lir, bool leave_mem_ref = false); 628 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 629 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 630 void SetupRegMask(uint64_t* mask, int reg); 631 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 632 void DumpPromotionMap(); 633 void CodegenDump(); 634 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 635 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 636 LIR* NewLIR0(int opcode); 637 LIR* NewLIR1(int opcode, int dest); 638 LIR* NewLIR2(int opcode, int dest, int src1); 639 LIR* NewLIR2NoDest(int opcode, int src, int info); 640 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 641 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 642 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 643 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 644 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 645 LIR* ScanLiteralPoolMethod(LIR* data_target, const MethodReference& method); 646 LIR* AddWordData(LIR* *constant_list_p, int value); 647 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 648 void ProcessSwitchTables(); 649 void DumpSparseSwitchTable(const uint16_t* table); 650 void DumpPackedSwitchTable(const uint16_t* table); 651 void MarkBoundary(DexOffset offset, const char* inst_str); 652 void NopLIR(LIR* lir); 653 void UnlinkLIR(LIR* lir); 654 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 655 bool IsInexpensiveConstant(RegLocation rl_src); 656 ConditionCode FlipComparisonOrder(ConditionCode before); 657 ConditionCode NegateComparison(ConditionCode before); 658 virtual void InstallLiteralPools(); 659 void InstallSwitchTables(); 660 void InstallFillArrayData(); 661 bool VerifyCatchEntries(); 662 void CreateMappingTables(); 663 void CreateNativeGcMap(); 664 int AssignLiteralOffset(CodeOffset offset); 665 int AssignSwitchTablesOffset(CodeOffset offset); 666 int AssignFillArrayDataOffset(CodeOffset offset); 667 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 668 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 669 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 670 671 virtual void StartSlowPath(LIR *label) {} 672 virtual void BeginInvoke(CallInfo* info) {} 673 virtual void EndInvoke(CallInfo* info) {} 674 675 676 // Handle bookkeeping to convert a wide RegLocation to a narrow RegLocation. No code generated. 677 RegLocation NarrowRegLoc(RegLocation loc); 678 679 // Shared by all targets - implemented in local_optimizations.cc 680 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 681 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 682 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 683 virtual void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 684 685 // Shared by all targets - implemented in ralloc_util.cc 686 int GetSRegHi(int lowSreg); 687 bool LiveOut(int s_reg); 688 void SimpleRegAlloc(); 689 void ResetRegPool(); 690 void CompilerInitPool(RegisterInfo* info, RegStorage* regs, int num); 691 void DumpRegPool(GrowableArray<RegisterInfo*>* regs); 692 void DumpCoreRegPool(); 693 void DumpFpRegPool(); 694 void DumpRegPools(); 695 /* Mark a temp register as dead. Does not affect allocation state. */ 696 void Clobber(RegStorage reg); 697 void ClobberSReg(int s_reg); 698 void ClobberAliases(RegisterInfo* info, uint32_t clobber_mask); 699 int SRegToPMap(int s_reg); 700 void RecordCorePromotion(RegStorage reg, int s_reg); 701 RegStorage AllocPreservedCoreReg(int s_reg); 702 void RecordSinglePromotion(RegStorage reg, int s_reg); 703 void RecordDoublePromotion(RegStorage reg, int s_reg); 704 RegStorage AllocPreservedSingle(int s_reg); 705 virtual RegStorage AllocPreservedDouble(int s_reg); 706 RegStorage AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required); 707 virtual RegStorage AllocFreeTemp(); 708 virtual RegStorage AllocTemp(); 709 virtual RegStorage AllocTempWide(); 710 virtual RegStorage AllocTempRef(); 711 virtual RegStorage AllocTempSingle(); 712 virtual RegStorage AllocTempDouble(); 713 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class); 714 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); 715 void FlushReg(RegStorage reg); 716 void FlushRegWide(RegStorage reg); 717 RegStorage AllocLiveReg(int s_reg, int reg_class, bool wide); 718 RegStorage FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg); 719 virtual void FreeTemp(RegStorage reg); 720 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 721 virtual bool IsLive(RegStorage reg); 722 virtual bool IsTemp(RegStorage reg); 723 bool IsPromoted(RegStorage reg); 724 bool IsDirty(RegStorage reg); 725 void LockTemp(RegStorage reg); 726 void ResetDef(RegStorage reg); 727 void NullifyRange(RegStorage reg, int s_reg); 728 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 729 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 730 void ResetDefLoc(RegLocation rl); 731 void ResetDefLocWide(RegLocation rl); 732 void ResetDefTracking(); 733 void ClobberAllTemps(); 734 void FlushSpecificReg(RegisterInfo* info); 735 void FlushAllRegs(); 736 bool RegClassMatches(int reg_class, RegStorage reg); 737 void MarkLive(RegLocation loc); 738 void MarkTemp(RegStorage reg); 739 void UnmarkTemp(RegStorage reg); 740 void MarkWide(RegStorage reg); 741 void MarkNarrow(RegStorage reg); 742 void MarkClean(RegLocation loc); 743 void MarkDirty(RegLocation loc); 744 void MarkInUse(RegStorage reg); 745 bool CheckCorePoolSanity(); 746 virtual RegLocation UpdateLoc(RegLocation loc); 747 virtual RegLocation UpdateLocWide(RegLocation loc); 748 RegLocation UpdateRawLoc(RegLocation loc); 749 750 /** 751 * @brief Used to prepare a register location to receive a wide value. 752 * @see EvalLoc 753 * @param loc the location where the value will be stored. 754 * @param reg_class Type of register needed. 755 * @param update Whether the liveness information should be updated. 756 * @return Returns the properly typed temporary in physical register pairs. 757 */ 758 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 759 760 /** 761 * @brief Used to prepare a register location to receive a value. 762 * @param loc the location where the value will be stored. 763 * @param reg_class Type of register needed. 764 * @param update Whether the liveness information should be updated. 765 * @return Returns the properly typed temporary in physical register. 766 */ 767 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 768 769 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 770 void DumpCounts(const RefCounts* arr, int size, const char* msg); 771 void DoPromotion(); 772 int VRegOffset(int v_reg); 773 int SRegOffset(int s_reg); 774 RegLocation GetReturnWide(RegisterClass reg_class); 775 RegLocation GetReturn(RegisterClass reg_class); 776 RegisterInfo* GetRegInfo(RegStorage reg); 777 778 // Shared by all targets - implemented in gen_common.cc. 779 void AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume = nullptr); 780 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 781 RegLocation rl_src, RegLocation rl_dest, int lit); 782 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 783 virtual void HandleSlowPaths(); 784 void GenBarrier(); 785 void GenDivZeroException(); 786 // c_code holds condition code that's generated from testing divisor against 0. 787 void GenDivZeroCheck(ConditionCode c_code); 788 // reg holds divisor. 789 void GenDivZeroCheck(RegStorage reg); 790 void GenArrayBoundsCheck(RegStorage index, RegStorage length); 791 void GenArrayBoundsCheck(int32_t index, RegStorage length); 792 LIR* GenNullCheck(RegStorage reg); 793 void MarkPossibleNullPointerException(int opt_flags); 794 void MarkPossibleStackOverflowException(); 795 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 796 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 797 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 798 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 799 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 800 RegLocation rl_src2, LIR* taken, LIR* fall_through); 801 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 802 LIR* taken, LIR* fall_through); 803 virtual void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 804 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 805 RegLocation rl_src); 806 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 807 RegLocation rl_src); 808 void GenFilledNewArray(CallInfo* info); 809 void GenSput(MIR* mir, RegLocation rl_src, 810 bool is_long_or_double, bool is_object); 811 void GenSget(MIR* mir, RegLocation rl_dest, 812 bool is_long_or_double, bool is_object); 813 void GenIGet(MIR* mir, int opt_flags, OpSize size, 814 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 815 void GenIPut(MIR* mir, int opt_flags, OpSize size, 816 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 817 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 818 RegLocation rl_src); 819 820 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 821 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 822 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 823 void GenThrow(RegLocation rl_src); 824 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 825 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 826 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 827 RegLocation rl_src1, RegLocation rl_src2); 828 virtual void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 829 RegLocation rl_src1, RegLocation rl_shift); 830 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 831 RegLocation rl_src, int lit); 832 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 833 RegLocation rl_src1, RegLocation rl_src2); 834 template <size_t pointer_size> 835 void GenConversionCall(ThreadOffset<pointer_size> func_offset, RegLocation rl_dest, 836 RegLocation rl_src); 837 virtual void GenSuspendTest(int opt_flags); 838 virtual void GenSuspendTestAndBranch(int opt_flags, LIR* target); 839 840 // This will be overridden by x86 implementation. 841 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 842 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 843 RegLocation rl_src1, RegLocation rl_src2); 844 845 // Shared by all targets - implemented in gen_invoke.cc. 846 template <size_t pointer_size> 847 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<pointer_size> helper_offset, bool safepoint_pc, 848 bool use_link = true); 849 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 850 RegStorage CallHelperSetup(ThreadOffset<8> helper_offset); 851 template <size_t pointer_size> 852 void CallRuntimeHelper(ThreadOffset<pointer_size> helper_offset, bool safepoint_pc); 853 template <size_t pointer_size> 854 void CallRuntimeHelperImm(ThreadOffset<pointer_size> helper_offset, int arg0, bool safepoint_pc); 855 template <size_t pointer_size> 856 void CallRuntimeHelperReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, bool safepoint_pc); 857 template <size_t pointer_size> 858 void CallRuntimeHelperRegLocation(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 859 bool safepoint_pc); 860 template <size_t pointer_size> 861 void CallRuntimeHelperImmImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg1, 862 bool safepoint_pc); 863 template <size_t pointer_size> 864 void CallRuntimeHelperImmRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 865 RegLocation arg1, bool safepoint_pc); 866 template <size_t pointer_size> 867 void CallRuntimeHelperRegLocationImm(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 868 int arg1, bool safepoint_pc); 869 template <size_t pointer_size> 870 void CallRuntimeHelperImmReg(ThreadOffset<pointer_size> helper_offset, int arg0, RegStorage arg1, 871 bool safepoint_pc); 872 template <size_t pointer_size> 873 void CallRuntimeHelperRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, int arg1, 874 bool safepoint_pc); 875 template <size_t pointer_size> 876 void CallRuntimeHelperImmMethod(ThreadOffset<pointer_size> helper_offset, int arg0, 877 bool safepoint_pc); 878 template <size_t pointer_size> 879 void CallRuntimeHelperRegMethod(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 880 bool safepoint_pc); 881 template <size_t pointer_size> 882 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<pointer_size> helper_offset, 883 RegStorage arg0, RegLocation arg2, bool safepoint_pc); 884 template <size_t pointer_size> 885 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 886 RegLocation arg0, RegLocation arg1, 887 bool safepoint_pc); 888 template <size_t pointer_size> 889 void CallRuntimeHelperRegReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 890 RegStorage arg1, bool safepoint_pc); 891 template <size_t pointer_size> 892 void CallRuntimeHelperRegRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 893 RegStorage arg1, int arg2, bool safepoint_pc); 894 template <size_t pointer_size> 895 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 896 RegLocation arg2, bool safepoint_pc); 897 template <size_t pointer_size> 898 void CallRuntimeHelperImmMethodImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg2, 899 bool safepoint_pc); 900 template <size_t pointer_size> 901 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 902 int arg0, RegLocation arg1, RegLocation arg2, 903 bool safepoint_pc); 904 template <size_t pointer_size> 905 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 906 RegLocation arg0, RegLocation arg1, 907 RegLocation arg2, 908 bool safepoint_pc); 909 void GenInvoke(CallInfo* info); 910 void GenInvokeNoInline(CallInfo* info); 911 virtual void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 912 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 913 NextCallInsn next_call_insn, 914 const MethodReference& target_method, 915 uint32_t vtable_idx, 916 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 917 bool skip_this); 918 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 919 NextCallInsn next_call_insn, 920 const MethodReference& target_method, 921 uint32_t vtable_idx, 922 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 923 bool skip_this); 924 925 /** 926 * @brief Used to determine the register location of destination. 927 * @details This is needed during generation of inline intrinsics because it finds destination 928 * of return, 929 * either the physical register or the target of move-result. 930 * @param info Information about the invoke. 931 * @return Returns the destination location. 932 */ 933 RegLocation InlineTarget(CallInfo* info); 934 935 /** 936 * @brief Used to determine the wide register location of destination. 937 * @see InlineTarget 938 * @param info Information about the invoke. 939 * @return Returns the destination location. 940 */ 941 RegLocation InlineTargetWide(CallInfo* info); 942 943 bool GenInlinedCharAt(CallInfo* info); 944 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 945 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 946 bool GenInlinedAbsInt(CallInfo* info); 947 bool GenInlinedAbsLong(CallInfo* info); 948 bool GenInlinedAbsFloat(CallInfo* info); 949 bool GenInlinedAbsDouble(CallInfo* info); 950 bool GenInlinedFloatCvt(CallInfo* info); 951 bool GenInlinedDoubleCvt(CallInfo* info); 952 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 953 bool GenInlinedStringCompareTo(CallInfo* info); 954 bool GenInlinedCurrentThread(CallInfo* info); 955 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 956 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 957 bool is_volatile, bool is_ordered); 958 virtual int LoadArgRegs(CallInfo* info, int call_state, 959 NextCallInsn next_call_insn, 960 const MethodReference& target_method, 961 uint32_t vtable_idx, 962 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 963 bool skip_this); 964 965 // Shared by all targets - implemented in gen_loadstore.cc. 966 RegLocation LoadCurrMethod(); 967 void LoadCurrMethodDirect(RegStorage r_tgt); 968 virtual LIR* LoadConstant(RegStorage r_dest, int value); 969 // Natural word size. 970 virtual LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 971 return LoadBaseDisp(r_base, displacement, r_dest, kWord); 972 } 973 // Load 32 bits, regardless of target. 974 virtual LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { 975 return LoadBaseDisp(r_base, displacement, r_dest, k32); 976 } 977 // Load a reference at base + displacement and decompress into register. 978 virtual LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 979 return LoadBaseDisp(r_base, displacement, r_dest, kReference); 980 } 981 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 982 virtual RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 983 // Same as above, but derive the target register class from the location record. 984 virtual RegLocation LoadValue(RegLocation rl_src); 985 // Load Dalvik value with 64-bit memory storage. 986 virtual RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 987 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 988 virtual void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 989 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 990 virtual void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 991 // Load Dalvik value with 64-bit memory storage. 992 virtual void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 993 // Load Dalvik value with 64-bit memory storage. 994 virtual void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 995 // Store an item of natural word size. 996 virtual LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { 997 return StoreBaseDisp(r_base, displacement, r_src, kWord); 998 } 999 // Store an uncompressed reference into a compressed 32-bit container. 1000 virtual LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src) { 1001 return StoreBaseDisp(r_base, displacement, r_src, kReference); 1002 } 1003 // Store 32 bits, regardless of target. 1004 virtual LIR* Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) { 1005 return StoreBaseDisp(r_base, displacement, r_src, k32); 1006 } 1007 1008 /** 1009 * @brief Used to do the final store in the destination as per bytecode semantics. 1010 * @param rl_dest The destination dalvik register location. 1011 * @param rl_src The source register location. Can be either physical register or dalvik register. 1012 */ 1013 virtual void StoreValue(RegLocation rl_dest, RegLocation rl_src); 1014 1015 /** 1016 * @brief Used to do the final store in a wide destination as per bytecode semantics. 1017 * @see StoreValue 1018 * @param rl_dest The destination dalvik register location. 1019 * @param rl_src The source register location. Can be either physical register or dalvik 1020 * register. 1021 */ 1022 virtual void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 1023 1024 /** 1025 * @brief Used to do the final store to a destination as per bytecode semantics. 1026 * @see StoreValue 1027 * @param rl_dest The destination dalvik register location. 1028 * @param rl_src The source register location. It must be kLocPhysReg 1029 * 1030 * This is used for x86 two operand computations, where we have computed the correct 1031 * register value that now needs to be properly registered. This is used to avoid an 1032 * extra register copy that would result if StoreValue was called. 1033 */ 1034 virtual void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 1035 1036 /** 1037 * @brief Used to do the final store in a wide destination as per bytecode semantics. 1038 * @see StoreValueWide 1039 * @param rl_dest The destination dalvik register location. 1040 * @param rl_src The source register location. It must be kLocPhysReg 1041 * 1042 * This is used for x86 two operand computations, where we have computed the correct 1043 * register values that now need to be properly registered. This is used to avoid an 1044 * extra pair of register copies that would result if StoreValueWide was called. 1045 */ 1046 virtual void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 1047 1048 // Shared by all targets - implemented in mir_to_lir.cc. 1049 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 1050 virtual void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1051 bool MethodBlockCodeGen(BasicBlock* bb); 1052 bool SpecialMIR2LIR(const InlineMethod& special); 1053 virtual void MethodMIR2LIR(); 1054 // Update LIR for verbose listings. 1055 void UpdateLIROffsets(); 1056 1057 /* 1058 * @brief Load the address of the dex method into the register. 1059 * @param target_method The MethodReference of the method to be invoked. 1060 * @param type How the method will be invoked. 1061 * @param register that will contain the code address. 1062 * @note register will be passed to TargetReg to get physical register. 1063 */ 1064 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 1065 SpecialTargetRegister symbolic_reg); 1066 1067 /* 1068 * @brief Load the Method* of a dex method into the register. 1069 * @param target_method The MethodReference of the method to be invoked. 1070 * @param type How the method will be invoked. 1071 * @param register that will contain the code address. 1072 * @note register will be passed to TargetReg to get physical register. 1073 */ 1074 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 1075 SpecialTargetRegister symbolic_reg); 1076 1077 /* 1078 * @brief Load the Class* of a Dex Class type into the register. 1079 * @param type How the method will be invoked. 1080 * @param register that will contain the code address. 1081 * @note register will be passed to TargetReg to get physical register. 1082 */ 1083 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 1084 1085 // Routines that work for the generic case, but may be overriden by target. 1086 /* 1087 * @brief Compare memory to immediate, and branch if condition true. 1088 * @param cond The condition code that when true will branch to the target. 1089 * @param temp_reg A temporary register that can be used if compare to memory is not 1090 * supported by the architecture. 1091 * @param base_reg The register holding the base address. 1092 * @param offset The offset from the base. 1093 * @param check_value The immediate to compare to. 1094 * @returns The branch instruction that was generated. 1095 */ 1096 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 1097 int offset, int check_value, LIR* target); 1098 1099 // Required for target - codegen helpers. 1100 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1101 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1102 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1103 virtual LIR* CheckSuspendUsingLoad() = 0; 1104 1105 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 1106 virtual RegStorage LoadHelper(ThreadOffset<8> offset) = 0; 1107 1108 virtual LIR* LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, 1109 OpSize size) = 0; 1110 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 1111 OpSize size) = 0; 1112 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 1113 int scale, OpSize size) = 0; 1114 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1115 int displacement, RegStorage r_dest, OpSize size) = 0; 1116 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 1117 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 1118 virtual LIR* StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src, 1119 OpSize size) = 0; 1120 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 1121 OpSize size) = 0; 1122 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 1123 int scale, OpSize size) = 0; 1124 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1125 int displacement, RegStorage r_src, OpSize size) = 0; 1126 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 1127 1128 // Required for target - register utilities. 1129 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 1130 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 1131 virtual RegLocation GetReturnAlt() = 0; 1132 virtual RegLocation GetReturnWideAlt() = 0; 1133 virtual RegLocation LocCReturn() = 0; 1134 virtual RegLocation LocCReturnRef() = 0; 1135 virtual RegLocation LocCReturnDouble() = 0; 1136 virtual RegLocation LocCReturnFloat() = 0; 1137 virtual RegLocation LocCReturnWide() = 0; 1138 virtual uint64_t GetRegMaskCommon(RegStorage reg) = 0; 1139 virtual void AdjustSpillMask() = 0; 1140 virtual void ClobberCallerSave() = 0; 1141 virtual void FreeCallTemps() = 0; 1142 virtual void LockCallTemps() = 0; 1143 virtual void MarkPreservedSingle(int v_reg, RegStorage reg) = 0; 1144 virtual void MarkPreservedDouble(int v_reg, RegStorage reg) = 0; 1145 virtual void CompilerInitializeRegAlloc() = 0; 1146 1147 // Required for target - miscellaneous. 1148 virtual void AssembleLIR() = 0; 1149 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 1150 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 1151 virtual const char* GetTargetInstFmt(int opcode) = 0; 1152 virtual const char* GetTargetInstName(int opcode) = 0; 1153 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 1154 virtual uint64_t GetPCUseDefEncoding() = 0; 1155 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 1156 virtual int GetInsnSize(LIR* lir) = 0; 1157 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 1158 1159 // Check support for volatile load/store of a given size. 1160 virtual bool SupportsVolatileLoadStore(OpSize size) = 0; 1161 // Get the register class for load/store of a field. 1162 virtual RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) = 0; 1163 1164 // Required for target - Dalvik-level generators. 1165 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1166 RegLocation rl_src1, RegLocation rl_src2) = 0; 1167 virtual void GenMulLong(Instruction::Code, 1168 RegLocation rl_dest, RegLocation rl_src1, 1169 RegLocation rl_src2) = 0; 1170 virtual void GenAddLong(Instruction::Code, 1171 RegLocation rl_dest, RegLocation rl_src1, 1172 RegLocation rl_src2) = 0; 1173 virtual void GenAndLong(Instruction::Code, 1174 RegLocation rl_dest, RegLocation rl_src1, 1175 RegLocation rl_src2) = 0; 1176 virtual void GenArithOpDouble(Instruction::Code opcode, 1177 RegLocation rl_dest, RegLocation rl_src1, 1178 RegLocation rl_src2) = 0; 1179 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 1180 RegLocation rl_src1, RegLocation rl_src2) = 0; 1181 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 1182 RegLocation rl_src1, RegLocation rl_src2) = 0; 1183 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 1184 RegLocation rl_src) = 0; 1185 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 1186 1187 /** 1188 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 1189 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 1190 * that applies on integers. The generated code will write the smallest or largest value 1191 * directly into the destination register as specified by the invoke information. 1192 * @param info Information about the invoke. 1193 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 1194 * @return Returns true if successfully generated 1195 */ 1196 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 1197 1198 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 1199 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 1200 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 1201 virtual void GenNotLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1202 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1203 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1204 RegLocation rl_src2) = 0; 1205 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1206 RegLocation rl_src2) = 0; 1207 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1208 RegLocation rl_src2) = 0; 1209 virtual void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1210 RegLocation rl_src2, bool is_div) = 0; 1211 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 1212 bool is_div) = 0; 1213 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 1214 bool is_div) = 0; 1215 /* 1216 * @brief Generate an integer div or rem operation by a literal. 1217 * @param rl_dest Destination Location. 1218 * @param rl_src1 Numerator Location. 1219 * @param rl_src2 Divisor Location. 1220 * @param is_div 'true' if this is a division, 'false' for a remainder. 1221 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 1222 */ 1223 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 1224 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 1225 /* 1226 * @brief Generate an integer div or rem operation by a literal. 1227 * @param rl_dest Destination Location. 1228 * @param rl_src Numerator Location. 1229 * @param lit Divisor. 1230 * @param is_div 'true' if this is a division, 'false' for a remainder. 1231 */ 1232 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 1233 bool is_div) = 0; 1234 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 1235 1236 /** 1237 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 1238 * @details This is used for generating DivideByZero checks when divisor is held in two 1239 * separate registers. 1240 * @param reg The register holding the pair of 32-bit values. 1241 */ 1242 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 1243 1244 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 1245 virtual void GenExitSequence() = 0; 1246 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 1247 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 1248 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 1249 1250 /* 1251 * @brief Handle Machine Specific MIR Extended opcodes. 1252 * @param bb The basic block in which the MIR is from. 1253 * @param mir The MIR whose opcode is not standard extended MIR. 1254 * @note Base class implementation will abort for unknown opcodes. 1255 */ 1256 virtual void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1257 1258 /** 1259 * @brief Lowers the kMirOpSelect MIR into LIR. 1260 * @param bb The basic block in which the MIR is from. 1261 * @param mir The MIR whose opcode is kMirOpSelect. 1262 */ 1263 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 1264 1265 /** 1266 * @brief Used to generate a memory barrier in an architecture specific way. 1267 * @details The last generated LIR will be considered for use as barrier. Namely, 1268 * if the last LIR can be updated in a way where it will serve the semantics of 1269 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 1270 * that can keep the semantics. 1271 * @param barrier_kind The kind of memory barrier to generate. 1272 * @return whether a new instruction was generated. 1273 */ 1274 virtual bool GenMemBarrier(MemBarrierKind barrier_kind) = 0; 1275 1276 virtual void GenMoveException(RegLocation rl_dest) = 0; 1277 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 1278 int first_bit, int second_bit) = 0; 1279 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 1280 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 1281 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1282 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1283 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1284 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1285 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1286 RegLocation rl_index, RegLocation rl_src, int scale, 1287 bool card_mark) = 0; 1288 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1289 RegLocation rl_src1, RegLocation rl_shift) = 0; 1290 1291 // Required for target - single operation generators. 1292 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1293 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1294 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1295 LIR* target) = 0; 1296 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1297 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1298 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1299 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1300 virtual void OpEndIT(LIR* it) = 0; 1301 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1302 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1303 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1304 virtual void OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1305 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1306 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1307 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1308 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1309 1310 /** 1311 * @brief Used to generate an LIR that does a load from mem to reg. 1312 * @param r_dest The destination physical register. 1313 * @param r_base The base physical register for memory operand. 1314 * @param offset The displacement for memory operand. 1315 * @param move_type Specification on the move desired (size, alignment, register kind). 1316 * @return Returns the generate move LIR. 1317 */ 1318 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1319 MoveType move_type) = 0; 1320 1321 /** 1322 * @brief Used to generate an LIR that does a store from reg to mem. 1323 * @param r_base The base physical register for memory operand. 1324 * @param offset The displacement for memory operand. 1325 * @param r_src The destination physical register. 1326 * @param bytes_to_move The number of bytes to move. 1327 * @param is_aligned Whether the memory location is known to be aligned. 1328 * @return Returns the generate move LIR. 1329 */ 1330 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1331 MoveType move_type) = 0; 1332 1333 /** 1334 * @brief Used for generating a conditional register to register operation. 1335 * @param op The opcode kind. 1336 * @param cc The condition code that when true will perform the opcode. 1337 * @param r_dest The destination physical register. 1338 * @param r_src The source physical register. 1339 * @return Returns the newly created LIR or null in case of creation failure. 1340 */ 1341 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1342 1343 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1344 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1345 RegStorage r_src2) = 0; 1346 virtual LIR* OpTestSuspend(LIR* target) = 0; 1347 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1348 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) = 0; 1349 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1350 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1351 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1352 int offset) = 0; 1353 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1354 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1355 virtual void OpTlsCmp(ThreadOffset<8> offset, int val) = 0; 1356 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1357 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1358 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1359 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1360 1361 // May be optimized by targets. 1362 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1363 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1364 1365 // Temp workaround 1366 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1367 1368 protected: 1369 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1370 1371 CompilationUnit* GetCompilationUnit() { 1372 return cu_; 1373 } 1374 /* 1375 * @brief Returns the index of the lowest set bit in 'x'. 1376 * @param x Value to be examined. 1377 * @returns The bit number of the lowest bit set in the value. 1378 */ 1379 int32_t LowestSetBit(uint64_t x); 1380 /* 1381 * @brief Is this value a power of two? 1382 * @param x Value to be examined. 1383 * @returns 'true' if only 1 bit is set in the value. 1384 */ 1385 bool IsPowerOfTwo(uint64_t x); 1386 /* 1387 * @brief Do these SRs overlap? 1388 * @param rl_op1 One RegLocation 1389 * @param rl_op2 The other RegLocation 1390 * @return 'true' if the VR pairs overlap 1391 * 1392 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1393 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1394 * dex, we'll want to make this case illegal. 1395 */ 1396 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1397 1398 /* 1399 * @brief Force a location (in a register) into a temporary register 1400 * @param loc location of result 1401 * @returns update location 1402 */ 1403 virtual RegLocation ForceTemp(RegLocation loc); 1404 1405 /* 1406 * @brief Force a wide location (in registers) into temporary registers 1407 * @param loc location of result 1408 * @returns update location 1409 */ 1410 virtual RegLocation ForceTempWide(RegLocation loc); 1411 1412 static constexpr OpSize LoadStoreOpSize(bool wide, bool ref) { 1413 return wide ? k64 : ref ? kReference : k32; 1414 } 1415 1416 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1417 RegLocation rl_dest, RegLocation rl_src); 1418 1419 void AddSlowPath(LIRSlowPath* slowpath); 1420 1421 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1422 bool type_known_abstract, bool use_declaring_class, 1423 bool can_assume_type_is_in_dex_cache, 1424 uint32_t type_idx, RegLocation rl_dest, 1425 RegLocation rl_src); 1426 /* 1427 * @brief Generate the debug_frame FDE information if possible. 1428 * @returns pointer to vector containg CFE information, or NULL. 1429 */ 1430 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1431 1432 /** 1433 * @brief Used to insert marker that can be used to associate MIR with LIR. 1434 * @details Only inserts marker if verbosity is enabled. 1435 * @param mir The mir that is currently being generated. 1436 */ 1437 void GenPrintLabel(MIR* mir); 1438 1439 /** 1440 * @brief Used to generate return sequence when there is no frame. 1441 * @details Assumes that the return registers have already been populated. 1442 */ 1443 virtual void GenSpecialExitSequence() = 0; 1444 1445 /** 1446 * @brief Used to generate code for special methods that are known to be 1447 * small enough to work in frameless mode. 1448 * @param bb The basic block of the first MIR. 1449 * @param mir The first MIR of the special method. 1450 * @param special Information about the special method. 1451 * @return Returns whether or not this was handled successfully. Returns false 1452 * if caller should punt to normal MIR2LIR conversion. 1453 */ 1454 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1455 1456 protected: 1457 void ClobberBody(RegisterInfo* p); 1458 void SetCurrentDexPc(DexOffset dexpc) { 1459 current_dalvik_offset_ = dexpc; 1460 } 1461 1462 /** 1463 * @brief Used to lock register if argument at in_position was passed that way. 1464 * @details Does nothing if the argument is passed via stack. 1465 * @param in_position The argument number whose register to lock. 1466 * @param wide Whether the argument is wide. 1467 */ 1468 void LockArg(int in_position, bool wide = false); 1469 1470 /** 1471 * @brief Used to load VR argument to a physical register. 1472 * @details The load is only done if the argument is not already in physical register. 1473 * LockArg must have been previously called. 1474 * @param in_position The argument number to load. 1475 * @param wide Whether the argument is 64-bit or not. 1476 * @return Returns the register (or register pair) for the loaded argument. 1477 */ 1478 RegStorage LoadArg(int in_position, RegisterClass reg_class, bool wide = false); 1479 1480 /** 1481 * @brief Used to load a VR argument directly to a specified register location. 1482 * @param in_position The argument number to place in register. 1483 * @param rl_dest The register location where to place argument. 1484 */ 1485 void LoadArgDirect(int in_position, RegLocation rl_dest); 1486 1487 /** 1488 * @brief Used to generate LIR for special getter method. 1489 * @param mir The mir that represents the iget. 1490 * @param special Information about the special getter method. 1491 * @return Returns whether LIR was successfully generated. 1492 */ 1493 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1494 1495 /** 1496 * @brief Used to generate LIR for special setter method. 1497 * @param mir The mir that represents the iput. 1498 * @param special Information about the special setter method. 1499 * @return Returns whether LIR was successfully generated. 1500 */ 1501 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1502 1503 /** 1504 * @brief Used to generate LIR for special return-args method. 1505 * @param mir The mir that represents the return of argument. 1506 * @param special Information about the special return-args method. 1507 * @return Returns whether LIR was successfully generated. 1508 */ 1509 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1510 1511 void AddDivZeroCheckSlowPath(LIR* branch); 1512 1513 // Copy arg0 and arg1 to kArg0 and kArg1 safely, possibly using 1514 // kArg2 as temp. 1515 virtual void CopyToArgumentRegs(RegStorage arg0, RegStorage arg1); 1516 1517 /** 1518 * @brief Load Constant into RegLocation 1519 * @param rl_dest Destination RegLocation 1520 * @param value Constant value 1521 */ 1522 virtual void GenConst(RegLocation rl_dest, int value); 1523 1524 public: 1525 // TODO: add accessors for these. 1526 LIR* literal_list_; // Constants. 1527 LIR* method_literal_list_; // Method literals requiring patching. 1528 LIR* class_literal_list_; // Class literals requiring patching. 1529 LIR* code_literal_list_; // Code literals requiring patching. 1530 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1531 1532 protected: 1533 CompilationUnit* const cu_; 1534 MIRGraph* const mir_graph_; 1535 GrowableArray<SwitchTable*> switch_tables_; 1536 GrowableArray<FillArrayData*> fill_array_data_; 1537 GrowableArray<RegisterInfo*> tempreg_info_; 1538 GrowableArray<RegisterInfo*> reginfo_map_; 1539 GrowableArray<void*> pointer_storage_; 1540 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1541 CodeOffset data_offset_; // starting offset of literal pool. 1542 size_t total_size_; // header + code size. 1543 LIR* block_label_list_; 1544 PromotionMap* promotion_map_; 1545 /* 1546 * TODO: The code generation utilities don't have a built-in 1547 * mechanism to propagate the original Dalvik opcode address to the 1548 * associated generated instructions. For the trace compiler, this wasn't 1549 * necessary because the interpreter handled all throws and debugging 1550 * requests. For now we'll handle this by placing the Dalvik offset 1551 * in the CompilationUnit struct before codegen for each instruction. 1552 * The low-level LIR creation utilites will pull it from here. Rework this. 1553 */ 1554 DexOffset current_dalvik_offset_; 1555 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1556 RegisterPool* reg_pool_; 1557 /* 1558 * Sanity checking for the register temp tracking. The same ssa 1559 * name should never be associated with one temp register per 1560 * instruction compilation. 1561 */ 1562 int live_sreg_; 1563 CodeBuffer code_buffer_; 1564 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1565 std::vector<uint8_t> encoded_mapping_table_; 1566 std::vector<uint32_t> core_vmap_table_; 1567 std::vector<uint32_t> fp_vmap_table_; 1568 std::vector<uint8_t> native_gc_map_; 1569 int num_core_spills_; 1570 int num_fp_spills_; 1571 int frame_size_; 1572 unsigned int core_spill_mask_; 1573 unsigned int fp_spill_mask_; 1574 LIR* first_lir_insn_; 1575 LIR* last_lir_insn_; 1576 1577 GrowableArray<LIRSlowPath*> slow_paths_; 1578}; // Class Mir2Lir 1579 1580} // namespace art 1581 1582#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1583