mir_to_lir.h revision b48819db07f9a0992a72173380c24249d7fc648a
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/backend.h" 25#include "dex/growable_array.h" 26#include "dex/arena_allocator.h" 27#include "driver/compiler_driver.h" 28#include "leb128_encoder.h" 29#include "safe_map.h" 30 31namespace art { 32 33// Set to 1 to measure cost of suspend check. 34#define NO_SUSPEND 0 35 36#define IS_BINARY_OP (1ULL << kIsBinaryOp) 37#define IS_BRANCH (1ULL << kIsBranch) 38#define IS_IT (1ULL << kIsIT) 39#define IS_LOAD (1ULL << kMemLoad) 40#define IS_QUAD_OP (1ULL << kIsQuadOp) 41#define IS_QUIN_OP (1ULL << kIsQuinOp) 42#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 43#define IS_STORE (1ULL << kMemStore) 44#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 45#define IS_UNARY_OP (1ULL << kIsUnaryOp) 46#define NEEDS_FIXUP (1ULL << kPCRelFixup) 47#define NO_OPERAND (1ULL << kNoOperand) 48#define REG_DEF0 (1ULL << kRegDef0) 49#define REG_DEF1 (1ULL << kRegDef1) 50#define REG_DEFA (1ULL << kRegDefA) 51#define REG_DEFD (1ULL << kRegDefD) 52#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 53#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 54#define REG_DEF_LIST0 (1ULL << kRegDefList0) 55#define REG_DEF_LIST1 (1ULL << kRegDefList1) 56#define REG_DEF_LR (1ULL << kRegDefLR) 57#define REG_DEF_SP (1ULL << kRegDefSP) 58#define REG_USE0 (1ULL << kRegUse0) 59#define REG_USE1 (1ULL << kRegUse1) 60#define REG_USE2 (1ULL << kRegUse2) 61#define REG_USE3 (1ULL << kRegUse3) 62#define REG_USE4 (1ULL << kRegUse4) 63#define REG_USEA (1ULL << kRegUseA) 64#define REG_USEC (1ULL << kRegUseC) 65#define REG_USED (1ULL << kRegUseD) 66#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 67#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 68#define REG_USE_LIST0 (1ULL << kRegUseList0) 69#define REG_USE_LIST1 (1ULL << kRegUseList1) 70#define REG_USE_LR (1ULL << kRegUseLR) 71#define REG_USE_PC (1ULL << kRegUsePC) 72#define REG_USE_SP (1ULL << kRegUseSP) 73#define SETS_CCODES (1ULL << kSetsCCodes) 74#define USES_CCODES (1ULL << kUsesCCodes) 75 76// Common combo register usage patterns. 77#define REG_DEF01 (REG_DEF0 | REG_DEF1) 78#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 79#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 80#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 81#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 82#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 83#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 84#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 85#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 86#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 87#define REG_USE012 (REG_USE01 | REG_USE2) 88#define REG_USE014 (REG_USE01 | REG_USE4) 89#define REG_USE01 (REG_USE0 | REG_USE1) 90#define REG_USE02 (REG_USE0 | REG_USE2) 91#define REG_USE12 (REG_USE1 | REG_USE2) 92#define REG_USE23 (REG_USE2 | REG_USE3) 93 94struct BasicBlock; 95struct CallInfo; 96struct CompilationUnit; 97struct MIR; 98struct LIR; 99struct RegLocation; 100struct RegisterInfo; 101class MIRGraph; 102class Mir2Lir; 103 104typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 105 const MethodReference& target_method, 106 uint32_t method_idx, uintptr_t direct_code, 107 uintptr_t direct_method, InvokeType type); 108 109typedef std::vector<uint8_t> CodeBuffer; 110 111struct UseDefMasks { 112 uint64_t use_mask; // Resource mask for use. 113 uint64_t def_mask; // Resource mask for def. 114}; 115 116struct AssemblyInfo { 117 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 118 uint8_t bytes[16]; // Encoded instruction bytes. 119}; 120 121struct LIR { 122 int offset; // Offset of this instruction. 123 uint16_t dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 124 int16_t opcode; 125 LIR* next; 126 LIR* prev; 127 LIR* target; 128 struct { 129 unsigned int alias_info:17; // For Dalvik register disambiguation. 130 bool is_nop:1; // LIR is optimized away. 131 unsigned int size:4; // Note: size of encoded instruction is in bytes. 132 bool use_def_invalid:1; // If true, masks should not be used. 133 unsigned int generation:1; // Used to track visitation state during fixup pass. 134 unsigned int fixup:8; // Fixup kind. 135 } flags; 136 union { 137 UseDefMasks m; // Use & Def masks used during optimization. 138 AssemblyInfo a; // Instruction encoding used during assembly phase. 139 } u; 140 int operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 141}; 142 143// Target-specific initialization. 144Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 145 ArenaAllocator* const arena); 146Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 147 ArenaAllocator* const arena); 148Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 149 ArenaAllocator* const arena); 150 151// Utility macros to traverse the LIR list. 152#define NEXT_LIR(lir) (lir->next) 153#define PREV_LIR(lir) (lir->prev) 154 155// Defines for alias_info (tracks Dalvik register references). 156#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 157#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 158#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 159#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 160 161// Common resource macros. 162#define ENCODE_CCODE (1ULL << kCCode) 163#define ENCODE_FP_STATUS (1ULL << kFPStatus) 164 165// Abstract memory locations. 166#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 167#define ENCODE_LITERAL (1ULL << kLiteral) 168#define ENCODE_HEAP_REF (1ULL << kHeapRef) 169#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 170 171#define ENCODE_ALL (~0ULL) 172#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 173 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 174 175// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 176#define STARTING_DOUBLE_SREG 0x10000 177 178// TODO: replace these macros 179#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 180#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 181#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 182#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 183#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 184#define is_pseudo_opcode(opcode) (static_cast<int>(opcode) < 0) 185 186class Mir2Lir : public Backend { 187 public: 188 struct SwitchTable { 189 int offset; 190 const uint16_t* table; // Original dex table. 191 int vaddr; // Dalvik offset of switch opcode. 192 LIR* anchor; // Reference instruction for relative offsets. 193 LIR** targets; // Array of case targets. 194 }; 195 196 struct FillArrayData { 197 int offset; 198 const uint16_t* table; // Original dex table. 199 int size; 200 int vaddr; // Dalvik offset of FILL_ARRAY_DATA opcode. 201 }; 202 203 /* Static register use counts */ 204 struct RefCounts { 205 int count; 206 int s_reg; 207 }; 208 209 /* 210 * Data structure tracking the mapping between a Dalvik register (pair) and a 211 * native register (pair). The idea is to reuse the previously loaded value 212 * if possible, otherwise to keep the value in a native register as long as 213 * possible. 214 */ 215 struct RegisterInfo { 216 int reg; // Reg number 217 bool in_use; // Has it been allocated? 218 bool is_temp; // Can allocate as temp? 219 bool pair; // Part of a register pair? 220 int partner; // If pair, other reg of pair. 221 bool live; // Is there an associated SSA name? 222 bool dirty; // If live, is it dirty? 223 int s_reg; // Name of live value. 224 LIR *def_start; // Starting inst in last def sequence. 225 LIR *def_end; // Ending inst in last def sequence. 226 }; 227 228 struct RegisterPool { 229 int num_core_regs; 230 RegisterInfo *core_regs; 231 int next_core_reg; 232 int num_fp_regs; 233 RegisterInfo *FPRegs; 234 int next_fp_reg; 235 }; 236 237 struct PromotionMap { 238 RegLocationType core_location:3; 239 uint8_t core_reg; 240 RegLocationType fp_location:3; 241 uint8_t FpReg; 242 bool first_in_pair; 243 }; 244 245 virtual ~Mir2Lir() {} 246 247 int32_t s4FromSwitchData(const void* switch_data) { 248 return *reinterpret_cast<const int32_t*>(switch_data); 249 } 250 251 RegisterClass oat_reg_class_by_size(OpSize size) { 252 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 253 size == kSignedByte) ? kCoreReg : kAnyReg; 254 } 255 256 size_t CodeBufferSizeInBytes() { 257 return code_buffer_.size() / sizeof(code_buffer_[0]); 258 } 259 260 // Shared by all targets - implemented in codegen_util.cc 261 void AppendLIR(LIR* lir); 262 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 263 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 264 265 int ComputeFrameSize(); 266 virtual void Materialize(); 267 virtual CompiledMethod* GetCompiledMethod(); 268 void MarkSafepointPC(LIR* inst); 269 bool FastInstance(uint32_t field_idx, bool is_put, int* field_offset, bool* is_volatile); 270 void SetupResourceMasks(LIR* lir); 271 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 272 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 273 void SetupRegMask(uint64_t* mask, int reg); 274 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 275 void DumpPromotionMap(); 276 void CodegenDump(); 277 LIR* RawLIR(int dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 278 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 279 LIR* NewLIR0(int opcode); 280 LIR* NewLIR1(int opcode, int dest); 281 LIR* NewLIR2(int opcode, int dest, int src1); 282 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 283 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 284 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 285 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 286 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 287 LIR* AddWordData(LIR* *constant_list_p, int value); 288 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 289 void ProcessSwitchTables(); 290 void DumpSparseSwitchTable(const uint16_t* table); 291 void DumpPackedSwitchTable(const uint16_t* table); 292 void MarkBoundary(int offset, const char* inst_str); 293 void NopLIR(LIR* lir); 294 void UnlinkLIR(LIR* lir); 295 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 296 bool IsInexpensiveConstant(RegLocation rl_src); 297 ConditionCode FlipComparisonOrder(ConditionCode before); 298 void DumpMappingTable(const char* table_name, const char* descriptor, 299 const char* name, const Signature& signature, 300 const std::vector<uint32_t>& v); 301 void InstallLiteralPools(); 302 void InstallSwitchTables(); 303 void InstallFillArrayData(); 304 bool VerifyCatchEntries(); 305 void CreateMappingTables(); 306 void CreateNativeGcMap(); 307 int AssignLiteralOffset(int offset); 308 int AssignSwitchTablesOffset(int offset); 309 int AssignFillArrayDataOffset(int offset); 310 LIR* InsertCaseLabel(int vaddr, int keyVal); 311 void MarkPackedCaseLabels(Mir2Lir::SwitchTable *tab_rec); 312 void MarkSparseCaseLabels(Mir2Lir::SwitchTable *tab_rec); 313 314 // Shared by all targets - implemented in local_optimizations.cc 315 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src); 316 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 317 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 318 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 319 320 // Shared by all targets - implemented in ralloc_util.cc 321 int GetSRegHi(int lowSreg); 322 bool oat_live_out(int s_reg); 323 int oatSSASrc(MIR* mir, int num); 324 void SimpleRegAlloc(); 325 void ResetRegPool(); 326 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 327 void DumpRegPool(RegisterInfo* p, int num_regs); 328 void DumpCoreRegPool(); 329 void DumpFpRegPool(); 330 /* Mark a temp register as dead. Does not affect allocation state. */ 331 void Clobber(int reg) { 332 ClobberBody(GetRegInfo(reg)); 333 } 334 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 335 void ClobberSReg(int s_reg); 336 int SRegToPMap(int s_reg); 337 void RecordCorePromotion(int reg, int s_reg); 338 int AllocPreservedCoreReg(int s_reg); 339 void RecordFpPromotion(int reg, int s_reg); 340 int AllocPreservedSingle(int s_reg); 341 int AllocPreservedDouble(int s_reg); 342 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 343 int AllocTempDouble(); 344 int AllocFreeTemp(); 345 int AllocTemp(); 346 int AllocTempFloat(); 347 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 348 RegisterInfo* AllocLive(int s_reg, int reg_class); 349 void FreeTemp(int reg); 350 RegisterInfo* IsLive(int reg); 351 RegisterInfo* IsTemp(int reg); 352 RegisterInfo* IsPromoted(int reg); 353 bool IsDirty(int reg); 354 void LockTemp(int reg); 355 void ResetDef(int reg); 356 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 357 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 358 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 359 RegLocation WideToNarrow(RegLocation rl); 360 void ResetDefLoc(RegLocation rl); 361 void ResetDefLocWide(RegLocation rl); 362 void ResetDefTracking(); 363 void ClobberAllRegs(); 364 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 365 void FlushAllRegs(); 366 bool RegClassMatches(int reg_class, int reg); 367 void MarkLive(int reg, int s_reg); 368 void MarkTemp(int reg); 369 void UnmarkTemp(int reg); 370 void MarkPair(int low_reg, int high_reg); 371 void MarkClean(RegLocation loc); 372 void MarkDirty(RegLocation loc); 373 void MarkInUse(int reg); 374 void CopyRegInfo(int new_reg, int old_reg); 375 bool CheckCorePoolSanity(); 376 RegLocation UpdateLoc(RegLocation loc); 377 RegLocation UpdateLocWide(RegLocation loc); 378 RegLocation UpdateRawLoc(RegLocation loc); 379 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 380 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 381 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 382 void DumpCounts(const RefCounts* arr, int size, const char* msg); 383 void DoPromotion(); 384 int VRegOffset(int v_reg); 385 int SRegOffset(int s_reg); 386 RegLocation GetReturnWide(bool is_double); 387 RegLocation GetReturn(bool is_float); 388 RegisterInfo* GetRegInfo(int reg); 389 390 // Shared by all targets - implemented in gen_common.cc. 391 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 392 RegLocation rl_src, RegLocation rl_dest, int lit); 393 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 394 void HandleSuspendLaunchPads(); 395 void HandleIntrinsicLaunchPads(); 396 void HandleThrowLaunchPads(); 397 void GenBarrier(); 398 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 399 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val, 400 ThrowKind kind); 401 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags); 402 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 403 ThrowKind kind); 404 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 405 RegLocation rl_src2, LIR* taken, LIR* fall_through); 406 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 407 LIR* taken, LIR* fall_through); 408 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 409 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 410 RegLocation rl_src); 411 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 412 RegLocation rl_src); 413 void GenFilledNewArray(CallInfo* info); 414 void GenSput(uint32_t field_idx, RegLocation rl_src, 415 bool is_long_or_double, bool is_object); 416 void GenSget(uint32_t field_idx, RegLocation rl_dest, 417 bool is_long_or_double, bool is_object); 418 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size, 419 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 420 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size, 421 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 422 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 423 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 424 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 425 void GenThrow(RegLocation rl_src); 426 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, 427 RegLocation rl_src); 428 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, 429 RegLocation rl_src); 430 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 431 RegLocation rl_src1, RegLocation rl_src2); 432 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 433 RegLocation rl_src1, RegLocation rl_shift); 434 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 435 RegLocation rl_src1, RegLocation rl_src2); 436 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 437 RegLocation rl_src, int lit); 438 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 439 RegLocation rl_src1, RegLocation rl_src2); 440 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 441 RegLocation rl_src); 442 void GenSuspendTest(int opt_flags); 443 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 444 445 // Shared by all targets - implemented in gen_invoke.cc. 446 int CallHelperSetup(ThreadOffset helper_offset); 447 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc); 448 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 449 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 450 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 451 bool safepoint_pc); 452 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 453 bool safepoint_pc); 454 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 455 RegLocation arg1, bool safepoint_pc); 456 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 457 int arg1, bool safepoint_pc); 458 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 459 bool safepoint_pc); 460 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 461 bool safepoint_pc); 462 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 463 bool safepoint_pc); 464 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 465 RegLocation arg0, RegLocation arg1, 466 bool safepoint_pc); 467 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 468 bool safepoint_pc); 469 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 470 int arg2, bool safepoint_pc); 471 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 472 RegLocation arg2, bool safepoint_pc); 473 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 474 bool safepoint_pc); 475 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 476 int arg0, RegLocation arg1, RegLocation arg2, 477 bool safepoint_pc); 478 void GenInvoke(CallInfo* info); 479 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 480 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 481 NextCallInsn next_call_insn, 482 const MethodReference& target_method, 483 uint32_t vtable_idx, 484 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 485 bool skip_this); 486 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 487 NextCallInsn next_call_insn, 488 const MethodReference& target_method, 489 uint32_t vtable_idx, 490 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 491 bool skip_this); 492 RegLocation InlineTarget(CallInfo* info); 493 RegLocation InlineTargetWide(CallInfo* info); 494 495 bool GenInlinedCharAt(CallInfo* info); 496 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 497 bool GenInlinedAbsInt(CallInfo* info); 498 bool GenInlinedAbsLong(CallInfo* info); 499 bool GenInlinedFloatCvt(CallInfo* info); 500 bool GenInlinedDoubleCvt(CallInfo* info); 501 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 502 bool GenInlinedStringCompareTo(CallInfo* info); 503 bool GenInlinedCurrentThread(CallInfo* info); 504 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 505 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 506 bool is_volatile, bool is_ordered); 507 bool GenIntrinsic(CallInfo* info); 508 int LoadArgRegs(CallInfo* info, int call_state, 509 NextCallInsn next_call_insn, 510 const MethodReference& target_method, 511 uint32_t vtable_idx, 512 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 513 bool skip_this); 514 515 // Shared by all targets - implemented in gen_loadstore.cc. 516 RegLocation LoadCurrMethod(); 517 void LoadCurrMethodDirect(int r_tgt); 518 LIR* LoadConstant(int r_dest, int value); 519 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 520 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 521 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 522 void LoadValueDirect(RegLocation rl_src, int r_dest); 523 void LoadValueDirectFixed(RegLocation rl_src, int r_dest); 524 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi); 525 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi); 526 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 527 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 528 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 529 530 // Shared by all targets - implemented in mir_to_lir.cc. 531 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 532 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 533 bool MethodBlockCodeGen(BasicBlock* bb); 534 void SpecialMIR2LIR(SpecialCaseHandler special_case); 535 void MethodMIR2LIR(); 536 537 538 539 // Required for target - codegen helpers. 540 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 541 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 542 virtual int LoadHelper(ThreadOffset offset) = 0; 543 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 544 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 545 int s_reg) = 0; 546 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 547 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 548 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0; 549 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0; 550 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0; 551 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 552 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 553 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 554 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 555 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 556 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0; 557 558 // Required for target - register utilities. 559 virtual bool IsFpReg(int reg) = 0; 560 virtual bool SameRegType(int reg1, int reg2) = 0; 561 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0; 562 virtual int AllocTypedTempPair(bool fp_hint, int reg_class) = 0; 563 virtual int S2d(int low_reg, int high_reg) = 0; 564 virtual int TargetReg(SpecialTargetRegister reg) = 0; 565 virtual RegLocation GetReturnAlt() = 0; 566 virtual RegLocation GetReturnWideAlt() = 0; 567 virtual RegLocation LocCReturn() = 0; 568 virtual RegLocation LocCReturnDouble() = 0; 569 virtual RegLocation LocCReturnFloat() = 0; 570 virtual RegLocation LocCReturnWide() = 0; 571 virtual uint32_t FpRegMask() = 0; 572 virtual uint64_t GetRegMaskCommon(int reg) = 0; 573 virtual void AdjustSpillMask() = 0; 574 virtual void ClobberCalleeSave() = 0; 575 virtual void FlushReg(int reg) = 0; 576 virtual void FlushRegWide(int reg1, int reg2) = 0; 577 virtual void FreeCallTemps() = 0; 578 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 579 virtual void LockCallTemps() = 0; 580 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 581 virtual void CompilerInitializeRegAlloc() = 0; 582 583 // Required for target - miscellaneous. 584 virtual void AssembleLIR() = 0; 585 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 586 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 587 virtual const char* GetTargetInstFmt(int opcode) = 0; 588 virtual const char* GetTargetInstName(int opcode) = 0; 589 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 590 virtual uint64_t GetPCUseDefEncoding() = 0; 591 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 592 virtual int GetInsnSize(LIR* lir) = 0; 593 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 594 595 // Required for target - Dalvik-level generators. 596 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 597 RegLocation rl_src1, RegLocation rl_src2) = 0; 598 virtual void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, 599 RegLocation rl_src2) = 0; 600 virtual void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, 601 RegLocation rl_src2) = 0; 602 virtual void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, 603 RegLocation rl_src2) = 0; 604 virtual void GenArithOpDouble(Instruction::Code opcode, 605 RegLocation rl_dest, RegLocation rl_src1, 606 RegLocation rl_src2) = 0; 607 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 608 RegLocation rl_src1, RegLocation rl_src2) = 0; 609 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 610 RegLocation rl_src1, RegLocation rl_src2) = 0; 611 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 612 RegLocation rl_src) = 0; 613 virtual bool GenInlinedCas32(CallInfo* info, bool need_write_barrier) = 0; 614 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 615 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 616 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 617 virtual void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, 618 RegLocation rl_src2) = 0; 619 virtual void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, 620 RegLocation rl_src2) = 0; 621 virtual void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, 622 RegLocation rl_src2) = 0; 623 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, 624 int offset, ThrowKind kind) = 0; 625 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, 626 bool is_div) = 0; 627 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, 628 bool is_div) = 0; 629 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 630 RegLocation rl_src2) = 0; 631 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0; 632 virtual void GenEntrySequence(RegLocation* ArgLocs, 633 RegLocation rl_method) = 0; 634 virtual void GenExitSequence() = 0; 635 virtual void GenFillArrayData(uint32_t table_offset, 636 RegLocation rl_src) = 0; 637 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, 638 bool is_double) = 0; 639 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 640 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 641 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 642 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src) = 0; 643 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src) = 0; 644 virtual void GenMoveException(RegLocation rl_dest) = 0; 645 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 646 RegLocation rl_result, int lit, int first_bit, 647 int second_bit) = 0; 648 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 649 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 650 virtual void GenPackedSwitch(MIR* mir, uint32_t table_offset, 651 RegLocation rl_src) = 0; 652 virtual void GenSparseSwitch(MIR* mir, uint32_t table_offset, 653 RegLocation rl_src) = 0; 654 virtual void GenSpecialCase(BasicBlock* bb, MIR* mir, 655 SpecialCaseHandler special_case) = 0; 656 virtual void GenArrayObjPut(int opt_flags, RegLocation rl_array, 657 RegLocation rl_index, RegLocation rl_src, int scale) = 0; 658 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 659 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 660 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 661 RegLocation rl_index, RegLocation rl_src, int scale) = 0; 662 virtual void GenShiftImmOpLong(Instruction::Code opcode, 663 RegLocation rl_dest, RegLocation rl_src1, 664 RegLocation rl_shift) = 0; 665 666 // Required for target - single operation generators. 667 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 668 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, 669 LIR* target) = 0; 670 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, 671 LIR* target) = 0; 672 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 673 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, 674 LIR* target) = 0; 675 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 676 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 677 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0; 678 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0; 679 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0; 680 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 681 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0; 682 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0; 683 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0; 684 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0; 685 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0; 686 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, 687 int r_src2) = 0; 688 virtual LIR* OpTestSuspend(LIR* target) = 0; 689 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 690 virtual LIR* OpVldm(int rBase, int count) = 0; 691 virtual LIR* OpVstm(int rBase, int count) = 0; 692 virtual void OpLea(int rBase, int reg1, int reg2, int scale, 693 int offset) = 0; 694 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, 695 int src_hi) = 0; 696 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 697 virtual bool InexpensiveConstantInt(int32_t value) = 0; 698 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 699 virtual bool InexpensiveConstantLong(int64_t value) = 0; 700 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 701 702 // Temp workaround 703 void Workaround7250540(RegLocation rl_dest, int value); 704 705 protected: 706 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 707 708 CompilationUnit* GetCompilationUnit() { 709 return cu_; 710 } 711 712 private: 713 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 714 RegLocation rl_src); 715 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 716 bool type_known_abstract, bool use_declaring_class, 717 bool can_assume_type_is_in_dex_cache, 718 uint32_t type_idx, RegLocation rl_dest, 719 RegLocation rl_src); 720 721 void ClobberBody(RegisterInfo* p); 722 void ResetDefBody(RegisterInfo* p) { 723 p->def_start = NULL; 724 p->def_end = NULL; 725 } 726 727 public: 728 // TODO: add accessors for these. 729 LIR* literal_list_; // Constants. 730 LIR* method_literal_list_; // Method literals requiring patching. 731 LIR* code_literal_list_; // Code literals requiring patching. 732 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 733 734 protected: 735 CompilationUnit* const cu_; 736 MIRGraph* const mir_graph_; 737 GrowableArray<SwitchTable*> switch_tables_; 738 GrowableArray<FillArrayData*> fill_array_data_; 739 GrowableArray<LIR*> throw_launchpads_; 740 GrowableArray<LIR*> suspend_launchpads_; 741 GrowableArray<LIR*> intrinsic_launchpads_; 742 GrowableArray<RegisterInfo*> tempreg_info_; 743 GrowableArray<RegisterInfo*> reginfo_map_; 744 /* 745 * Holds mapping from native PC to dex PC for safepoints where we may deoptimize. 746 * Native PC is on the return address of the safepointed operation. Dex PC is for 747 * the instruction being executed at the safepoint. 748 */ 749 std::vector<uint32_t> pc2dex_mapping_table_; 750 /* 751 * Holds mapping from Dex PC to native PC for catch entry points. Native PC and Dex PC 752 * immediately preceed the instruction. 753 */ 754 std::vector<uint32_t> dex2pc_mapping_table_; 755 int current_code_offset_; // Working byte offset of machine instructons. 756 int data_offset_; // starting offset of literal pool. 757 int total_size_; // header + code size. 758 LIR* block_label_list_; 759 PromotionMap* promotion_map_; 760 /* 761 * TODO: The code generation utilities don't have a built-in 762 * mechanism to propagate the original Dalvik opcode address to the 763 * associated generated instructions. For the trace compiler, this wasn't 764 * necessary because the interpreter handled all throws and debugging 765 * requests. For now we'll handle this by placing the Dalvik offset 766 * in the CompilationUnit struct before codegen for each instruction. 767 * The low-level LIR creation utilites will pull it from here. Rework this. 768 */ 769 int current_dalvik_offset_; 770 int estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 771 RegisterPool* reg_pool_; 772 /* 773 * Sanity checking for the register temp tracking. The same ssa 774 * name should never be associated with one temp register per 775 * instruction compilation. 776 */ 777 int live_sreg_; 778 CodeBuffer code_buffer_; 779 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 780 UnsignedLeb128EncodingVector encoded_mapping_table_; 781 std::vector<uint32_t> core_vmap_table_; 782 std::vector<uint32_t> fp_vmap_table_; 783 std::vector<uint8_t> native_gc_map_; 784 int num_core_spills_; 785 int num_fp_spills_; 786 int frame_size_; 787 unsigned int core_spill_mask_; 788 unsigned int fp_spill_mask_; 789 LIR* first_lir_insn_; 790 LIR* last_lir_insn_; 791}; // Class Mir2Lir 792 793} // namespace art 794 795#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 796