mir_to_lir.h revision bcec6fba95ee7974d3f7b81c3c02e7eb3ca3df00
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/backend.h" 25#include "dex/growable_array.h" 26#include "dex/arena_allocator.h" 27#include "driver/compiler_driver.h" 28#include "leb128_encoder.h" 29#include "safe_map.h" 30 31namespace art { 32 33/* 34 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 35 * add type safety (see runtime/offsets.h). 36 */ 37typedef uint32_t DexOffset; // Dex offset in code units. 38typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 39typedef uint32_t CodeOffset; // Native code offset in bytes. 40 41// Set to 1 to measure cost of suspend check. 42#define NO_SUSPEND 0 43 44#define IS_BINARY_OP (1ULL << kIsBinaryOp) 45#define IS_BRANCH (1ULL << kIsBranch) 46#define IS_IT (1ULL << kIsIT) 47#define IS_LOAD (1ULL << kMemLoad) 48#define IS_QUAD_OP (1ULL << kIsQuadOp) 49#define IS_QUIN_OP (1ULL << kIsQuinOp) 50#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 51#define IS_STORE (1ULL << kMemStore) 52#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 53#define IS_UNARY_OP (1ULL << kIsUnaryOp) 54#define NEEDS_FIXUP (1ULL << kPCRelFixup) 55#define NO_OPERAND (1ULL << kNoOperand) 56#define REG_DEF0 (1ULL << kRegDef0) 57#define REG_DEF1 (1ULL << kRegDef1) 58#define REG_DEFA (1ULL << kRegDefA) 59#define REG_DEFD (1ULL << kRegDefD) 60#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 61#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 62#define REG_DEF_LIST0 (1ULL << kRegDefList0) 63#define REG_DEF_LIST1 (1ULL << kRegDefList1) 64#define REG_DEF_LR (1ULL << kRegDefLR) 65#define REG_DEF_SP (1ULL << kRegDefSP) 66#define REG_USE0 (1ULL << kRegUse0) 67#define REG_USE1 (1ULL << kRegUse1) 68#define REG_USE2 (1ULL << kRegUse2) 69#define REG_USE3 (1ULL << kRegUse3) 70#define REG_USE4 (1ULL << kRegUse4) 71#define REG_USEA (1ULL << kRegUseA) 72#define REG_USEC (1ULL << kRegUseC) 73#define REG_USED (1ULL << kRegUseD) 74#define REG_USEB (1ULL << kRegUseB) 75#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 76#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 77#define REG_USE_LIST0 (1ULL << kRegUseList0) 78#define REG_USE_LIST1 (1ULL << kRegUseList1) 79#define REG_USE_LR (1ULL << kRegUseLR) 80#define REG_USE_PC (1ULL << kRegUsePC) 81#define REG_USE_SP (1ULL << kRegUseSP) 82#define SETS_CCODES (1ULL << kSetsCCodes) 83#define USES_CCODES (1ULL << kUsesCCodes) 84 85// Common combo register usage patterns. 86#define REG_DEF01 (REG_DEF0 | REG_DEF1) 87#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 88#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 89#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 90#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 91#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 92#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 93#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 94#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 95#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 96#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 97#define REG_USE012 (REG_USE01 | REG_USE2) 98#define REG_USE014 (REG_USE01 | REG_USE4) 99#define REG_USE01 (REG_USE0 | REG_USE1) 100#define REG_USE02 (REG_USE0 | REG_USE2) 101#define REG_USE12 (REG_USE1 | REG_USE2) 102#define REG_USE23 (REG_USE2 | REG_USE3) 103#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 104 105struct BasicBlock; 106struct CallInfo; 107struct CompilationUnit; 108struct InlineMethod; 109struct MIR; 110struct LIR; 111struct RegLocation; 112struct RegisterInfo; 113class DexFileMethodInliner; 114class MIRGraph; 115class Mir2Lir; 116 117typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 118 const MethodReference& target_method, 119 uint32_t method_idx, uintptr_t direct_code, 120 uintptr_t direct_method, InvokeType type); 121 122typedef std::vector<uint8_t> CodeBuffer; 123 124struct UseDefMasks { 125 uint64_t use_mask; // Resource mask for use. 126 uint64_t def_mask; // Resource mask for def. 127}; 128 129struct AssemblyInfo { 130 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 131 uint8_t bytes[16]; // Encoded instruction bytes. 132}; 133 134struct LIR { 135 CodeOffset offset; // Offset of this instruction. 136 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 137 int16_t opcode; 138 LIR* next; 139 LIR* prev; 140 LIR* target; 141 struct { 142 unsigned int alias_info:17; // For Dalvik register disambiguation. 143 bool is_nop:1; // LIR is optimized away. 144 unsigned int size:4; // Note: size of encoded instruction is in bytes. 145 bool use_def_invalid:1; // If true, masks should not be used. 146 unsigned int generation:1; // Used to track visitation state during fixup pass. 147 unsigned int fixup:8; // Fixup kind. 148 } flags; 149 union { 150 UseDefMasks m; // Use & Def masks used during optimization. 151 AssemblyInfo a; // Instruction encoding used during assembly phase. 152 } u; 153 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 154}; 155 156// Target-specific initialization. 157Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 158 ArenaAllocator* const arena); 159Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 160 ArenaAllocator* const arena); 161Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 162 ArenaAllocator* const arena); 163 164// Utility macros to traverse the LIR list. 165#define NEXT_LIR(lir) (lir->next) 166#define PREV_LIR(lir) (lir->prev) 167 168// Defines for alias_info (tracks Dalvik register references). 169#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 170#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 171#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 172#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 173 174// Common resource macros. 175#define ENCODE_CCODE (1ULL << kCCode) 176#define ENCODE_FP_STATUS (1ULL << kFPStatus) 177 178// Abstract memory locations. 179#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 180#define ENCODE_LITERAL (1ULL << kLiteral) 181#define ENCODE_HEAP_REF (1ULL << kHeapRef) 182#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 183 184#define ENCODE_ALL (~0ULL) 185#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 186 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 187 188// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 189#define STARTING_DOUBLE_SREG 0x10000 190 191// TODO: replace these macros 192#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 193#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 194#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 195#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 196#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 197 198class Mir2Lir : public Backend { 199 public: 200 /* 201 * Auxiliary information describing the location of data embedded in the Dalvik 202 * byte code stream. 203 */ 204 struct EmbeddedData { 205 CodeOffset offset; // Code offset of data block. 206 const uint16_t* table; // Original dex data. 207 DexOffset vaddr; // Dalvik offset of parent opcode. 208 }; 209 210 struct FillArrayData : EmbeddedData { 211 int32_t size; 212 }; 213 214 struct SwitchTable : EmbeddedData { 215 LIR* anchor; // Reference instruction for relative offsets. 216 LIR** targets; // Array of case targets. 217 }; 218 219 /* Static register use counts */ 220 struct RefCounts { 221 int count; 222 int s_reg; 223 }; 224 225 /* 226 * Data structure tracking the mapping between a Dalvik register (pair) and a 227 * native register (pair). The idea is to reuse the previously loaded value 228 * if possible, otherwise to keep the value in a native register as long as 229 * possible. 230 */ 231 struct RegisterInfo { 232 int reg; // Reg number 233 bool in_use; // Has it been allocated? 234 bool is_temp; // Can allocate as temp? 235 bool pair; // Part of a register pair? 236 int partner; // If pair, other reg of pair. 237 bool live; // Is there an associated SSA name? 238 bool dirty; // If live, is it dirty? 239 int s_reg; // Name of live value. 240 LIR *def_start; // Starting inst in last def sequence. 241 LIR *def_end; // Ending inst in last def sequence. 242 }; 243 244 struct RegisterPool { 245 int num_core_regs; 246 RegisterInfo *core_regs; 247 int next_core_reg; 248 int num_fp_regs; 249 RegisterInfo *FPRegs; 250 int next_fp_reg; 251 }; 252 253 struct PromotionMap { 254 RegLocationType core_location:3; 255 uint8_t core_reg; 256 RegLocationType fp_location:3; 257 uint8_t FpReg; 258 bool first_in_pair; 259 }; 260 261 // 262 // Slow paths. This object is used generate a sequence of code that is executed in the 263 // slow path. For example, resolving a string or class is slow as it will only be executed 264 // once (after that it is resolved and doesn't need to be done again). We want slow paths 265 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 266 // branch over them. 267 // 268 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 269 // the Compile() function that will be called near the end of the code generated by the 270 // method. 271 // 272 // The basic flow for a slow path is: 273 // 274 // CMP reg, #value 275 // BEQ fromfast 276 // cont: 277 // ... 278 // fast path code 279 // ... 280 // more code 281 // ... 282 // RETURN 283 /// 284 // fromfast: 285 // ... 286 // slow path code 287 // ... 288 // B cont 289 // 290 // So you see we need two labels and two branches. The first branch (called fromfast) is 291 // the conditional branch to the slow path code. The second label (called cont) is used 292 // as an unconditional branch target for getting back to the code after the slow path 293 // has completed. 294 // 295 296 class LIRSlowPath { 297 public: 298 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 299 LIR* cont = nullptr) : 300 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 301 } 302 virtual ~LIRSlowPath() {} 303 virtual void Compile() = 0; 304 305 static void* operator new(size_t size, ArenaAllocator* arena) { 306 return arena->Alloc(size, ArenaAllocator::kAllocData); 307 } 308 309 protected: 310 LIR* GenerateTargetLabel(); 311 312 Mir2Lir* const m2l_; 313 const DexOffset current_dex_pc_; 314 LIR* const fromfast_; 315 LIR* const cont_; 316 }; 317 318 virtual ~Mir2Lir() {} 319 320 int32_t s4FromSwitchData(const void* switch_data) { 321 return *reinterpret_cast<const int32_t*>(switch_data); 322 } 323 324 RegisterClass oat_reg_class_by_size(OpSize size) { 325 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 326 size == kSignedByte) ? kCoreReg : kAnyReg; 327 } 328 329 size_t CodeBufferSizeInBytes() { 330 return code_buffer_.size() / sizeof(code_buffer_[0]); 331 } 332 333 bool IsPseudoLirOp(int opcode) { 334 return (opcode < 0); 335 } 336 337 /* 338 * LIR operands are 32-bit integers. Sometimes, (especially for managing 339 * instructions which require PC-relative fixups), we need the operands to carry 340 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 341 * hold that index in the operand array. 342 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 343 * may be worth conditionally-compiling a set of identity functions here. 344 */ 345 uint32_t WrapPointer(void* pointer) { 346 uint32_t res = pointer_storage_.Size(); 347 pointer_storage_.Insert(pointer); 348 return res; 349 } 350 351 void* UnwrapPointer(size_t index) { 352 return pointer_storage_.Get(index); 353 } 354 355 // strdup(), but allocates from the arena. 356 char* ArenaStrdup(const char* str) { 357 size_t len = strlen(str) + 1; 358 char* res = reinterpret_cast<char*>(arena_->Alloc(len, ArenaAllocator::kAllocMisc)); 359 if (res != NULL) { 360 strncpy(res, str, len); 361 } 362 return res; 363 } 364 365 // Shared by all targets - implemented in codegen_util.cc 366 void AppendLIR(LIR* lir); 367 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 368 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 369 370 /** 371 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 372 * to place in a frame. 373 * @return Returns the maximum number of compiler temporaries. 374 */ 375 size_t GetMaxPossibleCompilerTemps() const; 376 377 /** 378 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 379 * @return Returns the size in bytes for space needed for compiler temporary spill region. 380 */ 381 size_t GetNumBytesForCompilerTempSpillRegion(); 382 383 DexOffset GetCurrentDexPc() const { 384 return current_dalvik_offset_; 385 } 386 387 int ComputeFrameSize(); 388 virtual void Materialize(); 389 virtual CompiledMethod* GetCompiledMethod(); 390 void MarkSafepointPC(LIR* inst); 391 bool FastInstance(uint32_t field_idx, bool is_put, int* field_offset, bool* is_volatile); 392 void SetupResourceMasks(LIR* lir); 393 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 394 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 395 void SetupRegMask(uint64_t* mask, int reg); 396 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 397 void DumpPromotionMap(); 398 void CodegenDump(); 399 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 400 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 401 LIR* NewLIR0(int opcode); 402 LIR* NewLIR1(int opcode, int dest); 403 LIR* NewLIR2(int opcode, int dest, int src1); 404 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 405 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 406 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 407 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 408 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 409 LIR* AddWordData(LIR* *constant_list_p, int value); 410 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 411 void ProcessSwitchTables(); 412 void DumpSparseSwitchTable(const uint16_t* table); 413 void DumpPackedSwitchTable(const uint16_t* table); 414 void MarkBoundary(DexOffset offset, const char* inst_str); 415 void NopLIR(LIR* lir); 416 void UnlinkLIR(LIR* lir); 417 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 418 bool IsInexpensiveConstant(RegLocation rl_src); 419 ConditionCode FlipComparisonOrder(ConditionCode before); 420 void InstallLiteralPools(); 421 void InstallSwitchTables(); 422 void InstallFillArrayData(); 423 bool VerifyCatchEntries(); 424 void CreateMappingTables(); 425 void CreateNativeGcMap(); 426 int AssignLiteralOffset(CodeOffset offset); 427 int AssignSwitchTablesOffset(CodeOffset offset); 428 int AssignFillArrayDataOffset(CodeOffset offset); 429 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 430 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 431 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 432 433 // Shared by all targets - implemented in local_optimizations.cc 434 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src); 435 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 436 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 437 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 438 439 // Shared by all targets - implemented in ralloc_util.cc 440 int GetSRegHi(int lowSreg); 441 bool oat_live_out(int s_reg); 442 int oatSSASrc(MIR* mir, int num); 443 void SimpleRegAlloc(); 444 void ResetRegPool(); 445 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 446 void DumpRegPool(RegisterInfo* p, int num_regs); 447 void DumpCoreRegPool(); 448 void DumpFpRegPool(); 449 /* Mark a temp register as dead. Does not affect allocation state. */ 450 void Clobber(int reg) { 451 ClobberBody(GetRegInfo(reg)); 452 } 453 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 454 void ClobberSReg(int s_reg); 455 int SRegToPMap(int s_reg); 456 void RecordCorePromotion(int reg, int s_reg); 457 int AllocPreservedCoreReg(int s_reg); 458 void RecordFpPromotion(int reg, int s_reg); 459 int AllocPreservedSingle(int s_reg); 460 int AllocPreservedDouble(int s_reg); 461 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 462 virtual int AllocTempDouble(); 463 int AllocFreeTemp(); 464 int AllocTemp(); 465 int AllocTempFloat(); 466 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 467 RegisterInfo* AllocLive(int s_reg, int reg_class); 468 void FreeTemp(int reg); 469 RegisterInfo* IsLive(int reg); 470 RegisterInfo* IsTemp(int reg); 471 RegisterInfo* IsPromoted(int reg); 472 bool IsDirty(int reg); 473 void LockTemp(int reg); 474 void ResetDef(int reg); 475 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 476 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 477 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 478 RegLocation WideToNarrow(RegLocation rl); 479 void ResetDefLoc(RegLocation rl); 480 virtual void ResetDefLocWide(RegLocation rl); 481 void ResetDefTracking(); 482 void ClobberAllRegs(); 483 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 484 void FlushAllRegs(); 485 bool RegClassMatches(int reg_class, int reg); 486 void MarkLive(int reg, int s_reg); 487 void MarkTemp(int reg); 488 void UnmarkTemp(int reg); 489 void MarkPair(int low_reg, int high_reg); 490 void MarkClean(RegLocation loc); 491 void MarkDirty(RegLocation loc); 492 void MarkInUse(int reg); 493 void CopyRegInfo(int new_reg, int old_reg); 494 bool CheckCorePoolSanity(); 495 RegLocation UpdateLoc(RegLocation loc); 496 virtual RegLocation UpdateLocWide(RegLocation loc); 497 RegLocation UpdateRawLoc(RegLocation loc); 498 499 /** 500 * @brief Used to load register location into a typed temporary or pair of temporaries. 501 * @see EvalLoc 502 * @param loc The register location to load from. 503 * @param reg_class Type of register needed. 504 * @param update Whether the liveness information should be updated. 505 * @return Returns the properly typed temporary in physical register pairs. 506 */ 507 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 508 509 /** 510 * @brief Used to load register location into a typed temporary. 511 * @param loc The register location to load from. 512 * @param reg_class Type of register needed. 513 * @param update Whether the liveness information should be updated. 514 * @return Returns the properly typed temporary in physical register. 515 */ 516 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 517 518 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 519 void DumpCounts(const RefCounts* arr, int size, const char* msg); 520 void DoPromotion(); 521 int VRegOffset(int v_reg); 522 int SRegOffset(int s_reg); 523 RegLocation GetReturnWide(bool is_double); 524 RegLocation GetReturn(bool is_float); 525 RegisterInfo* GetRegInfo(int reg); 526 527 // Shared by all targets - implemented in gen_common.cc. 528 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 529 RegLocation rl_src, RegLocation rl_dest, int lit); 530 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 531 void HandleSuspendLaunchPads(); 532 void HandleIntrinsicLaunchPads(); 533 void HandleThrowLaunchPads(); 534 void HandleSlowPaths(); 535 void GenBarrier(); 536 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 537 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val, 538 ThrowKind kind); 539 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags); 540 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 541 ThrowKind kind); 542 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 543 RegLocation rl_src2, LIR* taken, LIR* fall_through); 544 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 545 LIR* taken, LIR* fall_through); 546 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 547 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 548 RegLocation rl_src); 549 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 550 RegLocation rl_src); 551 void GenFilledNewArray(CallInfo* info); 552 void GenSput(uint32_t field_idx, RegLocation rl_src, 553 bool is_long_or_double, bool is_object); 554 void GenSget(uint32_t field_idx, RegLocation rl_dest, 555 bool is_long_or_double, bool is_object); 556 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size, 557 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 558 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size, 559 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 560 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 561 RegLocation rl_src); 562 563 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 564 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 565 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 566 void GenThrow(RegLocation rl_src); 567 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, 568 RegLocation rl_src); 569 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, 570 RegLocation rl_src); 571 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 572 RegLocation rl_src1, RegLocation rl_src2); 573 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 574 RegLocation rl_src1, RegLocation rl_shift); 575 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 576 RegLocation rl_src1, RegLocation rl_src2); 577 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 578 RegLocation rl_src, int lit); 579 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 580 RegLocation rl_src1, RegLocation rl_src2); 581 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 582 RegLocation rl_src); 583 void GenSuspendTest(int opt_flags); 584 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 585 // This will be overridden by x86 implementation. 586 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 587 588 // Shared by all targets - implemented in gen_invoke.cc. 589 int CallHelperSetup(ThreadOffset helper_offset); 590 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc); 591 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 592 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 593 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 594 bool safepoint_pc); 595 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 596 bool safepoint_pc); 597 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 598 RegLocation arg1, bool safepoint_pc); 599 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 600 int arg1, bool safepoint_pc); 601 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 602 bool safepoint_pc); 603 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 604 bool safepoint_pc); 605 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 606 bool safepoint_pc); 607 void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 608 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, int arg0, 609 RegLocation arg2, bool safepoint_pc); 610 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 611 RegLocation arg0, RegLocation arg1, 612 bool safepoint_pc); 613 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 614 bool safepoint_pc); 615 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 616 int arg2, bool safepoint_pc); 617 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 618 RegLocation arg2, bool safepoint_pc); 619 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 620 bool safepoint_pc); 621 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 622 int arg0, RegLocation arg1, RegLocation arg2, 623 bool safepoint_pc); 624 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 625 RegLocation arg0, RegLocation arg1, 626 RegLocation arg2, 627 bool safepoint_pc); 628 void GenInvoke(CallInfo* info); 629 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 630 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 631 NextCallInsn next_call_insn, 632 const MethodReference& target_method, 633 uint32_t vtable_idx, 634 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 635 bool skip_this); 636 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 637 NextCallInsn next_call_insn, 638 const MethodReference& target_method, 639 uint32_t vtable_idx, 640 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 641 bool skip_this); 642 643 /** 644 * @brief Used to determine the register location of destination. 645 * @details This is needed during generation of inline intrinsics because it finds destination of return, 646 * either the physical register or the target of move-result. 647 * @param info Information about the invoke. 648 * @return Returns the destination location. 649 */ 650 RegLocation InlineTarget(CallInfo* info); 651 652 /** 653 * @brief Used to determine the wide register location of destination. 654 * @see InlineTarget 655 * @param info Information about the invoke. 656 * @return Returns the destination location. 657 */ 658 RegLocation InlineTargetWide(CallInfo* info); 659 660 bool GenInlinedCharAt(CallInfo* info); 661 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 662 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 663 bool GenInlinedAbsInt(CallInfo* info); 664 bool GenInlinedAbsLong(CallInfo* info); 665 bool GenInlinedFloatCvt(CallInfo* info); 666 bool GenInlinedDoubleCvt(CallInfo* info); 667 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 668 bool GenInlinedStringCompareTo(CallInfo* info); 669 bool GenInlinedCurrentThread(CallInfo* info); 670 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 671 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 672 bool is_volatile, bool is_ordered); 673 int LoadArgRegs(CallInfo* info, int call_state, 674 NextCallInsn next_call_insn, 675 const MethodReference& target_method, 676 uint32_t vtable_idx, 677 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 678 bool skip_this); 679 680 // Shared by all targets - implemented in gen_loadstore.cc. 681 RegLocation LoadCurrMethod(); 682 void LoadCurrMethodDirect(int r_tgt); 683 LIR* LoadConstant(int r_dest, int value); 684 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 685 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 686 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 687 void LoadValueDirect(RegLocation rl_src, int r_dest); 688 void LoadValueDirectFixed(RegLocation rl_src, int r_dest); 689 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi); 690 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi); 691 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 692 693 /** 694 * @brief Used to do the final store in the destination as per bytecode semantics. 695 * @param rl_dest The destination dalvik register location. 696 * @param rl_src The source register location. Can be either physical register or dalvik register. 697 */ 698 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 699 700 /** 701 * @brief Used to do the final store in a wide destination as per bytecode semantics. 702 * @see StoreValue 703 * @param rl_dest The destination dalvik register location. 704 * @param rl_src The source register location. Can be either physical register or dalvik register. 705 */ 706 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 707 708 /** 709 * @brief Used to do the final store in a wide destination as per bytecode semantics. 710 * @see StoreValueWide 711 * @param rl_dest The destination dalvik register location. 712 * @param rl_src The source register location. It must be kLocPhysReg 713 * 714 * This is used for x86 two operand computations, where we have computed the correct 715 * register values that now need to be properly registered. This is used to avoid an 716 * extra pair of register copies that would result if StoreValueWide was called. 717 */ 718 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 719 720 // Shared by all targets - implemented in mir_to_lir.cc. 721 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 722 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 723 bool MethodBlockCodeGen(BasicBlock* bb); 724 void SpecialMIR2LIR(const InlineMethod& special); 725 void MethodMIR2LIR(); 726 727 // Routines that work for the generic case, but may be overriden by target. 728 /* 729 * @brief Compare memory to immediate, and branch if condition true. 730 * @param cond The condition code that when true will branch to the target. 731 * @param temp_reg A temporary register that can be used if compare to memory is not 732 * supported by the architecture. 733 * @param base_reg The register holding the base address. 734 * @param offset The offset from the base. 735 * @param check_value The immediate to compare to. 736 * @returns The branch instruction that was generated. 737 */ 738 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg, 739 int offset, int check_value, LIR* target); 740 741 // Required for target - codegen helpers. 742 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 743 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 744 virtual int LoadHelper(ThreadOffset offset) = 0; 745 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 746 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 747 int s_reg) = 0; 748 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 749 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 750 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0; 751 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0; 752 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0; 753 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 754 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 755 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 756 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 757 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 758 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0; 759 760 // Required for target - register utilities. 761 virtual bool IsFpReg(int reg) = 0; 762 virtual bool SameRegType(int reg1, int reg2) = 0; 763 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0; 764 virtual int AllocTypedTempPair(bool fp_hint, int reg_class) = 0; 765 virtual int S2d(int low_reg, int high_reg) = 0; 766 virtual int TargetReg(SpecialTargetRegister reg) = 0; 767 virtual RegLocation GetReturnAlt() = 0; 768 virtual RegLocation GetReturnWideAlt() = 0; 769 virtual RegLocation LocCReturn() = 0; 770 virtual RegLocation LocCReturnDouble() = 0; 771 virtual RegLocation LocCReturnFloat() = 0; 772 virtual RegLocation LocCReturnWide() = 0; 773 virtual uint32_t FpRegMask() = 0; 774 virtual uint64_t GetRegMaskCommon(int reg) = 0; 775 virtual void AdjustSpillMask() = 0; 776 virtual void ClobberCallerSave() = 0; 777 virtual void FlushReg(int reg) = 0; 778 virtual void FlushRegWide(int reg1, int reg2) = 0; 779 virtual void FreeCallTemps() = 0; 780 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 781 virtual void LockCallTemps() = 0; 782 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 783 virtual void CompilerInitializeRegAlloc() = 0; 784 785 // Required for target - miscellaneous. 786 virtual void AssembleLIR() = 0; 787 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 788 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 789 virtual const char* GetTargetInstFmt(int opcode) = 0; 790 virtual const char* GetTargetInstName(int opcode) = 0; 791 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 792 virtual uint64_t GetPCUseDefEncoding() = 0; 793 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 794 virtual int GetInsnSize(LIR* lir) = 0; 795 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 796 797 // Required for target - Dalvik-level generators. 798 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 799 RegLocation rl_src1, RegLocation rl_src2) = 0; 800 virtual void GenMulLong(Instruction::Code, 801 RegLocation rl_dest, RegLocation rl_src1, 802 RegLocation rl_src2) = 0; 803 virtual void GenAddLong(Instruction::Code, 804 RegLocation rl_dest, RegLocation rl_src1, 805 RegLocation rl_src2) = 0; 806 virtual void GenAndLong(Instruction::Code, 807 RegLocation rl_dest, RegLocation rl_src1, 808 RegLocation rl_src2) = 0; 809 virtual void GenArithOpDouble(Instruction::Code opcode, 810 RegLocation rl_dest, RegLocation rl_src1, 811 RegLocation rl_src2) = 0; 812 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 813 RegLocation rl_src1, RegLocation rl_src2) = 0; 814 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 815 RegLocation rl_src1, RegLocation rl_src2) = 0; 816 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 817 RegLocation rl_src) = 0; 818 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 819 820 /** 821 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 822 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 823 * that applies on integers. The generated code will write the smallest or largest value 824 * directly into the destination register as specified by the invoke information. 825 * @param info Information about the invoke. 826 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 827 * @return Returns true if successfully generated 828 */ 829 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 830 831 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 832 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 833 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 834 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 835 virtual void GenOrLong(Instruction::Code, 836 RegLocation rl_dest, RegLocation rl_src1, 837 RegLocation rl_src2) = 0; 838 virtual void GenSubLong(Instruction::Code, 839 RegLocation rl_dest, RegLocation rl_src1, 840 RegLocation rl_src2) = 0; 841 virtual void GenXorLong(Instruction::Code, 842 RegLocation rl_dest, RegLocation rl_src1, 843 RegLocation rl_src2) = 0; 844 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, 845 int offset, ThrowKind kind) = 0; 846 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, 847 bool is_div) = 0; 848 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, 849 bool is_div) = 0; 850 /* 851 * @brief Generate an integer div or rem operation by a literal. 852 * @param rl_dest Destination Location. 853 * @param rl_src1 Numerator Location. 854 * @param rl_src2 Divisor Location. 855 * @param is_div 'true' if this is a division, 'false' for a remainder. 856 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 857 */ 858 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 859 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 860 /* 861 * @brief Generate an integer div or rem operation by a literal. 862 * @param rl_dest Destination Location. 863 * @param rl_src Numerator Location. 864 * @param lit Divisor. 865 * @param is_div 'true' if this is a division, 'false' for a remainder. 866 */ 867 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, 868 int lit, bool is_div) = 0; 869 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 870 RegLocation rl_src2) = 0; 871 872 /** 873 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 874 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers. 875 * @param reg_lo The register holding the lower 32-bits. 876 * @param reg_hi The register holding the upper 32-bits. 877 */ 878 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0; 879 880 virtual void GenEntrySequence(RegLocation* ArgLocs, 881 RegLocation rl_method) = 0; 882 virtual void GenExitSequence() = 0; 883 virtual void GenFillArrayData(DexOffset table_offset, 884 RegLocation rl_src) = 0; 885 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, 886 bool is_double) = 0; 887 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 888 889 /** 890 * @brief Lowers the kMirOpSelect MIR into LIR. 891 * @param bb The basic block in which the MIR is from. 892 * @param mir The MIR whose opcode is kMirOpSelect. 893 */ 894 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 895 896 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 897 virtual void GenMoveException(RegLocation rl_dest) = 0; 898 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 899 RegLocation rl_result, int lit, int first_bit, 900 int second_bit) = 0; 901 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 902 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 903 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, 904 RegLocation rl_src) = 0; 905 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, 906 RegLocation rl_src) = 0; 907 virtual void GenSpecialCase(BasicBlock* bb, MIR* mir, 908 const InlineMethod& special) = 0; 909 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 910 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 911 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 912 RegLocation rl_index, RegLocation rl_src, int scale, 913 bool card_mark) = 0; 914 virtual void GenShiftImmOpLong(Instruction::Code opcode, 915 RegLocation rl_dest, RegLocation rl_src1, 916 RegLocation rl_shift) = 0; 917 918 // Required for target - single operation generators. 919 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 920 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target) = 0; 921 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target) = 0; 922 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 923 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) = 0; 924 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 925 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 926 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0; 927 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0; 928 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0; 929 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 930 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0; 931 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0; 932 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0; 933 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0; 934 935 /** 936 * @brief Used for generating a conditional register to register operation. 937 * @param op The opcode kind. 938 * @param cc The condition code that when true will perform the opcode. 939 * @param r_dest The destination physical register. 940 * @param r_src The source physical register. 941 * @return Returns the newly created LIR or null in case of creation failure. 942 */ 943 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) = 0; 944 945 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0; 946 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) = 0; 947 virtual LIR* OpTestSuspend(LIR* target) = 0; 948 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 949 virtual LIR* OpVldm(int rBase, int count) = 0; 950 virtual LIR* OpVstm(int rBase, int count) = 0; 951 virtual void OpLea(int rBase, int reg1, int reg2, int scale, int offset) = 0; 952 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi) = 0; 953 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 954 virtual bool InexpensiveConstantInt(int32_t value) = 0; 955 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 956 virtual bool InexpensiveConstantLong(int64_t value) = 0; 957 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 958 959 // May be optimized by targets. 960 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 961 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 962 963 // Temp workaround 964 void Workaround7250540(RegLocation rl_dest, int value); 965 966 protected: 967 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 968 969 CompilationUnit* GetCompilationUnit() { 970 return cu_; 971 } 972 /* 973 * @brief Returns the index of the lowest set bit in 'x'. 974 * @param x Value to be examined. 975 * @returns The bit number of the lowest bit set in the value. 976 */ 977 int32_t LowestSetBit(uint64_t x); 978 /* 979 * @brief Is this value a power of two? 980 * @param x Value to be examined. 981 * @returns 'true' if only 1 bit is set in the value. 982 */ 983 bool IsPowerOfTwo(uint64_t x); 984 /* 985 * @brief Do these SRs overlap? 986 * @param rl_op1 One RegLocation 987 * @param rl_op2 The other RegLocation 988 * @return 'true' if the VR pairs overlap 989 * 990 * Check to see if a result pair has a misaligned overlap with an operand pair. This 991 * is not usual for dx to generate, but it is legal (for now). In a future rev of 992 * dex, we'll want to make this case illegal. 993 */ 994 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 995 996 /* 997 * @brief Force a location (in a register) into a temporary register 998 * @param loc location of result 999 * @returns update location 1000 */ 1001 RegLocation ForceTemp(RegLocation loc); 1002 1003 /* 1004 * @brief Force a wide location (in registers) into temporary registers 1005 * @param loc location of result 1006 * @returns update location 1007 */ 1008 RegLocation ForceTempWide(RegLocation loc); 1009 1010 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1011 RegLocation rl_dest, RegLocation rl_src); 1012 1013 void AddSlowPath(LIRSlowPath* slowpath); 1014 1015 private: 1016 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1017 bool type_known_abstract, bool use_declaring_class, 1018 bool can_assume_type_is_in_dex_cache, 1019 uint32_t type_idx, RegLocation rl_dest, 1020 RegLocation rl_src); 1021 1022 void ClobberBody(RegisterInfo* p); 1023 void ResetDefBody(RegisterInfo* p) { 1024 p->def_start = NULL; 1025 p->def_end = NULL; 1026 } 1027 1028 void SetCurrentDexPc(DexOffset dexpc) { 1029 current_dalvik_offset_ = dexpc; 1030 } 1031 1032 1033 public: 1034 // TODO: add accessors for these. 1035 LIR* literal_list_; // Constants. 1036 LIR* method_literal_list_; // Method literals requiring patching. 1037 LIR* class_literal_list_; // Class literals requiring patching. 1038 LIR* code_literal_list_; // Code literals requiring patching. 1039 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1040 1041 protected: 1042 CompilationUnit* const cu_; 1043 MIRGraph* const mir_graph_; 1044 GrowableArray<SwitchTable*> switch_tables_; 1045 GrowableArray<FillArrayData*> fill_array_data_; 1046 GrowableArray<LIR*> throw_launchpads_; 1047 GrowableArray<LIR*> suspend_launchpads_; 1048 GrowableArray<LIR*> intrinsic_launchpads_; 1049 GrowableArray<RegisterInfo*> tempreg_info_; 1050 GrowableArray<RegisterInfo*> reginfo_map_; 1051 GrowableArray<void*> pointer_storage_; 1052 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1053 CodeOffset data_offset_; // starting offset of literal pool. 1054 size_t total_size_; // header + code size. 1055 LIR* block_label_list_; 1056 PromotionMap* promotion_map_; 1057 /* 1058 * TODO: The code generation utilities don't have a built-in 1059 * mechanism to propagate the original Dalvik opcode address to the 1060 * associated generated instructions. For the trace compiler, this wasn't 1061 * necessary because the interpreter handled all throws and debugging 1062 * requests. For now we'll handle this by placing the Dalvik offset 1063 * in the CompilationUnit struct before codegen for each instruction. 1064 * The low-level LIR creation utilites will pull it from here. Rework this. 1065 */ 1066 DexOffset current_dalvik_offset_; 1067 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1068 RegisterPool* reg_pool_; 1069 /* 1070 * Sanity checking for the register temp tracking. The same ssa 1071 * name should never be associated with one temp register per 1072 * instruction compilation. 1073 */ 1074 int live_sreg_; 1075 CodeBuffer code_buffer_; 1076 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1077 std::vector<uint8_t> encoded_mapping_table_; 1078 std::vector<uint32_t> core_vmap_table_; 1079 std::vector<uint32_t> fp_vmap_table_; 1080 std::vector<uint8_t> native_gc_map_; 1081 int num_core_spills_; 1082 int num_fp_spills_; 1083 int frame_size_; 1084 unsigned int core_spill_mask_; 1085 unsigned int fp_spill_mask_; 1086 LIR* first_lir_insn_; 1087 LIR* last_lir_insn_; 1088 1089 GrowableArray<LIRSlowPath*> slow_paths_; 1090}; // Class Mir2Lir 1091 1092} // namespace art 1093 1094#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1095