mir_to_lir.h revision c32447bcc8c36ee8ff265ed678c7df86936a9ebe
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_location.h" 25#include "dex/reg_storage.h" 26#include "dex/backend.h" 27#include "dex/quick/resource_mask.h" 28#include "driver/compiler_driver.h" 29#include "instruction_set.h" 30#include "leb128.h" 31#include "safe_map.h" 32#include "utils/array_ref.h" 33#include "utils/arena_allocator.h" 34#include "utils/growable_array.h" 35#include "utils/stack_checks.h" 36 37namespace art { 38 39/* 40 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 41 * add type safety (see runtime/offsets.h). 42 */ 43typedef uint32_t DexOffset; // Dex offset in code units. 44typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 45typedef uint32_t CodeOffset; // Native code offset in bytes. 46 47// Set to 1 to measure cost of suspend check. 48#define NO_SUSPEND 0 49 50#define IS_BINARY_OP (1ULL << kIsBinaryOp) 51#define IS_BRANCH (1ULL << kIsBranch) 52#define IS_IT (1ULL << kIsIT) 53#define IS_LOAD (1ULL << kMemLoad) 54#define IS_QUAD_OP (1ULL << kIsQuadOp) 55#define IS_QUIN_OP (1ULL << kIsQuinOp) 56#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 57#define IS_STORE (1ULL << kMemStore) 58#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 59#define IS_UNARY_OP (1ULL << kIsUnaryOp) 60#define NEEDS_FIXUP (1ULL << kPCRelFixup) 61#define NO_OPERAND (1ULL << kNoOperand) 62#define REG_DEF0 (1ULL << kRegDef0) 63#define REG_DEF1 (1ULL << kRegDef1) 64#define REG_DEF2 (1ULL << kRegDef2) 65#define REG_DEFA (1ULL << kRegDefA) 66#define REG_DEFD (1ULL << kRegDefD) 67#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 68#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 69#define REG_DEF_LIST0 (1ULL << kRegDefList0) 70#define REG_DEF_LIST1 (1ULL << kRegDefList1) 71#define REG_DEF_LR (1ULL << kRegDefLR) 72#define REG_DEF_SP (1ULL << kRegDefSP) 73#define REG_USE0 (1ULL << kRegUse0) 74#define REG_USE1 (1ULL << kRegUse1) 75#define REG_USE2 (1ULL << kRegUse2) 76#define REG_USE3 (1ULL << kRegUse3) 77#define REG_USE4 (1ULL << kRegUse4) 78#define REG_USEA (1ULL << kRegUseA) 79#define REG_USEC (1ULL << kRegUseC) 80#define REG_USED (1ULL << kRegUseD) 81#define REG_USEB (1ULL << kRegUseB) 82#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 83#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 84#define REG_USE_LIST0 (1ULL << kRegUseList0) 85#define REG_USE_LIST1 (1ULL << kRegUseList1) 86#define REG_USE_LR (1ULL << kRegUseLR) 87#define REG_USE_PC (1ULL << kRegUsePC) 88#define REG_USE_SP (1ULL << kRegUseSP) 89#define SETS_CCODES (1ULL << kSetsCCodes) 90#define USES_CCODES (1ULL << kUsesCCodes) 91#define USE_FP_STACK (1ULL << kUseFpStack) 92#define REG_USE_LO (1ULL << kUseLo) 93#define REG_USE_HI (1ULL << kUseHi) 94#define REG_DEF_LO (1ULL << kDefLo) 95#define REG_DEF_HI (1ULL << kDefHi) 96 97// Common combo register usage patterns. 98#define REG_DEF01 (REG_DEF0 | REG_DEF1) 99#define REG_DEF012 (REG_DEF0 | REG_DEF1 | REG_DEF2) 100#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 101#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 102#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 103#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 104#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 105#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 106#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 107#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 108#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 109#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 110#define REG_USE012 (REG_USE01 | REG_USE2) 111#define REG_USE014 (REG_USE01 | REG_USE4) 112#define REG_USE01 (REG_USE0 | REG_USE1) 113#define REG_USE02 (REG_USE0 | REG_USE2) 114#define REG_USE12 (REG_USE1 | REG_USE2) 115#define REG_USE23 (REG_USE2 | REG_USE3) 116#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 117 118// TODO: #includes need a cleanup 119#ifndef INVALID_SREG 120#define INVALID_SREG (-1) 121#endif 122 123struct BasicBlock; 124struct CallInfo; 125struct CompilationUnit; 126struct InlineMethod; 127struct MIR; 128struct LIR; 129struct RegisterInfo; 130class DexFileMethodInliner; 131class MIRGraph; 132class Mir2Lir; 133 134typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 135 const MethodReference& target_method, 136 uint32_t method_idx, uintptr_t direct_code, 137 uintptr_t direct_method, InvokeType type); 138 139typedef std::vector<uint8_t> CodeBuffer; 140 141struct UseDefMasks { 142 const ResourceMask* use_mask; // Resource mask for use. 143 const ResourceMask* def_mask; // Resource mask for def. 144}; 145 146struct AssemblyInfo { 147 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 148}; 149 150struct LIR { 151 CodeOffset offset; // Offset of this instruction. 152 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 153 int16_t opcode; 154 LIR* next; 155 LIR* prev; 156 LIR* target; 157 struct { 158 unsigned int alias_info:17; // For Dalvik register disambiguation. 159 bool is_nop:1; // LIR is optimized away. 160 unsigned int size:4; // Note: size of encoded instruction is in bytes. 161 bool use_def_invalid:1; // If true, masks should not be used. 162 unsigned int generation:1; // Used to track visitation state during fixup pass. 163 unsigned int fixup:8; // Fixup kind. 164 } flags; 165 union { 166 UseDefMasks m; // Use & Def masks used during optimization. 167 AssemblyInfo a; // Instruction info used during assembly phase. 168 } u; 169 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 170}; 171 172// Target-specific initialization. 173Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 174 ArenaAllocator* const arena); 175Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 176 ArenaAllocator* const arena); 177Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 178 ArenaAllocator* const arena); 179Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 180 ArenaAllocator* const arena); 181 182// Utility macros to traverse the LIR list. 183#define NEXT_LIR(lir) (lir->next) 184#define PREV_LIR(lir) (lir->prev) 185 186// Defines for alias_info (tracks Dalvik register references). 187#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 188#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 189#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 190#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 191 192#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 193#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 194 do { \ 195 low_reg = both_regs & 0xff; \ 196 high_reg = (both_regs >> 8) & 0xff; \ 197 } while (false) 198 199// Mask to denote sreg as the start of a 64-bit item. Must not interfere with low 16 bits. 200#define STARTING_WIDE_SREG 0x10000 201 202// TODO: replace these macros 203#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 204#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 205#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 206#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 207#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 208 209class Mir2Lir : public Backend { 210 public: 211 static constexpr bool kFailOnSizeError = true && kIsDebugBuild; 212 static constexpr bool kReportSizeError = true && kIsDebugBuild; 213 214 /* 215 * Auxiliary information describing the location of data embedded in the Dalvik 216 * byte code stream. 217 */ 218 struct EmbeddedData { 219 CodeOffset offset; // Code offset of data block. 220 const uint16_t* table; // Original dex data. 221 DexOffset vaddr; // Dalvik offset of parent opcode. 222 }; 223 224 struct FillArrayData : EmbeddedData { 225 int32_t size; 226 }; 227 228 struct SwitchTable : EmbeddedData { 229 LIR* anchor; // Reference instruction for relative offsets. 230 LIR** targets; // Array of case targets. 231 }; 232 233 /* Static register use counts */ 234 struct RefCounts { 235 int count; 236 int s_reg; 237 }; 238 239 /* 240 * Data structure tracking the mapping detween a Dalvik value (32 or 64 bits) 241 * and native register storage. The primary purpose is to reuse previuosly 242 * loaded values, if possible, and otherwise to keep the value in register 243 * storage as long as possible. 244 * 245 * NOTE 1: wide_value refers to the width of the Dalvik value contained in 246 * this register (or pair). For example, a 64-bit register containing a 32-bit 247 * Dalvik value would have wide_value==false even though the storage container itself 248 * is wide. Similarly, a 32-bit register containing half of a 64-bit Dalvik value 249 * would have wide_value==true (and additionally would have its partner field set to the 250 * other half whose wide_value field would also be true. 251 * 252 * NOTE 2: In the case of a register pair, you can determine which of the partners 253 * is the low half by looking at the s_reg names. The high s_reg will equal low_sreg + 1. 254 * 255 * NOTE 3: In the case of a 64-bit register holding a Dalvik wide value, wide_value 256 * will be true and partner==self. s_reg refers to the low-order word of the Dalvik 257 * value, and the s_reg of the high word is implied (s_reg + 1). 258 * 259 * NOTE 4: The reg and is_temp fields should always be correct. If is_temp is false no 260 * other fields have meaning. [perhaps not true, wide should work for promoted regs?] 261 * If is_temp==true and live==false, no other fields have 262 * meaning. If is_temp==true and live==true, wide_value, partner, dirty, s_reg, def_start 263 * and def_end describe the relationship between the temp register/register pair and 264 * the Dalvik value[s] described by s_reg/s_reg+1. 265 * 266 * The fields used_storage, master_storage and storage_mask are used to track allocation 267 * in light of potential aliasing. For example, consider Arm's d2, which overlaps s4 & s5. 268 * d2's storage mask would be 0x00000003, the two low-order bits denoting 64 bits of 269 * storage use. For s4, it would be 0x0000001; for s5 0x00000002. These values should not 270 * change once initialized. The "used_storage" field tracks current allocation status. 271 * Although each record contains this field, only the field from the largest member of 272 * an aliased group is used. In our case, it would be d2's. The master_storage pointer 273 * of d2, s4 and s5 would all point to d2's used_storage field. Each bit in a used_storage 274 * represents 32 bits of storage. d2's used_storage would be initialized to 0xfffffffc. 275 * Then, if we wanted to determine whether s4 could be allocated, we would "and" 276 * s4's storage_mask with s4's *master_storage. If the result is zero, s4 is free and 277 * to allocate: *master_storage |= storage_mask. To free, *master_storage &= ~storage_mask. 278 * 279 * For an X86 vector register example, storage_mask would be: 280 * 0x00000001 for 32-bit view of xmm1 281 * 0x00000003 for 64-bit view of xmm1 282 * 0x0000000f for 128-bit view of xmm1 283 * 0x000000ff for 256-bit view of ymm1 // future expansion, if needed 284 * 0x0000ffff for 512-bit view of ymm1 // future expansion, if needed 285 * 0xffffffff for 1024-bit view of ymm1 // future expansion, if needed 286 * 287 * The "liveness" of a register is handled in a similar way. The liveness_ storage is 288 * held in the widest member of an aliased set. Note, though, that for a temp register to 289 * reused as live, it must both be marked live and the associated SReg() must match the 290 * desired s_reg. This gets a little complicated when dealing with aliased registers. All 291 * members of an aliased set will share the same liveness flags, but each will individually 292 * maintain s_reg_. In this way we can know that at least one member of an 293 * aliased set is live, but will only fully match on the appropriate alias view. For example, 294 * if Arm d1 is live as a double and has s_reg_ set to Dalvik v8 (which also implies v9 295 * because it is wide), its aliases s2 and s3 will show as live, but will have 296 * s_reg_ == INVALID_SREG. An attempt to later AllocLiveReg() of v9 with a single-precision 297 * view will fail because although s3's liveness bit is set, its s_reg_ will not match v9. 298 * This will cause all members of the aliased set to be clobbered and AllocLiveReg() will 299 * report that v9 is currently not live as a single (which is what we want). 300 * 301 * NOTE: the x86 usage is still somewhat in flux. There are competing notions of how 302 * to treat xmm registers: 303 * 1. Treat them all as 128-bits wide, but denote how much data used via bytes field. 304 * o This more closely matches reality, but means you'd need to be able to get 305 * to the associated RegisterInfo struct to figure out how it's being used. 306 * o This is how 64-bit core registers will be used - always 64 bits, but the 307 * "bytes" field will be 4 for 32-bit usage and 8 for 64-bit usage. 308 * 2. View the xmm registers based on contents. 309 * o A single in a xmm2 register would be k32BitVector, while a double in xmm2 would 310 * be a k64BitVector. 311 * o Note that the two uses above would be considered distinct registers (but with 312 * the aliasing mechanism, we could detect interference). 313 * o This is how aliased double and single float registers will be handled on 314 * Arm and MIPS. 315 * Working plan is, for all targets, to follow mechanism 1 for 64-bit core registers, and 316 * mechanism 2 for aliased float registers and x86 vector registers. 317 */ 318 class RegisterInfo { 319 public: 320 RegisterInfo(RegStorage r, const ResourceMask& mask = kEncodeAll); 321 ~RegisterInfo() {} 322 static void* operator new(size_t size, ArenaAllocator* arena) { 323 return arena->Alloc(size, kArenaAllocRegAlloc); 324 } 325 326 static const uint32_t k32SoloStorageMask = 0x00000001; 327 static const uint32_t kLowSingleStorageMask = 0x00000001; 328 static const uint32_t kHighSingleStorageMask = 0x00000002; 329 static const uint32_t k64SoloStorageMask = 0x00000003; 330 static const uint32_t k128SoloStorageMask = 0x0000000f; 331 static const uint32_t k256SoloStorageMask = 0x000000ff; 332 static const uint32_t k512SoloStorageMask = 0x0000ffff; 333 static const uint32_t k1024SoloStorageMask = 0xffffffff; 334 335 bool InUse() { return (storage_mask_ & master_->used_storage_) != 0; } 336 void MarkInUse() { master_->used_storage_ |= storage_mask_; } 337 void MarkFree() { master_->used_storage_ &= ~storage_mask_; } 338 // No part of the containing storage is live in this view. 339 bool IsDead() { return (master_->liveness_ & storage_mask_) == 0; } 340 // Liveness of this view matches. Note: not equivalent to !IsDead(). 341 bool IsLive() { return (master_->liveness_ & storage_mask_) == storage_mask_; } 342 void MarkLive(int s_reg) { 343 // TODO: Anything useful to assert here? 344 s_reg_ = s_reg; 345 master_->liveness_ |= storage_mask_; 346 } 347 void MarkDead() { 348 if (SReg() != INVALID_SREG) { 349 s_reg_ = INVALID_SREG; 350 master_->liveness_ &= ~storage_mask_; 351 ResetDefBody(); 352 } 353 } 354 RegStorage GetReg() { return reg_; } 355 void SetReg(RegStorage reg) { reg_ = reg; } 356 bool IsTemp() { return is_temp_; } 357 void SetIsTemp(bool val) { is_temp_ = val; } 358 bool IsWide() { return wide_value_; } 359 void SetIsWide(bool val) { 360 wide_value_ = val; 361 if (!val) { 362 // If not wide, reset partner to self. 363 SetPartner(GetReg()); 364 } 365 } 366 bool IsDirty() { return dirty_; } 367 void SetIsDirty(bool val) { dirty_ = val; } 368 RegStorage Partner() { return partner_; } 369 void SetPartner(RegStorage partner) { partner_ = partner; } 370 int SReg() { return (!IsTemp() || IsLive()) ? s_reg_ : INVALID_SREG; } 371 const ResourceMask& DefUseMask() { return def_use_mask_; } 372 void SetDefUseMask(const ResourceMask& def_use_mask) { def_use_mask_ = def_use_mask; } 373 RegisterInfo* Master() { return master_; } 374 void SetMaster(RegisterInfo* master) { 375 master_ = master; 376 if (master != this) { 377 master_->aliased_ = true; 378 DCHECK(alias_chain_ == nullptr); 379 alias_chain_ = master_->alias_chain_; 380 master_->alias_chain_ = this; 381 } 382 } 383 bool IsAliased() { return aliased_; } 384 RegisterInfo* GetAliasChain() { return alias_chain_; } 385 uint32_t StorageMask() { return storage_mask_; } 386 void SetStorageMask(uint32_t storage_mask) { storage_mask_ = storage_mask; } 387 LIR* DefStart() { return def_start_; } 388 void SetDefStart(LIR* def_start) { def_start_ = def_start; } 389 LIR* DefEnd() { return def_end_; } 390 void SetDefEnd(LIR* def_end) { def_end_ = def_end; } 391 void ResetDefBody() { def_start_ = def_end_ = nullptr; } 392 // Find member of aliased set matching storage_used; return nullptr if none. 393 RegisterInfo* FindMatchingView(uint32_t storage_used) { 394 RegisterInfo* res = Master(); 395 for (; res != nullptr; res = res->GetAliasChain()) { 396 if (res->StorageMask() == storage_used) 397 break; 398 } 399 return res; 400 } 401 402 private: 403 RegStorage reg_; 404 bool is_temp_; // Can allocate as temp? 405 bool wide_value_; // Holds a Dalvik wide value (either itself, or part of a pair). 406 bool dirty_; // If live, is it dirty? 407 bool aliased_; // Is this the master for other aliased RegisterInfo's? 408 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register. 409 int s_reg_; // Name of live value. 410 ResourceMask def_use_mask_; // Resources for this element. 411 uint32_t used_storage_; // 1 bit per 4 bytes of storage. Unused by aliases. 412 uint32_t liveness_; // 1 bit per 4 bytes of storage. Unused by aliases. 413 RegisterInfo* master_; // Pointer to controlling storage mask. 414 uint32_t storage_mask_; // Track allocation of sub-units. 415 LIR *def_start_; // Starting inst in last def sequence. 416 LIR *def_end_; // Ending inst in last def sequence. 417 RegisterInfo* alias_chain_; // Chain of aliased registers. 418 }; 419 420 class RegisterPool { 421 public: 422 RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, 423 const ArrayRef<const RegStorage>& core_regs, 424 const ArrayRef<const RegStorage>& core64_regs, 425 const ArrayRef<const RegStorage>& sp_regs, 426 const ArrayRef<const RegStorage>& dp_regs, 427 const ArrayRef<const RegStorage>& reserved_regs, 428 const ArrayRef<const RegStorage>& reserved64_regs, 429 const ArrayRef<const RegStorage>& core_temps, 430 const ArrayRef<const RegStorage>& core64_temps, 431 const ArrayRef<const RegStorage>& sp_temps, 432 const ArrayRef<const RegStorage>& dp_temps); 433 ~RegisterPool() {} 434 static void* operator new(size_t size, ArenaAllocator* arena) { 435 return arena->Alloc(size, kArenaAllocRegAlloc); 436 } 437 void ResetNextTemp() { 438 next_core_reg_ = 0; 439 next_sp_reg_ = 0; 440 next_dp_reg_ = 0; 441 } 442 GrowableArray<RegisterInfo*> core_regs_; 443 int next_core_reg_; 444 GrowableArray<RegisterInfo*> core64_regs_; 445 int next_core64_reg_; 446 GrowableArray<RegisterInfo*> sp_regs_; // Single precision float. 447 int next_sp_reg_; 448 GrowableArray<RegisterInfo*> dp_regs_; // Double precision float. 449 int next_dp_reg_; 450 GrowableArray<RegisterInfo*>* ref_regs_; // Points to core_regs_ or core64_regs_ 451 int* next_ref_reg_; 452 453 private: 454 Mir2Lir* const m2l_; 455 }; 456 457 struct PromotionMap { 458 RegLocationType core_location:3; 459 uint8_t core_reg; 460 RegLocationType fp_location:3; 461 uint8_t fp_reg; 462 bool first_in_pair; 463 }; 464 465 // 466 // Slow paths. This object is used generate a sequence of code that is executed in the 467 // slow path. For example, resolving a string or class is slow as it will only be executed 468 // once (after that it is resolved and doesn't need to be done again). We want slow paths 469 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 470 // branch over them. 471 // 472 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 473 // the Compile() function that will be called near the end of the code generated by the 474 // method. 475 // 476 // The basic flow for a slow path is: 477 // 478 // CMP reg, #value 479 // BEQ fromfast 480 // cont: 481 // ... 482 // fast path code 483 // ... 484 // more code 485 // ... 486 // RETURN 487 /// 488 // fromfast: 489 // ... 490 // slow path code 491 // ... 492 // B cont 493 // 494 // So you see we need two labels and two branches. The first branch (called fromfast) is 495 // the conditional branch to the slow path code. The second label (called cont) is used 496 // as an unconditional branch target for getting back to the code after the slow path 497 // has completed. 498 // 499 500 class LIRSlowPath { 501 public: 502 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 503 LIR* cont = nullptr) : 504 m2l_(m2l), cu_(m2l->cu_), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 505 m2l->StartSlowPath(this); 506 } 507 virtual ~LIRSlowPath() {} 508 virtual void Compile() = 0; 509 510 static void* operator new(size_t size, ArenaAllocator* arena) { 511 return arena->Alloc(size, kArenaAllocData); 512 } 513 514 LIR *GetContinuationLabel() { 515 return cont_; 516 } 517 518 LIR *GetFromFast() { 519 return fromfast_; 520 } 521 522 protected: 523 LIR* GenerateTargetLabel(int opcode = kPseudoTargetLabel); 524 525 Mir2Lir* const m2l_; 526 CompilationUnit* const cu_; 527 const DexOffset current_dex_pc_; 528 LIR* const fromfast_; 529 LIR* const cont_; 530 }; 531 532 // Helper class for changing mem_ref_type_ until the end of current scope. See mem_ref_type_. 533 class ScopedMemRefType { 534 public: 535 ScopedMemRefType(Mir2Lir* m2l, ResourceMask::ResourceBit new_mem_ref_type) 536 : m2l_(m2l), 537 old_mem_ref_type_(m2l->mem_ref_type_) { 538 m2l_->mem_ref_type_ = new_mem_ref_type; 539 } 540 541 ~ScopedMemRefType() { 542 m2l_->mem_ref_type_ = old_mem_ref_type_; 543 } 544 545 private: 546 Mir2Lir* const m2l_; 547 ResourceMask::ResourceBit old_mem_ref_type_; 548 549 DISALLOW_COPY_AND_ASSIGN(ScopedMemRefType); 550 }; 551 552 virtual ~Mir2Lir() {} 553 554 int32_t s4FromSwitchData(const void* switch_data) { 555 return *reinterpret_cast<const int32_t*>(switch_data); 556 } 557 558 /* 559 * TODO: this is a trace JIT vestige, and its use should be reconsidered. At the time 560 * it was introduced, it was intended to be a quick best guess of type without having to 561 * take the time to do type analysis. Currently, though, we have a much better idea of 562 * the types of Dalvik virtual registers. Instead of using this for a best guess, why not 563 * just use our knowledge of type to select the most appropriate register class? 564 */ 565 RegisterClass RegClassBySize(OpSize size) { 566 if (size == kReference) { 567 return kRefReg; 568 } else { 569 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 570 size == kSignedByte) ? kCoreReg : kAnyReg; 571 } 572 } 573 574 size_t CodeBufferSizeInBytes() { 575 return code_buffer_.size() / sizeof(code_buffer_[0]); 576 } 577 578 static bool IsPseudoLirOp(int opcode) { 579 return (opcode < 0); 580 } 581 582 /* 583 * LIR operands are 32-bit integers. Sometimes, (especially for managing 584 * instructions which require PC-relative fixups), we need the operands to carry 585 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 586 * hold that index in the operand array. 587 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 588 * may be worth conditionally-compiling a set of identity functions here. 589 */ 590 uint32_t WrapPointer(void* pointer) { 591 uint32_t res = pointer_storage_.Size(); 592 pointer_storage_.Insert(pointer); 593 return res; 594 } 595 596 void* UnwrapPointer(size_t index) { 597 return pointer_storage_.Get(index); 598 } 599 600 // strdup(), but allocates from the arena. 601 char* ArenaStrdup(const char* str) { 602 size_t len = strlen(str) + 1; 603 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 604 if (res != NULL) { 605 strncpy(res, str, len); 606 } 607 return res; 608 } 609 610 // Shared by all targets - implemented in codegen_util.cc 611 void AppendLIR(LIR* lir); 612 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 613 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 614 615 /** 616 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 617 * to place in a frame. 618 * @return Returns the maximum number of compiler temporaries. 619 */ 620 size_t GetMaxPossibleCompilerTemps() const; 621 622 /** 623 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 624 * @return Returns the size in bytes for space needed for compiler temporary spill region. 625 */ 626 size_t GetNumBytesForCompilerTempSpillRegion(); 627 628 DexOffset GetCurrentDexPc() const { 629 return current_dalvik_offset_; 630 } 631 632 RegisterClass ShortyToRegClass(char shorty_type); 633 RegisterClass LocToRegClass(RegLocation loc); 634 int ComputeFrameSize(); 635 virtual void Materialize(); 636 virtual CompiledMethod* GetCompiledMethod(); 637 void MarkSafepointPC(LIR* inst); 638 void MarkSafepointPCAfter(LIR* after); 639 void SetupResourceMasks(LIR* lir); 640 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 641 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 642 void SetupRegMask(ResourceMask* mask, int reg); 643 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 644 void DumpPromotionMap(); 645 void CodegenDump(); 646 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 647 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 648 LIR* NewLIR0(int opcode); 649 LIR* NewLIR1(int opcode, int dest); 650 LIR* NewLIR2(int opcode, int dest, int src1); 651 LIR* NewLIR2NoDest(int opcode, int src, int info); 652 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 653 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 654 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 655 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 656 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 657 LIR* ScanLiteralPoolMethod(LIR* data_target, const MethodReference& method); 658 LIR* AddWordData(LIR* *constant_list_p, int value); 659 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 660 void ProcessSwitchTables(); 661 void DumpSparseSwitchTable(const uint16_t* table); 662 void DumpPackedSwitchTable(const uint16_t* table); 663 void MarkBoundary(DexOffset offset, const char* inst_str); 664 void NopLIR(LIR* lir); 665 void UnlinkLIR(LIR* lir); 666 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 667 bool IsInexpensiveConstant(RegLocation rl_src); 668 ConditionCode FlipComparisonOrder(ConditionCode before); 669 ConditionCode NegateComparison(ConditionCode before); 670 virtual void InstallLiteralPools(); 671 void InstallSwitchTables(); 672 void InstallFillArrayData(); 673 bool VerifyCatchEntries(); 674 void CreateMappingTables(); 675 void CreateNativeGcMap(); 676 int AssignLiteralOffset(CodeOffset offset); 677 int AssignSwitchTablesOffset(CodeOffset offset); 678 int AssignFillArrayDataOffset(CodeOffset offset); 679 virtual LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 680 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 681 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 682 683 virtual void StartSlowPath(LIRSlowPath* slowpath) {} 684 virtual void BeginInvoke(CallInfo* info) {} 685 virtual void EndInvoke(CallInfo* info) {} 686 687 688 // Handle bookkeeping to convert a wide RegLocation to a narrow RegLocation. No code generated. 689 virtual RegLocation NarrowRegLoc(RegLocation loc); 690 691 // Shared by all targets - implemented in local_optimizations.cc 692 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 693 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 694 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 695 virtual void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 696 697 // Shared by all targets - implemented in ralloc_util.cc 698 int GetSRegHi(int lowSreg); 699 bool LiveOut(int s_reg); 700 void SimpleRegAlloc(); 701 void ResetRegPool(); 702 void CompilerInitPool(RegisterInfo* info, RegStorage* regs, int num); 703 void DumpRegPool(GrowableArray<RegisterInfo*>* regs); 704 void DumpCoreRegPool(); 705 void DumpFpRegPool(); 706 void DumpRegPools(); 707 /* Mark a temp register as dead. Does not affect allocation state. */ 708 void Clobber(RegStorage reg); 709 void ClobberSReg(int s_reg); 710 void ClobberAliases(RegisterInfo* info, uint32_t clobber_mask); 711 int SRegToPMap(int s_reg); 712 void RecordCorePromotion(RegStorage reg, int s_reg); 713 RegStorage AllocPreservedCoreReg(int s_reg); 714 void RecordFpPromotion(RegStorage reg, int s_reg); 715 RegStorage AllocPreservedFpReg(int s_reg); 716 virtual RegStorage AllocPreservedSingle(int s_reg); 717 virtual RegStorage AllocPreservedDouble(int s_reg); 718 RegStorage AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required); 719 virtual RegStorage AllocTemp(bool required = true); 720 virtual RegStorage AllocTempWide(bool required = true); 721 virtual RegStorage AllocTempRef(bool required = true); 722 virtual RegStorage AllocTempSingle(bool required = true); 723 virtual RegStorage AllocTempDouble(bool required = true); 724 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class, bool required = true); 725 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class, bool required = true); 726 void FlushReg(RegStorage reg); 727 void FlushRegWide(RegStorage reg); 728 RegStorage AllocLiveReg(int s_reg, int reg_class, bool wide); 729 RegStorage FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg); 730 virtual void FreeTemp(RegStorage reg); 731 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 732 virtual bool IsLive(RegStorage reg); 733 virtual bool IsTemp(RegStorage reg); 734 bool IsPromoted(RegStorage reg); 735 bool IsDirty(RegStorage reg); 736 virtual void LockTemp(RegStorage reg); 737 void ResetDef(RegStorage reg); 738 void NullifyRange(RegStorage reg, int s_reg); 739 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 740 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 741 void ResetDefLoc(RegLocation rl); 742 void ResetDefLocWide(RegLocation rl); 743 void ResetDefTracking(); 744 void ClobberAllTemps(); 745 void FlushSpecificReg(RegisterInfo* info); 746 void FlushAllRegs(); 747 bool RegClassMatches(int reg_class, RegStorage reg); 748 void MarkLive(RegLocation loc); 749 void MarkTemp(RegStorage reg); 750 void UnmarkTemp(RegStorage reg); 751 void MarkWide(RegStorage reg); 752 void MarkNarrow(RegStorage reg); 753 void MarkClean(RegLocation loc); 754 void MarkDirty(RegLocation loc); 755 void MarkInUse(RegStorage reg); 756 bool CheckCorePoolSanity(); 757 virtual RegLocation UpdateLoc(RegLocation loc); 758 virtual RegLocation UpdateLocWide(RegLocation loc); 759 RegLocation UpdateRawLoc(RegLocation loc); 760 761 /** 762 * @brief Used to prepare a register location to receive a wide value. 763 * @see EvalLoc 764 * @param loc the location where the value will be stored. 765 * @param reg_class Type of register needed. 766 * @param update Whether the liveness information should be updated. 767 * @return Returns the properly typed temporary in physical register pairs. 768 */ 769 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 770 771 /** 772 * @brief Used to prepare a register location to receive a value. 773 * @param loc the location where the value will be stored. 774 * @param reg_class Type of register needed. 775 * @param update Whether the liveness information should be updated. 776 * @return Returns the properly typed temporary in physical register. 777 */ 778 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 779 780 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 781 void DumpCounts(const RefCounts* arr, int size, const char* msg); 782 void DoPromotion(); 783 int VRegOffset(int v_reg); 784 int SRegOffset(int s_reg); 785 RegLocation GetReturnWide(RegisterClass reg_class); 786 RegLocation GetReturn(RegisterClass reg_class); 787 RegisterInfo* GetRegInfo(RegStorage reg); 788 789 // Shared by all targets - implemented in gen_common.cc. 790 void AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume = nullptr); 791 virtual bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 792 RegLocation rl_src, RegLocation rl_dest, int lit); 793 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 794 virtual void HandleSlowPaths(); 795 void GenBarrier(); 796 void GenDivZeroException(); 797 // c_code holds condition code that's generated from testing divisor against 0. 798 void GenDivZeroCheck(ConditionCode c_code); 799 // reg holds divisor. 800 void GenDivZeroCheck(RegStorage reg); 801 void GenArrayBoundsCheck(RegStorage index, RegStorage length); 802 void GenArrayBoundsCheck(int32_t index, RegStorage length); 803 LIR* GenNullCheck(RegStorage reg); 804 void MarkPossibleNullPointerException(int opt_flags); 805 void MarkPossibleNullPointerExceptionAfter(int opt_flags, LIR* after); 806 void MarkPossibleStackOverflowException(); 807 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 808 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 809 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 810 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 811 virtual void GenImplicitNullCheck(RegStorage reg, int opt_flags); 812 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 813 RegLocation rl_src2, LIR* taken, LIR* fall_through); 814 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 815 LIR* taken, LIR* fall_through); 816 virtual void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 817 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 818 RegLocation rl_src); 819 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 820 RegLocation rl_src); 821 void GenFilledNewArray(CallInfo* info); 822 void GenSput(MIR* mir, RegLocation rl_src, 823 bool is_long_or_double, bool is_object); 824 void GenSget(MIR* mir, RegLocation rl_dest, 825 bool is_long_or_double, bool is_object); 826 void GenIGet(MIR* mir, int opt_flags, OpSize size, 827 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 828 void GenIPut(MIR* mir, int opt_flags, OpSize size, 829 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 830 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 831 RegLocation rl_src); 832 833 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 834 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 835 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 836 void GenThrow(RegLocation rl_src); 837 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 838 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 839 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 840 RegLocation rl_src1, RegLocation rl_src2); 841 virtual void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 842 RegLocation rl_src1, RegLocation rl_shift); 843 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 844 RegLocation rl_src, int lit); 845 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 846 RegLocation rl_src1, RegLocation rl_src2); 847 template <size_t pointer_size> 848 void GenConversionCall(ThreadOffset<pointer_size> func_offset, RegLocation rl_dest, 849 RegLocation rl_src); 850 virtual void GenSuspendTest(int opt_flags); 851 virtual void GenSuspendTestAndBranch(int opt_flags, LIR* target); 852 853 // This will be overridden by x86 implementation. 854 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 855 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 856 RegLocation rl_src1, RegLocation rl_src2); 857 858 // Shared by all targets - implemented in gen_invoke.cc. 859 template <size_t pointer_size> 860 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<pointer_size> helper_offset, bool safepoint_pc, 861 bool use_link = true); 862 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 863 RegStorage CallHelperSetup(ThreadOffset<8> helper_offset); 864 template <size_t pointer_size> 865 void CallRuntimeHelper(ThreadOffset<pointer_size> helper_offset, bool safepoint_pc); 866 template <size_t pointer_size> 867 void CallRuntimeHelperImm(ThreadOffset<pointer_size> helper_offset, int arg0, bool safepoint_pc); 868 template <size_t pointer_size> 869 void CallRuntimeHelperReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, bool safepoint_pc); 870 template <size_t pointer_size> 871 void CallRuntimeHelperRegLocation(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 872 bool safepoint_pc); 873 template <size_t pointer_size> 874 void CallRuntimeHelperImmImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg1, 875 bool safepoint_pc); 876 template <size_t pointer_size> 877 void CallRuntimeHelperImmRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 878 RegLocation arg1, bool safepoint_pc); 879 template <size_t pointer_size> 880 void CallRuntimeHelperRegLocationImm(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 881 int arg1, bool safepoint_pc); 882 template <size_t pointer_size> 883 void CallRuntimeHelperImmReg(ThreadOffset<pointer_size> helper_offset, int arg0, RegStorage arg1, 884 bool safepoint_pc); 885 template <size_t pointer_size> 886 void CallRuntimeHelperRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, int arg1, 887 bool safepoint_pc); 888 template <size_t pointer_size> 889 void CallRuntimeHelperImmMethod(ThreadOffset<pointer_size> helper_offset, int arg0, 890 bool safepoint_pc); 891 template <size_t pointer_size> 892 void CallRuntimeHelperRegMethod(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 893 bool safepoint_pc); 894 template <size_t pointer_size> 895 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<pointer_size> helper_offset, 896 RegStorage arg0, RegLocation arg2, bool safepoint_pc); 897 template <size_t pointer_size> 898 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 899 RegLocation arg0, RegLocation arg1, 900 bool safepoint_pc); 901 template <size_t pointer_size> 902 void CallRuntimeHelperRegReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 903 RegStorage arg1, bool safepoint_pc); 904 template <size_t pointer_size> 905 void CallRuntimeHelperRegRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 906 RegStorage arg1, int arg2, bool safepoint_pc); 907 template <size_t pointer_size> 908 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 909 RegLocation arg2, bool safepoint_pc); 910 template <size_t pointer_size> 911 void CallRuntimeHelperImmMethodImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg2, 912 bool safepoint_pc); 913 template <size_t pointer_size> 914 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 915 int arg0, RegLocation arg1, RegLocation arg2, 916 bool safepoint_pc); 917 template <size_t pointer_size> 918 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 919 RegLocation arg0, RegLocation arg1, 920 RegLocation arg2, 921 bool safepoint_pc); 922 void GenInvoke(CallInfo* info); 923 void GenInvokeNoInline(CallInfo* info); 924 virtual void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 925 virtual int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 926 NextCallInsn next_call_insn, 927 const MethodReference& target_method, 928 uint32_t vtable_idx, 929 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 930 bool skip_this); 931 virtual int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 932 NextCallInsn next_call_insn, 933 const MethodReference& target_method, 934 uint32_t vtable_idx, 935 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 936 bool skip_this); 937 938 /** 939 * @brief Used to determine the register location of destination. 940 * @details This is needed during generation of inline intrinsics because it finds destination 941 * of return, 942 * either the physical register or the target of move-result. 943 * @param info Information about the invoke. 944 * @return Returns the destination location. 945 */ 946 RegLocation InlineTarget(CallInfo* info); 947 948 /** 949 * @brief Used to determine the wide register location of destination. 950 * @see InlineTarget 951 * @param info Information about the invoke. 952 * @return Returns the destination location. 953 */ 954 RegLocation InlineTargetWide(CallInfo* info); 955 956 bool GenInlinedGet(CallInfo* info); 957 bool GenInlinedCharAt(CallInfo* info); 958 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 959 virtual bool GenInlinedReverseBits(CallInfo* info, OpSize size); 960 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 961 bool GenInlinedAbsInt(CallInfo* info); 962 virtual bool GenInlinedAbsLong(CallInfo* info); 963 virtual bool GenInlinedAbsFloat(CallInfo* info) = 0; 964 virtual bool GenInlinedAbsDouble(CallInfo* info) = 0; 965 bool GenInlinedFloatCvt(CallInfo* info); 966 bool GenInlinedDoubleCvt(CallInfo* info); 967 virtual bool GenInlinedArrayCopyCharArray(CallInfo* info); 968 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 969 bool GenInlinedStringCompareTo(CallInfo* info); 970 bool GenInlinedCurrentThread(CallInfo* info); 971 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 972 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 973 bool is_volatile, bool is_ordered); 974 virtual int LoadArgRegs(CallInfo* info, int call_state, 975 NextCallInsn next_call_insn, 976 const MethodReference& target_method, 977 uint32_t vtable_idx, 978 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 979 bool skip_this); 980 981 // Shared by all targets - implemented in gen_loadstore.cc. 982 RegLocation LoadCurrMethod(); 983 void LoadCurrMethodDirect(RegStorage r_tgt); 984 virtual LIR* LoadConstant(RegStorage r_dest, int value); 985 // Natural word size. 986 virtual LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 987 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile); 988 } 989 // Load 32 bits, regardless of target. 990 virtual LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { 991 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile); 992 } 993 // Load a reference at base + displacement and decompress into register. 994 virtual LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, 995 VolatileKind is_volatile) { 996 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile); 997 } 998 // Load a reference at base + index and decompress into register. 999 virtual LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 1000 int scale) { 1001 return LoadBaseIndexed(r_base, r_index, r_dest, scale, kReference); 1002 } 1003 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 1004 virtual RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 1005 // Same as above, but derive the target register class from the location record. 1006 virtual RegLocation LoadValue(RegLocation rl_src); 1007 // Load Dalvik value with 64-bit memory storage. 1008 virtual RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 1009 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 1010 virtual void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 1011 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 1012 virtual void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 1013 // Load Dalvik value with 64-bit memory storage. 1014 virtual void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 1015 // Load Dalvik value with 64-bit memory storage. 1016 virtual void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 1017 // Store an item of natural word size. 1018 virtual LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { 1019 return StoreBaseDisp(r_base, displacement, r_src, kWord, kNotVolatile); 1020 } 1021 // Store an uncompressed reference into a compressed 32-bit container. 1022 virtual LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, 1023 VolatileKind is_volatile) { 1024 return StoreBaseDisp(r_base, displacement, r_src, kReference, is_volatile); 1025 } 1026 // Store an uncompressed reference into a compressed 32-bit container by index. 1027 virtual LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 1028 int scale) { 1029 return StoreBaseIndexed(r_base, r_index, r_src, scale, kReference); 1030 } 1031 // Store 32 bits, regardless of target. 1032 virtual LIR* Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) { 1033 return StoreBaseDisp(r_base, displacement, r_src, k32, kNotVolatile); 1034 } 1035 1036 /** 1037 * @brief Used to do the final store in the destination as per bytecode semantics. 1038 * @param rl_dest The destination dalvik register location. 1039 * @param rl_src The source register location. Can be either physical register or dalvik register. 1040 */ 1041 virtual void StoreValue(RegLocation rl_dest, RegLocation rl_src); 1042 1043 /** 1044 * @brief Used to do the final store in a wide destination as per bytecode semantics. 1045 * @see StoreValue 1046 * @param rl_dest The destination dalvik register location. 1047 * @param rl_src The source register location. Can be either physical register or dalvik 1048 * register. 1049 */ 1050 virtual void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 1051 1052 /** 1053 * @brief Used to do the final store to a destination as per bytecode semantics. 1054 * @see StoreValue 1055 * @param rl_dest The destination dalvik register location. 1056 * @param rl_src The source register location. It must be kLocPhysReg 1057 * 1058 * This is used for x86 two operand computations, where we have computed the correct 1059 * register value that now needs to be properly registered. This is used to avoid an 1060 * extra register copy that would result if StoreValue was called. 1061 */ 1062 virtual void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 1063 1064 /** 1065 * @brief Used to do the final store in a wide destination as per bytecode semantics. 1066 * @see StoreValueWide 1067 * @param rl_dest The destination dalvik register location. 1068 * @param rl_src The source register location. It must be kLocPhysReg 1069 * 1070 * This is used for x86 two operand computations, where we have computed the correct 1071 * register values that now need to be properly registered. This is used to avoid an 1072 * extra pair of register copies that would result if StoreValueWide was called. 1073 */ 1074 virtual void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 1075 1076 // Shared by all targets - implemented in mir_to_lir.cc. 1077 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 1078 virtual void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1079 bool MethodBlockCodeGen(BasicBlock* bb); 1080 bool SpecialMIR2LIR(const InlineMethod& special); 1081 virtual void MethodMIR2LIR(); 1082 // Update LIR for verbose listings. 1083 void UpdateLIROffsets(); 1084 1085 /* 1086 * @brief Load the address of the dex method into the register. 1087 * @param target_method The MethodReference of the method to be invoked. 1088 * @param type How the method will be invoked. 1089 * @param register that will contain the code address. 1090 * @note register will be passed to TargetReg to get physical register. 1091 */ 1092 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 1093 SpecialTargetRegister symbolic_reg); 1094 1095 /* 1096 * @brief Load the Method* of a dex method into the register. 1097 * @param target_method The MethodReference of the method to be invoked. 1098 * @param type How the method will be invoked. 1099 * @param register that will contain the code address. 1100 * @note register will be passed to TargetReg to get physical register. 1101 */ 1102 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 1103 SpecialTargetRegister symbolic_reg); 1104 1105 /* 1106 * @brief Load the Class* of a Dex Class type into the register. 1107 * @param type How the method will be invoked. 1108 * @param register that will contain the code address. 1109 * @note register will be passed to TargetReg to get physical register. 1110 */ 1111 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 1112 1113 // Routines that work for the generic case, but may be overriden by target. 1114 /* 1115 * @brief Compare memory to immediate, and branch if condition true. 1116 * @param cond The condition code that when true will branch to the target. 1117 * @param temp_reg A temporary register that can be used if compare to memory is not 1118 * supported by the architecture. 1119 * @param base_reg The register holding the base address. 1120 * @param offset The offset from the base. 1121 * @param check_value The immediate to compare to. 1122 * @param target branch target (or nullptr) 1123 * @param compare output for getting LIR for comparison (or nullptr) 1124 * @returns The branch instruction that was generated. 1125 */ 1126 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 1127 int offset, int check_value, LIR* target, LIR** compare); 1128 1129 // Required for target - codegen helpers. 1130 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1131 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1132 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1133 virtual LIR* CheckSuspendUsingLoad() = 0; 1134 1135 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 1136 virtual RegStorage LoadHelper(ThreadOffset<8> offset) = 0; 1137 1138 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 1139 OpSize size, VolatileKind is_volatile) = 0; 1140 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 1141 int scale, OpSize size) = 0; 1142 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1143 int displacement, RegStorage r_dest, OpSize size) = 0; 1144 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 1145 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 1146 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 1147 OpSize size, VolatileKind is_volatile) = 0; 1148 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 1149 int scale, OpSize size) = 0; 1150 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1151 int displacement, RegStorage r_src, OpSize size) = 0; 1152 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 1153 1154 // Required for target - register utilities. 1155 1156 bool IsSameReg(RegStorage reg1, RegStorage reg2) { 1157 RegisterInfo* info1 = GetRegInfo(reg1); 1158 RegisterInfo* info2 = GetRegInfo(reg2); 1159 return (info1->Master() == info2->Master() && 1160 (info1->StorageMask() & info2->StorageMask()) != 0); 1161 } 1162 1163 /** 1164 * @brief Portable way of getting special registers from the backend. 1165 * @param reg Enumeration describing the purpose of the register. 1166 * @return Return the #RegStorage corresponding to the given purpose @p reg. 1167 * @note This function is currently allowed to return any suitable view of the registers 1168 * (e.g. this could be 64-bit solo or 32-bit solo for 64-bit backends). 1169 */ 1170 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 1171 1172 /** 1173 * @brief Portable way of getting special registers from the backend. 1174 * @param reg Enumeration describing the purpose of the register. 1175 * @param wide_kind What kind of view of the special register is required. 1176 * @return Return the #RegStorage corresponding to the given purpose @p reg. 1177 * 1178 * @note For 32b system, wide (kWide) views only make sense for the argument registers and the 1179 * return. In that case, this function should return a pair where the first component of 1180 * the result will be the indicated special register. 1181 */ 1182 virtual RegStorage TargetReg(SpecialTargetRegister reg, WideKind wide_kind) { 1183 if (wide_kind == kWide) { 1184 DCHECK((kArg0 <= reg && reg < kArg7) || (kFArg0 <= reg && reg < kFArg7) || (kRet0 == reg)); 1185 COMPILE_ASSERT((kArg1 == kArg0 + 1) && (kArg2 == kArg1 + 1) && (kArg3 == kArg2 + 1) && 1186 (kArg4 == kArg3 + 1) && (kArg5 == kArg4 + 1) && (kArg6 == kArg5 + 1) && 1187 (kArg7 == kArg6 + 1), kargs_range_unexpected); 1188 COMPILE_ASSERT((kFArg1 == kFArg0 + 1) && (kFArg2 == kFArg1 + 1) && (kFArg3 == kFArg2 + 1) && 1189 (kFArg4 == kFArg3 + 1) && (kFArg5 == kFArg4 + 1) && (kFArg6 == kFArg5 + 1) && 1190 (kFArg7 == kFArg6 + 1), kfargs_range_unexpected); 1191 COMPILE_ASSERT(kRet1 == kRet0 + 1, kret_range_unexpected); 1192 return RegStorage::MakeRegPair(TargetReg(reg), 1193 TargetReg(static_cast<SpecialTargetRegister>(reg + 1))); 1194 } else { 1195 return TargetReg(reg); 1196 } 1197 } 1198 1199 /** 1200 * @brief Portable way of getting a special register for storing a pointer. 1201 * @see TargetReg() 1202 */ 1203 virtual RegStorage TargetPtrReg(SpecialTargetRegister reg) { 1204 return TargetReg(reg); 1205 } 1206 1207 // Get a reg storage corresponding to the wide & ref flags of the reg location. 1208 virtual RegStorage TargetReg(SpecialTargetRegister reg, RegLocation loc) { 1209 if (loc.ref) { 1210 return TargetReg(reg, kRef); 1211 } else { 1212 return TargetReg(reg, loc.wide ? kWide : kNotWide); 1213 } 1214 } 1215 1216 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 1217 virtual RegLocation GetReturnAlt() = 0; 1218 virtual RegLocation GetReturnWideAlt() = 0; 1219 virtual RegLocation LocCReturn() = 0; 1220 virtual RegLocation LocCReturnRef() = 0; 1221 virtual RegLocation LocCReturnDouble() = 0; 1222 virtual RegLocation LocCReturnFloat() = 0; 1223 virtual RegLocation LocCReturnWide() = 0; 1224 virtual ResourceMask GetRegMaskCommon(const RegStorage& reg) const = 0; 1225 virtual void AdjustSpillMask() = 0; 1226 virtual void ClobberCallerSave() = 0; 1227 virtual void FreeCallTemps() = 0; 1228 virtual void LockCallTemps() = 0; 1229 virtual void CompilerInitializeRegAlloc() = 0; 1230 1231 // Required for target - miscellaneous. 1232 virtual void AssembleLIR() = 0; 1233 virtual void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) = 0; 1234 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 1235 ResourceMask* use_mask, ResourceMask* def_mask) = 0; 1236 virtual const char* GetTargetInstFmt(int opcode) = 0; 1237 virtual const char* GetTargetInstName(int opcode) = 0; 1238 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 1239 1240 // Note: This may return kEncodeNone on architectures that do not expose a PC. The caller must 1241 // take care of this. 1242 virtual ResourceMask GetPCUseDefEncoding() const = 0; 1243 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 1244 virtual size_t GetInsnSize(LIR* lir) = 0; 1245 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 1246 1247 // Get the register class for load/store of a field. 1248 virtual RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) = 0; 1249 1250 // Required for target - Dalvik-level generators. 1251 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1252 RegLocation rl_src1, RegLocation rl_src2) = 0; 1253 virtual void GenMulLong(Instruction::Code, 1254 RegLocation rl_dest, RegLocation rl_src1, 1255 RegLocation rl_src2) = 0; 1256 virtual void GenAddLong(Instruction::Code, 1257 RegLocation rl_dest, RegLocation rl_src1, 1258 RegLocation rl_src2) = 0; 1259 virtual void GenAndLong(Instruction::Code, 1260 RegLocation rl_dest, RegLocation rl_src1, 1261 RegLocation rl_src2) = 0; 1262 virtual void GenArithOpDouble(Instruction::Code opcode, 1263 RegLocation rl_dest, RegLocation rl_src1, 1264 RegLocation rl_src2) = 0; 1265 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 1266 RegLocation rl_src1, RegLocation rl_src2) = 0; 1267 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 1268 RegLocation rl_src1, RegLocation rl_src2) = 0; 1269 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 1270 RegLocation rl_src) = 0; 1271 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 1272 1273 /** 1274 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 1275 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 1276 * that applies on integers. The generated code will write the smallest or largest value 1277 * directly into the destination register as specified by the invoke information. 1278 * @param info Information about the invoke. 1279 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 1280 * @param is_long If true the value value is Long. Otherwise the value is Int. 1281 * @return Returns true if successfully generated 1282 */ 1283 virtual bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) = 0; 1284 virtual bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double); 1285 1286 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 1287 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 1288 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 1289 virtual void GenNotLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1290 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1291 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1292 RegLocation rl_src2) = 0; 1293 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1294 RegLocation rl_src2) = 0; 1295 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1296 RegLocation rl_src2) = 0; 1297 virtual void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1298 RegLocation rl_src2, bool is_div) = 0; 1299 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 1300 bool is_div) = 0; 1301 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 1302 bool is_div) = 0; 1303 /* 1304 * @brief Generate an integer div or rem operation by a literal. 1305 * @param rl_dest Destination Location. 1306 * @param rl_src1 Numerator Location. 1307 * @param rl_src2 Divisor Location. 1308 * @param is_div 'true' if this is a division, 'false' for a remainder. 1309 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 1310 */ 1311 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 1312 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 1313 /* 1314 * @brief Generate an integer div or rem operation by a literal. 1315 * @param rl_dest Destination Location. 1316 * @param rl_src Numerator Location. 1317 * @param lit Divisor. 1318 * @param is_div 'true' if this is a division, 'false' for a remainder. 1319 */ 1320 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 1321 bool is_div) = 0; 1322 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 1323 1324 /** 1325 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 1326 * @details This is used for generating DivideByZero checks when divisor is held in two 1327 * separate registers. 1328 * @param reg The register holding the pair of 32-bit values. 1329 */ 1330 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 1331 1332 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 1333 virtual void GenExitSequence() = 0; 1334 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 1335 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 1336 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 1337 1338 /* 1339 * @brief Handle Machine Specific MIR Extended opcodes. 1340 * @param bb The basic block in which the MIR is from. 1341 * @param mir The MIR whose opcode is not standard extended MIR. 1342 * @note Base class implementation will abort for unknown opcodes. 1343 */ 1344 virtual void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1345 1346 /** 1347 * @brief Lowers the kMirOpSelect MIR into LIR. 1348 * @param bb The basic block in which the MIR is from. 1349 * @param mir The MIR whose opcode is kMirOpSelect. 1350 */ 1351 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 1352 1353 /** 1354 * @brief Generates code to select one of the given constants depending on the given opcode. 1355 */ 1356 virtual void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 1357 int32_t true_val, int32_t false_val, RegStorage rs_dest, 1358 int dest_reg_class) = 0; 1359 1360 /** 1361 * @brief Used to generate a memory barrier in an architecture specific way. 1362 * @details The last generated LIR will be considered for use as barrier. Namely, 1363 * if the last LIR can be updated in a way where it will serve the semantics of 1364 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 1365 * that can keep the semantics. 1366 * @param barrier_kind The kind of memory barrier to generate. 1367 * @return whether a new instruction was generated. 1368 */ 1369 virtual bool GenMemBarrier(MemBarrierKind barrier_kind) = 0; 1370 1371 virtual void GenMoveException(RegLocation rl_dest) = 0; 1372 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 1373 int first_bit, int second_bit) = 0; 1374 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 1375 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 1376 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1377 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1378 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1379 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1380 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1381 RegLocation rl_index, RegLocation rl_src, int scale, 1382 bool card_mark) = 0; 1383 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1384 RegLocation rl_src1, RegLocation rl_shift) = 0; 1385 1386 // Required for target - single operation generators. 1387 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1388 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1389 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1390 LIR* target) = 0; 1391 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1392 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1393 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1394 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1395 virtual void OpEndIT(LIR* it) = 0; 1396 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1397 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1398 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1399 virtual void OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1400 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1401 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1402 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1403 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1404 1405 /** 1406 * @brief Used to generate an LIR that does a load from mem to reg. 1407 * @param r_dest The destination physical register. 1408 * @param r_base The base physical register for memory operand. 1409 * @param offset The displacement for memory operand. 1410 * @param move_type Specification on the move desired (size, alignment, register kind). 1411 * @return Returns the generate move LIR. 1412 */ 1413 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1414 MoveType move_type) = 0; 1415 1416 /** 1417 * @brief Used to generate an LIR that does a store from reg to mem. 1418 * @param r_base The base physical register for memory operand. 1419 * @param offset The displacement for memory operand. 1420 * @param r_src The destination physical register. 1421 * @param bytes_to_move The number of bytes to move. 1422 * @param is_aligned Whether the memory location is known to be aligned. 1423 * @return Returns the generate move LIR. 1424 */ 1425 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1426 MoveType move_type) = 0; 1427 1428 /** 1429 * @brief Used for generating a conditional register to register operation. 1430 * @param op The opcode kind. 1431 * @param cc The condition code that when true will perform the opcode. 1432 * @param r_dest The destination physical register. 1433 * @param r_src The source physical register. 1434 * @return Returns the newly created LIR or null in case of creation failure. 1435 */ 1436 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1437 1438 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1439 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1440 RegStorage r_src2) = 0; 1441 virtual LIR* OpTestSuspend(LIR* target) = 0; 1442 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1443 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) = 0; 1444 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1445 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1446 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1447 int offset) = 0; 1448 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1449 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1450 virtual void OpTlsCmp(ThreadOffset<8> offset, int val) = 0; 1451 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1452 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1453 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1454 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1455 1456 // May be optimized by targets. 1457 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1458 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1459 1460 // Temp workaround 1461 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1462 1463 protected: 1464 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1465 1466 CompilationUnit* GetCompilationUnit() { 1467 return cu_; 1468 } 1469 /* 1470 * @brief Returns the index of the lowest set bit in 'x'. 1471 * @param x Value to be examined. 1472 * @returns The bit number of the lowest bit set in the value. 1473 */ 1474 int32_t LowestSetBit(uint64_t x); 1475 /* 1476 * @brief Is this value a power of two? 1477 * @param x Value to be examined. 1478 * @returns 'true' if only 1 bit is set in the value. 1479 */ 1480 bool IsPowerOfTwo(uint64_t x); 1481 /* 1482 * @brief Do these SRs overlap? 1483 * @param rl_op1 One RegLocation 1484 * @param rl_op2 The other RegLocation 1485 * @return 'true' if the VR pairs overlap 1486 * 1487 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1488 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1489 * dex, we'll want to make this case illegal. 1490 */ 1491 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1492 1493 /* 1494 * @brief Force a location (in a register) into a temporary register 1495 * @param loc location of result 1496 * @returns update location 1497 */ 1498 virtual RegLocation ForceTemp(RegLocation loc); 1499 1500 /* 1501 * @brief Force a wide location (in registers) into temporary registers 1502 * @param loc location of result 1503 * @returns update location 1504 */ 1505 virtual RegLocation ForceTempWide(RegLocation loc); 1506 1507 static constexpr OpSize LoadStoreOpSize(bool wide, bool ref) { 1508 return wide ? k64 : ref ? kReference : k32; 1509 } 1510 1511 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1512 RegLocation rl_dest, RegLocation rl_src); 1513 1514 void AddSlowPath(LIRSlowPath* slowpath); 1515 1516 /* 1517 * 1518 * @brief Implement Set up instanceof a class. 1519 * @param needs_access_check 'true' if we must check the access. 1520 * @param type_known_final 'true' if the type is known to be a final class. 1521 * @param type_known_abstract 'true' if the type is known to be an abstract class. 1522 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 1523 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 1524 * @param type_idx Type index to use if use_declaring_class is 'false'. 1525 * @param rl_dest Result to be set to 0 or 1. 1526 * @param rl_src Object to be tested. 1527 */ 1528 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1529 bool type_known_abstract, bool use_declaring_class, 1530 bool can_assume_type_is_in_dex_cache, 1531 uint32_t type_idx, RegLocation rl_dest, 1532 RegLocation rl_src); 1533 /* 1534 * @brief Generate the debug_frame FDE information if possible. 1535 * @returns pointer to vector containg CFE information, or NULL. 1536 */ 1537 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1538 1539 /** 1540 * @brief Used to insert marker that can be used to associate MIR with LIR. 1541 * @details Only inserts marker if verbosity is enabled. 1542 * @param mir The mir that is currently being generated. 1543 */ 1544 void GenPrintLabel(MIR* mir); 1545 1546 /** 1547 * @brief Used to generate return sequence when there is no frame. 1548 * @details Assumes that the return registers have already been populated. 1549 */ 1550 virtual void GenSpecialExitSequence() = 0; 1551 1552 /** 1553 * @brief Used to generate code for special methods that are known to be 1554 * small enough to work in frameless mode. 1555 * @param bb The basic block of the first MIR. 1556 * @param mir The first MIR of the special method. 1557 * @param special Information about the special method. 1558 * @return Returns whether or not this was handled successfully. Returns false 1559 * if caller should punt to normal MIR2LIR conversion. 1560 */ 1561 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1562 1563 protected: 1564 void ClobberBody(RegisterInfo* p); 1565 void SetCurrentDexPc(DexOffset dexpc) { 1566 current_dalvik_offset_ = dexpc; 1567 } 1568 1569 /** 1570 * @brief Used to lock register if argument at in_position was passed that way. 1571 * @details Does nothing if the argument is passed via stack. 1572 * @param in_position The argument number whose register to lock. 1573 * @param wide Whether the argument is wide. 1574 */ 1575 void LockArg(int in_position, bool wide = false); 1576 1577 /** 1578 * @brief Used to load VR argument to a physical register. 1579 * @details The load is only done if the argument is not already in physical register. 1580 * LockArg must have been previously called. 1581 * @param in_position The argument number to load. 1582 * @param wide Whether the argument is 64-bit or not. 1583 * @return Returns the register (or register pair) for the loaded argument. 1584 */ 1585 RegStorage LoadArg(int in_position, RegisterClass reg_class, bool wide = false); 1586 1587 /** 1588 * @brief Used to load a VR argument directly to a specified register location. 1589 * @param in_position The argument number to place in register. 1590 * @param rl_dest The register location where to place argument. 1591 */ 1592 void LoadArgDirect(int in_position, RegLocation rl_dest); 1593 1594 /** 1595 * @brief Used to generate LIR for special getter method. 1596 * @param mir The mir that represents the iget. 1597 * @param special Information about the special getter method. 1598 * @return Returns whether LIR was successfully generated. 1599 */ 1600 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1601 1602 /** 1603 * @brief Used to generate LIR for special setter method. 1604 * @param mir The mir that represents the iput. 1605 * @param special Information about the special setter method. 1606 * @return Returns whether LIR was successfully generated. 1607 */ 1608 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1609 1610 /** 1611 * @brief Used to generate LIR for special return-args method. 1612 * @param mir The mir that represents the return of argument. 1613 * @param special Information about the special return-args method. 1614 * @return Returns whether LIR was successfully generated. 1615 */ 1616 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1617 1618 void AddDivZeroCheckSlowPath(LIR* branch); 1619 1620 // Copy arg0 and arg1 to kArg0 and kArg1 safely, possibly using 1621 // kArg2 as temp. 1622 virtual void CopyToArgumentRegs(RegStorage arg0, RegStorage arg1); 1623 1624 /** 1625 * @brief Load Constant into RegLocation 1626 * @param rl_dest Destination RegLocation 1627 * @param value Constant value 1628 */ 1629 virtual void GenConst(RegLocation rl_dest, int value); 1630 1631 /** 1632 * Returns true iff wide GPRs are just different views on the same physical register. 1633 */ 1634 virtual bool WideGPRsAreAliases() = 0; 1635 1636 /** 1637 * Returns true iff wide FPRs are just different views on the same physical register. 1638 */ 1639 virtual bool WideFPRsAreAliases() = 0; 1640 1641 1642 enum class WidenessCheck { // private 1643 kIgnoreWide, 1644 kCheckWide, 1645 kCheckNotWide 1646 }; 1647 1648 enum class RefCheck { // private 1649 kIgnoreRef, 1650 kCheckRef, 1651 kCheckNotRef 1652 }; 1653 1654 enum class FPCheck { // private 1655 kIgnoreFP, 1656 kCheckFP, 1657 kCheckNotFP 1658 }; 1659 1660 /** 1661 * Check whether a reg storage seems well-formed, that is, if a reg storage is valid, 1662 * that it has the expected form for the flags. 1663 * A flag value of 0 means ignore. A flag value of -1 means false. A flag value of 1 means true. 1664 */ 1665 void CheckRegStorageImpl(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp, bool fail, 1666 bool report) 1667 const; 1668 1669 /** 1670 * Check whether a reg location seems well-formed, that is, if a reg storage is encoded, 1671 * that it has the expected size. 1672 */ 1673 void CheckRegLocationImpl(RegLocation rl, bool fail, bool report) const; 1674 1675 // See CheckRegStorageImpl. Will print or fail depending on kFailOnSizeError and 1676 // kReportSizeError. 1677 void CheckRegStorage(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp) const; 1678 // See CheckRegLocationImpl. 1679 void CheckRegLocation(RegLocation rl) const; 1680 1681 public: 1682 // TODO: add accessors for these. 1683 LIR* literal_list_; // Constants. 1684 LIR* method_literal_list_; // Method literals requiring patching. 1685 LIR* class_literal_list_; // Class literals requiring patching. 1686 LIR* code_literal_list_; // Code literals requiring patching. 1687 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1688 1689 protected: 1690 CompilationUnit* const cu_; 1691 MIRGraph* const mir_graph_; 1692 GrowableArray<SwitchTable*> switch_tables_; 1693 GrowableArray<FillArrayData*> fill_array_data_; 1694 GrowableArray<RegisterInfo*> tempreg_info_; 1695 GrowableArray<RegisterInfo*> reginfo_map_; 1696 GrowableArray<void*> pointer_storage_; 1697 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1698 CodeOffset data_offset_; // starting offset of literal pool. 1699 size_t total_size_; // header + code size. 1700 LIR* block_label_list_; 1701 PromotionMap* promotion_map_; 1702 /* 1703 * TODO: The code generation utilities don't have a built-in 1704 * mechanism to propagate the original Dalvik opcode address to the 1705 * associated generated instructions. For the trace compiler, this wasn't 1706 * necessary because the interpreter handled all throws and debugging 1707 * requests. For now we'll handle this by placing the Dalvik offset 1708 * in the CompilationUnit struct before codegen for each instruction. 1709 * The low-level LIR creation utilites will pull it from here. Rework this. 1710 */ 1711 DexOffset current_dalvik_offset_; 1712 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1713 RegisterPool* reg_pool_; 1714 /* 1715 * Sanity checking for the register temp tracking. The same ssa 1716 * name should never be associated with one temp register per 1717 * instruction compilation. 1718 */ 1719 int live_sreg_; 1720 CodeBuffer code_buffer_; 1721 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1722 std::vector<uint8_t> encoded_mapping_table_; 1723 std::vector<uint32_t> core_vmap_table_; 1724 std::vector<uint32_t> fp_vmap_table_; 1725 std::vector<uint8_t> native_gc_map_; 1726 int num_core_spills_; 1727 int num_fp_spills_; 1728 int frame_size_; 1729 unsigned int core_spill_mask_; 1730 unsigned int fp_spill_mask_; 1731 LIR* first_lir_insn_; 1732 LIR* last_lir_insn_; 1733 1734 GrowableArray<LIRSlowPath*> slow_paths_; 1735 1736 // The memory reference type for new LIRs. 1737 // NOTE: Passing this as an explicit parameter by all functions that directly or indirectly 1738 // invoke RawLIR() would clutter the code and reduce the readability. 1739 ResourceMask::ResourceBit mem_ref_type_; 1740 1741 // Each resource mask now takes 16-bytes, so having both use/def masks directly in a LIR 1742 // would consume 32 bytes per LIR. Instead, the LIR now holds only pointers to the masks 1743 // (i.e. 8 bytes on 32-bit arch, 16 bytes on 64-bit arch) and we use ResourceMaskCache 1744 // to deduplicate the masks. 1745 ResourceMaskCache mask_cache_; 1746}; // Class Mir2Lir 1747 1748} // namespace art 1749 1750#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1751