mir_to_lir.h revision d6ed642458c8820e1beca72f3d7b5f0be4a4b64b
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 95#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 96#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 97#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 98#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 99#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 100#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 101#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 102#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 103#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 104#define REG_USE012 (REG_USE01 | REG_USE2) 105#define REG_USE014 (REG_USE01 | REG_USE4) 106#define REG_USE01 (REG_USE0 | REG_USE1) 107#define REG_USE02 (REG_USE0 | REG_USE2) 108#define REG_USE12 (REG_USE1 | REG_USE2) 109#define REG_USE23 (REG_USE2 | REG_USE3) 110#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 111 112struct BasicBlock; 113struct CallInfo; 114struct CompilationUnit; 115struct InlineMethod; 116struct MIR; 117struct LIR; 118struct RegLocation; 119struct RegisterInfo; 120class DexFileMethodInliner; 121class MIRGraph; 122class Mir2Lir; 123 124typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 125 const MethodReference& target_method, 126 uint32_t method_idx, uintptr_t direct_code, 127 uintptr_t direct_method, InvokeType type); 128 129typedef std::vector<uint8_t> CodeBuffer; 130 131struct UseDefMasks { 132 uint64_t use_mask; // Resource mask for use. 133 uint64_t def_mask; // Resource mask for def. 134}; 135 136struct AssemblyInfo { 137 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 138}; 139 140struct LIR { 141 CodeOffset offset; // Offset of this instruction. 142 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 143 int16_t opcode; 144 LIR* next; 145 LIR* prev; 146 LIR* target; 147 struct { 148 unsigned int alias_info:17; // For Dalvik register disambiguation. 149 bool is_nop:1; // LIR is optimized away. 150 unsigned int size:4; // Note: size of encoded instruction is in bytes. 151 bool use_def_invalid:1; // If true, masks should not be used. 152 unsigned int generation:1; // Used to track visitation state during fixup pass. 153 unsigned int fixup:8; // Fixup kind. 154 } flags; 155 union { 156 UseDefMasks m; // Use & Def masks used during optimization. 157 AssemblyInfo a; // Instruction info used during assembly phase. 158 } u; 159 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 160}; 161 162// Target-specific initialization. 163Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 164 ArenaAllocator* const arena); 165Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 166 ArenaAllocator* const arena); 167Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 168 ArenaAllocator* const arena); 169 170// Utility macros to traverse the LIR list. 171#define NEXT_LIR(lir) (lir->next) 172#define PREV_LIR(lir) (lir->prev) 173 174// Defines for alias_info (tracks Dalvik register references). 175#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 176#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 177#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 178#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 179 180// Common resource macros. 181#define ENCODE_CCODE (1ULL << kCCode) 182#define ENCODE_FP_STATUS (1ULL << kFPStatus) 183 184// Abstract memory locations. 185#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 186#define ENCODE_LITERAL (1ULL << kLiteral) 187#define ENCODE_HEAP_REF (1ULL << kHeapRef) 188#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 189 190#define ENCODE_ALL (~0ULL) 191#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 192 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 193 194#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 195#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 196 do { \ 197 low_reg = both_regs & 0xff; \ 198 high_reg = (both_regs >> 8) & 0xff; \ 199 } while (false) 200 201// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 202#define STARTING_DOUBLE_SREG 0x10000 203 204// TODO: replace these macros 205#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 206#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 207#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 208#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 209#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 210 211class Mir2Lir : public Backend { 212 public: 213 /* 214 * Auxiliary information describing the location of data embedded in the Dalvik 215 * byte code stream. 216 */ 217 struct EmbeddedData { 218 CodeOffset offset; // Code offset of data block. 219 const uint16_t* table; // Original dex data. 220 DexOffset vaddr; // Dalvik offset of parent opcode. 221 }; 222 223 struct FillArrayData : EmbeddedData { 224 int32_t size; 225 }; 226 227 struct SwitchTable : EmbeddedData { 228 LIR* anchor; // Reference instruction for relative offsets. 229 LIR** targets; // Array of case targets. 230 }; 231 232 /* Static register use counts */ 233 struct RefCounts { 234 int count; 235 int s_reg; 236 }; 237 238 /* 239 * Data structure tracking the mapping between a Dalvik register (pair) and a 240 * native register (pair). The idea is to reuse the previously loaded value 241 * if possible, otherwise to keep the value in a native register as long as 242 * possible. 243 */ 244 struct RegisterInfo { 245 int reg; // Reg number 246 bool in_use; // Has it been allocated? 247 bool is_temp; // Can allocate as temp? 248 bool pair; // Part of a register pair? 249 int partner; // If pair, other reg of pair. 250 bool live; // Is there an associated SSA name? 251 bool dirty; // If live, is it dirty? 252 int s_reg; // Name of live value. 253 LIR *def_start; // Starting inst in last def sequence. 254 LIR *def_end; // Ending inst in last def sequence. 255 }; 256 257 struct RegisterPool { 258 int num_core_regs; 259 RegisterInfo *core_regs; 260 int next_core_reg; 261 int num_fp_regs; 262 RegisterInfo *FPRegs; 263 int next_fp_reg; 264 }; 265 266 struct PromotionMap { 267 RegLocationType core_location:3; 268 uint8_t core_reg; 269 RegLocationType fp_location:3; 270 uint8_t FpReg; 271 bool first_in_pair; 272 }; 273 274 // 275 // Slow paths. This object is used generate a sequence of code that is executed in the 276 // slow path. For example, resolving a string or class is slow as it will only be executed 277 // once (after that it is resolved and doesn't need to be done again). We want slow paths 278 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 279 // branch over them. 280 // 281 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 282 // the Compile() function that will be called near the end of the code generated by the 283 // method. 284 // 285 // The basic flow for a slow path is: 286 // 287 // CMP reg, #value 288 // BEQ fromfast 289 // cont: 290 // ... 291 // fast path code 292 // ... 293 // more code 294 // ... 295 // RETURN 296 /// 297 // fromfast: 298 // ... 299 // slow path code 300 // ... 301 // B cont 302 // 303 // So you see we need two labels and two branches. The first branch (called fromfast) is 304 // the conditional branch to the slow path code. The second label (called cont) is used 305 // as an unconditional branch target for getting back to the code after the slow path 306 // has completed. 307 // 308 309 class LIRSlowPath { 310 public: 311 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 312 LIR* cont = nullptr) : 313 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 314 } 315 virtual ~LIRSlowPath() {} 316 virtual void Compile() = 0; 317 318 static void* operator new(size_t size, ArenaAllocator* arena) { 319 return arena->Alloc(size, kArenaAllocData); 320 } 321 322 protected: 323 LIR* GenerateTargetLabel(); 324 325 Mir2Lir* const m2l_; 326 const DexOffset current_dex_pc_; 327 LIR* const fromfast_; 328 LIR* const cont_; 329 }; 330 331 virtual ~Mir2Lir() {} 332 333 int32_t s4FromSwitchData(const void* switch_data) { 334 return *reinterpret_cast<const int32_t*>(switch_data); 335 } 336 337 RegisterClass oat_reg_class_by_size(OpSize size) { 338 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 339 size == kSignedByte) ? kCoreReg : kAnyReg; 340 } 341 342 size_t CodeBufferSizeInBytes() { 343 return code_buffer_.size() / sizeof(code_buffer_[0]); 344 } 345 346 static bool IsPseudoLirOp(int opcode) { 347 return (opcode < 0); 348 } 349 350 /* 351 * LIR operands are 32-bit integers. Sometimes, (especially for managing 352 * instructions which require PC-relative fixups), we need the operands to carry 353 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 354 * hold that index in the operand array. 355 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 356 * may be worth conditionally-compiling a set of identity functions here. 357 */ 358 uint32_t WrapPointer(void* pointer) { 359 uint32_t res = pointer_storage_.Size(); 360 pointer_storage_.Insert(pointer); 361 return res; 362 } 363 364 void* UnwrapPointer(size_t index) { 365 return pointer_storage_.Get(index); 366 } 367 368 // strdup(), but allocates from the arena. 369 char* ArenaStrdup(const char* str) { 370 size_t len = strlen(str) + 1; 371 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 372 if (res != NULL) { 373 strncpy(res, str, len); 374 } 375 return res; 376 } 377 378 // Shared by all targets - implemented in codegen_util.cc 379 void AppendLIR(LIR* lir); 380 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 381 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 382 383 /** 384 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 385 * to place in a frame. 386 * @return Returns the maximum number of compiler temporaries. 387 */ 388 size_t GetMaxPossibleCompilerTemps() const; 389 390 /** 391 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 392 * @return Returns the size in bytes for space needed for compiler temporary spill region. 393 */ 394 size_t GetNumBytesForCompilerTempSpillRegion(); 395 396 DexOffset GetCurrentDexPc() const { 397 return current_dalvik_offset_; 398 } 399 400 int ComputeFrameSize(); 401 virtual void Materialize(); 402 virtual CompiledMethod* GetCompiledMethod(); 403 void MarkSafepointPC(LIR* inst); 404 void SetupResourceMasks(LIR* lir); 405 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 406 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 407 void SetupRegMask(uint64_t* mask, int reg); 408 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 409 void DumpPromotionMap(); 410 void CodegenDump(); 411 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 412 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 413 LIR* NewLIR0(int opcode); 414 LIR* NewLIR1(int opcode, int dest); 415 LIR* NewLIR2(int opcode, int dest, int src1); 416 LIR* NewLIR2NoDest(int opcode, int src, int info); 417 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 418 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 419 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 420 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 421 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 422 LIR* AddWordData(LIR* *constant_list_p, int value); 423 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 424 void ProcessSwitchTables(); 425 void DumpSparseSwitchTable(const uint16_t* table); 426 void DumpPackedSwitchTable(const uint16_t* table); 427 void MarkBoundary(DexOffset offset, const char* inst_str); 428 void NopLIR(LIR* lir); 429 void UnlinkLIR(LIR* lir); 430 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 431 bool IsInexpensiveConstant(RegLocation rl_src); 432 ConditionCode FlipComparisonOrder(ConditionCode before); 433 ConditionCode NegateComparison(ConditionCode before); 434 virtual void InstallLiteralPools(); 435 void InstallSwitchTables(); 436 void InstallFillArrayData(); 437 bool VerifyCatchEntries(); 438 void CreateMappingTables(); 439 void CreateNativeGcMap(); 440 int AssignLiteralOffset(CodeOffset offset); 441 int AssignSwitchTablesOffset(CodeOffset offset); 442 int AssignFillArrayDataOffset(CodeOffset offset); 443 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 444 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 445 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 446 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 447 RegLocation NarrowRegLoc(RegLocation loc); 448 449 // Shared by all targets - implemented in local_optimizations.cc 450 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 451 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 452 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 453 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 454 455 // Shared by all targets - implemented in ralloc_util.cc 456 int GetSRegHi(int lowSreg); 457 bool oat_live_out(int s_reg); 458 int oatSSASrc(MIR* mir, int num); 459 void SimpleRegAlloc(); 460 void ResetRegPool(); 461 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 462 void DumpRegPool(RegisterInfo* p, int num_regs); 463 void DumpCoreRegPool(); 464 void DumpFpRegPool(); 465 /* Mark a temp register as dead. Does not affect allocation state. */ 466 void Clobber(int reg) { 467 ClobberBody(GetRegInfo(reg)); 468 } 469 void Clobber(RegStorage reg); 470 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 471 void ClobberSReg(int s_reg); 472 int SRegToPMap(int s_reg); 473 void RecordCorePromotion(RegStorage reg, int s_reg); 474 RegStorage AllocPreservedCoreReg(int s_reg); 475 void RecordFpPromotion(RegStorage reg, int s_reg); 476 RegStorage AllocPreservedSingle(int s_reg); 477 RegStorage AllocPreservedDouble(int s_reg); 478 RegStorage AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 479 virtual RegStorage AllocTempDouble(); 480 RegStorage AllocFreeTemp(); 481 RegStorage AllocTemp(); 482 RegStorage AllocTempFloat(); 483 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 484 RegisterInfo* AllocLive(int s_reg, int reg_class); 485 void FreeTemp(int reg); 486 void FreeTemp(RegStorage reg); 487 RegisterInfo* IsLive(int reg); 488 bool IsLive(RegStorage reg); 489 RegisterInfo* IsTemp(int reg); 490 bool IsTemp(RegStorage reg); 491 RegisterInfo* IsPromoted(int reg); 492 bool IsPromoted(RegStorage reg); 493 bool IsDirty(int reg); 494 bool IsDirty(RegStorage reg); 495 void LockTemp(int reg); 496 void LockTemp(RegStorage reg); 497 void ResetDef(int reg); 498 void ResetDef(RegStorage reg); 499 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 500 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 501 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 502 RegLocation WideToNarrow(RegLocation rl); 503 void ResetDefLoc(RegLocation rl); 504 virtual void ResetDefLocWide(RegLocation rl); 505 void ResetDefTracking(); 506 void ClobberAllRegs(); 507 void FlushSpecificReg(RegisterInfo* info); 508 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 509 void FlushAllRegs(); 510 bool RegClassMatches(int reg_class, RegStorage reg); 511 void MarkLive(RegStorage reg, int s_reg); 512 void MarkTemp(int reg); 513 void MarkTemp(RegStorage reg); 514 void UnmarkTemp(int reg); 515 void UnmarkTemp(RegStorage reg); 516 void MarkPair(int low_reg, int high_reg); 517 void MarkClean(RegLocation loc); 518 void MarkDirty(RegLocation loc); 519 void MarkInUse(int reg); 520 void MarkInUse(RegStorage reg); 521 void CopyRegInfo(int new_reg, int old_reg); 522 void CopyRegInfo(RegStorage new_reg, RegStorage old_reg); 523 bool CheckCorePoolSanity(); 524 RegLocation UpdateLoc(RegLocation loc); 525 virtual RegLocation UpdateLocWide(RegLocation loc); 526 RegLocation UpdateRawLoc(RegLocation loc); 527 528 /** 529 * @brief Used to load register location into a typed temporary or pair of temporaries. 530 * @see EvalLoc 531 * @param loc The register location to load from. 532 * @param reg_class Type of register needed. 533 * @param update Whether the liveness information should be updated. 534 * @return Returns the properly typed temporary in physical register pairs. 535 */ 536 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 537 538 /** 539 * @brief Used to load register location into a typed temporary. 540 * @param loc The register location to load from. 541 * @param reg_class Type of register needed. 542 * @param update Whether the liveness information should be updated. 543 * @return Returns the properly typed temporary in physical register. 544 */ 545 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 546 547 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 548 void DumpCounts(const RefCounts* arr, int size, const char* msg); 549 void DoPromotion(); 550 int VRegOffset(int v_reg); 551 int SRegOffset(int s_reg); 552 RegLocation GetReturnWide(bool is_double); 553 RegLocation GetReturn(bool is_float); 554 RegisterInfo* GetRegInfo(int reg); 555 556 // Shared by all targets - implemented in gen_common.cc. 557 void AddIntrinsicLaunchpad(CallInfo* info, LIR* branch, LIR* resume = nullptr); 558 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 559 RegLocation rl_src, RegLocation rl_dest, int lit); 560 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 561 void HandleSuspendLaunchPads(); 562 void HandleThrowLaunchPads(); 563 void HandleSlowPaths(); 564 void GenBarrier(); 565 void AddDivZeroSlowPath(ConditionCode c_code); 566 void AddDivZeroSlowPath(ConditionCode c_code, RegStorage reg, int imm_val); 567 void MarkPossibleNullPointerException(int opt_flags); 568 void MarkPossibleStackOverflowException(); 569 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 570 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 571 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 572 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 573 LIR* GenRegRegCheck(ConditionCode c_code, RegStorage reg1, RegStorage reg2, ThrowKind kind); 574 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 575 RegLocation rl_src2, LIR* taken, LIR* fall_through); 576 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 577 LIR* taken, LIR* fall_through); 578 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 579 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 580 RegLocation rl_src); 581 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 582 RegLocation rl_src); 583 void GenFilledNewArray(CallInfo* info); 584 void GenSput(MIR* mir, RegLocation rl_src, 585 bool is_long_or_double, bool is_object); 586 void GenSget(MIR* mir, RegLocation rl_dest, 587 bool is_long_or_double, bool is_object); 588 void GenIGet(MIR* mir, int opt_flags, OpSize size, 589 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 590 void GenIPut(MIR* mir, int opt_flags, OpSize size, 591 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 592 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 593 RegLocation rl_src); 594 595 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 596 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 597 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 598 void GenThrow(RegLocation rl_src); 599 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 600 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 601 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 602 RegLocation rl_src1, RegLocation rl_src2); 603 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 604 RegLocation rl_src1, RegLocation rl_shift); 605 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 606 RegLocation rl_src, int lit); 607 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 608 RegLocation rl_src1, RegLocation rl_src2); 609 void GenConversionCall(ThreadOffset<4> func_offset, RegLocation rl_dest, 610 RegLocation rl_src); 611 void GenSuspendTest(int opt_flags); 612 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 613 614 // This will be overridden by x86 implementation. 615 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 616 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 617 RegLocation rl_src1, RegLocation rl_src2); 618 619 // Shared by all targets - implemented in gen_invoke.cc. 620 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, bool safepoint_pc, 621 bool use_link = true); 622 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 623 void CallRuntimeHelper(ThreadOffset<4> helper_offset, bool safepoint_pc); 624 void CallRuntimeHelperImm(ThreadOffset<4> helper_offset, int arg0, bool safepoint_pc); 625 void CallRuntimeHelperReg(ThreadOffset<4> helper_offset, RegStorage arg0, bool safepoint_pc); 626 void CallRuntimeHelperRegLocation(ThreadOffset<4> helper_offset, RegLocation arg0, 627 bool safepoint_pc); 628 void CallRuntimeHelperImmImm(ThreadOffset<4> helper_offset, int arg0, int arg1, 629 bool safepoint_pc); 630 void CallRuntimeHelperImmRegLocation(ThreadOffset<4> helper_offset, int arg0, 631 RegLocation arg1, bool safepoint_pc); 632 void CallRuntimeHelperRegLocationImm(ThreadOffset<4> helper_offset, RegLocation arg0, 633 int arg1, bool safepoint_pc); 634 void CallRuntimeHelperImmReg(ThreadOffset<4> helper_offset, int arg0, RegStorage arg1, 635 bool safepoint_pc); 636 void CallRuntimeHelperRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, int arg1, 637 bool safepoint_pc); 638 void CallRuntimeHelperImmMethod(ThreadOffset<4> helper_offset, int arg0, 639 bool safepoint_pc); 640 void CallRuntimeHelperRegMethod(ThreadOffset<4> helper_offset, RegStorage arg0, 641 bool safepoint_pc); 642 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<4> helper_offset, RegStorage arg0, 643 RegLocation arg2, bool safepoint_pc); 644 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<4> helper_offset, 645 RegLocation arg0, RegLocation arg1, 646 bool safepoint_pc); 647 void CallRuntimeHelperRegReg(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 648 bool safepoint_pc); 649 void CallRuntimeHelperRegRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 650 int arg2, bool safepoint_pc); 651 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<4> helper_offset, int arg0, 652 RegLocation arg2, bool safepoint_pc); 653 void CallRuntimeHelperImmMethodImm(ThreadOffset<4> helper_offset, int arg0, int arg2, 654 bool safepoint_pc); 655 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<4> helper_offset, 656 int arg0, RegLocation arg1, RegLocation arg2, 657 bool safepoint_pc); 658 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<4> helper_offset, 659 RegLocation arg0, RegLocation arg1, 660 RegLocation arg2, 661 bool safepoint_pc); 662 void GenInvoke(CallInfo* info); 663 void GenInvokeNoInline(CallInfo* info); 664 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 665 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 666 NextCallInsn next_call_insn, 667 const MethodReference& target_method, 668 uint32_t vtable_idx, 669 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 670 bool skip_this); 671 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 672 NextCallInsn next_call_insn, 673 const MethodReference& target_method, 674 uint32_t vtable_idx, 675 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 676 bool skip_this); 677 678 /** 679 * @brief Used to determine the register location of destination. 680 * @details This is needed during generation of inline intrinsics because it finds destination 681 * of return, 682 * either the physical register or the target of move-result. 683 * @param info Information about the invoke. 684 * @return Returns the destination location. 685 */ 686 RegLocation InlineTarget(CallInfo* info); 687 688 /** 689 * @brief Used to determine the wide register location of destination. 690 * @see InlineTarget 691 * @param info Information about the invoke. 692 * @return Returns the destination location. 693 */ 694 RegLocation InlineTargetWide(CallInfo* info); 695 696 bool GenInlinedCharAt(CallInfo* info); 697 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 698 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 699 bool GenInlinedAbsInt(CallInfo* info); 700 bool GenInlinedAbsLong(CallInfo* info); 701 bool GenInlinedAbsFloat(CallInfo* info); 702 bool GenInlinedAbsDouble(CallInfo* info); 703 bool GenInlinedFloatCvt(CallInfo* info); 704 bool GenInlinedDoubleCvt(CallInfo* info); 705 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 706 bool GenInlinedStringCompareTo(CallInfo* info); 707 bool GenInlinedCurrentThread(CallInfo* info); 708 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 709 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 710 bool is_volatile, bool is_ordered); 711 int LoadArgRegs(CallInfo* info, int call_state, 712 NextCallInsn next_call_insn, 713 const MethodReference& target_method, 714 uint32_t vtable_idx, 715 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 716 bool skip_this); 717 718 // Shared by all targets - implemented in gen_loadstore.cc. 719 RegLocation LoadCurrMethod(); 720 void LoadCurrMethodDirect(RegStorage r_tgt); 721 LIR* LoadConstant(RegStorage r_dest, int value); 722 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest); 723 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 724 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 725 void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 726 void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 727 void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 728 void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 729 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src); 730 731 /** 732 * @brief Used to do the final store in the destination as per bytecode semantics. 733 * @param rl_dest The destination dalvik register location. 734 * @param rl_src The source register location. Can be either physical register or dalvik register. 735 */ 736 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 737 738 /** 739 * @brief Used to do the final store in a wide destination as per bytecode semantics. 740 * @see StoreValue 741 * @param rl_dest The destination dalvik register location. 742 * @param rl_src The source register location. Can be either physical register or dalvik 743 * register. 744 */ 745 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 746 747 /** 748 * @brief Used to do the final store to a destination as per bytecode semantics. 749 * @see StoreValue 750 * @param rl_dest The destination dalvik register location. 751 * @param rl_src The source register location. It must be kLocPhysReg 752 * 753 * This is used for x86 two operand computations, where we have computed the correct 754 * register value that now needs to be properly registered. This is used to avoid an 755 * extra register copy that would result if StoreValue was called. 756 */ 757 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 758 759 /** 760 * @brief Used to do the final store in a wide destination as per bytecode semantics. 761 * @see StoreValueWide 762 * @param rl_dest The destination dalvik register location. 763 * @param rl_src The source register location. It must be kLocPhysReg 764 * 765 * This is used for x86 two operand computations, where we have computed the correct 766 * register values that now need to be properly registered. This is used to avoid an 767 * extra pair of register copies that would result if StoreValueWide was called. 768 */ 769 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 770 771 // Shared by all targets - implemented in mir_to_lir.cc. 772 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 773 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 774 bool MethodBlockCodeGen(BasicBlock* bb); 775 bool SpecialMIR2LIR(const InlineMethod& special); 776 void MethodMIR2LIR(); 777 778 /* 779 * @brief Load the address of the dex method into the register. 780 * @param target_method The MethodReference of the method to be invoked. 781 * @param type How the method will be invoked. 782 * @param register that will contain the code address. 783 * @note register will be passed to TargetReg to get physical register. 784 */ 785 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 786 SpecialTargetRegister symbolic_reg); 787 788 /* 789 * @brief Load the Method* of a dex method into the register. 790 * @param target_method The MethodReference of the method to be invoked. 791 * @param type How the method will be invoked. 792 * @param register that will contain the code address. 793 * @note register will be passed to TargetReg to get physical register. 794 */ 795 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 796 SpecialTargetRegister symbolic_reg); 797 798 /* 799 * @brief Load the Class* of a Dex Class type into the register. 800 * @param type How the method will be invoked. 801 * @param register that will contain the code address. 802 * @note register will be passed to TargetReg to get physical register. 803 */ 804 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 805 806 // Routines that work for the generic case, but may be overriden by target. 807 /* 808 * @brief Compare memory to immediate, and branch if condition true. 809 * @param cond The condition code that when true will branch to the target. 810 * @param temp_reg A temporary register that can be used if compare to memory is not 811 * supported by the architecture. 812 * @param base_reg The register holding the base address. 813 * @param offset The offset from the base. 814 * @param check_value The immediate to compare to. 815 * @returns The branch instruction that was generated. 816 */ 817 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 818 int offset, int check_value, LIR* target); 819 820 // Required for target - codegen helpers. 821 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 822 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 823 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 824 virtual LIR* CheckSuspendUsingLoad() = 0; 825 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 826 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 827 int s_reg) = 0; 828 virtual LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, 829 int s_reg) = 0; 830 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 831 int scale, OpSize size) = 0; 832 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 833 int displacement, RegStorage r_dest, RegStorage r_dest_hi, 834 OpSize size, int s_reg) = 0; 835 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 836 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 837 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 838 OpSize size) = 0; 839 virtual LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) = 0; 840 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 841 int scale, OpSize size) = 0; 842 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 843 int displacement, RegStorage r_src, RegStorage r_src_hi, 844 OpSize size, int s_reg) = 0; 845 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 846 847 // Required for target - register utilities. 848 virtual bool IsFpReg(int reg) = 0; 849 virtual bool IsFpReg(RegStorage reg) = 0; 850 virtual bool SameRegType(int reg1, int reg2) = 0; 851 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 852 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 853 // TODO: elminate S2d. 854 virtual int S2d(int low_reg, int high_reg) = 0; 855 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 856 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 857 virtual RegLocation GetReturnAlt() = 0; 858 virtual RegLocation GetReturnWideAlt() = 0; 859 virtual RegLocation LocCReturn() = 0; 860 virtual RegLocation LocCReturnDouble() = 0; 861 virtual RegLocation LocCReturnFloat() = 0; 862 virtual RegLocation LocCReturnWide() = 0; 863 // TODO: use to reduce/eliminate xx_FPREG() macro use. 864 virtual uint32_t FpRegMask() = 0; 865 virtual uint64_t GetRegMaskCommon(int reg) = 0; 866 virtual void AdjustSpillMask() = 0; 867 virtual void ClobberCallerSave() = 0; 868 virtual void FlushReg(RegStorage reg) = 0; 869 virtual void FlushRegWide(RegStorage reg) = 0; 870 virtual void FreeCallTemps() = 0; 871 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 872 virtual void LockCallTemps() = 0; 873 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 874 virtual void CompilerInitializeRegAlloc() = 0; 875 876 // Required for target - miscellaneous. 877 virtual void AssembleLIR() = 0; 878 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 879 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 880 virtual const char* GetTargetInstFmt(int opcode) = 0; 881 virtual const char* GetTargetInstName(int opcode) = 0; 882 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 883 virtual uint64_t GetPCUseDefEncoding() = 0; 884 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 885 virtual int GetInsnSize(LIR* lir) = 0; 886 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 887 888 // Required for target - Dalvik-level generators. 889 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 890 RegLocation rl_src1, RegLocation rl_src2) = 0; 891 virtual void GenMulLong(Instruction::Code, 892 RegLocation rl_dest, RegLocation rl_src1, 893 RegLocation rl_src2) = 0; 894 virtual void GenAddLong(Instruction::Code, 895 RegLocation rl_dest, RegLocation rl_src1, 896 RegLocation rl_src2) = 0; 897 virtual void GenAndLong(Instruction::Code, 898 RegLocation rl_dest, RegLocation rl_src1, 899 RegLocation rl_src2) = 0; 900 virtual void GenArithOpDouble(Instruction::Code opcode, 901 RegLocation rl_dest, RegLocation rl_src1, 902 RegLocation rl_src2) = 0; 903 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 904 RegLocation rl_src1, RegLocation rl_src2) = 0; 905 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 906 RegLocation rl_src1, RegLocation rl_src2) = 0; 907 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 908 RegLocation rl_src) = 0; 909 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 910 911 /** 912 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 913 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 914 * that applies on integers. The generated code will write the smallest or largest value 915 * directly into the destination register as specified by the invoke information. 916 * @param info Information about the invoke. 917 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 918 * @return Returns true if successfully generated 919 */ 920 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 921 922 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 923 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 924 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 925 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 926 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 927 RegLocation rl_src2) = 0; 928 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 929 RegLocation rl_src2) = 0; 930 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 931 RegLocation rl_src2) = 0; 932 virtual LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, 933 int offset, ThrowKind kind) = 0; 934 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 935 bool is_div) = 0; 936 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 937 bool is_div) = 0; 938 /* 939 * @brief Generate an integer div or rem operation by a literal. 940 * @param rl_dest Destination Location. 941 * @param rl_src1 Numerator Location. 942 * @param rl_src2 Divisor Location. 943 * @param is_div 'true' if this is a division, 'false' for a remainder. 944 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 945 */ 946 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 947 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 948 /* 949 * @brief Generate an integer div or rem operation by a literal. 950 * @param rl_dest Destination Location. 951 * @param rl_src Numerator Location. 952 * @param lit Divisor. 953 * @param is_div 'true' if this is a division, 'false' for a remainder. 954 */ 955 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 956 bool is_div) = 0; 957 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 958 959 /** 960 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 961 * @details This is used for generating DivideByZero checks when divisor is held in two 962 * separate registers. 963 * @param reg_lo The register holding the lower 32-bits. 964 * @param reg_hi The register holding the upper 32-bits. 965 */ 966 virtual void GenDivZeroCheck(RegStorage reg) = 0; 967 968 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 969 virtual void GenExitSequence() = 0; 970 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 971 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 972 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 973 974 /** 975 * @brief Lowers the kMirOpSelect MIR into LIR. 976 * @param bb The basic block in which the MIR is from. 977 * @param mir The MIR whose opcode is kMirOpSelect. 978 */ 979 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 980 981 /** 982 * @brief Used to generate a memory barrier in an architecture specific way. 983 * @details The last generated LIR will be considered for use as barrier. Namely, 984 * if the last LIR can be updated in a way where it will serve the semantics of 985 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 986 * that can keep the semantics. 987 * @param barrier_kind The kind of memory barrier to generate. 988 */ 989 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 990 991 virtual void GenMoveException(RegLocation rl_dest) = 0; 992 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 993 int first_bit, int second_bit) = 0; 994 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 995 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 996 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 997 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 998 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 999 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1000 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1001 RegLocation rl_index, RegLocation rl_src, int scale, 1002 bool card_mark) = 0; 1003 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1004 RegLocation rl_src1, RegLocation rl_shift) = 0; 1005 1006 // Required for target - single operation generators. 1007 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1008 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1009 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1010 LIR* target) = 0; 1011 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1012 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1013 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1014 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1015 virtual void OpEndIT(LIR* it) = 0; 1016 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1017 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1018 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1019 virtual LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1020 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1021 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1022 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1023 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1024 1025 /** 1026 * @brief Used to generate an LIR that does a load from mem to reg. 1027 * @param r_dest The destination physical register. 1028 * @param r_base The base physical register for memory operand. 1029 * @param offset The displacement for memory operand. 1030 * @param move_type Specification on the move desired (size, alignment, register kind). 1031 * @return Returns the generate move LIR. 1032 */ 1033 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1034 MoveType move_type) = 0; 1035 1036 /** 1037 * @brief Used to generate an LIR that does a store from reg to mem. 1038 * @param r_base The base physical register for memory operand. 1039 * @param offset The displacement for memory operand. 1040 * @param r_src The destination physical register. 1041 * @param bytes_to_move The number of bytes to move. 1042 * @param is_aligned Whether the memory location is known to be aligned. 1043 * @return Returns the generate move LIR. 1044 */ 1045 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1046 MoveType move_type) = 0; 1047 1048 /** 1049 * @brief Used for generating a conditional register to register operation. 1050 * @param op The opcode kind. 1051 * @param cc The condition code that when true will perform the opcode. 1052 * @param r_dest The destination physical register. 1053 * @param r_src The source physical register. 1054 * @return Returns the newly created LIR or null in case of creation failure. 1055 */ 1056 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1057 1058 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1059 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1060 RegStorage r_src2) = 0; 1061 virtual LIR* OpTestSuspend(LIR* target) = 0; 1062 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1063 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1064 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1065 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1066 int offset) = 0; 1067 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1068 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1069 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1070 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1071 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1072 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1073 1074 // May be optimized by targets. 1075 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1076 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1077 1078 // Temp workaround 1079 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1080 1081 protected: 1082 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1083 1084 CompilationUnit* GetCompilationUnit() { 1085 return cu_; 1086 } 1087 /* 1088 * @brief Returns the index of the lowest set bit in 'x'. 1089 * @param x Value to be examined. 1090 * @returns The bit number of the lowest bit set in the value. 1091 */ 1092 int32_t LowestSetBit(uint64_t x); 1093 /* 1094 * @brief Is this value a power of two? 1095 * @param x Value to be examined. 1096 * @returns 'true' if only 1 bit is set in the value. 1097 */ 1098 bool IsPowerOfTwo(uint64_t x); 1099 /* 1100 * @brief Do these SRs overlap? 1101 * @param rl_op1 One RegLocation 1102 * @param rl_op2 The other RegLocation 1103 * @return 'true' if the VR pairs overlap 1104 * 1105 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1106 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1107 * dex, we'll want to make this case illegal. 1108 */ 1109 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1110 1111 /* 1112 * @brief Force a location (in a register) into a temporary register 1113 * @param loc location of result 1114 * @returns update location 1115 */ 1116 RegLocation ForceTemp(RegLocation loc); 1117 1118 /* 1119 * @brief Force a wide location (in registers) into temporary registers 1120 * @param loc location of result 1121 * @returns update location 1122 */ 1123 RegLocation ForceTempWide(RegLocation loc); 1124 1125 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1126 RegLocation rl_dest, RegLocation rl_src); 1127 1128 void AddSlowPath(LIRSlowPath* slowpath); 1129 1130 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1131 bool type_known_abstract, bool use_declaring_class, 1132 bool can_assume_type_is_in_dex_cache, 1133 uint32_t type_idx, RegLocation rl_dest, 1134 RegLocation rl_src); 1135 /* 1136 * @brief Generate the debug_frame FDE information if possible. 1137 * @returns pointer to vector containg CFE information, or NULL. 1138 */ 1139 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1140 1141 /** 1142 * @brief Used to insert marker that can be used to associate MIR with LIR. 1143 * @details Only inserts marker if verbosity is enabled. 1144 * @param mir The mir that is currently being generated. 1145 */ 1146 void GenPrintLabel(MIR* mir); 1147 1148 /** 1149 * @brief Used to generate return sequence when there is no frame. 1150 * @details Assumes that the return registers have already been populated. 1151 */ 1152 virtual void GenSpecialExitSequence() = 0; 1153 1154 /** 1155 * @brief Used to generate code for special methods that are known to be 1156 * small enough to work in frameless mode. 1157 * @param bb The basic block of the first MIR. 1158 * @param mir The first MIR of the special method. 1159 * @param special Information about the special method. 1160 * @return Returns whether or not this was handled successfully. Returns false 1161 * if caller should punt to normal MIR2LIR conversion. 1162 */ 1163 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1164 1165 private: 1166 void ClobberBody(RegisterInfo* p); 1167 void ResetDefBody(RegisterInfo* p) { 1168 p->def_start = NULL; 1169 p->def_end = NULL; 1170 } 1171 1172 void SetCurrentDexPc(DexOffset dexpc) { 1173 current_dalvik_offset_ = dexpc; 1174 } 1175 1176 /** 1177 * @brief Used to lock register if argument at in_position was passed that way. 1178 * @details Does nothing if the argument is passed via stack. 1179 * @param in_position The argument number whose register to lock. 1180 * @param wide Whether the argument is wide. 1181 */ 1182 void LockArg(int in_position, bool wide = false); 1183 1184 /** 1185 * @brief Used to load VR argument to a physical register. 1186 * @details The load is only done if the argument is not already in physical register. 1187 * LockArg must have been previously called. 1188 * @param in_position The argument number to load. 1189 * @param wide Whether the argument is 64-bit or not. 1190 * @return Returns the register (or register pair) for the loaded argument. 1191 */ 1192 RegStorage LoadArg(int in_position, bool wide = false); 1193 1194 /** 1195 * @brief Used to load a VR argument directly to a specified register location. 1196 * @param in_position The argument number to place in register. 1197 * @param rl_dest The register location where to place argument. 1198 */ 1199 void LoadArgDirect(int in_position, RegLocation rl_dest); 1200 1201 /** 1202 * @brief Used to generate LIR for special getter method. 1203 * @param mir The mir that represents the iget. 1204 * @param special Information about the special getter method. 1205 * @return Returns whether LIR was successfully generated. 1206 */ 1207 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1208 1209 /** 1210 * @brief Used to generate LIR for special setter method. 1211 * @param mir The mir that represents the iput. 1212 * @param special Information about the special setter method. 1213 * @return Returns whether LIR was successfully generated. 1214 */ 1215 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1216 1217 /** 1218 * @brief Used to generate LIR for special return-args method. 1219 * @param mir The mir that represents the return of argument. 1220 * @param special Information about the special return-args method. 1221 * @return Returns whether LIR was successfully generated. 1222 */ 1223 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1224 1225 void AddDivZeroCheckSlowPath(LIR* branch); 1226 1227 public: 1228 // TODO: add accessors for these. 1229 LIR* literal_list_; // Constants. 1230 LIR* method_literal_list_; // Method literals requiring patching. 1231 LIR* class_literal_list_; // Class literals requiring patching. 1232 LIR* code_literal_list_; // Code literals requiring patching. 1233 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1234 1235 protected: 1236 CompilationUnit* const cu_; 1237 MIRGraph* const mir_graph_; 1238 GrowableArray<SwitchTable*> switch_tables_; 1239 GrowableArray<FillArrayData*> fill_array_data_; 1240 GrowableArray<LIR*> throw_launchpads_; 1241 GrowableArray<LIR*> suspend_launchpads_; 1242 GrowableArray<RegisterInfo*> tempreg_info_; 1243 GrowableArray<RegisterInfo*> reginfo_map_; 1244 GrowableArray<void*> pointer_storage_; 1245 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1246 CodeOffset data_offset_; // starting offset of literal pool. 1247 size_t total_size_; // header + code size. 1248 LIR* block_label_list_; 1249 PromotionMap* promotion_map_; 1250 /* 1251 * TODO: The code generation utilities don't have a built-in 1252 * mechanism to propagate the original Dalvik opcode address to the 1253 * associated generated instructions. For the trace compiler, this wasn't 1254 * necessary because the interpreter handled all throws and debugging 1255 * requests. For now we'll handle this by placing the Dalvik offset 1256 * in the CompilationUnit struct before codegen for each instruction. 1257 * The low-level LIR creation utilites will pull it from here. Rework this. 1258 */ 1259 DexOffset current_dalvik_offset_; 1260 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1261 RegisterPool* reg_pool_; 1262 /* 1263 * Sanity checking for the register temp tracking. The same ssa 1264 * name should never be associated with one temp register per 1265 * instruction compilation. 1266 */ 1267 int live_sreg_; 1268 CodeBuffer code_buffer_; 1269 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1270 std::vector<uint8_t> encoded_mapping_table_; 1271 std::vector<uint32_t> core_vmap_table_; 1272 std::vector<uint32_t> fp_vmap_table_; 1273 std::vector<uint8_t> native_gc_map_; 1274 int num_core_spills_; 1275 int num_fp_spills_; 1276 int frame_size_; 1277 unsigned int core_spill_mask_; 1278 unsigned int fp_spill_mask_; 1279 LIR* first_lir_insn_; 1280 LIR* last_lir_insn_; 1281 1282 GrowableArray<LIRSlowPath*> slow_paths_; 1283}; // Class Mir2Lir 1284 1285} // namespace art 1286 1287#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1288