mir_to_lir.h revision e02d48fb24747f90fd893e1c3572bb3c500afced
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/backend.h" 25#include "dex/growable_array.h" 26#include "dex/arena_allocator.h" 27#include "driver/compiler_driver.h" 28#include "leb128_encoder.h" 29#include "safe_map.h" 30 31namespace art { 32 33/* 34 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 35 * add type safety (see runtime/offsets.h). 36 */ 37typedef uint32_t DexOffset; // Dex offset in code units. 38typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 39typedef uint32_t CodeOffset; // Native code offset in bytes. 40 41// Set to 1 to measure cost of suspend check. 42#define NO_SUSPEND 0 43 44#define IS_BINARY_OP (1ULL << kIsBinaryOp) 45#define IS_BRANCH (1ULL << kIsBranch) 46#define IS_IT (1ULL << kIsIT) 47#define IS_LOAD (1ULL << kMemLoad) 48#define IS_QUAD_OP (1ULL << kIsQuadOp) 49#define IS_QUIN_OP (1ULL << kIsQuinOp) 50#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 51#define IS_STORE (1ULL << kMemStore) 52#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 53#define IS_UNARY_OP (1ULL << kIsUnaryOp) 54#define NEEDS_FIXUP (1ULL << kPCRelFixup) 55#define NO_OPERAND (1ULL << kNoOperand) 56#define REG_DEF0 (1ULL << kRegDef0) 57#define REG_DEF1 (1ULL << kRegDef1) 58#define REG_DEFA (1ULL << kRegDefA) 59#define REG_DEFD (1ULL << kRegDefD) 60#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 61#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 62#define REG_DEF_LIST0 (1ULL << kRegDefList0) 63#define REG_DEF_LIST1 (1ULL << kRegDefList1) 64#define REG_DEF_LR (1ULL << kRegDefLR) 65#define REG_DEF_SP (1ULL << kRegDefSP) 66#define REG_USE0 (1ULL << kRegUse0) 67#define REG_USE1 (1ULL << kRegUse1) 68#define REG_USE2 (1ULL << kRegUse2) 69#define REG_USE3 (1ULL << kRegUse3) 70#define REG_USE4 (1ULL << kRegUse4) 71#define REG_USEA (1ULL << kRegUseA) 72#define REG_USEC (1ULL << kRegUseC) 73#define REG_USED (1ULL << kRegUseD) 74#define REG_USEB (1ULL << kRegUseB) 75#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 76#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 77#define REG_USE_LIST0 (1ULL << kRegUseList0) 78#define REG_USE_LIST1 (1ULL << kRegUseList1) 79#define REG_USE_LR (1ULL << kRegUseLR) 80#define REG_USE_PC (1ULL << kRegUsePC) 81#define REG_USE_SP (1ULL << kRegUseSP) 82#define SETS_CCODES (1ULL << kSetsCCodes) 83#define USES_CCODES (1ULL << kUsesCCodes) 84 85// Common combo register usage patterns. 86#define REG_DEF01 (REG_DEF0 | REG_DEF1) 87#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 88#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 89#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 90#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 91#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 92#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 93#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 94#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 95#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 96#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 97#define REG_USE012 (REG_USE01 | REG_USE2) 98#define REG_USE014 (REG_USE01 | REG_USE4) 99#define REG_USE01 (REG_USE0 | REG_USE1) 100#define REG_USE02 (REG_USE0 | REG_USE2) 101#define REG_USE12 (REG_USE1 | REG_USE2) 102#define REG_USE23 (REG_USE2 | REG_USE3) 103#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 104 105struct BasicBlock; 106struct CallInfo; 107struct CompilationUnit; 108struct InlineMethod; 109struct MIR; 110struct LIR; 111struct RegLocation; 112struct RegisterInfo; 113class DexFileMethodInliner; 114class MIRGraph; 115class Mir2Lir; 116 117typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 118 const MethodReference& target_method, 119 uint32_t method_idx, uintptr_t direct_code, 120 uintptr_t direct_method, InvokeType type); 121 122typedef std::vector<uint8_t> CodeBuffer; 123 124struct UseDefMasks { 125 uint64_t use_mask; // Resource mask for use. 126 uint64_t def_mask; // Resource mask for def. 127}; 128 129struct AssemblyInfo { 130 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 131 uint8_t bytes[16]; // Encoded instruction bytes. 132}; 133 134struct LIR { 135 CodeOffset offset; // Offset of this instruction. 136 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 137 int16_t opcode; 138 LIR* next; 139 LIR* prev; 140 LIR* target; 141 struct { 142 unsigned int alias_info:17; // For Dalvik register disambiguation. 143 bool is_nop:1; // LIR is optimized away. 144 unsigned int size:4; // Note: size of encoded instruction is in bytes. 145 bool use_def_invalid:1; // If true, masks should not be used. 146 unsigned int generation:1; // Used to track visitation state during fixup pass. 147 unsigned int fixup:8; // Fixup kind. 148 } flags; 149 union { 150 UseDefMasks m; // Use & Def masks used during optimization. 151 AssemblyInfo a; // Instruction encoding used during assembly phase. 152 } u; 153 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 154}; 155 156// Target-specific initialization. 157Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 158 ArenaAllocator* const arena); 159Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 160 ArenaAllocator* const arena); 161Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 162 ArenaAllocator* const arena); 163 164// Utility macros to traverse the LIR list. 165#define NEXT_LIR(lir) (lir->next) 166#define PREV_LIR(lir) (lir->prev) 167 168// Defines for alias_info (tracks Dalvik register references). 169#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 170#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 171#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 172#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 173 174// Common resource macros. 175#define ENCODE_CCODE (1ULL << kCCode) 176#define ENCODE_FP_STATUS (1ULL << kFPStatus) 177 178// Abstract memory locations. 179#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 180#define ENCODE_LITERAL (1ULL << kLiteral) 181#define ENCODE_HEAP_REF (1ULL << kHeapRef) 182#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 183 184#define ENCODE_ALL (~0ULL) 185#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 186 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 187 188// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 189#define STARTING_DOUBLE_SREG 0x10000 190 191// TODO: replace these macros 192#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 193#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 194#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 195#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 196#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 197 198class Mir2Lir : public Backend { 199 public: 200 /* 201 * Auxiliary information describing the location of data embedded in the Dalvik 202 * byte code stream. 203 */ 204 struct EmbeddedData { 205 CodeOffset offset; // Code offset of data block. 206 const uint16_t* table; // Original dex data. 207 DexOffset vaddr; // Dalvik offset of parent opcode. 208 }; 209 210 struct FillArrayData : EmbeddedData { 211 int32_t size; 212 }; 213 214 struct SwitchTable : EmbeddedData { 215 LIR* anchor; // Reference instruction for relative offsets. 216 LIR** targets; // Array of case targets. 217 }; 218 219 /* Static register use counts */ 220 struct RefCounts { 221 int count; 222 int s_reg; 223 }; 224 225 /* 226 * Data structure tracking the mapping between a Dalvik register (pair) and a 227 * native register (pair). The idea is to reuse the previously loaded value 228 * if possible, otherwise to keep the value in a native register as long as 229 * possible. 230 */ 231 struct RegisterInfo { 232 int reg; // Reg number 233 bool in_use; // Has it been allocated? 234 bool is_temp; // Can allocate as temp? 235 bool pair; // Part of a register pair? 236 int partner; // If pair, other reg of pair. 237 bool live; // Is there an associated SSA name? 238 bool dirty; // If live, is it dirty? 239 int s_reg; // Name of live value. 240 LIR *def_start; // Starting inst in last def sequence. 241 LIR *def_end; // Ending inst in last def sequence. 242 }; 243 244 struct RegisterPool { 245 int num_core_regs; 246 RegisterInfo *core_regs; 247 int next_core_reg; 248 int num_fp_regs; 249 RegisterInfo *FPRegs; 250 int next_fp_reg; 251 }; 252 253 struct PromotionMap { 254 RegLocationType core_location:3; 255 uint8_t core_reg; 256 RegLocationType fp_location:3; 257 uint8_t FpReg; 258 bool first_in_pair; 259 }; 260 261 virtual ~Mir2Lir() {} 262 263 int32_t s4FromSwitchData(const void* switch_data) { 264 return *reinterpret_cast<const int32_t*>(switch_data); 265 } 266 267 RegisterClass oat_reg_class_by_size(OpSize size) { 268 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 269 size == kSignedByte) ? kCoreReg : kAnyReg; 270 } 271 272 size_t CodeBufferSizeInBytes() { 273 return code_buffer_.size() / sizeof(code_buffer_[0]); 274 } 275 276 bool IsPseudoLirOp(int opcode) { 277 return (opcode < 0); 278 } 279 280 /* 281 * LIR operands are 32-bit integers. Sometimes, (especially for managing 282 * instructions which require PC-relative fixups), we need the operands to carry 283 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 284 * hold that index in the operand array. 285 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 286 * may be worth conditionally-compiling a set of identity functions here. 287 */ 288 uint32_t WrapPointer(void* pointer) { 289 uint32_t res = pointer_storage_.Size(); 290 pointer_storage_.Insert(pointer); 291 return res; 292 } 293 294 void* UnwrapPointer(size_t index) { 295 return pointer_storage_.Get(index); 296 } 297 298 // strdup(), but allocates from the arena. 299 char* ArenaStrdup(const char* str) { 300 size_t len = strlen(str) + 1; 301 char* res = reinterpret_cast<char*>(arena_->Alloc(len, ArenaAllocator::kAllocMisc)); 302 if (res != NULL) { 303 strncpy(res, str, len); 304 } 305 return res; 306 } 307 308 // Shared by all targets - implemented in codegen_util.cc 309 void AppendLIR(LIR* lir); 310 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 311 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 312 313 int ComputeFrameSize(); 314 virtual void Materialize(); 315 virtual CompiledMethod* GetCompiledMethod(); 316 void MarkSafepointPC(LIR* inst); 317 bool FastInstance(uint32_t field_idx, bool is_put, int* field_offset, bool* is_volatile); 318 void SetupResourceMasks(LIR* lir); 319 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 320 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 321 void SetupRegMask(uint64_t* mask, int reg); 322 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 323 void DumpPromotionMap(); 324 void CodegenDump(); 325 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 326 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 327 LIR* NewLIR0(int opcode); 328 LIR* NewLIR1(int opcode, int dest); 329 LIR* NewLIR2(int opcode, int dest, int src1); 330 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 331 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 332 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 333 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 334 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 335 LIR* AddWordData(LIR* *constant_list_p, int value); 336 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 337 void ProcessSwitchTables(); 338 void DumpSparseSwitchTable(const uint16_t* table); 339 void DumpPackedSwitchTable(const uint16_t* table); 340 void MarkBoundary(DexOffset offset, const char* inst_str); 341 void NopLIR(LIR* lir); 342 void UnlinkLIR(LIR* lir); 343 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 344 bool IsInexpensiveConstant(RegLocation rl_src); 345 ConditionCode FlipComparisonOrder(ConditionCode before); 346 void InstallLiteralPools(); 347 void InstallSwitchTables(); 348 void InstallFillArrayData(); 349 bool VerifyCatchEntries(); 350 void CreateMappingTables(); 351 void CreateNativeGcMap(); 352 int AssignLiteralOffset(CodeOffset offset); 353 int AssignSwitchTablesOffset(CodeOffset offset); 354 int AssignFillArrayDataOffset(CodeOffset offset); 355 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 356 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 357 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 358 359 // Shared by all targets - implemented in local_optimizations.cc 360 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src); 361 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 362 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 363 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 364 365 // Shared by all targets - implemented in ralloc_util.cc 366 int GetSRegHi(int lowSreg); 367 bool oat_live_out(int s_reg); 368 int oatSSASrc(MIR* mir, int num); 369 void SimpleRegAlloc(); 370 void ResetRegPool(); 371 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 372 void DumpRegPool(RegisterInfo* p, int num_regs); 373 void DumpCoreRegPool(); 374 void DumpFpRegPool(); 375 /* Mark a temp register as dead. Does not affect allocation state. */ 376 void Clobber(int reg) { 377 ClobberBody(GetRegInfo(reg)); 378 } 379 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 380 void ClobberSReg(int s_reg); 381 int SRegToPMap(int s_reg); 382 void RecordCorePromotion(int reg, int s_reg); 383 int AllocPreservedCoreReg(int s_reg); 384 void RecordFpPromotion(int reg, int s_reg); 385 int AllocPreservedSingle(int s_reg); 386 int AllocPreservedDouble(int s_reg); 387 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 388 virtual int AllocTempDouble(); 389 int AllocFreeTemp(); 390 int AllocTemp(); 391 int AllocTempFloat(); 392 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 393 RegisterInfo* AllocLive(int s_reg, int reg_class); 394 void FreeTemp(int reg); 395 RegisterInfo* IsLive(int reg); 396 RegisterInfo* IsTemp(int reg); 397 RegisterInfo* IsPromoted(int reg); 398 bool IsDirty(int reg); 399 void LockTemp(int reg); 400 void ResetDef(int reg); 401 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 402 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 403 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 404 RegLocation WideToNarrow(RegLocation rl); 405 void ResetDefLoc(RegLocation rl); 406 virtual void ResetDefLocWide(RegLocation rl); 407 void ResetDefTracking(); 408 void ClobberAllRegs(); 409 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 410 void FlushAllRegs(); 411 bool RegClassMatches(int reg_class, int reg); 412 void MarkLive(int reg, int s_reg); 413 void MarkTemp(int reg); 414 void UnmarkTemp(int reg); 415 void MarkPair(int low_reg, int high_reg); 416 void MarkClean(RegLocation loc); 417 void MarkDirty(RegLocation loc); 418 void MarkInUse(int reg); 419 void CopyRegInfo(int new_reg, int old_reg); 420 bool CheckCorePoolSanity(); 421 RegLocation UpdateLoc(RegLocation loc); 422 virtual RegLocation UpdateLocWide(RegLocation loc); 423 RegLocation UpdateRawLoc(RegLocation loc); 424 425 /** 426 * @brief Used to load register location into a typed temporary or pair of temporaries. 427 * @see EvalLoc 428 * @param loc The register location to load from. 429 * @param reg_class Type of register needed. 430 * @param update Whether the liveness information should be updated. 431 * @return Returns the properly typed temporary in physical register pairs. 432 */ 433 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 434 435 /** 436 * @brief Used to load register location into a typed temporary. 437 * @param loc The register location to load from. 438 * @param reg_class Type of register needed. 439 * @param update Whether the liveness information should be updated. 440 * @return Returns the properly typed temporary in physical register. 441 */ 442 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 443 444 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 445 void DumpCounts(const RefCounts* arr, int size, const char* msg); 446 void DoPromotion(); 447 int VRegOffset(int v_reg); 448 int SRegOffset(int s_reg); 449 RegLocation GetReturnWide(bool is_double); 450 RegLocation GetReturn(bool is_float); 451 RegisterInfo* GetRegInfo(int reg); 452 453 // Shared by all targets - implemented in gen_common.cc. 454 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 455 RegLocation rl_src, RegLocation rl_dest, int lit); 456 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 457 void HandleSuspendLaunchPads(); 458 void HandleIntrinsicLaunchPads(); 459 void HandleThrowLaunchPads(); 460 void GenBarrier(); 461 LIR* GenCheck(ConditionCode c_code, ThrowKind kind); 462 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val, 463 ThrowKind kind); 464 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags); 465 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 466 ThrowKind kind); 467 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 468 RegLocation rl_src2, LIR* taken, LIR* fall_through); 469 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 470 LIR* taken, LIR* fall_through); 471 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 472 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 473 RegLocation rl_src); 474 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 475 RegLocation rl_src); 476 void GenFilledNewArray(CallInfo* info); 477 void GenSput(uint32_t field_idx, RegLocation rl_src, 478 bool is_long_or_double, bool is_object); 479 void GenSget(uint32_t field_idx, RegLocation rl_dest, 480 bool is_long_or_double, bool is_object); 481 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size, 482 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 483 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size, 484 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 485 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 486 RegLocation rl_src); 487 488 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 489 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 490 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 491 void GenThrow(RegLocation rl_src); 492 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, 493 RegLocation rl_src); 494 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, 495 RegLocation rl_src); 496 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 497 RegLocation rl_src1, RegLocation rl_src2); 498 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 499 RegLocation rl_src1, RegLocation rl_shift); 500 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 501 RegLocation rl_src1, RegLocation rl_src2); 502 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 503 RegLocation rl_src, int lit); 504 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 505 RegLocation rl_src1, RegLocation rl_src2); 506 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest, 507 RegLocation rl_src); 508 void GenSuspendTest(int opt_flags); 509 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 510 // This will be overridden by x86 implementation. 511 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 512 513 // Shared by all targets - implemented in gen_invoke.cc. 514 int CallHelperSetup(ThreadOffset helper_offset); 515 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc); 516 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 517 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc); 518 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 519 bool safepoint_pc); 520 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 521 bool safepoint_pc); 522 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 523 RegLocation arg1, bool safepoint_pc); 524 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, 525 int arg1, bool safepoint_pc); 526 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 527 bool safepoint_pc); 528 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 529 bool safepoint_pc); 530 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, 531 bool safepoint_pc); 532 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, 533 RegLocation arg0, RegLocation arg1, 534 bool safepoint_pc); 535 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 536 bool safepoint_pc); 537 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 538 int arg2, bool safepoint_pc); 539 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0, 540 RegLocation arg2, bool safepoint_pc); 541 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2, 542 bool safepoint_pc); 543 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 544 int arg0, RegLocation arg1, RegLocation arg2, 545 bool safepoint_pc); 546 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 547 RegLocation arg0, RegLocation arg1, 548 RegLocation arg2, 549 bool safepoint_pc); 550 void GenInvoke(CallInfo* info); 551 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 552 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 553 NextCallInsn next_call_insn, 554 const MethodReference& target_method, 555 uint32_t vtable_idx, 556 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 557 bool skip_this); 558 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 559 NextCallInsn next_call_insn, 560 const MethodReference& target_method, 561 uint32_t vtable_idx, 562 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 563 bool skip_this); 564 565 /** 566 * @brief Used to determine the register location of destination. 567 * @details This is needed during generation of inline intrinsics because it finds destination of return, 568 * either the physical register or the target of move-result. 569 * @param info Information about the invoke. 570 * @return Returns the destination location. 571 */ 572 RegLocation InlineTarget(CallInfo* info); 573 574 /** 575 * @brief Used to determine the wide register location of destination. 576 * @see InlineTarget 577 * @param info Information about the invoke. 578 * @return Returns the destination location. 579 */ 580 RegLocation InlineTargetWide(CallInfo* info); 581 582 bool GenInlinedCharAt(CallInfo* info); 583 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 584 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 585 bool GenInlinedAbsInt(CallInfo* info); 586 bool GenInlinedAbsLong(CallInfo* info); 587 bool GenInlinedFloatCvt(CallInfo* info); 588 bool GenInlinedDoubleCvt(CallInfo* info); 589 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 590 bool GenInlinedStringCompareTo(CallInfo* info); 591 bool GenInlinedCurrentThread(CallInfo* info); 592 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 593 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 594 bool is_volatile, bool is_ordered); 595 int LoadArgRegs(CallInfo* info, int call_state, 596 NextCallInsn next_call_insn, 597 const MethodReference& target_method, 598 uint32_t vtable_idx, 599 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 600 bool skip_this); 601 602 // Shared by all targets - implemented in gen_loadstore.cc. 603 RegLocation LoadCurrMethod(); 604 void LoadCurrMethodDirect(int r_tgt); 605 LIR* LoadConstant(int r_dest, int value); 606 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 607 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 608 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 609 void LoadValueDirect(RegLocation rl_src, int r_dest); 610 void LoadValueDirectFixed(RegLocation rl_src, int r_dest); 611 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi); 612 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi); 613 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 614 615 /** 616 * @brief Used to do the final store in the destination as per bytecode semantics. 617 * @param rl_dest The destination dalvik register location. 618 * @param rl_src The source register location. Can be either physical register or dalvik register. 619 */ 620 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 621 622 /** 623 * @brief Used to do the final store in a wide destination as per bytecode semantics. 624 * @see StoreValue 625 * @param rl_dest The destination dalvik register location. 626 * @param rl_src The source register location. Can be either physical register or dalvik register. 627 */ 628 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 629 630 /** 631 * @brief Used to do the final store in a wide destination as per bytecode semantics. 632 * @see StoreValueWide 633 * @param rl_dest The destination dalvik register location. 634 * @param rl_src The source register location. It must be kLocPhysReg 635 * 636 * This is used for x86 two operand computations, where we have computed the correct 637 * register values that now need to be properly registered. This is used to avoid an 638 * extra pair of register copies that would result if StoreValueWide was called. 639 */ 640 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 641 642 // Shared by all targets - implemented in mir_to_lir.cc. 643 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 644 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 645 bool MethodBlockCodeGen(BasicBlock* bb); 646 void SpecialMIR2LIR(const InlineMethod& special); 647 void MethodMIR2LIR(); 648 649 650 651 // Required for target - codegen helpers. 652 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 653 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 654 virtual int LoadHelper(ThreadOffset offset) = 0; 655 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 656 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 657 int s_reg) = 0; 658 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 659 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 660 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0; 661 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0; 662 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0; 663 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 664 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 665 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 666 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 667 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 668 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0; 669 670 // Required for target - register utilities. 671 virtual bool IsFpReg(int reg) = 0; 672 virtual bool SameRegType(int reg1, int reg2) = 0; 673 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0; 674 virtual int AllocTypedTempPair(bool fp_hint, int reg_class) = 0; 675 virtual int S2d(int low_reg, int high_reg) = 0; 676 virtual int TargetReg(SpecialTargetRegister reg) = 0; 677 virtual RegLocation GetReturnAlt() = 0; 678 virtual RegLocation GetReturnWideAlt() = 0; 679 virtual RegLocation LocCReturn() = 0; 680 virtual RegLocation LocCReturnDouble() = 0; 681 virtual RegLocation LocCReturnFloat() = 0; 682 virtual RegLocation LocCReturnWide() = 0; 683 virtual uint32_t FpRegMask() = 0; 684 virtual uint64_t GetRegMaskCommon(int reg) = 0; 685 virtual void AdjustSpillMask() = 0; 686 virtual void ClobberCallerSave() = 0; 687 virtual void FlushReg(int reg) = 0; 688 virtual void FlushRegWide(int reg1, int reg2) = 0; 689 virtual void FreeCallTemps() = 0; 690 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 691 virtual void LockCallTemps() = 0; 692 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 693 virtual void CompilerInitializeRegAlloc() = 0; 694 695 // Required for target - miscellaneous. 696 virtual void AssembleLIR() = 0; 697 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 698 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 699 virtual const char* GetTargetInstFmt(int opcode) = 0; 700 virtual const char* GetTargetInstName(int opcode) = 0; 701 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 702 virtual uint64_t GetPCUseDefEncoding() = 0; 703 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 704 virtual int GetInsnSize(LIR* lir) = 0; 705 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 706 707 // Required for target - Dalvik-level generators. 708 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 709 RegLocation rl_src1, RegLocation rl_src2) = 0; 710 virtual void GenMulLong(Instruction::Code, 711 RegLocation rl_dest, RegLocation rl_src1, 712 RegLocation rl_src2) = 0; 713 virtual void GenAddLong(Instruction::Code, 714 RegLocation rl_dest, RegLocation rl_src1, 715 RegLocation rl_src2) = 0; 716 virtual void GenAndLong(Instruction::Code, 717 RegLocation rl_dest, RegLocation rl_src1, 718 RegLocation rl_src2) = 0; 719 virtual void GenArithOpDouble(Instruction::Code opcode, 720 RegLocation rl_dest, RegLocation rl_src1, 721 RegLocation rl_src2) = 0; 722 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 723 RegLocation rl_src1, RegLocation rl_src2) = 0; 724 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 725 RegLocation rl_src1, RegLocation rl_src2) = 0; 726 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 727 RegLocation rl_src) = 0; 728 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 729 730 /** 731 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 732 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 733 * that applies on integers. The generated code will write the smallest or largest value 734 * directly into the destination register as specified by the invoke information. 735 * @param info Information about the invoke. 736 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 737 * @return Returns true if successfully generated 738 */ 739 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 740 741 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 742 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 743 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 744 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 745 virtual void GenOrLong(Instruction::Code, 746 RegLocation rl_dest, RegLocation rl_src1, 747 RegLocation rl_src2) = 0; 748 virtual void GenSubLong(Instruction::Code, 749 RegLocation rl_dest, RegLocation rl_src1, 750 RegLocation rl_src2) = 0; 751 virtual void GenXorLong(Instruction::Code, 752 RegLocation rl_dest, RegLocation rl_src1, 753 RegLocation rl_src2) = 0; 754 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, 755 int offset, ThrowKind kind) = 0; 756 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, 757 bool is_div) = 0; 758 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, 759 bool is_div) = 0; 760 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 761 RegLocation rl_src2) = 0; 762 763 /** 764 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 765 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers. 766 * @param reg_lo The register holding the lower 32-bits. 767 * @param reg_hi The register holding the upper 32-bits. 768 */ 769 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0; 770 771 virtual void GenEntrySequence(RegLocation* ArgLocs, 772 RegLocation rl_method) = 0; 773 virtual void GenExitSequence() = 0; 774 virtual void GenFillArrayData(DexOffset table_offset, 775 RegLocation rl_src) = 0; 776 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, 777 bool is_double) = 0; 778 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 779 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 780 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 781 virtual void GenMoveException(RegLocation rl_dest) = 0; 782 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 783 RegLocation rl_result, int lit, int first_bit, 784 int second_bit) = 0; 785 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 786 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 787 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, 788 RegLocation rl_src) = 0; 789 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, 790 RegLocation rl_src) = 0; 791 virtual void GenSpecialCase(BasicBlock* bb, MIR* mir, 792 const InlineMethod& special) = 0; 793 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 794 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 795 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 796 RegLocation rl_index, RegLocation rl_src, int scale, 797 bool card_mark) = 0; 798 virtual void GenShiftImmOpLong(Instruction::Code opcode, 799 RegLocation rl_dest, RegLocation rl_src1, 800 RegLocation rl_shift) = 0; 801 802 // Required for target - single operation generators. 803 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 804 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target) = 0; 805 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target) = 0; 806 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 807 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) = 0; 808 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 809 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 810 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0; 811 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0; 812 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0; 813 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 814 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0; 815 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0; 816 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0; 817 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0; 818 819 /** 820 * @brief Used for generating a conditional register to register operation. 821 * @param op The opcode kind. 822 * @param cc The condition code that when true will perform the opcode. 823 * @param r_dest The destination physical register. 824 * @param r_src The source physical register. 825 * @return Returns the newly created LIR or null in case of creation failure. 826 */ 827 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) = 0; 828 829 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0; 830 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) = 0; 831 virtual LIR* OpTestSuspend(LIR* target) = 0; 832 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0; 833 virtual LIR* OpVldm(int rBase, int count) = 0; 834 virtual LIR* OpVstm(int rBase, int count) = 0; 835 virtual void OpLea(int rBase, int reg1, int reg2, int scale, int offset) = 0; 836 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi) = 0; 837 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0; 838 virtual bool InexpensiveConstantInt(int32_t value) = 0; 839 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 840 virtual bool InexpensiveConstantLong(int64_t value) = 0; 841 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 842 843 // May be optimized by targets. 844 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 845 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 846 847 // Temp workaround 848 void Workaround7250540(RegLocation rl_dest, int value); 849 850 protected: 851 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 852 853 CompilationUnit* GetCompilationUnit() { 854 return cu_; 855 } 856 857 /* 858 * @brief Force a location (in a register) into a temporary register 859 * @param loc location of result 860 * @returns update location 861 */ 862 RegLocation ForceTemp(RegLocation loc); 863 864 /* 865 * @brief Force a wide location (in registers) into temporary registers 866 * @param loc location of result 867 * @returns update location 868 */ 869 RegLocation ForceTempWide(RegLocation loc); 870 871 private: 872 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 873 RegLocation rl_src); 874 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 875 bool type_known_abstract, bool use_declaring_class, 876 bool can_assume_type_is_in_dex_cache, 877 uint32_t type_idx, RegLocation rl_dest, 878 RegLocation rl_src); 879 880 void ClobberBody(RegisterInfo* p); 881 void ResetDefBody(RegisterInfo* p) { 882 p->def_start = NULL; 883 p->def_end = NULL; 884 } 885 886 public: 887 // TODO: add accessors for these. 888 LIR* literal_list_; // Constants. 889 LIR* method_literal_list_; // Method literals requiring patching. 890 LIR* code_literal_list_; // Code literals requiring patching. 891 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 892 893 protected: 894 CompilationUnit* const cu_; 895 MIRGraph* const mir_graph_; 896 GrowableArray<SwitchTable*> switch_tables_; 897 GrowableArray<FillArrayData*> fill_array_data_; 898 GrowableArray<LIR*> throw_launchpads_; 899 GrowableArray<LIR*> suspend_launchpads_; 900 GrowableArray<LIR*> intrinsic_launchpads_; 901 GrowableArray<RegisterInfo*> tempreg_info_; 902 GrowableArray<RegisterInfo*> reginfo_map_; 903 GrowableArray<void*> pointer_storage_; 904 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 905 CodeOffset data_offset_; // starting offset of literal pool. 906 size_t total_size_; // header + code size. 907 LIR* block_label_list_; 908 PromotionMap* promotion_map_; 909 /* 910 * TODO: The code generation utilities don't have a built-in 911 * mechanism to propagate the original Dalvik opcode address to the 912 * associated generated instructions. For the trace compiler, this wasn't 913 * necessary because the interpreter handled all throws and debugging 914 * requests. For now we'll handle this by placing the Dalvik offset 915 * in the CompilationUnit struct before codegen for each instruction. 916 * The low-level LIR creation utilites will pull it from here. Rework this. 917 */ 918 DexOffset current_dalvik_offset_; 919 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 920 RegisterPool* reg_pool_; 921 /* 922 * Sanity checking for the register temp tracking. The same ssa 923 * name should never be associated with one temp register per 924 * instruction compilation. 925 */ 926 int live_sreg_; 927 CodeBuffer code_buffer_; 928 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 929 std::vector<uint8_t> encoded_mapping_table_; 930 std::vector<uint32_t> core_vmap_table_; 931 std::vector<uint32_t> fp_vmap_table_; 932 std::vector<uint8_t> native_gc_map_; 933 int num_core_spills_; 934 int num_fp_spills_; 935 int frame_size_; 936 unsigned int core_spill_mask_; 937 unsigned int fp_spill_mask_; 938 LIR* first_lir_insn_; 939 LIR* last_lir_insn_; 940}; // Class Mir2Lir 941 942} // namespace art 943 944#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 945