mir_to_lir.h revision e87f9b5185379c8cf8392d65a63e7bf7e51b97e7
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF012 (REG_DEF0 | REG_DEF1 | REG_DEF2) 95#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 96#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 97#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 98#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 99#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 100#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 101#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 102#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 103#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 104#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 105#define REG_USE012 (REG_USE01 | REG_USE2) 106#define REG_USE014 (REG_USE01 | REG_USE4) 107#define REG_USE01 (REG_USE0 | REG_USE1) 108#define REG_USE02 (REG_USE0 | REG_USE2) 109#define REG_USE12 (REG_USE1 | REG_USE2) 110#define REG_USE23 (REG_USE2 | REG_USE3) 111#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 112 113// TODO: #includes need a cleanup 114#ifndef INVALID_SREG 115#define INVALID_SREG (-1) 116#endif 117 118struct BasicBlock; 119struct CallInfo; 120struct CompilationUnit; 121struct InlineMethod; 122struct MIR; 123struct LIR; 124struct RegLocation; 125struct RegisterInfo; 126class DexFileMethodInliner; 127class MIRGraph; 128class Mir2Lir; 129 130typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 131 const MethodReference& target_method, 132 uint32_t method_idx, uintptr_t direct_code, 133 uintptr_t direct_method, InvokeType type); 134 135typedef std::vector<uint8_t> CodeBuffer; 136 137struct UseDefMasks { 138 uint64_t use_mask; // Resource mask for use. 139 uint64_t def_mask; // Resource mask for def. 140}; 141 142struct AssemblyInfo { 143 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 144}; 145 146struct LIR { 147 CodeOffset offset; // Offset of this instruction. 148 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 149 int16_t opcode; 150 LIR* next; 151 LIR* prev; 152 LIR* target; 153 struct { 154 unsigned int alias_info:17; // For Dalvik register disambiguation. 155 bool is_nop:1; // LIR is optimized away. 156 unsigned int size:4; // Note: size of encoded instruction is in bytes. 157 bool use_def_invalid:1; // If true, masks should not be used. 158 unsigned int generation:1; // Used to track visitation state during fixup pass. 159 unsigned int fixup:8; // Fixup kind. 160 } flags; 161 union { 162 UseDefMasks m; // Use & Def masks used during optimization. 163 AssemblyInfo a; // Instruction info used during assembly phase. 164 } u; 165 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 166}; 167 168// Target-specific initialization. 169Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 170 ArenaAllocator* const arena); 171Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 172 ArenaAllocator* const arena); 173Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 174 ArenaAllocator* const arena); 175Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 176 ArenaAllocator* const arena); 177Mir2Lir* X86_64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 178 ArenaAllocator* const arena); 179 180// Utility macros to traverse the LIR list. 181#define NEXT_LIR(lir) (lir->next) 182#define PREV_LIR(lir) (lir->prev) 183 184// Defines for alias_info (tracks Dalvik register references). 185#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 186#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 187#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 188#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 189 190// Common resource macros. 191#define ENCODE_CCODE (1ULL << kCCode) 192#define ENCODE_FP_STATUS (1ULL << kFPStatus) 193 194// Abstract memory locations. 195#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 196#define ENCODE_LITERAL (1ULL << kLiteral) 197#define ENCODE_HEAP_REF (1ULL << kHeapRef) 198#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 199 200#define ENCODE_ALL (~0ULL) 201#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 202 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 203 204#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 205#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 206 do { \ 207 low_reg = both_regs & 0xff; \ 208 high_reg = (both_regs >> 8) & 0xff; \ 209 } while (false) 210 211// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 212#define STARTING_DOUBLE_SREG 0x10000 213 214// TODO: replace these macros 215#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 216#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 217#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 218#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 219#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 220 221class Mir2Lir : public Backend { 222 public: 223 /* 224 * Auxiliary information describing the location of data embedded in the Dalvik 225 * byte code stream. 226 */ 227 struct EmbeddedData { 228 CodeOffset offset; // Code offset of data block. 229 const uint16_t* table; // Original dex data. 230 DexOffset vaddr; // Dalvik offset of parent opcode. 231 }; 232 233 struct FillArrayData : EmbeddedData { 234 int32_t size; 235 }; 236 237 struct SwitchTable : EmbeddedData { 238 LIR* anchor; // Reference instruction for relative offsets. 239 LIR** targets; // Array of case targets. 240 }; 241 242 /* Static register use counts */ 243 struct RefCounts { 244 int count; 245 int s_reg; 246 }; 247 248 /* 249 * Data structure tracking the mapping detween a Dalvik value (32 or 64 bits) 250 * and native register storage. The primary purpose is to reuse previuosly 251 * loaded values, if possible, and otherwise to keep the value in register 252 * storage as long as possible. 253 * 254 * NOTE 1: wide_value refers to the width of the Dalvik value contained in 255 * this register (or pair). For example, a 64-bit register containing a 32-bit 256 * Dalvik value would have wide_value==false even though the storage container itself 257 * is wide. Similarly, a 32-bit register containing half of a 64-bit Dalvik value 258 * would have wide_value==true (and additionally would have its partner field set to the 259 * other half whose wide_value field would also be true. 260 * 261 * NOTE 2: In the case of a register pair, you can determine which of the partners 262 * is the low half by looking at the s_reg names. The high s_reg will equal low_sreg + 1. 263 * 264 * NOTE 3: In the case of a 64-bit register holding a Dalvik wide value, wide_value 265 * will be true and partner==self. s_reg refers to the low-order word of the Dalvik 266 * value, and the s_reg of the high word is implied (s_reg + 1). 267 * 268 * NOTE 4: The reg and is_temp fields should always be correct. If is_temp is false no 269 * other fields have meaning. [perhaps not true, wide should work for promoted regs?] 270 * If is_temp==true and live==false, no other fields have 271 * meaning. If is_temp==true and live==true, wide_value, partner, dirty, s_reg, def_start 272 * and def_end describe the relationship between the temp register/register pair and 273 * the Dalvik value[s] described by s_reg/s_reg+1. 274 * 275 * The fields used_storage, master_storage and storage_mask are used to track allocation 276 * in light of potential aliasing. For example, consider Arm's d2, which overlaps s4 & s5. 277 * d2's storage mask would be 0x00000003, the two low-order bits denoting 64 bits of 278 * storage use. For s4, it would be 0x0000001; for s5 0x00000002. These values should not 279 * change once initialized. The "used_storage" field tracks current allocation status. 280 * Although each record contains this field, only the field from the largest member of 281 * an aliased group is used. In our case, it would be d2's. The master_storage pointer 282 * of d2, s4 and s5 would all point to d2's used_storage field. Each bit in a used_storage 283 * represents 32 bits of storage. d2's used_storage would be initialized to 0xfffffffc. 284 * Then, if we wanted to determine whether s4 could be allocated, we would "and" 285 * s4's storage_mask with s4's *master_storage. If the result is zero, s4 is free and 286 * to allocate: *master_storage |= storage_mask. To free, *master_storage &= ~storage_mask. 287 * 288 * For an X86 vector register example, storage_mask would be: 289 * 0x00000001 for 32-bit view of xmm1 290 * 0x00000003 for 64-bit view of xmm1 291 * 0x0000000f for 128-bit view of xmm1 292 * 0x000000ff for 256-bit view of ymm1 // future expansion, if needed 293 * 0x0000ffff for 512-bit view of ymm1 // future expansion, if needed 294 * 0xffffffff for 1024-bit view of ymm1 // future expansion, if needed 295 * 296 * The "liveness" of a register is handled in a similar way. The liveness_ storage is 297 * held in the widest member of an aliased set. Note, though, that for a temp register to 298 * reused as live, it must both be marked live and the associated SReg() must match the 299 * desired s_reg. This gets a little complicated when dealing with aliased registers. All 300 * members of an aliased set will share the same liveness flags, but each will individually 301 * maintain s_reg_. In this way we can know that at least one member of an 302 * aliased set is live, but will only fully match on the appropriate alias view. For example, 303 * if Arm d1 is live as a double and has s_reg_ set to Dalvik v8 (which also implies v9 304 * because it is wide), its aliases s2 and s3 will show as live, but will have 305 * s_reg_ == INVALID_SREG. An attempt to later AllocLiveReg() of v9 with a single-precision 306 * view will fail because although s3's liveness bit is set, its s_reg_ will not match v9. 307 * This will cause all members of the aliased set to be clobbered and AllocLiveReg() will 308 * report that v9 is currently not live as a single (which is what we want). 309 * 310 * NOTE: the x86 usage is still somewhat in flux. There are competing notions of how 311 * to treat xmm registers: 312 * 1. Treat them all as 128-bits wide, but denote how much data used via bytes field. 313 * o This more closely matches reality, but means you'd need to be able to get 314 * to the associated RegisterInfo struct to figure out how it's being used. 315 * o This is how 64-bit core registers will be used - always 64 bits, but the 316 * "bytes" field will be 4 for 32-bit usage and 8 for 64-bit usage. 317 * 2. View the xmm registers based on contents. 318 * o A single in a xmm2 register would be k32BitVector, while a double in xmm2 would 319 * be a k64BitVector. 320 * o Note that the two uses above would be considered distinct registers (but with 321 * the aliasing mechanism, we could detect interference). 322 * o This is how aliased double and single float registers will be handled on 323 * Arm and MIPS. 324 * Working plan is, for all targets, to follow mechanism 1 for 64-bit core registers, and 325 * mechanism 2 for aliased float registers and x86 vector registers. 326 */ 327 class RegisterInfo { 328 public: 329 RegisterInfo(RegStorage r, uint64_t mask = ENCODE_ALL); 330 ~RegisterInfo() {} 331 static void* operator new(size_t size, ArenaAllocator* arena) { 332 return arena->Alloc(size, kArenaAllocRegAlloc); 333 } 334 335 bool InUse() { return (storage_mask_ & master_->used_storage_) != 0; } 336 void MarkInUse() { master_->used_storage_ |= storage_mask_; } 337 void MarkFree() { master_->used_storage_ &= ~storage_mask_; } 338 // No part of the containing storage is live in this view. 339 bool IsDead() { return (master_->liveness_ & storage_mask_) == 0; } 340 // Liveness of this view matches. Note: not equivalent to !IsDead(). 341 bool IsLive() { return (master_->liveness_ & storage_mask_) == storage_mask_; } 342 void MarkLive(int s_reg) { 343 // TODO: Anything useful to assert here? 344 s_reg_ = s_reg; 345 master_->liveness_ |= storage_mask_; 346 } 347 void MarkDead() { 348 if (SReg() != INVALID_SREG) { 349 s_reg_ = INVALID_SREG; 350 master_->liveness_ &= ~storage_mask_; 351 ResetDefBody(); 352 } 353 } 354 RegStorage GetReg() { return reg_; } 355 void SetReg(RegStorage reg) { reg_ = reg; } 356 bool IsTemp() { return is_temp_; } 357 void SetIsTemp(bool val) { is_temp_ = val; } 358 bool IsWide() { return wide_value_; } 359 void SetIsWide(bool val) { 360 wide_value_ = val; 361 if (!val) { 362 // If not wide, reset partner to self. 363 SetPartner(GetReg()); 364 } 365 } 366 bool IsDirty() { return dirty_; } 367 void SetIsDirty(bool val) { dirty_ = val; } 368 RegStorage Partner() { return partner_; } 369 void SetPartner(RegStorage partner) { partner_ = partner; } 370 int SReg() { return (!IsTemp() || IsLive()) ? s_reg_ : INVALID_SREG; } 371 uint64_t DefUseMask() { return def_use_mask_; } 372 void SetDefUseMask(uint64_t def_use_mask) { def_use_mask_ = def_use_mask; } 373 RegisterInfo* Master() { return master_; } 374 void SetMaster(RegisterInfo* master) { 375 master_ = master; 376 if (master != this) { 377 master_->aliased_ = true; 378 DCHECK(alias_chain_ == nullptr); 379 alias_chain_ = master_->alias_chain_; 380 master_->alias_chain_ = this; 381 } 382 } 383 bool IsAliased() { return aliased_; } 384 RegisterInfo* GetAliasChain() { return alias_chain_; } 385 uint32_t StorageMask() { return storage_mask_; } 386 void SetStorageMask(uint32_t storage_mask) { storage_mask_ = storage_mask; } 387 LIR* DefStart() { return def_start_; } 388 void SetDefStart(LIR* def_start) { def_start_ = def_start; } 389 LIR* DefEnd() { return def_end_; } 390 void SetDefEnd(LIR* def_end) { def_end_ = def_end; } 391 void ResetDefBody() { def_start_ = def_end_ = nullptr; } 392 393 394 private: 395 RegStorage reg_; 396 bool is_temp_; // Can allocate as temp? 397 bool wide_value_; // Holds a Dalvik wide value (either itself, or part of a pair). 398 bool dirty_; // If live, is it dirty? 399 bool aliased_; // Is this the master for other aliased RegisterInfo's? 400 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register. 401 int s_reg_; // Name of live value. 402 uint64_t def_use_mask_; // Resources for this element. 403 uint32_t used_storage_; // 1 bit per 4 bytes of storage. Unused by aliases. 404 uint32_t liveness_; // 1 bit per 4 bytes of storage. Unused by aliases. 405 RegisterInfo* master_; // Pointer to controlling storage mask. 406 uint32_t storage_mask_; // Track allocation of sub-units. 407 LIR *def_start_; // Starting inst in last def sequence. 408 LIR *def_end_; // Ending inst in last def sequence. 409 RegisterInfo* alias_chain_; // Chain of aliased registers. 410 }; 411 412 class RegisterPool { 413 public: 414 RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, const std::vector<RegStorage>& core_regs, 415 const std::vector<RegStorage>& sp_regs, const std::vector<RegStorage>& dp_regs, 416 const std::vector<RegStorage>& reserved_regs, 417 const std::vector<RegStorage>& core_temps, 418 const std::vector<RegStorage>& sp_temps, 419 const std::vector<RegStorage>& dp_temps); 420 ~RegisterPool() {} 421 static void* operator new(size_t size, ArenaAllocator* arena) { 422 return arena->Alloc(size, kArenaAllocRegAlloc); 423 } 424 void ResetNextTemp() { 425 next_core_reg_ = 0; 426 next_sp_reg_ = 0; 427 next_dp_reg_ = 0; 428 } 429 GrowableArray<RegisterInfo*> core_regs_; 430 int next_core_reg_; 431 GrowableArray<RegisterInfo*> sp_regs_; // Single precision float. 432 int next_sp_reg_; 433 GrowableArray<RegisterInfo*> dp_regs_; // Double precision float. 434 int next_dp_reg_; 435 436 private: 437 Mir2Lir* const m2l_; 438 }; 439 440 struct PromotionMap { 441 RegLocationType core_location:3; 442 uint8_t core_reg; 443 RegLocationType fp_location:3; 444 uint8_t FpReg; 445 bool first_in_pair; 446 }; 447 448 // 449 // Slow paths. This object is used generate a sequence of code that is executed in the 450 // slow path. For example, resolving a string or class is slow as it will only be executed 451 // once (after that it is resolved and doesn't need to be done again). We want slow paths 452 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 453 // branch over them. 454 // 455 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 456 // the Compile() function that will be called near the end of the code generated by the 457 // method. 458 // 459 // The basic flow for a slow path is: 460 // 461 // CMP reg, #value 462 // BEQ fromfast 463 // cont: 464 // ... 465 // fast path code 466 // ... 467 // more code 468 // ... 469 // RETURN 470 /// 471 // fromfast: 472 // ... 473 // slow path code 474 // ... 475 // B cont 476 // 477 // So you see we need two labels and two branches. The first branch (called fromfast) is 478 // the conditional branch to the slow path code. The second label (called cont) is used 479 // as an unconditional branch target for getting back to the code after the slow path 480 // has completed. 481 // 482 483 class LIRSlowPath { 484 public: 485 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 486 LIR* cont = nullptr) : 487 m2l_(m2l), cu_(m2l->cu_), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 488 m2l->StartSlowPath(cont); 489 } 490 virtual ~LIRSlowPath() {} 491 virtual void Compile() = 0; 492 493 static void* operator new(size_t size, ArenaAllocator* arena) { 494 return arena->Alloc(size, kArenaAllocData); 495 } 496 497 LIR *GetContinuationLabel() { 498 return cont_; 499 } 500 501 LIR *GetFromFast() { 502 return fromfast_; 503 } 504 505 protected: 506 LIR* GenerateTargetLabel(int opcode = kPseudoTargetLabel); 507 508 Mir2Lir* const m2l_; 509 CompilationUnit* const cu_; 510 const DexOffset current_dex_pc_; 511 LIR* const fromfast_; 512 LIR* const cont_; 513 }; 514 515 virtual ~Mir2Lir() {} 516 517 int32_t s4FromSwitchData(const void* switch_data) { 518 return *reinterpret_cast<const int32_t*>(switch_data); 519 } 520 521 /* 522 * TODO: this is a trace JIT vestige, and its use should be reconsidered. At the time 523 * it was introduced, it was intended to be a quick best guess of type without having to 524 * take the time to do type analysis. Currently, though, we have a much better idea of 525 * the types of Dalvik virtual registers. Instead of using this for a best guess, why not 526 * just use our knowledge of type to select the most appropriate register class? 527 */ 528 RegisterClass RegClassBySize(OpSize size) { 529 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 530 size == kSignedByte) ? kCoreReg : kAnyReg; 531 } 532 533 size_t CodeBufferSizeInBytes() { 534 return code_buffer_.size() / sizeof(code_buffer_[0]); 535 } 536 537 static bool IsPseudoLirOp(int opcode) { 538 return (opcode < 0); 539 } 540 541 /* 542 * LIR operands are 32-bit integers. Sometimes, (especially for managing 543 * instructions which require PC-relative fixups), we need the operands to carry 544 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 545 * hold that index in the operand array. 546 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 547 * may be worth conditionally-compiling a set of identity functions here. 548 */ 549 uint32_t WrapPointer(void* pointer) { 550 uint32_t res = pointer_storage_.Size(); 551 pointer_storage_.Insert(pointer); 552 return res; 553 } 554 555 void* UnwrapPointer(size_t index) { 556 return pointer_storage_.Get(index); 557 } 558 559 // strdup(), but allocates from the arena. 560 char* ArenaStrdup(const char* str) { 561 size_t len = strlen(str) + 1; 562 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 563 if (res != NULL) { 564 strncpy(res, str, len); 565 } 566 return res; 567 } 568 569 // Shared by all targets - implemented in codegen_util.cc 570 void AppendLIR(LIR* lir); 571 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 572 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 573 574 /** 575 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 576 * to place in a frame. 577 * @return Returns the maximum number of compiler temporaries. 578 */ 579 size_t GetMaxPossibleCompilerTemps() const; 580 581 /** 582 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 583 * @return Returns the size in bytes for space needed for compiler temporary spill region. 584 */ 585 size_t GetNumBytesForCompilerTempSpillRegion(); 586 587 DexOffset GetCurrentDexPc() const { 588 return current_dalvik_offset_; 589 } 590 591 int ComputeFrameSize(); 592 virtual void Materialize(); 593 virtual CompiledMethod* GetCompiledMethod(); 594 void MarkSafepointPC(LIR* inst); 595 void SetupResourceMasks(LIR* lir, bool leave_mem_ref = false); 596 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 597 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 598 void SetupRegMask(uint64_t* mask, int reg); 599 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 600 void DumpPromotionMap(); 601 void CodegenDump(); 602 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 603 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 604 LIR* NewLIR0(int opcode); 605 LIR* NewLIR1(int opcode, int dest); 606 LIR* NewLIR2(int opcode, int dest, int src1); 607 LIR* NewLIR2NoDest(int opcode, int src, int info); 608 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 609 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 610 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 611 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 612 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 613 LIR* AddWordData(LIR* *constant_list_p, int value); 614 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 615 void ProcessSwitchTables(); 616 void DumpSparseSwitchTable(const uint16_t* table); 617 void DumpPackedSwitchTable(const uint16_t* table); 618 void MarkBoundary(DexOffset offset, const char* inst_str); 619 void NopLIR(LIR* lir); 620 void UnlinkLIR(LIR* lir); 621 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 622 bool IsInexpensiveConstant(RegLocation rl_src); 623 ConditionCode FlipComparisonOrder(ConditionCode before); 624 ConditionCode NegateComparison(ConditionCode before); 625 virtual void InstallLiteralPools(); 626 void InstallSwitchTables(); 627 void InstallFillArrayData(); 628 bool VerifyCatchEntries(); 629 void CreateMappingTables(); 630 void CreateNativeGcMap(); 631 int AssignLiteralOffset(CodeOffset offset); 632 int AssignSwitchTablesOffset(CodeOffset offset); 633 int AssignFillArrayDataOffset(CodeOffset offset); 634 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 635 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 636 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 637 638 virtual void StartSlowPath(LIR *label) {} 639 virtual void BeginInvoke(CallInfo* info) {} 640 virtual void EndInvoke(CallInfo* info) {} 641 642 643 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 644 RegLocation NarrowRegLoc(RegLocation loc); 645 646 // Shared by all targets - implemented in local_optimizations.cc 647 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 648 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 649 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 650 virtual void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 651 652 // Shared by all targets - implemented in ralloc_util.cc 653 int GetSRegHi(int lowSreg); 654 bool LiveOut(int s_reg); 655 void SimpleRegAlloc(); 656 void ResetRegPool(); 657 void CompilerInitPool(RegisterInfo* info, RegStorage* regs, int num); 658 void DumpRegPool(GrowableArray<RegisterInfo*>* regs); 659 void DumpCoreRegPool(); 660 void DumpFpRegPool(); 661 void DumpRegPools(); 662 /* Mark a temp register as dead. Does not affect allocation state. */ 663 void Clobber(RegStorage reg); 664 void ClobberSReg(int s_reg); 665 void ClobberAliases(RegisterInfo* info); 666 int SRegToPMap(int s_reg); 667 void RecordCorePromotion(RegStorage reg, int s_reg); 668 RegStorage AllocPreservedCoreReg(int s_reg); 669 void RecordSinglePromotion(RegStorage reg, int s_reg); 670 void RecordDoublePromotion(RegStorage reg, int s_reg); 671 RegStorage AllocPreservedSingle(int s_reg); 672 virtual RegStorage AllocPreservedDouble(int s_reg); 673 RegStorage AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required); 674 virtual RegStorage AllocFreeTemp(); 675 virtual RegStorage AllocTemp(); 676 virtual RegStorage AllocTempSingle(); 677 virtual RegStorage AllocTempDouble(); 678 void FlushReg(RegStorage reg); 679 void FlushRegWide(RegStorage reg); 680 RegStorage AllocLiveReg(int s_reg, int reg_class, bool wide); 681 RegStorage FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg); 682 virtual void FreeTemp(RegStorage reg); 683 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 684 virtual bool IsLive(RegStorage reg); 685 virtual bool IsTemp(RegStorage reg); 686 bool IsPromoted(RegStorage reg); 687 bool IsDirty(RegStorage reg); 688 void LockTemp(RegStorage reg); 689 void ResetDef(RegStorage reg); 690 void NullifyRange(RegStorage reg, int s_reg); 691 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 692 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 693 virtual RegLocation WideToNarrow(RegLocation rl); 694 void ResetDefLoc(RegLocation rl); 695 void ResetDefLocWide(RegLocation rl); 696 void ResetDefTracking(); 697 void ClobberAllTemps(); 698 void FlushSpecificReg(RegisterInfo* info); 699 void FlushAllRegs(); 700 bool RegClassMatches(int reg_class, RegStorage reg); 701 void MarkLive(RegLocation loc); 702 void MarkTemp(RegStorage reg); 703 void UnmarkTemp(RegStorage reg); 704 void MarkWide(RegStorage reg); 705 void MarkNarrow(RegStorage reg); 706 void MarkClean(RegLocation loc); 707 void MarkDirty(RegLocation loc); 708 void MarkInUse(RegStorage reg); 709 bool CheckCorePoolSanity(); 710 virtual RegLocation UpdateLoc(RegLocation loc); 711 virtual RegLocation UpdateLocWide(RegLocation loc); 712 RegLocation UpdateRawLoc(RegLocation loc); 713 714 /** 715 * @brief Used to prepare a register location to receive a wide value. 716 * @see EvalLoc 717 * @param loc the location where the value will be stored. 718 * @param reg_class Type of register needed. 719 * @param update Whether the liveness information should be updated. 720 * @return Returns the properly typed temporary in physical register pairs. 721 */ 722 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 723 724 /** 725 * @brief Used to prepare a register location to receive a value. 726 * @param loc the location where the value will be stored. 727 * @param reg_class Type of register needed. 728 * @param update Whether the liveness information should be updated. 729 * @return Returns the properly typed temporary in physical register. 730 */ 731 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 732 733 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 734 void DumpCounts(const RefCounts* arr, int size, const char* msg); 735 void DoPromotion(); 736 int VRegOffset(int v_reg); 737 int SRegOffset(int s_reg); 738 RegLocation GetReturnWide(bool is_double); 739 RegLocation GetReturn(bool is_float); 740 RegisterInfo* GetRegInfo(RegStorage reg); 741 742 // Shared by all targets - implemented in gen_common.cc. 743 void AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume = nullptr); 744 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 745 RegLocation rl_src, RegLocation rl_dest, int lit); 746 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 747 virtual void HandleSlowPaths(); 748 void GenBarrier(); 749 void GenDivZeroException(); 750 // c_code holds condition code that's generated from testing divisor against 0. 751 void GenDivZeroCheck(ConditionCode c_code); 752 // reg holds divisor. 753 void GenDivZeroCheck(RegStorage reg); 754 void GenArrayBoundsCheck(RegStorage index, RegStorage length); 755 void GenArrayBoundsCheck(int32_t index, RegStorage length); 756 LIR* GenNullCheck(RegStorage reg); 757 void MarkPossibleNullPointerException(int opt_flags); 758 void MarkPossibleStackOverflowException(); 759 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 760 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 761 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 762 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 763 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 764 RegLocation rl_src2, LIR* taken, LIR* fall_through); 765 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 766 LIR* taken, LIR* fall_through); 767 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 768 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 769 RegLocation rl_src); 770 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 771 RegLocation rl_src); 772 void GenFilledNewArray(CallInfo* info); 773 void GenSput(MIR* mir, RegLocation rl_src, 774 bool is_long_or_double, bool is_object); 775 void GenSget(MIR* mir, RegLocation rl_dest, 776 bool is_long_or_double, bool is_object); 777 void GenIGet(MIR* mir, int opt_flags, OpSize size, 778 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 779 void GenIPut(MIR* mir, int opt_flags, OpSize size, 780 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 781 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 782 RegLocation rl_src); 783 784 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 785 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 786 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 787 void GenThrow(RegLocation rl_src); 788 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 789 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 790 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 791 RegLocation rl_src1, RegLocation rl_src2); 792 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 793 RegLocation rl_src1, RegLocation rl_shift); 794 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 795 RegLocation rl_src, int lit); 796 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 797 RegLocation rl_src1, RegLocation rl_src2); 798 template <size_t pointer_size> 799 void GenConversionCall(ThreadOffset<pointer_size> func_offset, RegLocation rl_dest, 800 RegLocation rl_src); 801 virtual void GenSuspendTest(int opt_flags); 802 virtual void GenSuspendTestAndBranch(int opt_flags, LIR* target); 803 804 // This will be overridden by x86 implementation. 805 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 806 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 807 RegLocation rl_src1, RegLocation rl_src2); 808 809 // Shared by all targets - implemented in gen_invoke.cc. 810 template <size_t pointer_size> 811 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<pointer_size> helper_offset, bool safepoint_pc, 812 bool use_link = true); 813 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 814 RegStorage CallHelperSetup(ThreadOffset<8> helper_offset); 815 template <size_t pointer_size> 816 void CallRuntimeHelper(ThreadOffset<pointer_size> helper_offset, bool safepoint_pc); 817 template <size_t pointer_size> 818 void CallRuntimeHelperImm(ThreadOffset<pointer_size> helper_offset, int arg0, bool safepoint_pc); 819 template <size_t pointer_size> 820 void CallRuntimeHelperReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, bool safepoint_pc); 821 template <size_t pointer_size> 822 void CallRuntimeHelperRegLocation(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 823 bool safepoint_pc); 824 template <size_t pointer_size> 825 void CallRuntimeHelperImmImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg1, 826 bool safepoint_pc); 827 template <size_t pointer_size> 828 void CallRuntimeHelperImmRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 829 RegLocation arg1, bool safepoint_pc); 830 template <size_t pointer_size> 831 void CallRuntimeHelperRegLocationImm(ThreadOffset<pointer_size> helper_offset, RegLocation arg0, 832 int arg1, bool safepoint_pc); 833 template <size_t pointer_size> 834 void CallRuntimeHelperImmReg(ThreadOffset<pointer_size> helper_offset, int arg0, RegStorage arg1, 835 bool safepoint_pc); 836 template <size_t pointer_size> 837 void CallRuntimeHelperRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, int arg1, 838 bool safepoint_pc); 839 template <size_t pointer_size> 840 void CallRuntimeHelperImmMethod(ThreadOffset<pointer_size> helper_offset, int arg0, 841 bool safepoint_pc); 842 template <size_t pointer_size> 843 void CallRuntimeHelperRegMethod(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 844 bool safepoint_pc); 845 template <size_t pointer_size> 846 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<pointer_size> helper_offset, 847 RegStorage arg0, RegLocation arg2, bool safepoint_pc); 848 template <size_t pointer_size> 849 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 850 RegLocation arg0, RegLocation arg1, 851 bool safepoint_pc); 852 template <size_t pointer_size> 853 void CallRuntimeHelperRegReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 854 RegStorage arg1, bool safepoint_pc); 855 template <size_t pointer_size> 856 void CallRuntimeHelperRegRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 857 RegStorage arg1, int arg2, bool safepoint_pc); 858 template <size_t pointer_size> 859 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 860 RegLocation arg2, bool safepoint_pc); 861 template <size_t pointer_size> 862 void CallRuntimeHelperImmMethodImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg2, 863 bool safepoint_pc); 864 template <size_t pointer_size> 865 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 866 int arg0, RegLocation arg1, RegLocation arg2, 867 bool safepoint_pc); 868 template <size_t pointer_size> 869 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 870 RegLocation arg0, RegLocation arg1, 871 RegLocation arg2, 872 bool safepoint_pc); 873 void GenInvoke(CallInfo* info); 874 void GenInvokeNoInline(CallInfo* info); 875 virtual void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 876 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 877 NextCallInsn next_call_insn, 878 const MethodReference& target_method, 879 uint32_t vtable_idx, 880 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 881 bool skip_this); 882 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 883 NextCallInsn next_call_insn, 884 const MethodReference& target_method, 885 uint32_t vtable_idx, 886 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 887 bool skip_this); 888 889 /** 890 * @brief Used to determine the register location of destination. 891 * @details This is needed during generation of inline intrinsics because it finds destination 892 * of return, 893 * either the physical register or the target of move-result. 894 * @param info Information about the invoke. 895 * @return Returns the destination location. 896 */ 897 RegLocation InlineTarget(CallInfo* info); 898 899 /** 900 * @brief Used to determine the wide register location of destination. 901 * @see InlineTarget 902 * @param info Information about the invoke. 903 * @return Returns the destination location. 904 */ 905 RegLocation InlineTargetWide(CallInfo* info); 906 907 bool GenInlinedCharAt(CallInfo* info); 908 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 909 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 910 bool GenInlinedAbsInt(CallInfo* info); 911 bool GenInlinedAbsLong(CallInfo* info); 912 bool GenInlinedAbsFloat(CallInfo* info); 913 bool GenInlinedAbsDouble(CallInfo* info); 914 bool GenInlinedFloatCvt(CallInfo* info); 915 bool GenInlinedDoubleCvt(CallInfo* info); 916 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 917 bool GenInlinedStringCompareTo(CallInfo* info); 918 bool GenInlinedCurrentThread(CallInfo* info); 919 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 920 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 921 bool is_volatile, bool is_ordered); 922 virtual int LoadArgRegs(CallInfo* info, int call_state, 923 NextCallInsn next_call_insn, 924 const MethodReference& target_method, 925 uint32_t vtable_idx, 926 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 927 bool skip_this); 928 929 // Shared by all targets - implemented in gen_loadstore.cc. 930 RegLocation LoadCurrMethod(); 931 void LoadCurrMethodDirect(RegStorage r_tgt); 932 virtual LIR* LoadConstant(RegStorage r_dest, int value); 933 // Natural word size. 934 virtual LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 935 return LoadBaseDisp(r_base, displacement, r_dest, kWord); 936 } 937 // Load 32 bits, regardless of target. 938 virtual LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { 939 return LoadBaseDisp(r_base, displacement, r_dest, k32); 940 } 941 // Load a reference at base + displacement and decompress into register. 942 virtual LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 943 return LoadBaseDisp(r_base, displacement, r_dest, kReference); 944 } 945 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 946 virtual RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 947 // Load Dalvik value with 64-bit memory storage. 948 virtual RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 949 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 950 virtual void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 951 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 952 virtual void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 953 // Load Dalvik value with 64-bit memory storage. 954 virtual void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 955 // Load Dalvik value with 64-bit memory storage. 956 virtual void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 957 // Store an item of natural word size. 958 virtual LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { 959 return StoreBaseDisp(r_base, displacement, r_src, kWord); 960 } 961 // Store an uncompressed reference into a compressed 32-bit container. 962 virtual LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src) { 963 return StoreBaseDisp(r_base, displacement, r_src, kReference); 964 } 965 // Store 32 bits, regardless of target. 966 virtual LIR* Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) { 967 return StoreBaseDisp(r_base, displacement, r_src, k32); 968 } 969 970 /** 971 * @brief Used to do the final store in the destination as per bytecode semantics. 972 * @param rl_dest The destination dalvik register location. 973 * @param rl_src The source register location. Can be either physical register or dalvik register. 974 */ 975 virtual void StoreValue(RegLocation rl_dest, RegLocation rl_src); 976 977 /** 978 * @brief Used to do the final store in a wide destination as per bytecode semantics. 979 * @see StoreValue 980 * @param rl_dest The destination dalvik register location. 981 * @param rl_src The source register location. Can be either physical register or dalvik 982 * register. 983 */ 984 virtual void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 985 986 /** 987 * @brief Used to do the final store to a destination as per bytecode semantics. 988 * @see StoreValue 989 * @param rl_dest The destination dalvik register location. 990 * @param rl_src The source register location. It must be kLocPhysReg 991 * 992 * This is used for x86 two operand computations, where we have computed the correct 993 * register value that now needs to be properly registered. This is used to avoid an 994 * extra register copy that would result if StoreValue was called. 995 */ 996 virtual void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 997 998 /** 999 * @brief Used to do the final store in a wide destination as per bytecode semantics. 1000 * @see StoreValueWide 1001 * @param rl_dest The destination dalvik register location. 1002 * @param rl_src The source register location. It must be kLocPhysReg 1003 * 1004 * This is used for x86 two operand computations, where we have computed the correct 1005 * register values that now need to be properly registered. This is used to avoid an 1006 * extra pair of register copies that would result if StoreValueWide was called. 1007 */ 1008 virtual void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 1009 1010 // Shared by all targets - implemented in mir_to_lir.cc. 1011 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 1012 virtual void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1013 bool MethodBlockCodeGen(BasicBlock* bb); 1014 bool SpecialMIR2LIR(const InlineMethod& special); 1015 virtual void MethodMIR2LIR(); 1016 // Update LIR for verbose listings. 1017 void UpdateLIROffsets(); 1018 1019 /* 1020 * @brief Load the address of the dex method into the register. 1021 * @param target_method The MethodReference of the method to be invoked. 1022 * @param type How the method will be invoked. 1023 * @param register that will contain the code address. 1024 * @note register will be passed to TargetReg to get physical register. 1025 */ 1026 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 1027 SpecialTargetRegister symbolic_reg); 1028 1029 /* 1030 * @brief Load the Method* of a dex method into the register. 1031 * @param target_method The MethodReference of the method to be invoked. 1032 * @param type How the method will be invoked. 1033 * @param register that will contain the code address. 1034 * @note register will be passed to TargetReg to get physical register. 1035 */ 1036 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 1037 SpecialTargetRegister symbolic_reg); 1038 1039 /* 1040 * @brief Load the Class* of a Dex Class type into the register. 1041 * @param type How the method will be invoked. 1042 * @param register that will contain the code address. 1043 * @note register will be passed to TargetReg to get physical register. 1044 */ 1045 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 1046 1047 // Routines that work for the generic case, but may be overriden by target. 1048 /* 1049 * @brief Compare memory to immediate, and branch if condition true. 1050 * @param cond The condition code that when true will branch to the target. 1051 * @param temp_reg A temporary register that can be used if compare to memory is not 1052 * supported by the architecture. 1053 * @param base_reg The register holding the base address. 1054 * @param offset The offset from the base. 1055 * @param check_value The immediate to compare to. 1056 * @returns The branch instruction that was generated. 1057 */ 1058 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 1059 int offset, int check_value, LIR* target); 1060 1061 // Required for target - codegen helpers. 1062 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1063 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1064 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1065 virtual LIR* CheckSuspendUsingLoad() = 0; 1066 1067 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 1068 virtual RegStorage LoadHelper(ThreadOffset<8> offset) = 0; 1069 1070 virtual LIR* LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, 1071 OpSize size) = 0; 1072 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 1073 OpSize size) = 0; 1074 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 1075 int scale, OpSize size) = 0; 1076 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1077 int displacement, RegStorage r_dest, OpSize size) = 0; 1078 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 1079 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 1080 virtual LIR* StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src, 1081 OpSize size) = 0; 1082 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 1083 OpSize size) = 0; 1084 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 1085 int scale, OpSize size) = 0; 1086 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1087 int displacement, RegStorage r_src, OpSize size) = 0; 1088 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 1089 1090 // Required for target - register utilities. 1091 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 1092 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 1093 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 1094 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 1095 virtual RegLocation GetReturnAlt() = 0; 1096 virtual RegLocation GetReturnWideAlt() = 0; 1097 virtual RegLocation LocCReturn() = 0; 1098 virtual RegLocation LocCReturnDouble() = 0; 1099 virtual RegLocation LocCReturnFloat() = 0; 1100 virtual RegLocation LocCReturnWide() = 0; 1101 virtual uint64_t GetRegMaskCommon(RegStorage reg) = 0; 1102 virtual void AdjustSpillMask() = 0; 1103 virtual void ClobberCallerSave() = 0; 1104 virtual void FreeCallTemps() = 0; 1105 virtual void LockCallTemps() = 0; 1106 virtual void MarkPreservedSingle(int v_reg, RegStorage reg) = 0; 1107 virtual void MarkPreservedDouble(int v_reg, RegStorage reg) = 0; 1108 virtual void CompilerInitializeRegAlloc() = 0; 1109 1110 // Required for target - miscellaneous. 1111 virtual void AssembleLIR() = 0; 1112 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 1113 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 1114 virtual const char* GetTargetInstFmt(int opcode) = 0; 1115 virtual const char* GetTargetInstName(int opcode) = 0; 1116 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 1117 virtual uint64_t GetPCUseDefEncoding() = 0; 1118 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 1119 virtual int GetInsnSize(LIR* lir) = 0; 1120 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 1121 1122 // Check support for volatile load/store of a given size. 1123 virtual bool SupportsVolatileLoadStore(OpSize size) = 0; 1124 // Get the register class for load/store of a field. 1125 virtual RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) = 0; 1126 1127 // Required for target - Dalvik-level generators. 1128 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1129 RegLocation rl_src1, RegLocation rl_src2) = 0; 1130 virtual void GenMulLong(Instruction::Code, 1131 RegLocation rl_dest, RegLocation rl_src1, 1132 RegLocation rl_src2) = 0; 1133 virtual void GenAddLong(Instruction::Code, 1134 RegLocation rl_dest, RegLocation rl_src1, 1135 RegLocation rl_src2) = 0; 1136 virtual void GenAndLong(Instruction::Code, 1137 RegLocation rl_dest, RegLocation rl_src1, 1138 RegLocation rl_src2) = 0; 1139 virtual void GenArithOpDouble(Instruction::Code opcode, 1140 RegLocation rl_dest, RegLocation rl_src1, 1141 RegLocation rl_src2) = 0; 1142 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 1143 RegLocation rl_src1, RegLocation rl_src2) = 0; 1144 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 1145 RegLocation rl_src1, RegLocation rl_src2) = 0; 1146 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 1147 RegLocation rl_src) = 0; 1148 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 1149 1150 /** 1151 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 1152 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 1153 * that applies on integers. The generated code will write the smallest or largest value 1154 * directly into the destination register as specified by the invoke information. 1155 * @param info Information about the invoke. 1156 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 1157 * @return Returns true if successfully generated 1158 */ 1159 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 1160 1161 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 1162 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 1163 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 1164 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1165 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1166 RegLocation rl_src2) = 0; 1167 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1168 RegLocation rl_src2) = 0; 1169 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1170 RegLocation rl_src2) = 0; 1171 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 1172 bool is_div) = 0; 1173 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 1174 bool is_div) = 0; 1175 /* 1176 * @brief Generate an integer div or rem operation by a literal. 1177 * @param rl_dest Destination Location. 1178 * @param rl_src1 Numerator Location. 1179 * @param rl_src2 Divisor Location. 1180 * @param is_div 'true' if this is a division, 'false' for a remainder. 1181 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 1182 */ 1183 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 1184 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 1185 /* 1186 * @brief Generate an integer div or rem operation by a literal. 1187 * @param rl_dest Destination Location. 1188 * @param rl_src Numerator Location. 1189 * @param lit Divisor. 1190 * @param is_div 'true' if this is a division, 'false' for a remainder. 1191 */ 1192 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 1193 bool is_div) = 0; 1194 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 1195 1196 /** 1197 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 1198 * @details This is used for generating DivideByZero checks when divisor is held in two 1199 * separate registers. 1200 * @param reg The register holding the pair of 32-bit values. 1201 */ 1202 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 1203 1204 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 1205 virtual void GenExitSequence() = 0; 1206 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 1207 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 1208 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 1209 1210 /* 1211 * @brief Handle Machine Specific MIR Extended opcodes. 1212 * @param bb The basic block in which the MIR is from. 1213 * @param mir The MIR whose opcode is not standard extended MIR. 1214 * @note Base class implementation will abort for unknown opcodes. 1215 */ 1216 virtual void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 1217 1218 /** 1219 * @brief Lowers the kMirOpSelect MIR into LIR. 1220 * @param bb The basic block in which the MIR is from. 1221 * @param mir The MIR whose opcode is kMirOpSelect. 1222 */ 1223 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 1224 1225 /** 1226 * @brief Used to generate a memory barrier in an architecture specific way. 1227 * @details The last generated LIR will be considered for use as barrier. Namely, 1228 * if the last LIR can be updated in a way where it will serve the semantics of 1229 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 1230 * that can keep the semantics. 1231 * @param barrier_kind The kind of memory barrier to generate. 1232 * @return whether a new instruction was generated. 1233 */ 1234 virtual bool GenMemBarrier(MemBarrierKind barrier_kind) = 0; 1235 1236 virtual void GenMoveException(RegLocation rl_dest) = 0; 1237 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 1238 int first_bit, int second_bit) = 0; 1239 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 1240 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 1241 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1242 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1243 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1244 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1245 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1246 RegLocation rl_index, RegLocation rl_src, int scale, 1247 bool card_mark) = 0; 1248 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1249 RegLocation rl_src1, RegLocation rl_shift) = 0; 1250 1251 // Required for target - single operation generators. 1252 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1253 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1254 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1255 LIR* target) = 0; 1256 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1257 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1258 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1259 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1260 virtual void OpEndIT(LIR* it) = 0; 1261 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1262 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1263 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1264 virtual void OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1265 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1266 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1267 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1268 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1269 1270 /** 1271 * @brief Used to generate an LIR that does a load from mem to reg. 1272 * @param r_dest The destination physical register. 1273 * @param r_base The base physical register for memory operand. 1274 * @param offset The displacement for memory operand. 1275 * @param move_type Specification on the move desired (size, alignment, register kind). 1276 * @return Returns the generate move LIR. 1277 */ 1278 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1279 MoveType move_type) = 0; 1280 1281 /** 1282 * @brief Used to generate an LIR that does a store from reg to mem. 1283 * @param r_base The base physical register for memory operand. 1284 * @param offset The displacement for memory operand. 1285 * @param r_src The destination physical register. 1286 * @param bytes_to_move The number of bytes to move. 1287 * @param is_aligned Whether the memory location is known to be aligned. 1288 * @return Returns the generate move LIR. 1289 */ 1290 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1291 MoveType move_type) = 0; 1292 1293 /** 1294 * @brief Used for generating a conditional register to register operation. 1295 * @param op The opcode kind. 1296 * @param cc The condition code that when true will perform the opcode. 1297 * @param r_dest The destination physical register. 1298 * @param r_src The source physical register. 1299 * @return Returns the newly created LIR or null in case of creation failure. 1300 */ 1301 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1302 1303 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1304 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1305 RegStorage r_src2) = 0; 1306 virtual LIR* OpTestSuspend(LIR* target) = 0; 1307 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1308 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) = 0; 1309 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1310 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1311 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1312 int offset) = 0; 1313 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1314 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1315 virtual void OpTlsCmp(ThreadOffset<8> offset, int val) = 0; 1316 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1317 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1318 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1319 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1320 1321 // May be optimized by targets. 1322 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1323 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1324 1325 // Temp workaround 1326 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1327 1328 protected: 1329 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1330 1331 CompilationUnit* GetCompilationUnit() { 1332 return cu_; 1333 } 1334 /* 1335 * @brief Returns the index of the lowest set bit in 'x'. 1336 * @param x Value to be examined. 1337 * @returns The bit number of the lowest bit set in the value. 1338 */ 1339 int32_t LowestSetBit(uint64_t x); 1340 /* 1341 * @brief Is this value a power of two? 1342 * @param x Value to be examined. 1343 * @returns 'true' if only 1 bit is set in the value. 1344 */ 1345 bool IsPowerOfTwo(uint64_t x); 1346 /* 1347 * @brief Do these SRs overlap? 1348 * @param rl_op1 One RegLocation 1349 * @param rl_op2 The other RegLocation 1350 * @return 'true' if the VR pairs overlap 1351 * 1352 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1353 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1354 * dex, we'll want to make this case illegal. 1355 */ 1356 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1357 1358 /* 1359 * @brief Force a location (in a register) into a temporary register 1360 * @param loc location of result 1361 * @returns update location 1362 */ 1363 virtual RegLocation ForceTemp(RegLocation loc); 1364 1365 /* 1366 * @brief Force a wide location (in registers) into temporary registers 1367 * @param loc location of result 1368 * @returns update location 1369 */ 1370 virtual RegLocation ForceTempWide(RegLocation loc); 1371 1372 static constexpr OpSize LoadStoreOpSize(bool wide, bool ref) { 1373 return wide ? k64 : ref ? kReference : k32; 1374 } 1375 1376 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1377 RegLocation rl_dest, RegLocation rl_src); 1378 1379 void AddSlowPath(LIRSlowPath* slowpath); 1380 1381 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1382 bool type_known_abstract, bool use_declaring_class, 1383 bool can_assume_type_is_in_dex_cache, 1384 uint32_t type_idx, RegLocation rl_dest, 1385 RegLocation rl_src); 1386 /* 1387 * @brief Generate the debug_frame FDE information if possible. 1388 * @returns pointer to vector containg CFE information, or NULL. 1389 */ 1390 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1391 1392 /** 1393 * @brief Used to insert marker that can be used to associate MIR with LIR. 1394 * @details Only inserts marker if verbosity is enabled. 1395 * @param mir The mir that is currently being generated. 1396 */ 1397 void GenPrintLabel(MIR* mir); 1398 1399 /** 1400 * @brief Used to generate return sequence when there is no frame. 1401 * @details Assumes that the return registers have already been populated. 1402 */ 1403 virtual void GenSpecialExitSequence() = 0; 1404 1405 /** 1406 * @brief Used to generate code for special methods that are known to be 1407 * small enough to work in frameless mode. 1408 * @param bb The basic block of the first MIR. 1409 * @param mir The first MIR of the special method. 1410 * @param special Information about the special method. 1411 * @return Returns whether or not this was handled successfully. Returns false 1412 * if caller should punt to normal MIR2LIR conversion. 1413 */ 1414 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1415 1416 protected: 1417 void ClobberBody(RegisterInfo* p); 1418 void SetCurrentDexPc(DexOffset dexpc) { 1419 current_dalvik_offset_ = dexpc; 1420 } 1421 1422 /** 1423 * @brief Used to lock register if argument at in_position was passed that way. 1424 * @details Does nothing if the argument is passed via stack. 1425 * @param in_position The argument number whose register to lock. 1426 * @param wide Whether the argument is wide. 1427 */ 1428 void LockArg(int in_position, bool wide = false); 1429 1430 /** 1431 * @brief Used to load VR argument to a physical register. 1432 * @details The load is only done if the argument is not already in physical register. 1433 * LockArg must have been previously called. 1434 * @param in_position The argument number to load. 1435 * @param wide Whether the argument is 64-bit or not. 1436 * @return Returns the register (or register pair) for the loaded argument. 1437 */ 1438 RegStorage LoadArg(int in_position, RegisterClass reg_class, bool wide = false); 1439 1440 /** 1441 * @brief Used to load a VR argument directly to a specified register location. 1442 * @param in_position The argument number to place in register. 1443 * @param rl_dest The register location where to place argument. 1444 */ 1445 void LoadArgDirect(int in_position, RegLocation rl_dest); 1446 1447 /** 1448 * @brief Used to generate LIR for special getter method. 1449 * @param mir The mir that represents the iget. 1450 * @param special Information about the special getter method. 1451 * @return Returns whether LIR was successfully generated. 1452 */ 1453 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1454 1455 /** 1456 * @brief Used to generate LIR for special setter method. 1457 * @param mir The mir that represents the iput. 1458 * @param special Information about the special setter method. 1459 * @return Returns whether LIR was successfully generated. 1460 */ 1461 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1462 1463 /** 1464 * @brief Used to generate LIR for special return-args method. 1465 * @param mir The mir that represents the return of argument. 1466 * @param special Information about the special return-args method. 1467 * @return Returns whether LIR was successfully generated. 1468 */ 1469 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1470 1471 void AddDivZeroCheckSlowPath(LIR* branch); 1472 1473 // Copy arg0 and arg1 to kArg0 and kArg1 safely, possibly using 1474 // kArg2 as temp. 1475 virtual void CopyToArgumentRegs(RegStorage arg0, RegStorage arg1); 1476 1477 /** 1478 * @brief Load Constant into RegLocation 1479 * @param rl_dest Destination RegLocation 1480 * @param value Constant value 1481 */ 1482 virtual void GenConst(RegLocation rl_dest, int value); 1483 1484 public: 1485 // TODO: add accessors for these. 1486 LIR* literal_list_; // Constants. 1487 LIR* method_literal_list_; // Method literals requiring patching. 1488 LIR* class_literal_list_; // Class literals requiring patching. 1489 LIR* code_literal_list_; // Code literals requiring patching. 1490 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1491 1492 protected: 1493 CompilationUnit* const cu_; 1494 MIRGraph* const mir_graph_; 1495 GrowableArray<SwitchTable*> switch_tables_; 1496 GrowableArray<FillArrayData*> fill_array_data_; 1497 GrowableArray<RegisterInfo*> tempreg_info_; 1498 GrowableArray<RegisterInfo*> reginfo_map_; 1499 GrowableArray<void*> pointer_storage_; 1500 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1501 CodeOffset data_offset_; // starting offset of literal pool. 1502 size_t total_size_; // header + code size. 1503 LIR* block_label_list_; 1504 PromotionMap* promotion_map_; 1505 /* 1506 * TODO: The code generation utilities don't have a built-in 1507 * mechanism to propagate the original Dalvik opcode address to the 1508 * associated generated instructions. For the trace compiler, this wasn't 1509 * necessary because the interpreter handled all throws and debugging 1510 * requests. For now we'll handle this by placing the Dalvik offset 1511 * in the CompilationUnit struct before codegen for each instruction. 1512 * The low-level LIR creation utilites will pull it from here. Rework this. 1513 */ 1514 DexOffset current_dalvik_offset_; 1515 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1516 RegisterPool* reg_pool_; 1517 /* 1518 * Sanity checking for the register temp tracking. The same ssa 1519 * name should never be associated with one temp register per 1520 * instruction compilation. 1521 */ 1522 int live_sreg_; 1523 CodeBuffer code_buffer_; 1524 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1525 std::vector<uint8_t> encoded_mapping_table_; 1526 std::vector<uint32_t> core_vmap_table_; 1527 std::vector<uint32_t> fp_vmap_table_; 1528 std::vector<uint8_t> native_gc_map_; 1529 int num_core_spills_; 1530 int num_fp_spills_; 1531 int frame_size_; 1532 unsigned int core_spill_mask_; 1533 unsigned int fp_spill_mask_; 1534 LIR* first_lir_insn_; 1535 LIR* last_lir_insn_; 1536 1537 GrowableArray<LIRSlowPath*> slow_paths_; 1538}; // Class Mir2Lir 1539 1540} // namespace art 1541 1542#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1543