ralloc_util.cc revision c763e350da562b0c6bebf10599588d4901140e45
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains register alloction support. */ 18 19#include "dex/compiler_ir.h" 20#include "dex/compiler_internals.h" 21#include "mir_to_lir-inl.h" 22 23namespace art { 24 25/* 26 * Free all allocated temps in the temp pools. Note that this does 27 * not affect the "liveness" of a temp register, which will stay 28 * live until it is either explicitly killed or reallocated. 29 */ 30void Mir2Lir::ResetRegPool() { 31 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); 32 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { 33 info->MarkFree(); 34 } 35 // Reset temp tracking sanity check. 36 if (kIsDebugBuild) { 37 live_sreg_ = INVALID_SREG; 38 } 39} 40 41Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, const ResourceMask& mask) 42 : reg_(r), is_temp_(false), wide_value_(false), dirty_(false), aliased_(false), partner_(r), 43 s_reg_(INVALID_SREG), def_use_mask_(mask), master_(this), def_start_(nullptr), 44 def_end_(nullptr), alias_chain_(nullptr) { 45 switch (r.StorageSize()) { 46 case 0: storage_mask_ = 0xffffffff; break; 47 case 4: storage_mask_ = 0x00000001; break; 48 case 8: storage_mask_ = 0x00000003; break; 49 case 16: storage_mask_ = 0x0000000f; break; 50 case 32: storage_mask_ = 0x000000ff; break; 51 case 64: storage_mask_ = 0x0000ffff; break; 52 case 128: storage_mask_ = 0xffffffff; break; 53 } 54 used_storage_ = r.Valid() ? ~storage_mask_ : storage_mask_; 55 liveness_ = used_storage_; 56} 57 58Mir2Lir::RegisterPool::RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, 59 const ArrayRef<const RegStorage>& core_regs, 60 const ArrayRef<const RegStorage>& core64_regs, 61 const ArrayRef<const RegStorage>& sp_regs, 62 const ArrayRef<const RegStorage>& dp_regs, 63 const ArrayRef<const RegStorage>& reserved_regs, 64 const ArrayRef<const RegStorage>& reserved64_regs, 65 const ArrayRef<const RegStorage>& core_temps, 66 const ArrayRef<const RegStorage>& core64_temps, 67 const ArrayRef<const RegStorage>& sp_temps, 68 const ArrayRef<const RegStorage>& dp_temps) : 69 core_regs_(arena, core_regs.size()), next_core_reg_(0), 70 core64_regs_(arena, core64_regs.size()), next_core64_reg_(0), 71 sp_regs_(arena, sp_regs.size()), next_sp_reg_(0), 72 dp_regs_(arena, dp_regs.size()), next_dp_reg_(0), m2l_(m2l) { 73 // Initialize the fast lookup map. 74 m2l_->reginfo_map_.Reset(); 75 if (kIsDebugBuild) { 76 m2l_->reginfo_map_.Resize(RegStorage::kMaxRegs); 77 for (unsigned i = 0; i < RegStorage::kMaxRegs; i++) { 78 m2l_->reginfo_map_.Insert(nullptr); 79 } 80 } else { 81 m2l_->reginfo_map_.SetSize(RegStorage::kMaxRegs); 82 } 83 84 // Construct the register pool. 85 for (const RegStorage& reg : core_regs) { 86 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 87 m2l_->reginfo_map_.Put(reg.GetReg(), info); 88 core_regs_.Insert(info); 89 } 90 for (const RegStorage& reg : core64_regs) { 91 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 92 m2l_->reginfo_map_.Put(reg.GetReg(), info); 93 core64_regs_.Insert(info); 94 } 95 for (const RegStorage& reg : sp_regs) { 96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 97 m2l_->reginfo_map_.Put(reg.GetReg(), info); 98 sp_regs_.Insert(info); 99 } 100 for (const RegStorage& reg : dp_regs) { 101 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 102 m2l_->reginfo_map_.Put(reg.GetReg(), info); 103 dp_regs_.Insert(info); 104 } 105 106 // Keep special registers from being allocated. 107 for (RegStorage reg : reserved_regs) { 108 m2l_->MarkInUse(reg); 109 } 110 for (RegStorage reg : reserved64_regs) { 111 m2l_->MarkInUse(reg); 112 } 113 114 // Mark temp regs - all others not in use can be used for promotion 115 for (RegStorage reg : core_temps) { 116 m2l_->MarkTemp(reg); 117 } 118 for (RegStorage reg : core64_temps) { 119 m2l_->MarkTemp(reg); 120 } 121 for (RegStorage reg : sp_temps) { 122 m2l_->MarkTemp(reg); 123 } 124 for (RegStorage reg : dp_temps) { 125 m2l_->MarkTemp(reg); 126 } 127 128 // Add an entry for InvalidReg with zero'd mask. 129 RegisterInfo* invalid_reg = new (arena) RegisterInfo(RegStorage::InvalidReg(), kEncodeNone); 130 m2l_->reginfo_map_.Put(RegStorage::InvalidReg().GetReg(), invalid_reg); 131 132 // Existence of core64 registers implies wide references. 133 if (core64_regs_.Size() != 0) { 134 ref_regs_ = &core64_regs_; 135 next_ref_reg_ = &next_core64_reg_; 136 } else { 137 ref_regs_ = &core_regs_; 138 next_ref_reg_ = &next_core_reg_; 139 } 140} 141 142void Mir2Lir::DumpRegPool(GrowableArray<RegisterInfo*>* regs) { 143 LOG(INFO) << "================================================"; 144 GrowableArray<RegisterInfo*>::Iterator it(regs); 145 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 146 LOG(INFO) << StringPrintf( 147 "R[%d:%d:%c]: T:%d, U:%d, W:%d, p:%d, LV:%d, D:%d, SR:%d, DEF:%d", 148 info->GetReg().GetReg(), info->GetReg().GetRegNum(), info->GetReg().IsFloat() ? 'f' : 'c', 149 info->IsTemp(), info->InUse(), info->IsWide(), info->Partner().GetReg(), info->IsLive(), 150 info->IsDirty(), info->SReg(), info->DefStart() != nullptr); 151 } 152 LOG(INFO) << "================================================"; 153} 154 155void Mir2Lir::DumpCoreRegPool() { 156 DumpRegPool(®_pool_->core_regs_); 157 DumpRegPool(®_pool_->core64_regs_); 158} 159 160void Mir2Lir::DumpFpRegPool() { 161 DumpRegPool(®_pool_->sp_regs_); 162 DumpRegPool(®_pool_->dp_regs_); 163} 164 165void Mir2Lir::DumpRegPools() { 166 LOG(INFO) << "Core registers"; 167 DumpCoreRegPool(); 168 LOG(INFO) << "FP registers"; 169 DumpFpRegPool(); 170} 171 172void Mir2Lir::Clobber(RegStorage reg) { 173 if (UNLIKELY(reg.IsPair())) { 174 DCHECK(!GetRegInfo(reg.GetLow())->IsAliased()); 175 Clobber(reg.GetLow()); 176 DCHECK(!GetRegInfo(reg.GetHigh())->IsAliased()); 177 Clobber(reg.GetHigh()); 178 } else { 179 RegisterInfo* info = GetRegInfo(reg); 180 if (info->IsTemp() && !info->IsDead()) { 181 if (info->GetReg().NotExactlyEquals(info->Partner())) { 182 ClobberBody(GetRegInfo(info->Partner())); 183 } 184 ClobberBody(info); 185 if (info->IsAliased()) { 186 ClobberAliases(info, info->StorageMask()); 187 } else { 188 RegisterInfo* master = info->Master(); 189 if (info != master) { 190 ClobberBody(info->Master()); 191 ClobberAliases(info->Master(), info->StorageMask()); 192 } 193 } 194 } 195 } 196} 197 198void Mir2Lir::ClobberAliases(RegisterInfo* info, uint32_t clobber_mask) { 199 for (RegisterInfo* alias = info->GetAliasChain(); alias != nullptr; 200 alias = alias->GetAliasChain()) { 201 DCHECK(!alias->IsAliased()); // Only the master should be marked as alised. 202 // Only clobber if we have overlap. 203 if ((alias->StorageMask() & clobber_mask) != 0) { 204 ClobberBody(alias); 205 } 206 } 207} 208 209/* 210 * Break the association between a Dalvik vreg and a physical temp register of either register 211 * class. 212 * TODO: Ideally, the public version of this code should not exist. Besides its local usage 213 * in the register utilities, is is also used by code gen routines to work around a deficiency in 214 * local register allocation, which fails to distinguish between the "in" and "out" identities 215 * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg 216 * is used both as the source and destination register of an operation in which the type 217 * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is 218 * addressed. 219 */ 220void Mir2Lir::ClobberSReg(int s_reg) { 221 if (s_reg != INVALID_SREG) { 222 if (kIsDebugBuild && s_reg == live_sreg_) { 223 live_sreg_ = INVALID_SREG; 224 } 225 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); 226 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { 227 if (info->SReg() == s_reg) { 228 if (info->GetReg().NotExactlyEquals(info->Partner())) { 229 // Dealing with a pair - clobber the other half. 230 DCHECK(!info->IsAliased()); 231 ClobberBody(GetRegInfo(info->Partner())); 232 } 233 ClobberBody(info); 234 if (info->IsAliased()) { 235 ClobberAliases(info, info->StorageMask()); 236 } 237 } 238 } 239 } 240} 241 242/* 243 * SSA names associated with the initial definitions of Dalvik 244 * registers are the same as the Dalvik register number (and 245 * thus take the same position in the promotion_map. However, 246 * the special Method* and compiler temp resisters use negative 247 * v_reg numbers to distinguish them and can have an arbitrary 248 * ssa name (above the last original Dalvik register). This function 249 * maps SSA names to positions in the promotion_map array. 250 */ 251int Mir2Lir::SRegToPMap(int s_reg) { 252 DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); 253 DCHECK_GE(s_reg, 0); 254 int v_reg = mir_graph_->SRegToVReg(s_reg); 255 if (v_reg >= 0) { 256 DCHECK_LT(v_reg, cu_->num_dalvik_registers); 257 return v_reg; 258 } else { 259 /* 260 * It must be the case that the v_reg for temporary is less than or equal to the 261 * base reg for temps. For that reason, "position" must be zero or positive. 262 */ 263 unsigned int position = std::abs(v_reg) - std::abs(static_cast<int>(kVRegTempBaseReg)); 264 265 // The temporaries are placed after dalvik registers in the promotion map 266 DCHECK_LT(position, mir_graph_->GetNumUsedCompilerTemps()); 267 return cu_->num_dalvik_registers + position; 268 } 269} 270 271// TODO: refactor following Alloc/Record routines - much commonality. 272void Mir2Lir::RecordCorePromotion(RegStorage reg, int s_reg) { 273 int p_map_idx = SRegToPMap(s_reg); 274 int v_reg = mir_graph_->SRegToVReg(s_reg); 275 int reg_num = reg.GetRegNum(); 276 GetRegInfo(reg)->MarkInUse(); 277 core_spill_mask_ |= (1 << reg_num); 278 // Include reg for later sort 279 core_vmap_table_.push_back(reg_num << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); 280 num_core_spills_++; 281 promotion_map_[p_map_idx].core_location = kLocPhysReg; 282 promotion_map_[p_map_idx].core_reg = reg_num; 283} 284 285/* Reserve a callee-save register. Return InvalidReg if none available */ 286RegStorage Mir2Lir::AllocPreservedCoreReg(int s_reg) { 287 RegStorage res; 288 /* 289 * Note: it really doesn't matter much whether we allocate from the core or core64 290 * pool for 64-bit targets - but for some targets it does matter whether allocations 291 * happens from the single or double pool. This entire section of code could stand 292 * a good refactoring. 293 */ 294 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->core_regs_); 295 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 296 if (!info->IsTemp() && !info->InUse()) { 297 res = info->GetReg(); 298 RecordCorePromotion(res, s_reg); 299 break; 300 } 301 } 302 return res; 303} 304 305void Mir2Lir::RecordFpPromotion(RegStorage reg, int s_reg) { 306 DCHECK_NE(cu_->instruction_set, kThumb2); 307 int p_map_idx = SRegToPMap(s_reg); 308 int v_reg = mir_graph_->SRegToVReg(s_reg); 309 int reg_num = reg.GetRegNum(); 310 GetRegInfo(reg)->MarkInUse(); 311 fp_spill_mask_ |= (1 << reg_num); 312 // Include reg for later sort 313 fp_vmap_table_.push_back(reg_num << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); 314 num_fp_spills_++; 315 promotion_map_[p_map_idx].fp_location = kLocPhysReg; 316 promotion_map_[p_map_idx].fp_reg = reg.GetReg(); 317} 318 319// Reserve a callee-save floating point. 320RegStorage Mir2Lir::AllocPreservedFpReg(int s_reg) { 321 /* 322 * For targets other than Thumb2, it doesn't matter whether we allocate from 323 * the sp_regs_ or dp_regs_ pool. Some refactoring is in order here. 324 */ 325 DCHECK_NE(cu_->instruction_set, kThumb2); 326 RegStorage res; 327 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); 328 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 329 if (!info->IsTemp() && !info->InUse()) { 330 res = info->GetReg(); 331 RecordFpPromotion(res, s_reg); 332 break; 333 } 334 } 335 return res; 336} 337 338// TODO: this is Thumb2 only. Remove when DoPromotion refactored. 339RegStorage Mir2Lir::AllocPreservedDouble(int s_reg) { 340 RegStorage res; 341 UNIMPLEMENTED(FATAL) << "Unexpected use of AllocPreservedDouble"; 342 return res; 343} 344 345// TODO: this is Thumb2 only. Remove when DoPromotion refactored. 346RegStorage Mir2Lir::AllocPreservedSingle(int s_reg) { 347 RegStorage res; 348 UNIMPLEMENTED(FATAL) << "Unexpected use of AllocPreservedSingle"; 349 return res; 350} 351 352 353RegStorage Mir2Lir::AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required) { 354 int num_regs = regs.Size(); 355 int next = *next_temp; 356 for (int i = 0; i< num_regs; i++) { 357 if (next >= num_regs) 358 next = 0; 359 RegisterInfo* info = regs.Get(next); 360 // Try to allocate a register that doesn't hold a live value. 361 if (info->IsTemp() && !info->InUse() && info->IsDead()) { 362 Clobber(info->GetReg()); 363 info->MarkInUse(); 364 /* 365 * NOTE: "wideness" is an attribute of how the container is used, not its physical size. 366 * The caller will set wideness as appropriate. 367 */ 368 if (info->IsWide()) { 369 RegisterInfo* partner = GetRegInfo(info->Partner()); 370 DCHECK_EQ(info->GetReg().GetRegNum(), partner->Partner().GetRegNum()); 371 DCHECK(partner->IsWide()); 372 info->SetIsWide(false); 373 partner->SetIsWide(false); 374 } 375 *next_temp = next + 1; 376 return info->GetReg(); 377 } 378 next++; 379 } 380 next = *next_temp; 381 // No free non-live regs. Anything we can kill? 382 for (int i = 0; i< num_regs; i++) { 383 if (next >= num_regs) 384 next = 0; 385 RegisterInfo* info = regs.Get(next); 386 if (info->IsTemp() && !info->InUse()) { 387 // Got one. Kill it. 388 ClobberSReg(info->SReg()); 389 Clobber(info->GetReg()); 390 info->MarkInUse(); 391 if (info->IsWide()) { 392 RegisterInfo* partner = GetRegInfo(info->Partner()); 393 DCHECK_EQ(info->GetReg().GetRegNum(), partner->Partner().GetRegNum()); 394 DCHECK(partner->IsWide()); 395 info->SetIsWide(false); 396 partner->SetIsWide(false); 397 } 398 *next_temp = next + 1; 399 return info->GetReg(); 400 } 401 next++; 402 } 403 if (required) { 404 CodegenDump(); 405 DumpRegPools(); 406 LOG(FATAL) << "No free temp registers"; 407 } 408 return RegStorage::InvalidReg(); // No register available 409} 410 411RegStorage Mir2Lir::AllocTemp(bool required) { 412 return AllocTempBody(reg_pool_->core_regs_, ®_pool_->next_core_reg_, required); 413} 414 415RegStorage Mir2Lir::AllocTempWide(bool required) { 416 RegStorage res; 417 if (reg_pool_->core64_regs_.Size() != 0) { 418 res = AllocTempBody(reg_pool_->core64_regs_, ®_pool_->next_core64_reg_, required); 419 } else { 420 RegStorage low_reg = AllocTemp(); 421 RegStorage high_reg = AllocTemp(); 422 res = RegStorage::MakeRegPair(low_reg, high_reg); 423 } 424 if (required) { 425 CheckRegStorage(res, WidenessCheck::kCheckWide, RefCheck::kIgnoreRef, FPCheck::kCheckNotFP); 426 } 427 return res; 428} 429 430RegStorage Mir2Lir::AllocTempRef(bool required) { 431 RegStorage res = AllocTempBody(*reg_pool_->ref_regs_, reg_pool_->next_ref_reg_, required); 432 if (required) { 433 DCHECK(!res.IsPair()); 434 CheckRegStorage(res, WidenessCheck::kCheckNotWide, RefCheck::kCheckRef, FPCheck::kCheckNotFP); 435 } 436 return res; 437} 438 439RegStorage Mir2Lir::AllocTempSingle(bool required) { 440 RegStorage res = AllocTempBody(reg_pool_->sp_regs_, ®_pool_->next_sp_reg_, required); 441 if (required) { 442 DCHECK(res.IsSingle()) << "Reg: 0x" << std::hex << res.GetRawBits(); 443 CheckRegStorage(res, WidenessCheck::kCheckNotWide, RefCheck::kCheckNotRef, FPCheck::kIgnoreFP); 444 } 445 return res; 446} 447 448RegStorage Mir2Lir::AllocTempDouble(bool required) { 449 RegStorage res = AllocTempBody(reg_pool_->dp_regs_, ®_pool_->next_dp_reg_, required); 450 if (required) { 451 DCHECK(res.IsDouble()) << "Reg: 0x" << std::hex << res.GetRawBits(); 452 CheckRegStorage(res, WidenessCheck::kCheckWide, RefCheck::kCheckNotRef, FPCheck::kIgnoreFP); 453 } 454 return res; 455} 456 457RegStorage Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class, bool required) { 458 DCHECK_NE(reg_class, kRefReg); // NOTE: the Dalvik width of a reference is always 32 bits. 459 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 460 return AllocTempDouble(required); 461 } 462 return AllocTempWide(required); 463} 464 465RegStorage Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class, bool required) { 466 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 467 return AllocTempSingle(required); 468 } else if (reg_class == kRefReg) { 469 return AllocTempRef(required); 470 } 471 return AllocTemp(required); 472} 473 474RegStorage Mir2Lir::FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg) { 475 RegStorage res; 476 GrowableArray<RegisterInfo*>::Iterator it(®s); 477 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 478 if ((info->SReg() == s_reg) && info->IsLive()) { 479 res = info->GetReg(); 480 break; 481 } 482 } 483 return res; 484} 485 486RegStorage Mir2Lir::AllocLiveReg(int s_reg, int reg_class, bool wide) { 487 RegStorage reg; 488 if (reg_class == kRefReg) { 489 reg = FindLiveReg(*reg_pool_->ref_regs_, s_reg); 490 CheckRegStorage(reg, WidenessCheck::kCheckNotWide, RefCheck::kCheckRef, FPCheck::kCheckNotFP); 491 } 492 if (!reg.Valid() && ((reg_class == kAnyReg) || (reg_class == kFPReg))) { 493 reg = FindLiveReg(wide ? reg_pool_->dp_regs_ : reg_pool_->sp_regs_, s_reg); 494 } 495 if (!reg.Valid() && (reg_class != kFPReg)) { 496 if (cu_->target64) { 497 reg = FindLiveReg(wide || reg_class == kRefReg ? reg_pool_->core64_regs_ : 498 reg_pool_->core_regs_, s_reg); 499 } else { 500 reg = FindLiveReg(reg_pool_->core_regs_, s_reg); 501 } 502 } 503 if (reg.Valid()) { 504 if (wide && !reg.IsFloat() && !cu_->target64) { 505 // Only allow reg pairs for core regs on 32-bit targets. 506 RegStorage high_reg = FindLiveReg(reg_pool_->core_regs_, s_reg + 1); 507 if (high_reg.Valid()) { 508 reg = RegStorage::MakeRegPair(reg, high_reg); 509 MarkWide(reg); 510 } else { 511 // Only half available. 512 reg = RegStorage::InvalidReg(); 513 } 514 } 515 if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) { 516 // Width mismatch - don't try to reuse. 517 reg = RegStorage::InvalidReg(); 518 } 519 } 520 if (reg.Valid()) { 521 if (reg.IsPair()) { 522 RegisterInfo* info_low = GetRegInfo(reg.GetLow()); 523 RegisterInfo* info_high = GetRegInfo(reg.GetHigh()); 524 if (info_low->IsTemp()) { 525 info_low->MarkInUse(); 526 } 527 if (info_high->IsTemp()) { 528 info_high->MarkInUse(); 529 } 530 } else { 531 RegisterInfo* info = GetRegInfo(reg); 532 if (info->IsTemp()) { 533 info->MarkInUse(); 534 } 535 } 536 } else { 537 // Either not found, or something didn't match up. Clobber to prevent any stale instances. 538 ClobberSReg(s_reg); 539 if (wide) { 540 ClobberSReg(s_reg + 1); 541 } 542 } 543 CheckRegStorage(reg, WidenessCheck::kIgnoreWide, 544 reg_class == kRefReg ? RefCheck::kCheckRef : RefCheck::kIgnoreRef, 545 FPCheck::kIgnoreFP); 546 return reg; 547} 548 549void Mir2Lir::FreeTemp(RegStorage reg) { 550 if (reg.IsPair()) { 551 FreeTemp(reg.GetLow()); 552 FreeTemp(reg.GetHigh()); 553 } else { 554 RegisterInfo* p = GetRegInfo(reg); 555 if (p->IsTemp()) { 556 p->MarkFree(); 557 p->SetIsWide(false); 558 p->SetPartner(reg); 559 } 560 } 561} 562 563void Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) { 564 DCHECK(rl_keep.wide); 565 DCHECK(rl_free.wide); 566 int free_low = rl_free.reg.GetLowReg(); 567 int free_high = rl_free.reg.GetHighReg(); 568 int keep_low = rl_keep.reg.GetLowReg(); 569 int keep_high = rl_keep.reg.GetHighReg(); 570 if ((free_low != keep_low) && (free_low != keep_high) && 571 (free_high != keep_low) && (free_high != keep_high)) { 572 // No overlap, free both 573 FreeTemp(rl_free.reg); 574 } 575} 576 577bool Mir2Lir::IsLive(RegStorage reg) { 578 bool res; 579 if (reg.IsPair()) { 580 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 581 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 582 DCHECK_EQ(p_lo->IsLive(), p_hi->IsLive()); 583 res = p_lo->IsLive() || p_hi->IsLive(); 584 } else { 585 RegisterInfo* p = GetRegInfo(reg); 586 res = p->IsLive(); 587 } 588 return res; 589} 590 591bool Mir2Lir::IsTemp(RegStorage reg) { 592 bool res; 593 if (reg.IsPair()) { 594 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 595 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 596 res = p_lo->IsTemp() || p_hi->IsTemp(); 597 } else { 598 RegisterInfo* p = GetRegInfo(reg); 599 res = p->IsTemp(); 600 } 601 return res; 602} 603 604bool Mir2Lir::IsPromoted(RegStorage reg) { 605 bool res; 606 if (reg.IsPair()) { 607 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 608 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 609 res = !p_lo->IsTemp() || !p_hi->IsTemp(); 610 } else { 611 RegisterInfo* p = GetRegInfo(reg); 612 res = !p->IsTemp(); 613 } 614 return res; 615} 616 617bool Mir2Lir::IsDirty(RegStorage reg) { 618 bool res; 619 if (reg.IsPair()) { 620 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 621 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 622 res = p_lo->IsDirty() || p_hi->IsDirty(); 623 } else { 624 RegisterInfo* p = GetRegInfo(reg); 625 res = p->IsDirty(); 626 } 627 return res; 628} 629 630/* 631 * Similar to AllocTemp(), but forces the allocation of a specific 632 * register. No check is made to see if the register was previously 633 * allocated. Use with caution. 634 */ 635void Mir2Lir::LockTemp(RegStorage reg) { 636 DCHECK(IsTemp(reg)); 637 if (reg.IsPair()) { 638 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 639 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 640 p_lo->MarkInUse(); 641 p_lo->MarkDead(); 642 p_hi->MarkInUse(); 643 p_hi->MarkDead(); 644 } else { 645 RegisterInfo* p = GetRegInfo(reg); 646 p->MarkInUse(); 647 p->MarkDead(); 648 } 649} 650 651void Mir2Lir::ResetDef(RegStorage reg) { 652 if (reg.IsPair()) { 653 GetRegInfo(reg.GetLow())->ResetDefBody(); 654 GetRegInfo(reg.GetHigh())->ResetDefBody(); 655 } else { 656 GetRegInfo(reg)->ResetDefBody(); 657 } 658} 659 660void Mir2Lir::NullifyRange(RegStorage reg, int s_reg) { 661 RegisterInfo* info = nullptr; 662 RegStorage rs = reg.IsPair() ? reg.GetLow() : reg; 663 if (IsTemp(rs)) { 664 info = GetRegInfo(reg); 665 } 666 if ((info != nullptr) && (info->DefStart() != nullptr) && (info->DefEnd() != nullptr)) { 667 DCHECK_EQ(info->SReg(), s_reg); // Make sure we're on the same page. 668 for (LIR* p = info->DefStart();; p = p->next) { 669 NopLIR(p); 670 if (p == info->DefEnd()) { 671 break; 672 } 673 } 674 } 675} 676 677/* 678 * Mark the beginning and end LIR of a def sequence. Note that 679 * on entry start points to the LIR prior to the beginning of the 680 * sequence. 681 */ 682void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) { 683 DCHECK(!rl.wide); 684 DCHECK(start && start->next); 685 DCHECK(finish); 686 RegisterInfo* p = GetRegInfo(rl.reg); 687 p->SetDefStart(start->next); 688 p->SetDefEnd(finish); 689} 690 691/* 692 * Mark the beginning and end LIR of a def sequence. Note that 693 * on entry start points to the LIR prior to the beginning of the 694 * sequence. 695 */ 696void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) { 697 DCHECK(rl.wide); 698 DCHECK(start && start->next); 699 DCHECK(finish); 700 RegisterInfo* p; 701 if (rl.reg.IsPair()) { 702 p = GetRegInfo(rl.reg.GetLow()); 703 ResetDef(rl.reg.GetHigh()); // Only track low of pair 704 } else { 705 p = GetRegInfo(rl.reg); 706 } 707 p->SetDefStart(start->next); 708 p->SetDefEnd(finish); 709} 710 711void Mir2Lir::ResetDefLoc(RegLocation rl) { 712 DCHECK(!rl.wide); 713 if (IsTemp(rl.reg) && !(cu_->disable_opt & (1 << kSuppressLoads))) { 714 NullifyRange(rl.reg, rl.s_reg_low); 715 } 716 ResetDef(rl.reg); 717} 718 719void Mir2Lir::ResetDefLocWide(RegLocation rl) { 720 DCHECK(rl.wide); 721 // If pair, only track low reg of pair. 722 RegStorage rs = rl.reg.IsPair() ? rl.reg.GetLow() : rl.reg; 723 if (IsTemp(rs) && !(cu_->disable_opt & (1 << kSuppressLoads))) { 724 NullifyRange(rs, rl.s_reg_low); 725 } 726 ResetDef(rs); 727} 728 729void Mir2Lir::ResetDefTracking() { 730 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); 731 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { 732 info->ResetDefBody(); 733 } 734} 735 736void Mir2Lir::ClobberAllTemps() { 737 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); 738 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { 739 ClobberBody(info); 740 } 741} 742 743void Mir2Lir::FlushRegWide(RegStorage reg) { 744 if (reg.IsPair()) { 745 RegisterInfo* info1 = GetRegInfo(reg.GetLow()); 746 RegisterInfo* info2 = GetRegInfo(reg.GetHigh()); 747 DCHECK(info1 && info2 && info1->IsWide() && info2->IsWide() && 748 (info1->Partner().ExactlyEquals(info2->GetReg())) && 749 (info2->Partner().ExactlyEquals(info1->GetReg()))); 750 if ((info1->IsLive() && info1->IsDirty()) || (info2->IsLive() && info2->IsDirty())) { 751 if (!(info1->IsTemp() && info2->IsTemp())) { 752 /* Should not happen. If it does, there's a problem in eval_loc */ 753 LOG(FATAL) << "Long half-temp, half-promoted"; 754 } 755 756 info1->SetIsDirty(false); 757 info2->SetIsDirty(false); 758 if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) { 759 info1 = info2; 760 } 761 int v_reg = mir_graph_->SRegToVReg(info1->SReg()); 762 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 763 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); 764 } 765 } else { 766 RegisterInfo* info = GetRegInfo(reg); 767 if (info->IsLive() && info->IsDirty()) { 768 info->SetIsDirty(false); 769 int v_reg = mir_graph_->SRegToVReg(info->SReg()); 770 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 771 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); 772 } 773 } 774} 775 776void Mir2Lir::FlushReg(RegStorage reg) { 777 DCHECK(!reg.IsPair()); 778 RegisterInfo* info = GetRegInfo(reg); 779 if (info->IsLive() && info->IsDirty()) { 780 info->SetIsDirty(false); 781 int v_reg = mir_graph_->SRegToVReg(info->SReg()); 782 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 783 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, kWord, kNotVolatile); 784 } 785} 786 787void Mir2Lir::FlushSpecificReg(RegisterInfo* info) { 788 if (info->IsWide()) { 789 FlushRegWide(info->GetReg()); 790 } else { 791 FlushReg(info->GetReg()); 792 } 793} 794 795void Mir2Lir::FlushAllRegs() { 796 GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_); 797 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 798 if (info->IsDirty() && info->IsLive()) { 799 FlushSpecificReg(info); 800 } 801 info->MarkDead(); 802 info->SetIsWide(false); 803 } 804} 805 806 807bool Mir2Lir::RegClassMatches(int reg_class, RegStorage reg) { 808 if (reg_class == kAnyReg) { 809 return true; 810 } else if ((reg_class == kCoreReg) || (reg_class == kRefReg)) { 811 /* 812 * For this purpose, consider Core and Ref to be the same class. We aren't dealing 813 * with width here - that should be checked at a higher level (if needed). 814 */ 815 return !reg.IsFloat(); 816 } else { 817 return reg.IsFloat(); 818 } 819} 820 821void Mir2Lir::MarkLive(RegLocation loc) { 822 RegStorage reg = loc.reg; 823 if (!IsTemp(reg)) { 824 return; 825 } 826 int s_reg = loc.s_reg_low; 827 if (s_reg == INVALID_SREG) { 828 // Can't be live if no associated sreg. 829 if (reg.IsPair()) { 830 GetRegInfo(reg.GetLow())->MarkDead(); 831 GetRegInfo(reg.GetHigh())->MarkDead(); 832 } else { 833 GetRegInfo(reg)->MarkDead(); 834 } 835 } else { 836 if (reg.IsPair()) { 837 RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); 838 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); 839 if (info_lo->IsLive() && (info_lo->SReg() == s_reg) && info_hi->IsLive() && 840 (info_hi->SReg() == s_reg)) { 841 return; // Already live. 842 } 843 ClobberSReg(s_reg); 844 ClobberSReg(s_reg + 1); 845 info_lo->MarkLive(s_reg); 846 info_hi->MarkLive(s_reg + 1); 847 } else { 848 RegisterInfo* info = GetRegInfo(reg); 849 if (info->IsLive() && (info->SReg() == s_reg)) { 850 return; // Already live. 851 } 852 ClobberSReg(s_reg); 853 if (loc.wide) { 854 ClobberSReg(s_reg + 1); 855 } 856 info->MarkLive(s_reg); 857 } 858 if (loc.wide) { 859 MarkWide(reg); 860 } else { 861 MarkNarrow(reg); 862 } 863 } 864} 865 866void Mir2Lir::MarkTemp(RegStorage reg) { 867 DCHECK(!reg.IsPair()); 868 RegisterInfo* info = GetRegInfo(reg); 869 tempreg_info_.Insert(info); 870 info->SetIsTemp(true); 871} 872 873void Mir2Lir::UnmarkTemp(RegStorage reg) { 874 DCHECK(!reg.IsPair()); 875 RegisterInfo* info = GetRegInfo(reg); 876 tempreg_info_.Delete(info); 877 info->SetIsTemp(false); 878} 879 880void Mir2Lir::MarkWide(RegStorage reg) { 881 if (reg.IsPair()) { 882 RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); 883 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); 884 // Unpair any old partners. 885 if (info_lo->IsWide() && info_lo->Partner().NotExactlyEquals(info_hi->GetReg())) { 886 GetRegInfo(info_lo->Partner())->SetIsWide(false); 887 } 888 if (info_hi->IsWide() && info_hi->Partner().NotExactlyEquals(info_lo->GetReg())) { 889 GetRegInfo(info_hi->Partner())->SetIsWide(false); 890 } 891 info_lo->SetIsWide(true); 892 info_hi->SetIsWide(true); 893 info_lo->SetPartner(reg.GetHigh()); 894 info_hi->SetPartner(reg.GetLow()); 895 } else { 896 RegisterInfo* info = GetRegInfo(reg); 897 info->SetIsWide(true); 898 info->SetPartner(reg); 899 } 900} 901 902void Mir2Lir::MarkNarrow(RegStorage reg) { 903 DCHECK(!reg.IsPair()); 904 RegisterInfo* info = GetRegInfo(reg); 905 info->SetIsWide(false); 906 info->SetPartner(reg); 907} 908 909void Mir2Lir::MarkClean(RegLocation loc) { 910 if (loc.reg.IsPair()) { 911 RegisterInfo* info = GetRegInfo(loc.reg.GetLow()); 912 info->SetIsDirty(false); 913 info = GetRegInfo(loc.reg.GetHigh()); 914 info->SetIsDirty(false); 915 } else { 916 RegisterInfo* info = GetRegInfo(loc.reg); 917 info->SetIsDirty(false); 918 } 919} 920 921// FIXME: need to verify rules/assumptions about how wide values are treated in 64BitSolos. 922void Mir2Lir::MarkDirty(RegLocation loc) { 923 if (loc.home) { 924 // If already home, can't be dirty 925 return; 926 } 927 if (loc.reg.IsPair()) { 928 RegisterInfo* info = GetRegInfo(loc.reg.GetLow()); 929 info->SetIsDirty(true); 930 info = GetRegInfo(loc.reg.GetHigh()); 931 info->SetIsDirty(true); 932 } else { 933 RegisterInfo* info = GetRegInfo(loc.reg); 934 info->SetIsDirty(true); 935 } 936} 937 938void Mir2Lir::MarkInUse(RegStorage reg) { 939 if (reg.IsPair()) { 940 GetRegInfo(reg.GetLow())->MarkInUse(); 941 GetRegInfo(reg.GetHigh())->MarkInUse(); 942 } else { 943 GetRegInfo(reg)->MarkInUse(); 944 } 945} 946 947bool Mir2Lir::CheckCorePoolSanity() { 948 GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_); 949 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 950 if (info->IsTemp() && info->IsLive() && info->IsWide()) { 951 RegStorage my_reg = info->GetReg(); 952 int my_sreg = info->SReg(); 953 RegStorage partner_reg = info->Partner(); 954 RegisterInfo* partner = GetRegInfo(partner_reg); 955 DCHECK(partner != NULL); 956 DCHECK(partner->IsWide()); 957 DCHECK_EQ(my_reg.GetReg(), partner->Partner().GetReg()); 958 DCHECK(partner->IsLive()); 959 int partner_sreg = partner->SReg(); 960 if (my_sreg == INVALID_SREG) { 961 DCHECK_EQ(partner_sreg, INVALID_SREG); 962 } else { 963 int diff = my_sreg - partner_sreg; 964 DCHECK((diff == 0) || (diff == -1) || (diff == 1)); 965 } 966 } 967 if (info->Master() != info) { 968 // Aliased. 969 if (info->IsLive() && (info->SReg() != INVALID_SREG)) { 970 // If I'm live, master should not be live, but should show liveness in alias set. 971 DCHECK_EQ(info->Master()->SReg(), INVALID_SREG); 972 DCHECK(!info->Master()->IsDead()); 973 } 974// TODO: Add checks in !info->IsDead() case to ensure every live bit is owned by exactly 1 reg. 975 } 976 if (info->IsAliased()) { 977 // Has child aliases. 978 DCHECK_EQ(info->Master(), info); 979 if (info->IsLive() && (info->SReg() != INVALID_SREG)) { 980 // Master live, no child should be dead - all should show liveness in set. 981 for (RegisterInfo* p = info->GetAliasChain(); p != nullptr; p = p->GetAliasChain()) { 982 DCHECK(!p->IsDead()); 983 DCHECK_EQ(p->SReg(), INVALID_SREG); 984 } 985 } else if (!info->IsDead()) { 986 // Master not live, one or more aliases must be. 987 bool live_alias = false; 988 for (RegisterInfo* p = info->GetAliasChain(); p != nullptr; p = p->GetAliasChain()) { 989 live_alias |= p->IsLive(); 990 } 991 DCHECK(live_alias); 992 } 993 } 994 if (info->IsLive() && (info->SReg() == INVALID_SREG)) { 995 // If not fully live, should have INVALID_SREG and def's should be null. 996 DCHECK(info->DefStart() == nullptr); 997 DCHECK(info->DefEnd() == nullptr); 998 } 999 } 1000 return true; 1001} 1002 1003/* 1004 * Return an updated location record with current in-register status. 1005 * If the value lives in live temps, reflect that fact. No code 1006 * is generated. If the live value is part of an older pair, 1007 * clobber both low and high. 1008 * TUNING: clobbering both is a bit heavy-handed, but the alternative 1009 * is a bit complex when dealing with FP regs. Examine code to see 1010 * if it's worthwhile trying to be more clever here. 1011 */ 1012RegLocation Mir2Lir::UpdateLoc(RegLocation loc) { 1013 DCHECK(!loc.wide); 1014 DCHECK(CheckCorePoolSanity()); 1015 if (loc.location != kLocPhysReg) { 1016 DCHECK((loc.location == kLocDalvikFrame) || 1017 (loc.location == kLocCompilerTemp)); 1018 RegStorage reg = AllocLiveReg(loc.s_reg_low, loc.ref ? kRefReg : kAnyReg, false); 1019 if (reg.Valid()) { 1020 bool match = true; 1021 RegisterInfo* info = GetRegInfo(reg); 1022 match &= !reg.IsPair(); 1023 match &= !info->IsWide(); 1024 if (match) { 1025 loc.location = kLocPhysReg; 1026 loc.reg = reg; 1027 } else { 1028 Clobber(reg); 1029 FreeTemp(reg); 1030 } 1031 } 1032 CheckRegLocation(loc); 1033 } 1034 return loc; 1035} 1036 1037RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) { 1038 DCHECK(loc.wide); 1039 DCHECK(CheckCorePoolSanity()); 1040 if (loc.location != kLocPhysReg) { 1041 DCHECK((loc.location == kLocDalvikFrame) || 1042 (loc.location == kLocCompilerTemp)); 1043 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true); 1044 if (reg.Valid()) { 1045 bool match = true; 1046 if (reg.IsPair()) { 1047 // If we've got a register pair, make sure that it was last used as the same pair. 1048 RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); 1049 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); 1050 match &= info_lo->IsWide(); 1051 match &= info_hi->IsWide(); 1052 match &= (info_lo->Partner().ExactlyEquals(info_hi->GetReg())); 1053 match &= (info_hi->Partner().ExactlyEquals(info_lo->GetReg())); 1054 } else { 1055 RegisterInfo* info = GetRegInfo(reg); 1056 match &= info->IsWide(); 1057 match &= (info->GetReg().ExactlyEquals(info->Partner())); 1058 } 1059 if (match) { 1060 loc.location = kLocPhysReg; 1061 loc.reg = reg; 1062 } else { 1063 Clobber(reg); 1064 FreeTemp(reg); 1065 } 1066 } 1067 CheckRegLocation(loc); 1068 } 1069 return loc; 1070} 1071 1072/* For use in cases we don't know (or care) width */ 1073RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) { 1074 if (loc.wide) 1075 return UpdateLocWide(loc); 1076 else 1077 return UpdateLoc(loc); 1078} 1079 1080RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { 1081 DCHECK(loc.wide); 1082 1083 loc = UpdateLocWide(loc); 1084 1085 /* If already in registers, we can assume proper form. Right reg class? */ 1086 if (loc.location == kLocPhysReg) { 1087 if (!RegClassMatches(reg_class, loc.reg)) { 1088 // Wrong register class. Reallocate and transfer ownership. 1089 RegStorage new_regs = AllocTypedTempWide(loc.fp, reg_class); 1090 // Clobber the old regs. 1091 Clobber(loc.reg); 1092 // ...and mark the new ones live. 1093 loc.reg = new_regs; 1094 MarkWide(loc.reg); 1095 MarkLive(loc); 1096 } 1097 CheckRegLocation(loc); 1098 return loc; 1099 } 1100 1101 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 1102 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 1103 1104 loc.reg = AllocTypedTempWide(loc.fp, reg_class); 1105 MarkWide(loc.reg); 1106 1107 if (update) { 1108 loc.location = kLocPhysReg; 1109 MarkLive(loc); 1110 } 1111 CheckRegLocation(loc); 1112 return loc; 1113} 1114 1115RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { 1116 // Narrow reg_class if the loc is a ref. 1117 if (loc.ref && reg_class == kAnyReg) { 1118 reg_class = kRefReg; 1119 } 1120 1121 if (loc.wide) { 1122 return EvalLocWide(loc, reg_class, update); 1123 } 1124 1125 loc = UpdateLoc(loc); 1126 1127 if (loc.location == kLocPhysReg) { 1128 if (!RegClassMatches(reg_class, loc.reg)) { 1129 // Wrong register class. Reallocate and transfer ownership. 1130 RegStorage new_reg = AllocTypedTemp(loc.fp, reg_class); 1131 // Clobber the old reg. 1132 Clobber(loc.reg); 1133 // ...and mark the new one live. 1134 loc.reg = new_reg; 1135 MarkLive(loc); 1136 } 1137 CheckRegLocation(loc); 1138 return loc; 1139 } 1140 1141 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 1142 1143 loc.reg = AllocTypedTemp(loc.fp, reg_class); 1144 CheckRegLocation(loc); 1145 1146 if (update) { 1147 loc.location = kLocPhysReg; 1148 MarkLive(loc); 1149 } 1150 CheckRegLocation(loc); 1151 return loc; 1152} 1153 1154/* USE SSA names to count references of base Dalvik v_regs. */ 1155void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs) { 1156 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { 1157 RegLocation loc = mir_graph_->reg_location_[i]; 1158 RefCounts* counts = loc.fp ? fp_counts : core_counts; 1159 int p_map_idx = SRegToPMap(loc.s_reg_low); 1160 int use_count = mir_graph_->GetUseCount(i); 1161 if (loc.fp) { 1162 if (loc.wide) { 1163 if (WideFPRsAreAliases()) { 1164 // Floats and doubles can be counted together. 1165 counts[p_map_idx].count += use_count; 1166 } else { 1167 // Treat doubles as a unit, using upper half of fp_counts array. 1168 counts[p_map_idx + num_regs].count += use_count; 1169 } 1170 i++; 1171 } else { 1172 counts[p_map_idx].count += use_count; 1173 } 1174 } else { 1175 if (loc.wide && WideGPRsAreAliases()) { 1176 i++; 1177 } 1178 if (!IsInexpensiveConstant(loc)) { 1179 counts[p_map_idx].count += use_count; 1180 } 1181 } 1182 } 1183} 1184 1185/* qsort callback function, sort descending */ 1186static int SortCounts(const void *val1, const void *val2) { 1187 const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1); 1188 const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2); 1189 // Note that we fall back to sorting on reg so we get stable output on differing qsort 1190 // implementations (such as on host and target or between local host and build servers). 1191 // Note also that if a wide val1 and a non-wide val2 have the same count, then val1 always 1192 // ``loses'' (as STARTING_WIDE_SREG is or-ed in val1->s_reg). 1193 return (op1->count == op2->count) 1194 ? (op1->s_reg - op2->s_reg) 1195 : (op1->count < op2->count ? 1 : -1); 1196} 1197 1198void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) { 1199 LOG(INFO) << msg; 1200 for (int i = 0; i < size; i++) { 1201 if ((arr[i].s_reg & STARTING_WIDE_SREG) != 0) { 1202 LOG(INFO) << "s_reg[64_" << (arr[i].s_reg & ~STARTING_WIDE_SREG) << "]: " << arr[i].count; 1203 } else { 1204 LOG(INFO) << "s_reg[32_" << arr[i].s_reg << "]: " << arr[i].count; 1205 } 1206 } 1207} 1208 1209/* 1210 * Note: some portions of this code required even if the kPromoteRegs 1211 * optimization is disabled. 1212 */ 1213void Mir2Lir::DoPromotion() { 1214 int dalvik_regs = cu_->num_dalvik_registers; 1215 int num_regs = dalvik_regs + mir_graph_->GetNumUsedCompilerTemps(); 1216 const int promotion_threshold = 1; 1217 // Allocate the promotion map - one entry for each Dalvik vReg or compiler temp 1218 promotion_map_ = static_cast<PromotionMap*> 1219 (arena_->Alloc(num_regs * sizeof(promotion_map_[0]), kArenaAllocRegAlloc)); 1220 1221 // Allow target code to add any special registers 1222 AdjustSpillMask(); 1223 1224 /* 1225 * Simple register promotion. Just do a static count of the uses 1226 * of Dalvik registers. Note that we examine the SSA names, but 1227 * count based on original Dalvik register name. Count refs 1228 * separately based on type in order to give allocation 1229 * preference to fp doubles - which must be allocated sequential 1230 * physical single fp registers starting with an even-numbered 1231 * reg. 1232 * TUNING: replace with linear scan once we have the ability 1233 * to describe register live ranges for GC. 1234 */ 1235 size_t core_reg_count_size = WideGPRsAreAliases() ? num_regs : num_regs * 2; 1236 size_t fp_reg_count_size = WideFPRsAreAliases() ? num_regs : num_regs * 2; 1237 RefCounts *core_regs = 1238 static_cast<RefCounts*>(arena_->Alloc(sizeof(RefCounts) * core_reg_count_size, 1239 kArenaAllocRegAlloc)); 1240 RefCounts *fp_regs = 1241 static_cast<RefCounts *>(arena_->Alloc(sizeof(RefCounts) * fp_reg_count_size, 1242 kArenaAllocRegAlloc)); 1243 // Set ssa names for original Dalvik registers 1244 for (int i = 0; i < dalvik_regs; i++) { 1245 core_regs[i].s_reg = fp_regs[i].s_reg = i; 1246 } 1247 1248 // Set ssa names for compiler temporaries 1249 for (unsigned int ct_idx = 0; ct_idx < mir_graph_->GetNumUsedCompilerTemps(); ct_idx++) { 1250 CompilerTemp* ct = mir_graph_->GetCompilerTemp(ct_idx); 1251 core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; 1252 fp_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; 1253 } 1254 1255 // Duplicate in upper half to represent possible wide starting sregs. 1256 for (size_t i = num_regs; i < fp_reg_count_size; i++) { 1257 fp_regs[i].s_reg = fp_regs[i - num_regs].s_reg | STARTING_WIDE_SREG; 1258 } 1259 for (size_t i = num_regs; i < core_reg_count_size; i++) { 1260 core_regs[i].s_reg = core_regs[i - num_regs].s_reg | STARTING_WIDE_SREG; 1261 } 1262 1263 // Sum use counts of SSA regs by original Dalvik vreg. 1264 CountRefs(core_regs, fp_regs, num_regs); 1265 1266 // Sort the count arrays 1267 qsort(core_regs, core_reg_count_size, sizeof(RefCounts), SortCounts); 1268 qsort(fp_regs, fp_reg_count_size, sizeof(RefCounts), SortCounts); 1269 1270 if (cu_->verbose) { 1271 DumpCounts(core_regs, core_reg_count_size, "Core regs after sort"); 1272 DumpCounts(fp_regs, fp_reg_count_size, "Fp regs after sort"); 1273 } 1274 1275 if (!(cu_->disable_opt & (1 << kPromoteRegs))) { 1276 // Promote fp regs 1277 for (size_t i = 0; (i < fp_reg_count_size) && (fp_regs[i].count >= promotion_threshold); i++) { 1278 int low_sreg = fp_regs[i].s_reg & ~STARTING_WIDE_SREG; 1279 size_t p_map_idx = SRegToPMap(low_sreg); 1280 RegStorage reg = RegStorage::InvalidReg(); 1281 if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) { 1282 // TODO: break out the Thumb2-specific code. 1283 if (cu_->instruction_set == kThumb2) { 1284 bool wide = fp_regs[i].s_reg & STARTING_WIDE_SREG; 1285 if (wide) { 1286 if (promotion_map_[p_map_idx + 1].fp_location != kLocPhysReg) { 1287 // Ignore result - if can't alloc double may still be able to alloc singles. 1288 AllocPreservedDouble(low_sreg); 1289 } 1290 // Continue regardless of success - might still be able to grab a single. 1291 continue; 1292 } else { 1293 reg = AllocPreservedSingle(low_sreg); 1294 } 1295 } else { 1296 reg = AllocPreservedFpReg(low_sreg); 1297 } 1298 if (!reg.Valid()) { 1299 break; // No more left 1300 } 1301 } 1302 } 1303 1304 // Promote core regs 1305 for (size_t i = 0; (i < core_reg_count_size) && 1306 (core_regs[i].count >= promotion_threshold); i++) { 1307 int low_sreg = core_regs[i].s_reg & ~STARTING_WIDE_SREG; 1308 size_t p_map_idx = SRegToPMap(low_sreg); 1309 if (promotion_map_[p_map_idx].core_location != kLocPhysReg) { 1310 RegStorage reg = AllocPreservedCoreReg(low_sreg); 1311 if (!reg.Valid()) { 1312 break; // No more left 1313 } 1314 } 1315 } 1316 } 1317 1318 // Now, update SSA names to new home locations 1319 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { 1320 RegLocation *curr = &mir_graph_->reg_location_[i]; 1321 int p_map_idx = SRegToPMap(curr->s_reg_low); 1322 int reg_num = curr->fp ? promotion_map_[p_map_idx].fp_reg : promotion_map_[p_map_idx].core_reg; 1323 bool wide = curr->wide || (cu_->target64 && curr->ref); 1324 RegStorage reg = RegStorage::InvalidReg(); 1325 if (curr->fp && promotion_map_[p_map_idx].fp_location == kLocPhysReg) { 1326 if (wide && cu_->instruction_set == kThumb2) { 1327 if (promotion_map_[p_map_idx + 1].fp_location == kLocPhysReg) { 1328 int high_reg = promotion_map_[p_map_idx+1].fp_reg; 1329 // TODO: move target-specific restrictions out of here. 1330 if (((reg_num & 0x1) == 0) && ((reg_num + 1) == high_reg)) { 1331 reg = RegStorage::FloatSolo64(RegStorage::RegNum(reg_num) >> 1); 1332 } 1333 } 1334 } else { 1335 reg = wide ? RegStorage::FloatSolo64(reg_num) : RegStorage::FloatSolo32(reg_num); 1336 } 1337 } else if (!curr->fp && promotion_map_[p_map_idx].core_location == kLocPhysReg) { 1338 if (wide && !cu_->target64) { 1339 if (promotion_map_[p_map_idx + 1].core_location == kLocPhysReg) { 1340 int high_reg = promotion_map_[p_map_idx+1].core_reg; 1341 reg = RegStorage(RegStorage::k64BitPair, reg_num, high_reg); 1342 } 1343 } else { 1344 reg = wide ? RegStorage::Solo64(reg_num) : RegStorage::Solo32(reg_num); 1345 } 1346 } 1347 if (reg.Valid()) { 1348 curr->reg = reg; 1349 curr->location = kLocPhysReg; 1350 curr->home = true; 1351 } 1352 } 1353 if (cu_->verbose) { 1354 DumpPromotionMap(); 1355 } 1356} 1357 1358/* Returns sp-relative offset in bytes for a VReg */ 1359int Mir2Lir::VRegOffset(int v_reg) { 1360 return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_, 1361 fp_spill_mask_, frame_size_, v_reg, 1362 cu_->instruction_set); 1363} 1364 1365/* Returns sp-relative offset in bytes for a SReg */ 1366int Mir2Lir::SRegOffset(int s_reg) { 1367 return VRegOffset(mir_graph_->SRegToVReg(s_reg)); 1368} 1369 1370/* Mark register usage state and return long retloc */ 1371RegLocation Mir2Lir::GetReturnWide(RegisterClass reg_class) { 1372 RegLocation res; 1373 switch (reg_class) { 1374 case kRefReg: LOG(FATAL); break; 1375 case kFPReg: res = LocCReturnDouble(); break; 1376 default: res = LocCReturnWide(); break; 1377 } 1378 Clobber(res.reg); 1379 LockTemp(res.reg); 1380 MarkWide(res.reg); 1381 CheckRegLocation(res); 1382 return res; 1383} 1384 1385RegLocation Mir2Lir::GetReturn(RegisterClass reg_class) { 1386 RegLocation res; 1387 switch (reg_class) { 1388 case kRefReg: res = LocCReturnRef(); break; 1389 case kFPReg: res = LocCReturnFloat(); break; 1390 default: res = LocCReturn(); break; 1391 } 1392 Clobber(res.reg); 1393 if (cu_->instruction_set == kMips) { 1394 MarkInUse(res.reg); 1395 } else { 1396 LockTemp(res.reg); 1397 } 1398 CheckRegLocation(res); 1399 return res; 1400} 1401 1402void Mir2Lir::SimpleRegAlloc() { 1403 DoPromotion(); 1404 1405 if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) { 1406 LOG(INFO) << "After Promotion"; 1407 mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs()); 1408 } 1409 1410 /* Set the frame size */ 1411 frame_size_ = ComputeFrameSize(); 1412} 1413 1414/* 1415 * Get the "real" sreg number associated with an s_reg slot. In general, 1416 * s_reg values passed through codegen are the SSA names created by 1417 * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location 1418 * array. However, renaming is accomplished by simply replacing RegLocation 1419 * entries in the reglocation[] array. Therefore, when location 1420 * records for operands are first created, we need to ask the locRecord 1421 * identified by the dataflow pass what it's new name is. 1422 */ 1423int Mir2Lir::GetSRegHi(int lowSreg) { 1424 return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; 1425} 1426 1427bool Mir2Lir::LiveOut(int s_reg) { 1428 // For now. 1429 return true; 1430} 1431 1432} // namespace art 1433