assemble_x86.cc revision 69dfe51b684dd9d510dbcb63295fe180f998efde
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "x86_lir.h" 20 21namespace art { 22 23#define MAX_ASSEMBLER_RETRIES 50 24 25const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { 26 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4, false }, "data", "0x!0d" }, 27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0, false }, "int 3", "" }, 28 { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0, false }, "nop", "" }, 29 30#define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ 31 rm8_r8, rm32_r32, \ 32 r8_rm8, r32_rm32, \ 33 ax8_i8, ax32_i32, \ 34 rm8_i8, rm8_i8_modrm, \ 35 rm32_i32, rm32_i32_modrm, \ 36 rm32_i8, rm32_i8_modrm) \ 37{ kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8MR", "[!0r+!1d],!2r" }, \ 38{ kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true}, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 39{ kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \ 40{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RR", "!0r,!1r" }, \ 41{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RM", "!0r,[!1r+!2d]" }, \ 42{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 43{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RT", "!0r,fs:[!1d]" }, \ 44{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1, true }, #opname "8RI", "!0r,!1d" }, \ 45{ kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ 46{ kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 47{ kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8TI", "fs:[!0d],!1d" }, \ 48 \ 49{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16MR", "[!0r+!1d],!2r" }, \ 50{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 51{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \ 52{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RR", "!0r,!1r" }, \ 53{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RM", "!0r,[!1r+!2d]" }, \ 54{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 55{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RT", "!0r,fs:[!1d]" }, \ 56{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2, false }, #opname "16RI", "!0r,!1d" }, \ 57{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ 58{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 59{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16TI", "fs:[!0d],!1d" }, \ 60{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16RI8", "!0r,!1d" }, \ 61{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16MI8", "[!0r+!1d],!2d" }, \ 62{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 63{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16TI8", "fs:[!0d],!1d" }, \ 64 \ 65{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32MR", "[!0r+!1d],!2r" }, \ 66{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 67{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \ 68{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RR", "!0r,!1r" }, \ 69{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RM", "!0r,[!1r+!2d]" }, \ 70{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 71{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RT", "!0r,fs:[!1d]" }, \ 72{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "32RI", "!0r,!1d" }, \ 73{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ 74{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 75{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32TI", "fs:[!0d],!1d" }, \ 76{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32RI8", "!0r,!1d" }, \ 77{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32MI8", "[!0r+!1d],!2d" }, \ 78{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 79{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32TI8", "fs:[!0d],!1d" }, \ 80 \ 81{ kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64MR", "[!0r+!1d],!2r" }, \ 82{ kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 83{ kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \ 84{ kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RR", "!0r,!1r" }, \ 85{ kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RM", "!0r,[!1r+!2d]" }, \ 86{ kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 87{ kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RT", "!0r,fs:[!1d]" }, \ 88{ kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "64RI", "!0r,!1d" }, \ 89{ kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ 90{ kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 91{ kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64TI", "fs:[!0d],!1d" }, \ 92{ kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64RI8", "!0r,!1d" }, \ 93{ kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64MI8", "[!0r+!1d],!2d" }, \ 94{ kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 95{ kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64TI8", "fs:[!0d],!1d" } 96 97ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, 98 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, 99 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, 100 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, 101 0x80, 0x0 /* RegMem8/imm8 */, 102 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), 103ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, 104 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, 105 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, 106 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, 107 0x80, 0x1 /* RegMem8/imm8 */, 108 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), 109ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 110 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, 111 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, 112 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, 113 0x80, 0x2 /* RegMem8/imm8 */, 114 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), 115ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 116 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, 117 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, 118 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, 119 0x80, 0x3 /* RegMem8/imm8 */, 120 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), 121ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, 122 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, 123 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, 124 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, 125 0x80, 0x4 /* RegMem8/imm8 */, 126 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), 127ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, 128 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, 129 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, 130 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, 131 0x80, 0x5 /* RegMem8/imm8 */, 132 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), 133ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, 134 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, 135 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, 136 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, 137 0x80, 0x6 /* RegMem8/imm8 */, 138 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), 139ENCODING_MAP(Cmp, IS_LOAD, 0, 0, 140 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, 141 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, 142 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, 143 0x80, 0x7 /* RegMem8/imm8 */, 144 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), 145#undef ENCODING_MAP 146 147 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RRI", "!0r,!1r,!2d" }, 148 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, 149 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 150 151 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RRI", "!0r,!1r,!2d" }, 152 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, 153 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 154 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RRI8", "!0r,!1r,!2d" }, 155 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, 156 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 157 158 { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RRI", "!0r,!1r,!2d" }, 159 { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" }, 160 { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 161 { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RRI8", "!0r,!1r,!2d" }, 162 { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" }, 163 { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 164 165 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8MR", "[!0r+!1d],!2r" }, 166 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, 167 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8TR", "fs:[!0d],!1r" }, 168 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RR", "!0r,!1r" }, 169 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RM", "!0r,[!1r+!2d]" }, 170 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 171 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" }, 172 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" }, 173 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8MI", "[!0r+!1d],!2d" }, 174 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 175 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8TI", "fs:[!0d],!1d" }, 176 177 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16MR", "[!0r+!1d],!2r" }, 178 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, 179 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0, false }, "Mov16TR", "fs:[!0d],!1r" }, 180 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RR", "!0r,!1r" }, 181 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RM", "!0r,[!1r+!2d]" }, 182 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 183 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" }, 184 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2, false }, "Mov16RI", "!0r,!1d" }, 185 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16MI", "[!0r+!1d],!2d" }, 186 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 187 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16TI", "fs:[!0d],!1d" }, 188 189 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" }, 190 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, 191 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" }, 192 { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" }, 193 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" }, 194 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 195 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RT", "!0r,fs:[!1d]" }, 196 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "Mov32RI", "!0r,!1d" }, 197 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32MI", "[!0r+!1d],!2d" }, 198 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 199 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32TI", "fs:[!0d],!1d" }, 200 201 { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RM", "!0r,[!1r+!2d]" }, 202 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 203 204 { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" }, 205 { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" }, 206 { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" }, 207 { kX86Mov64RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" }, 208 { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" }, 209 { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 210 { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" }, 211 { kX86Mov64RI32, kRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64RI32", "!0r,!1d" }, 212 { kX86Mov64RI64, kMovRegQuadImm, IS_TERTIARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI64", "!0r,!1q" }, 213 { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" }, 214 { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" }, 215 { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" }, 216 217 { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RM", "!0r,[!1r+!2d]" }, 218 { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 219 220 { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RR", "!2c !0r,!1r" }, 221 { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RR", "!2c !0r,!1r" }, 222 223 { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" }, 224 { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" }, 225 226#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ 227{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8RI", "!0r,!1d" }, \ 228{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ 229{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 230{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8RC", "!0r,cl" }, \ 231{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8MC", "[!0r+!1d],cl" }, \ 232{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 233 \ 234{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16RI", "!0r,!1d" }, \ 235{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ 236{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 237{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16RC", "!0r,cl" }, \ 238{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16MC", "[!0r+!1d],cl" }, \ 239{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 240 \ 241{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32RI", "!0r,!1d" }, \ 242{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ 243{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 244{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32RC", "!0r,cl" }, \ 245{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32MC", "[!0r+!1d],cl" }, \ 246{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 247 \ 248{ kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64RI", "!0r,!1d" }, \ 249{ kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ 250{ kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 251{ kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64RC", "!0r,cl" }, \ 252{ kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64MC", "[!0r+!1d],cl" }, \ 253{ kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" } 254 255 SHIFT_ENCODING_MAP(Rol, 0x0), 256 SHIFT_ENCODING_MAP(Ror, 0x1), 257 SHIFT_ENCODING_MAP(Rcl, 0x2), 258 SHIFT_ENCODING_MAP(Rcr, 0x3), 259 SHIFT_ENCODING_MAP(Sal, 0x4), 260 SHIFT_ENCODING_MAP(Shr, 0x5), 261 SHIFT_ENCODING_MAP(Sar, 0x7), 262#undef SHIFT_ENCODING_MAP 263 264 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0, false }, "Cmc", "" }, 265 { kX86Shld32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32RRI", "!0r,!1r,!2d" }, 266 { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32MRI", "[!0r+!1d],!2r,!3d" }, 267 { kX86Shrd32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32RRI", "!0r,!1r,!2d" }, 268 { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32MRI", "[!0r+!1d],!2r,!3d" }, 269 { kX86Shld64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64RRI", "!0r,!1r,!2d" }, 270 { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64MRI", "[!0r+!1d],!2r,!3d" }, 271 { kX86Shrd64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64RRI", "!0r,!1r,!2d" }, 272 { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64MRI", "[!0r+!1d],!2r,!3d" }, 273 274 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8RI", "!0r,!1d" }, 275 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8MI", "[!0r+!1d],!2d" }, 276 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 277 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16RI", "!0r,!1d" }, 278 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16MI", "[!0r+!1d],!2d" }, 279 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 280 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32RI", "!0r,!1d" }, 281 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32MI", "[!0r+!1d],!2d" }, 282 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 283 { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64RI", "!0r,!1d" }, 284 { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64MI", "[!0r+!1d],!2d" }, 285 { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" }, 286 287 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RR", "!0r,!1r" }, 288 { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test64RR", "!0r,!1r" }, 289 { kX86Test32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RM", "!0r,[!1r+!1d]" }, 290 291#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ 292 reg, reg_kind, reg_flags, \ 293 mem, mem_kind, mem_flags, \ 294 arr, arr_kind, arr_flags, imm, \ 295 b_flags, hw_flags, w_flags, \ 296 b_format, hw_format, w_format) \ 297{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \ 298{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \ 299{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \ 300{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \ 301{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \ 302{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \ 303{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \ 304{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \ 305{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \ 306{ kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \ 307{ kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \ 308{ kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" } 309 310 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 311 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 312 313 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 314 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 315 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 316 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 317#undef UNARY_ENCODING_MAP 318 319 { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cdq", "" }, 320 { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cqo", "" }, 321 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap32R", "!0r" }, 322 { kX86Bswap64R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { REX_W, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap64R", "!0r" }, 323 { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0, false }, "Push32R", "!0r" }, 324 { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0, false }, "Pop32R", "!0r" }, 325 326#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 327{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 328{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 329{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 330 331// This is a special encoding with r8_form on the second register only 332// for Movzx8 and Movsx8. 333#define EXT_0F_R8_FORM_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 334{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, true }, #opname "RR", "!0r,!1r" }, \ 335{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 336{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 337 338#define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 339{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 340{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 341{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 342 343#define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \ 344{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 345{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 346{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 347 348 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), 349 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdMR", "[!0r+!1d],!2r" }, 350 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, 351 352 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), 353 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssMR", "[!0r+!1d],!2r" }, 354 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, 355 356 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), 357 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), 358 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0), 359 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0), 360 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), 361 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), 362 EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0), 363 EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0), 364 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), 365 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), 366 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0), 367 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0), 368 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0), 369 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0), 370 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0), 371 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0), 372 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0), 373 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0), 374 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0), 375 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0), 376 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), 377 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), 378 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0), 379 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0), 380 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0), 381 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0), 382 EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0), 383 EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0), 384 EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0), 385 EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0), 386 EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0), 387 EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0), 388 EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0), 389 EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0), 390 EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0), 391 EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0), 392 EXT_0F_ENCODING_MAP(Addpd, 0xF2, 0x58, REG_DEF0_USE0), 393 EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0), 394 EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0), 395 EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0), 396 EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0), 397 EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0), 398 EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0), 399 EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0), 400 EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0), 401 EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0), 402 EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0), 403 EXT_0F_ENCODING_MAP(Haddpd, 0x66, 0x7C, REG_DEF0_USE0), 404 EXT_0F_ENCODING_MAP(Haddps, 0xF2, 0x7C, REG_DEF0_USE0), 405 406 { kX86PextrbRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1, false }, "PextbRRI", "!0r,!1r,!2d" }, 407 { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1, false }, "PextwRRI", "!0r,!1r,!2d" }, 408 { kX86PextrdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextdRRI", "!0r,!1r,!2d" }, 409 { kX86PextrbMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrbMRI", "[!0r+!1d],!2r,!3d" }, 410 { kX86PextrwMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrwMRI", "[!0r+!1d],!2r,!3d" }, 411 { kX86PextrdMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "kX86PextrdMRI", "[!0r+!1d],!2r,!3d" }, 412 413 { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuflwRRI", "!0r,!1r,!2d" }, 414 { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuffRRI", "!0r,!1r,!2d" }, 415 416 { kX86ShufpsRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x00, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "kX86ShufpsRRI", "!0r,!1r,!2d" }, 417 { kX86ShufpdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "kX86ShufpdRRI", "!0r,!1r,!2d" }, 418 419 { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1, false }, "PsrawRI", "!0r,!1d" }, 420 { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1, false }, "PsradRI", "!0r,!1d" }, 421 { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1, false }, "PsrlwRI", "!0r,!1d" }, 422 { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1, false }, "PsrldRI", "!0r,!1d" }, 423 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1, false }, "PsrlqRI", "!0r,!1d" }, 424 { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1, false }, "PsllwRI", "!0r,!1d" }, 425 { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1, false }, "PslldRI", "!0r,!1d" }, 426 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1, false }, "PsllqRI", "!0r,!1d" }, 427 428 { kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0, false }, "Fild32M", "[!0r,!1d]" }, 429 { kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0, false }, "Fild64M", "[!0r,!1d]" }, 430 { kX86Fld32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 0, 0, 0, false }, "Fld32M", "[!0r,!1d]" }, 431 { kX86Fld64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 0, 0, 0, false }, "Fld64M", "[!0r,!1d]" }, 432 { kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0, false }, "Fstps32M", "[!0r,!1d]" }, 433 { kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0, false }, "Fstpd64M", "[!0r,!1d]" }, 434 { kX86Fst32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 2, 0, 0, false }, "Fsts32M", "[!0r,!1d]" }, 435 { kX86Fst64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 2, 0, 0, false }, "Fstd64M", "[!0r,!1d]" }, 436 { kX86Fprem, kNullary, NO_OPERAND | USE_FP_STACK, { 0xD9, 0, 0xF8, 0, 0, 0, 0, 0, false }, "Fprem64", "" }, 437 { kX86Fucompp, kNullary, NO_OPERAND | USE_FP_STACK, { 0xDA, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Fucompp", "" }, 438 { kX86Fstsw16R, kNullary, NO_OPERAND | REG_DEFA | USE_FP_STACK, { 0x9B, 0xDF, 0xE0, 0, 0, 0, 0, 0, false }, "Fstsw16R", "ax" }, 439 440 EXT_0F_ENCODING_MAP(Mova128, 0x66, 0x6F, REG_DEF0), 441 { kX86Mova128MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128MR", "[!0r+!1d],!2r" }, 442 { kX86Mova128AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128AR", "[!0r+!1r<<!2d+!3d],!4r" }, 443 444 445 EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0), 446 { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsMR", "[!0r+!1d],!2r" }, 447 { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 448 449 EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0), 450 { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsMR", "[!0r+!1d],!2r" }, 451 { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 452 453 { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRM", "!0r,[!1r+!2d]" }, 454 { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 455 { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsMR", "[!0r+!1d],!2r" }, 456 { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 457 458 { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRM", "!0r,[!1r+!2d]" }, 459 { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 460 { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsMR", "[!0r+!1d],!2r" }, 461 { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 462 463 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), 464 EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0), 465 { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxRR", "!0r,!1r" }, 466 { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxMR", "[!0r+!1d],!2r" }, 467 { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 468 469 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxRR", "!0r,!1r" }, 470 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxMR", "[!0r+!1d],!2r" }, 471 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 472 473 { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRR", "!0r,!1r" }, 474 { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRM", "!0r,[!1r+!2d]" }, 475 { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 476 477 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, true }, "Set8R", "!1c !0r" }, 478 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8M", "!2c [!0r+!1d]" }, 479 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, 480 481 // TODO: load/store? 482 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. 483 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0, false }, "Mfence", "" }, 484 485 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 486 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 487 EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 488 489 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "!0r,!1r" }, 490 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1d],!2r" }, 491 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 492 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, 493 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 494 { kX86LockCmpxchg64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, REX_W, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 495 { kX86LockCmpxchg64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1d]" }, 496 { kX86LockCmpxchg64A, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, 497 { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0, false }, "Xchg", "[!0r+!1d],!2r" }, 498 499 EXT_0F_R8_FORM_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), 500 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), 501 EXT_0F_R8_FORM_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), 502 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), 503 EXT_0F_ENCODING_MAP(Movzx8q, REX_W, 0xB6, REG_DEF0), 504 EXT_0F_ENCODING_MAP(Movzx16q, REX_W, 0xB7, REG_DEF0), 505 EXT_0F_ENCODING_MAP(Movsx8q, REX, 0xBE, REG_DEF0), 506 EXT_0F_ENCODING_MAP(Movsx16q, REX_W, 0xBF, REG_DEF0), 507#undef EXT_0F_ENCODING_MAP 508 509 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0, false }, "Jcc8", "!1c !0t" }, 510 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0, false }, "Jcc32", "!1c !0t" }, 511 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0, false }, "Jmp8", "!0t" }, 512 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Jmp32", "!0t" }, 513 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpR", "!0r" }, 514 { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0, false }, "Jecxz", "!0t" }, 515 { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpT", "fs:[!0d]" }, 516 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0, false }, "CallR", "!0r" }, 517 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallM", "[!0r+!1d]" }, 518 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallA", "[!0r+!1r<<!2d+!3d]" }, 519 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallT", "fs:[!0d]" }, 520 { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4, false }, "CallI", "!0d" }, 521 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Ret", "" }, 522 523 { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0, false }, "StartOfMethod", "!0r" }, 524 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, 525 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "PcRelAdr", "!0r,!1d" }, 526 { kX86RepneScasw, kNullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0, false }, "RepNE ScasW", "" }, 527}; 528 529static bool NeedsRex(int32_t raw_reg) { 530 return RegStorage::RegNum(raw_reg) > 7; 531} 532 533static uint8_t LowRegisterBits(int32_t raw_reg) { 534 uint8_t low_reg = RegStorage::RegNum(raw_reg) & kRegNumMask32; // 3 bits 535 DCHECK_LT(low_reg, 8); 536 return low_reg; 537} 538 539static bool HasModrm(const X86EncodingMap* entry) { 540 switch (entry->kind) { 541 case kNullary: return false; 542 case kRegOpcode: return false; 543 default: return true; 544 } 545} 546 547static bool HasSib(const X86EncodingMap* entry) { 548 switch (entry->kind) { 549 case kArray: return true; 550 case kArrayReg: return true; 551 case kRegArray: return true; 552 case kArrayImm: return true; 553 case kRegArrayImm: return true; 554 case kShiftArrayImm: return true; 555 case kShiftArrayCl: return true; 556 case kArrayCond: return true; 557 case kCall: 558 switch (entry->opcode) { 559 case kX86CallA: return true; 560 default: return false; 561 } 562 case kPcRel: return true; 563 switch (entry->opcode) { 564 case kX86PcRelLoadRA: return true; 565 default: return false; 566 } 567 default: return false; 568 } 569} 570 571static bool ModrmIsRegReg(const X86EncodingMap* entry) { 572 switch (entry->kind) { 573 // There is no modrm for this kind of instruction, therefore the reg doesn't form part of the 574 // modrm: 575 case kNullary: return true; 576 case kRegOpcode: return true; 577 case kMovRegImm: return true; 578 // Regular modrm value of 3 cases, when there is one register the other register holds an 579 // opcode so the base register is special. 580 case kReg: return true; 581 case kRegReg: return true; 582 case kRegRegStore: return true; 583 case kRegImm: return true; 584 case kRegRegImm: return true; 585 case kRegRegImmStore: return true; 586 case kShiftRegImm: return true; 587 case kShiftRegCl: return true; 588 case kRegCond: return true; 589 case kRegRegCond: return true; 590 case kJmp: 591 switch (entry->opcode) { 592 case kX86JmpR: return true; 593 default: return false; 594 } 595 case kCall: 596 switch (entry->opcode) { 597 case kX86CallR: return true; 598 default: return false; 599 } 600 default: return false; 601 } 602} 603 604static bool IsByteSecondOperand(const X86EncodingMap* entry) { 605 return StartsWith(entry->name, "Movzx8") || StartsWith(entry->name, "Movsx8"); 606} 607 608size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 609 int32_t raw_base, int32_t displacement) { 610 bool has_modrm = HasModrm(entry); 611 bool has_sib = HasSib(entry); 612 bool r8_form = entry->skeleton.r8_form; 613 bool modrm_is_reg_reg = ModrmIsRegReg(entry); 614 if (has_sib) { 615 DCHECK(!modrm_is_reg_reg); 616 } 617 size_t size = 0; 618 if (entry->skeleton.prefix1 > 0) { 619 ++size; 620 if (entry->skeleton.prefix2 > 0) { 621 ++size; 622 } 623 } 624 if (cu_->target64 || kIsDebugBuild) { 625 bool registers_need_rex_prefix = NeedsRex(raw_reg) || NeedsRex(raw_index) || NeedsRex(raw_base); 626 if (r8_form) { 627 // Do we need an empty REX prefix to normalize byte registers? 628 registers_need_rex_prefix = registers_need_rex_prefix || 629 (RegStorage::RegNum(raw_reg) >= 4 && !IsByteSecondOperand(entry)); 630 registers_need_rex_prefix = registers_need_rex_prefix || 631 (modrm_is_reg_reg && (RegStorage::RegNum(raw_base) >= 4)); 632 } 633 if (registers_need_rex_prefix) { 634 DCHECK(cu_->target64) << "Attempt to use a 64-bit only addressable register " 635 << RegStorage::RegNum(raw_reg) << " with instruction " << entry->name; 636 if (entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W 637 && entry->skeleton.prefix1 != REX && entry->skeleton.prefix2 != REX) { 638 ++size; // rex 639 } 640 } 641 } 642 ++size; // opcode 643 if (entry->skeleton.opcode == 0x0F) { 644 ++size; 645 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 646 ++size; 647 } 648 } 649 if (has_modrm) { 650 ++size; // modrm 651 } 652 if (!modrm_is_reg_reg) { 653 if (has_sib || LowRegisterBits(raw_base) == rs_rX86_SP.GetRegNum() 654 || (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX)) { 655 // SP requires a SIB byte. 656 // GS access also needs a SIB byte for absolute adressing in 64-bit mode. 657 ++size; 658 } 659 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { 660 // BP requires an explicit displacement, even when it's 0. 661 if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA) { 662 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), UINT64_C(0)) << entry->name; 663 } 664 size += IS_SIMM8(displacement) ? 1 : 4; 665 } 666 } 667 size += entry->skeleton.immediate_bytes; 668 return size; 669} 670 671size_t X86Mir2Lir::GetInsnSize(LIR* lir) { 672 DCHECK(!IsPseudoLirOp(lir->opcode)); 673 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 674 DCHECK_EQ(entry->opcode, lir->opcode) << entry->name; 675 676 switch (entry->kind) { 677 case kData: 678 return 4; // 4 bytes of data. 679 case kNop: 680 return lir->operands[0]; // Length of nop is sole operand. 681 case kNullary: 682 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0); 683 case kRegOpcode: // lir operands - 0: reg 684 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 685 case kReg: // lir operands - 0: reg 686 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 687 case kMem: // lir operands - 0: base, 1: disp 688 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 689 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 690 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 691 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 692 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); 693 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate 694 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); 695 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 696 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], 697 lir->operands[3]); 698 case kThreadReg: // lir operands - 0: disp, 1: reg 699 // Thread displacement size is always 32bit. 700 return ComputeSize(entry, lir->operands[1], NO_REG, NO_REG, 0x12345678); 701 case kRegReg: // lir operands - 0: reg1, 1: reg2 702 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); 703 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 704 return ComputeSize(entry, lir->operands[1], NO_REG, lir->operands[0], 0); 705 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 706 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 707 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 708 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 709 lir->operands[4]); 710 case kRegThread: // lir operands - 0: reg, 1: disp 711 // Thread displacement size is always 32bit. 712 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0x12345678); 713 case kRegImm: { // lir operands - 0: reg, 1: immediate 714 size_t size = ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); 715 // AX opcodes don't require the modrm byte. 716 if (entry->skeleton.ax_opcode == 0) { 717 return size; 718 } else { 719 return size - (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); 720 } 721 } 722 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 723 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 724 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 725 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 726 case kThreadImm: // lir operands - 0: disp, 1: imm 727 // Thread displacement size is always 32bit. 728 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 729 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm 730 // Note: RegRegImm form passes reg2 as index but encodes it using base. 731 return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, 0); 732 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm 733 // Note: RegRegImmStore form passes reg1 as index but encodes it using base. 734 return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, 0); 735 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 736 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 737 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm 738 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 739 lir->operands[4]); 740 case kMovRegImm: // lir operands - 0: reg, 1: immediate 741 case kMovRegQuadImm: 742 return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 + 743 entry->skeleton.immediate_bytes; 744 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 745 // Shift by immediate one has a shorter opcode. 746 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0) - 747 (lir->operands[1] == 1 ? 1 : 0); 748 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate 749 // Shift by immediate one has a shorter opcode. 750 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]) - 751 (lir->operands[2] == 1 ? 1 : 0); 752 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 753 // Shift by immediate one has a shorter opcode. 754 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]) - 755 (lir->operands[4] == 1 ? 1 : 0); 756 case kShiftRegCl: // lir operands - 0: reg, 1: cl 757 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[1])); 758 // Note: ShiftRegCl form passes reg as reg but encodes it using base. 759 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); 760 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl 761 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2])); 762 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 763 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl 764 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[4])); 765 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], 766 lir->operands[3]); 767 case kRegCond: // lir operands - 0: reg, 1: cond 768 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 769 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond 770 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 771 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond 772 DCHECK_EQ(false, entry->skeleton.r8_form); 773 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 774 case kRegRegCond: // lir operands - 0: reg1, 1: reg2, 2: cond 775 DCHECK_EQ(false, entry->skeleton.r8_form); 776 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); 777 case kRegMemCond: // lir operands - 0: reg, 1: base, 2: disp, 3:cond 778 DCHECK_EQ(false, entry->skeleton.r8_form); 779 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 780 case kJcc: 781 if (lir->opcode == kX86Jcc8) { 782 return 2; // opcode + rel8 783 } else { 784 DCHECK(lir->opcode == kX86Jcc32); 785 return 6; // 2 byte opcode + rel32 786 } 787 case kJmp: 788 if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) { 789 return 2; // opcode + rel8 790 } else if (lir->opcode == kX86Jmp32) { 791 return 5; // opcode + rel32 792 } else if (lir->opcode == kX86JmpT) { 793 // Thread displacement size is always 32bit. 794 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 795 } else { 796 DCHECK(lir->opcode == kX86JmpR); 797 if (NeedsRex(lir->operands[0])) { 798 return 3; // REX.B + opcode + modrm 799 } else { 800 return 2; // opcode + modrm 801 } 802 } 803 case kCall: 804 switch (lir->opcode) { 805 case kX86CallI: return 5; // opcode 0:disp 806 case kX86CallR: return 2; // opcode modrm 807 case kX86CallM: // lir operands - 0: base, 1: disp 808 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 809 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp 810 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 811 case kX86CallT: // lir operands - 0: disp 812 // Thread displacement size is always 32bit. 813 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 814 default: 815 break; 816 } 817 break; 818 case kPcRel: 819 if (entry->opcode == kX86PcRelLoadRA) { 820 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 821 // Force the displacement size to 32bit, it will hold a computed offset later. 822 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 823 0x12345678); 824 } else { 825 DCHECK_EQ(entry->opcode, kX86PcRelAdr); 826 return 5; // opcode with reg + 4 byte immediate 827 } 828 case kMacro: // lir operands - 0: reg 829 DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); 830 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + 831 ComputeSize(&X86Mir2Lir::EncodingMap[cu_->target64 ? kX86Sub64RI : kX86Sub32RI], 832 lir->operands[0], NO_REG, NO_REG, 0) - 833 // Shorter ax encoding. 834 (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); 835 case kUnimplemented: 836 break; 837 } 838 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; 839 return 0; 840} 841 842static uint8_t ModrmForDisp(int base, int disp) { 843 // BP requires an explicit disp, so do not omit it in the 0 case 844 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { 845 return 0; 846 } else if (IS_SIMM8(disp)) { 847 return 1; 848 } else { 849 return 2; 850 } 851} 852 853void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) { 854 if (kIsDebugBuild) { 855 // Sanity check r8_form is correctly specified. 856 if (entry->skeleton.r8_form) { 857 CHECK(strchr(entry->name, '8') != nullptr) << entry->name; 858 } else { 859 if (entry->skeleton.immediate_bytes != 1) { // Ignore ...I8 instructions. 860 if (!StartsWith(entry->name, "Movzx8") && !StartsWith(entry->name, "Movsx8") 861 && !StartsWith(entry->name, "Movzx8q") && !StartsWith(entry->name, "Movsx8q")) { 862 CHECK(strchr(entry->name, '8') == nullptr) << entry->name; 863 } 864 } 865 } 866 if (RegStorage::RegNum(raw_reg) >= 4) { 867 // ah, bh, ch and dh are not valid registers in 32-bit. 868 CHECK(cu_->target64 || !entry->skeleton.r8_form) 869 << "Invalid register " << static_cast<int>(RegStorage::RegNum(raw_reg)) 870 << " for instruction " << entry->name << " in " 871 << PrettyMethod(cu_->method_idx, *cu_->dex_file); 872 } 873 } 874} 875 876void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, 877 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { 878 // REX.WRXB 879 // W - 64-bit operand 880 // R - MODRM.reg 881 // X - SIB.index 882 // B - MODRM.rm/SIB.base 883 bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W); 884 bool r = NeedsRex(raw_reg_r); 885 bool x = NeedsRex(raw_reg_x); 886 bool b = NeedsRex(raw_reg_b); 887 bool r8_form = entry->skeleton.r8_form; 888 bool modrm_is_reg_reg = ModrmIsRegReg(entry); 889 890 uint8_t rex = 0; 891 if (r8_form) { 892 // Do we need an empty REX prefix to normalize byte register addressing? 893 if (RegStorage::RegNum(raw_reg_r) >= 4 && !IsByteSecondOperand(entry)) { 894 rex |= 0x40; // REX.0000 895 } else if (modrm_is_reg_reg && RegStorage::RegNum(raw_reg_b) >= 4) { 896 rex |= 0x40; // REX.0000 897 } 898 } 899 if (w) { 900 rex |= 0x48; // REX.W000 901 } 902 if (r) { 903 rex |= 0x44; // REX.0R00 904 } 905 if (x) { 906 rex |= 0x42; // REX.00X0 907 } 908 if (b) { 909 rex |= 0x41; // REX.000B 910 } 911 if (entry->skeleton.prefix1 != 0) { 912 if (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX) { 913 // 64 bit addresses by GS, not FS. 914 code_buffer_.push_back(THREAD_PREFIX_GS); 915 } else { 916 if (entry->skeleton.prefix1 == REX_W || entry->skeleton.prefix1 == REX) { 917 DCHECK(cu_->target64); 918 rex |= entry->skeleton.prefix1; 919 code_buffer_.push_back(rex); 920 rex = 0; 921 } else { 922 code_buffer_.push_back(entry->skeleton.prefix1); 923 } 924 } 925 if (entry->skeleton.prefix2 != 0) { 926 if (entry->skeleton.prefix2 == REX_W || entry->skeleton.prefix1 == REX) { 927 DCHECK(cu_->target64); 928 rex |= entry->skeleton.prefix2; 929 code_buffer_.push_back(rex); 930 rex = 0; 931 } else { 932 code_buffer_.push_back(entry->skeleton.prefix2); 933 } 934 } 935 } else { 936 DCHECK_EQ(0, entry->skeleton.prefix2); 937 } 938 if (rex != 0) { 939 DCHECK(cu_->target64); 940 code_buffer_.push_back(rex); 941 } 942} 943 944void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { 945 code_buffer_.push_back(entry->skeleton.opcode); 946 if (entry->skeleton.opcode == 0x0F) { 947 code_buffer_.push_back(entry->skeleton.extra_opcode1); 948 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 949 code_buffer_.push_back(entry->skeleton.extra_opcode2); 950 } else { 951 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 952 } 953 } else { 954 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 955 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 956 } 957} 958 959void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, 960 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { 961 EmitPrefix(entry, raw_reg_r, raw_reg_x, raw_reg_b); 962 EmitOpcode(entry); 963} 964 965void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) { 966 // BP requires an explicit disp, so do not omit it in the 0 case 967 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { 968 return; 969 } else if (IS_SIMM8(disp)) { 970 code_buffer_.push_back(disp & 0xFF); 971 } else { 972 code_buffer_.push_back(disp & 0xFF); 973 code_buffer_.push_back((disp >> 8) & 0xFF); 974 code_buffer_.push_back((disp >> 16) & 0xFF); 975 code_buffer_.push_back((disp >> 24) & 0xFF); 976 } 977} 978 979void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) { 980 if (cu_->target64) { 981 // Absolute adressing for GS access. 982 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP.GetRegNum(); 983 code_buffer_.push_back(modrm); 984 uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP.GetRegNum() << 3) | rs_rBP.GetRegNum(); 985 code_buffer_.push_back(sib); 986 } else { 987 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum(); 988 code_buffer_.push_back(modrm); 989 } 990} 991 992void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) { 993 DCHECK_LT(reg_or_opcode, 8); 994 DCHECK_LT(base, 8); 995 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base; 996 code_buffer_.push_back(modrm); 997 if (base == rs_rX86_SP.GetRegNum()) { 998 // Special SIB for SP base 999 code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum()); 1000 } 1001 EmitDisp(base, disp); 1002} 1003 1004void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, 1005 int scale, int32_t disp) { 1006 DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8); 1007 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 | 1008 rs_rX86_SP.GetRegNum(); 1009 code_buffer_.push_back(modrm); 1010 DCHECK_LT(scale, 4); 1011 DCHECK_LT(RegStorage::RegNum(index), 8); 1012 DCHECK_LT(RegStorage::RegNum(base), 8); 1013 uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base); 1014 code_buffer_.push_back(sib); 1015 EmitDisp(base, disp); 1016} 1017 1018void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) { 1019 switch (entry->skeleton.immediate_bytes) { 1020 case 1: 1021 DCHECK(IS_SIMM8(imm)); 1022 code_buffer_.push_back(imm & 0xFF); 1023 break; 1024 case 2: 1025 DCHECK(IS_SIMM16(imm)); 1026 code_buffer_.push_back(imm & 0xFF); 1027 code_buffer_.push_back((imm >> 8) & 0xFF); 1028 break; 1029 case 4: 1030 DCHECK(IS_SIMM32(imm)); 1031 code_buffer_.push_back(imm & 0xFF); 1032 code_buffer_.push_back((imm >> 8) & 0xFF); 1033 code_buffer_.push_back((imm >> 16) & 0xFF); 1034 code_buffer_.push_back((imm >> 24) & 0xFF); 1035 break; 1036 case 8: 1037 code_buffer_.push_back(imm & 0xFF); 1038 code_buffer_.push_back((imm >> 8) & 0xFF); 1039 code_buffer_.push_back((imm >> 16) & 0xFF); 1040 code_buffer_.push_back((imm >> 24) & 0xFF); 1041 code_buffer_.push_back((imm >> 32) & 0xFF); 1042 code_buffer_.push_back((imm >> 40) & 0xFF); 1043 code_buffer_.push_back((imm >> 48) & 0xFF); 1044 code_buffer_.push_back((imm >> 56) & 0xFF); 1045 break; 1046 default: 1047 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 1048 << ") for instruction: " << entry->name; 1049 break; 1050 } 1051} 1052 1053void X86Mir2Lir::EmitNullary(const X86EncodingMap* entry) { 1054 DCHECK_EQ(false, entry->skeleton.r8_form); 1055 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1056 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1057 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1058 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1059} 1060 1061void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg) { 1062 DCHECK_EQ(false, entry->skeleton.r8_form); 1063 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); 1064 // There's no 3-byte instruction with +rd 1065 DCHECK(entry->skeleton.opcode != 0x0F || 1066 (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); 1067 DCHECK(!RegStorage::IsFloat(raw_reg)); 1068 uint8_t low_reg = LowRegisterBits(raw_reg); 1069 code_buffer_.back() += low_reg; 1070 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1071 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1072} 1073 1074void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg) { 1075 CheckValidByteRegister(entry, raw_reg); 1076 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); 1077 uint8_t low_reg = LowRegisterBits(raw_reg); 1078 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1079 code_buffer_.push_back(modrm); 1080 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1081 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1082} 1083 1084void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { 1085 DCHECK_EQ(false, entry->skeleton.r8_form); 1086 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1087 code_buffer_.push_back(entry->skeleton.opcode); 1088 DCHECK_NE(0x0F, entry->skeleton.opcode); 1089 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1090 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1091 uint8_t low_base = LowRegisterBits(raw_base); 1092 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1093 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1094 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1095} 1096 1097void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, 1098 int scale, int32_t disp) { 1099 DCHECK_EQ(false, entry->skeleton.r8_form); 1100 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); 1101 uint8_t low_index = LowRegisterBits(raw_index); 1102 uint8_t low_base = LowRegisterBits(raw_base); 1103 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); 1104 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1105 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1106} 1107 1108void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1109 int32_t raw_reg) { 1110 CheckValidByteRegister(entry, raw_reg); 1111 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); 1112 uint8_t low_reg = LowRegisterBits(raw_reg); 1113 uint8_t low_base = LowRegisterBits(raw_base); 1114 EmitModrmDisp(low_reg, low_base, disp); 1115 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1116 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1117 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1118} 1119 1120void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 1121 int32_t disp) { 1122 // Opcode will flip operands. 1123 EmitMemReg(entry, raw_base, disp, raw_reg); 1124} 1125 1126void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 1127 int32_t raw_index, int scale, int32_t disp) { 1128 CheckValidByteRegister(entry, raw_reg); 1129 EmitPrefixAndOpcode(entry, raw_reg, raw_index, raw_base); 1130 uint8_t low_reg = LowRegisterBits(raw_reg); 1131 uint8_t low_index = LowRegisterBits(raw_index); 1132 uint8_t low_base = LowRegisterBits(raw_base); 1133 EmitModrmSibDisp(low_reg, low_base, low_index, scale, disp); 1134 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1135 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1136 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1137} 1138 1139void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, 1140 int scale, int32_t disp, int32_t raw_reg) { 1141 // Opcode will flip operands. 1142 EmitRegArray(entry, raw_reg, raw_base, raw_index, scale, disp); 1143} 1144 1145void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1146 int32_t imm) { 1147 DCHECK_EQ(false, entry->skeleton.r8_form); 1148 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); 1149 uint8_t low_base = LowRegisterBits(raw_base); 1150 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1151 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1152 EmitImm(entry, imm); 1153} 1154 1155void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry, 1156 int32_t raw_base, int32_t raw_index, int scale, int32_t disp, 1157 int32_t imm) { 1158 DCHECK_EQ(false, entry->skeleton.r8_form); 1159 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); 1160 uint8_t low_index = LowRegisterBits(raw_index); 1161 uint8_t low_base = LowRegisterBits(raw_base); 1162 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); 1163 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1164 EmitImm(entry, imm); 1165} 1166 1167void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) { 1168 DCHECK_EQ(false, entry->skeleton.r8_form); 1169 DCHECK_NE(entry->skeleton.prefix1, 0); 1170 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, NO_REG); 1171 uint8_t low_reg = LowRegisterBits(raw_reg); 1172 EmitModrmThread(low_reg); 1173 code_buffer_.push_back(disp & 0xFF); 1174 code_buffer_.push_back((disp >> 8) & 0xFF); 1175 code_buffer_.push_back((disp >> 16) & 0xFF); 1176 code_buffer_.push_back((disp >> 24) & 0xFF); 1177 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1178 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1179 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1180} 1181 1182void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2) { 1183 if (!IsByteSecondOperand(entry)) { 1184 CheckValidByteRegister(entry, raw_reg1); 1185 } 1186 CheckValidByteRegister(entry, raw_reg2); 1187 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1188 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1189 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1190 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; 1191 code_buffer_.push_back(modrm); 1192 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1193 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1194 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1195} 1196 1197void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, 1198 int32_t imm) { 1199 DCHECK_EQ(false, entry->skeleton.r8_form); 1200 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1201 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1202 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1203 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; 1204 code_buffer_.push_back(modrm); 1205 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1206 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1207 EmitImm(entry, imm); 1208} 1209 1210void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry, 1211 int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) { 1212 DCHECK(!RegStorage::IsFloat(raw_reg)); 1213 CheckValidByteRegister(entry, raw_reg); 1214 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); 1215 uint8_t low_reg = LowRegisterBits(raw_reg); 1216 uint8_t low_base = LowRegisterBits(raw_base); 1217 EmitModrmDisp(low_reg, low_base, disp); 1218 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1219 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1220 EmitImm(entry, imm); 1221} 1222 1223void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry, 1224 int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) { 1225 // Opcode will flip operands. 1226 EmitRegMemImm(entry, raw_reg, raw_base, disp, imm); 1227} 1228 1229void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { 1230 CheckValidByteRegister(entry, raw_reg); 1231 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1232 if (RegStorage::RegNum(raw_reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) { 1233 code_buffer_.push_back(entry->skeleton.ax_opcode); 1234 } else { 1235 uint8_t low_reg = LowRegisterBits(raw_reg); 1236 EmitOpcode(entry); 1237 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1238 code_buffer_.push_back(modrm); 1239 } 1240 EmitImm(entry, imm); 1241} 1242 1243void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) { 1244 DCHECK_EQ(false, entry->skeleton.r8_form); 1245 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1246 EmitModrmThread(entry->skeleton.modrm_opcode); 1247 code_buffer_.push_back(disp & 0xFF); 1248 code_buffer_.push_back((disp >> 8) & 0xFF); 1249 code_buffer_.push_back((disp >> 16) & 0xFF); 1250 code_buffer_.push_back((disp >> 24) & 0xFF); 1251 EmitImm(entry, imm); 1252 DCHECK_EQ(entry->skeleton.ax_opcode, 0); 1253} 1254 1255void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) { 1256 DCHECK_EQ(false, entry->skeleton.r8_form); 1257 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1258 uint8_t low_reg = LowRegisterBits(raw_reg); 1259 code_buffer_.push_back(0xB8 + low_reg); 1260 switch (entry->skeleton.immediate_bytes) { 1261 case 4: 1262 code_buffer_.push_back(imm & 0xFF); 1263 code_buffer_.push_back((imm >> 8) & 0xFF); 1264 code_buffer_.push_back((imm >> 16) & 0xFF); 1265 code_buffer_.push_back((imm >> 24) & 0xFF); 1266 break; 1267 case 8: 1268 code_buffer_.push_back(imm & 0xFF); 1269 code_buffer_.push_back((imm >> 8) & 0xFF); 1270 code_buffer_.push_back((imm >> 16) & 0xFF); 1271 code_buffer_.push_back((imm >> 24) & 0xFF); 1272 code_buffer_.push_back((imm >> 32) & 0xFF); 1273 code_buffer_.push_back((imm >> 40) & 0xFF); 1274 code_buffer_.push_back((imm >> 48) & 0xFF); 1275 code_buffer_.push_back((imm >> 56) & 0xFF); 1276 break; 1277 default: 1278 LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: " 1279 << static_cast<uint32_t>(entry->skeleton.immediate_bytes); 1280 } 1281} 1282 1283void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { 1284 CheckValidByteRegister(entry, raw_reg); 1285 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1286 if (imm != 1) { 1287 code_buffer_.push_back(entry->skeleton.opcode); 1288 } else { 1289 // Shorter encoding for 1 bit shift 1290 code_buffer_.push_back(entry->skeleton.ax_opcode); 1291 } 1292 DCHECK_NE(0x0F, entry->skeleton.opcode); 1293 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1294 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1295 uint8_t low_reg = LowRegisterBits(raw_reg); 1296 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1297 code_buffer_.push_back(modrm); 1298 if (imm != 1) { 1299 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 1300 DCHECK(IS_SIMM8(imm)); 1301 code_buffer_.push_back(imm & 0xFF); 1302 } 1303} 1304 1305void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl) { 1306 CheckValidByteRegister(entry, raw_reg); 1307 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); 1308 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1309 code_buffer_.push_back(entry->skeleton.opcode); 1310 DCHECK_NE(0x0F, entry->skeleton.opcode); 1311 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1312 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1313 uint8_t low_reg = LowRegisterBits(raw_reg); 1314 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1315 code_buffer_.push_back(modrm); 1316 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1317 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1318} 1319 1320void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, 1321 int32_t displacement, int32_t raw_cl) { 1322 DCHECK_EQ(false, entry->skeleton.r8_form); 1323 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); 1324 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1325 code_buffer_.push_back(entry->skeleton.opcode); 1326 DCHECK_NE(0x0F, entry->skeleton.opcode); 1327 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1328 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1329 uint8_t low_base = LowRegisterBits(raw_base); 1330 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement); 1331 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1332 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1333} 1334 1335void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1336 int32_t imm) { 1337 DCHECK_EQ(false, entry->skeleton.r8_form); 1338 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1339 if (imm != 1) { 1340 code_buffer_.push_back(entry->skeleton.opcode); 1341 } else { 1342 // Shorter encoding for 1 bit shift 1343 code_buffer_.push_back(entry->skeleton.ax_opcode); 1344 } 1345 DCHECK_NE(0x0F, entry->skeleton.opcode); 1346 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1347 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1348 uint8_t low_base = LowRegisterBits(raw_base); 1349 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1350 if (imm != 1) { 1351 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 1352 DCHECK(IS_SIMM8(imm)); 1353 code_buffer_.push_back(imm & 0xFF); 1354 } 1355} 1356 1357void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc) { 1358 CheckValidByteRegister(entry, raw_reg); 1359 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1360 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1361 DCHECK_EQ(0x0F, entry->skeleton.opcode); 1362 code_buffer_.push_back(0x0F); 1363 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 1364 DCHECK_GE(cc, 0); 1365 DCHECK_LT(cc, 16); 1366 code_buffer_.push_back(0x90 | cc); 1367 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1368 uint8_t low_reg = LowRegisterBits(raw_reg); 1369 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1370 code_buffer_.push_back(modrm); 1371 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 1372} 1373 1374void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1375 int32_t cc) { 1376 DCHECK_EQ(false, entry->skeleton.r8_form); 1377 if (entry->skeleton.prefix1 != 0) { 1378 code_buffer_.push_back(entry->skeleton.prefix1); 1379 if (entry->skeleton.prefix2 != 0) { 1380 code_buffer_.push_back(entry->skeleton.prefix2); 1381 } 1382 } else { 1383 DCHECK_EQ(0, entry->skeleton.prefix2); 1384 } 1385 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1386 DCHECK_EQ(0x0F, entry->skeleton.opcode); 1387 code_buffer_.push_back(0x0F); 1388 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 1389 DCHECK_GE(cc, 0); 1390 DCHECK_LT(cc, 16); 1391 code_buffer_.push_back(0x90 | cc); 1392 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1393 uint8_t low_base = LowRegisterBits(raw_base); 1394 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1395 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 1396} 1397 1398void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, 1399 int32_t cc) { 1400 // Generate prefix and opcode without the condition. 1401 DCHECK_EQ(false, entry->skeleton.r8_form); 1402 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1403 1404 // Now add the condition. The last byte of opcode is the one that receives it. 1405 DCHECK_GE(cc, 0); 1406 DCHECK_LT(cc, 16); 1407 code_buffer_.back() += cc; 1408 1409 // Not expecting to have to encode immediate or do anything special for ModR/M since there are 1410 // two registers. 1411 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1412 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1413 1414 // For register to register encoding, the mod is 3. 1415 const uint8_t mod = (3 << 6); 1416 1417 // Encode the ModR/M byte now. 1418 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1419 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1420 const uint8_t modrm = mod | (low_reg1 << 3) | low_reg2; 1421 code_buffer_.push_back(modrm); 1422} 1423 1424void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, 1425 int32_t disp, int32_t cc) { 1426 // Generate prefix and opcode without the condition. 1427 DCHECK_EQ(false, entry->skeleton.r8_form); 1428 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_base); 1429 1430 // Now add the condition. The last byte of opcode is the one that receives it. 1431 DCHECK_GE(cc, 0); 1432 DCHECK_LT(cc, 16); 1433 code_buffer_.back() += cc; 1434 1435 // Not expecting to have to encode immediate or do anything special for ModR/M since there are 1436 // two registers. 1437 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1438 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1439 1440 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1441 uint8_t low_base = LowRegisterBits(raw_base); 1442 EmitModrmDisp(low_reg1, low_base, disp); 1443} 1444 1445void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int32_t rel) { 1446 if (entry->opcode == kX86Jmp8) { 1447 DCHECK(IS_SIMM8(rel)); 1448 code_buffer_.push_back(0xEB); 1449 code_buffer_.push_back(rel & 0xFF); 1450 } else if (entry->opcode == kX86Jmp32) { 1451 code_buffer_.push_back(0xE9); 1452 code_buffer_.push_back(rel & 0xFF); 1453 code_buffer_.push_back((rel >> 8) & 0xFF); 1454 code_buffer_.push_back((rel >> 16) & 0xFF); 1455 code_buffer_.push_back((rel >> 24) & 0xFF); 1456 } else if (entry->opcode == kX86Jecxz8) { 1457 DCHECK(IS_SIMM8(rel)); 1458 code_buffer_.push_back(0xE3); 1459 code_buffer_.push_back(rel & 0xFF); 1460 } else { 1461 DCHECK(entry->opcode == kX86JmpR); 1462 DCHECK_EQ(false, entry->skeleton.r8_form); 1463 EmitPrefix(entry, NO_REG, NO_REG, rel); 1464 code_buffer_.push_back(entry->skeleton.opcode); 1465 uint8_t low_reg = LowRegisterBits(rel); 1466 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1467 code_buffer_.push_back(modrm); 1468 } 1469} 1470 1471void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc) { 1472 DCHECK_GE(cc, 0); 1473 DCHECK_LT(cc, 16); 1474 if (entry->opcode == kX86Jcc8) { 1475 DCHECK(IS_SIMM8(rel)); 1476 code_buffer_.push_back(0x70 | cc); 1477 code_buffer_.push_back(rel & 0xFF); 1478 } else { 1479 DCHECK(entry->opcode == kX86Jcc32); 1480 code_buffer_.push_back(0x0F); 1481 code_buffer_.push_back(0x80 | cc); 1482 code_buffer_.push_back(rel & 0xFF); 1483 code_buffer_.push_back((rel >> 8) & 0xFF); 1484 code_buffer_.push_back((rel >> 16) & 0xFF); 1485 code_buffer_.push_back((rel >> 24) & 0xFF); 1486 } 1487} 1488 1489void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { 1490 DCHECK_EQ(false, entry->skeleton.r8_form); 1491 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); 1492 uint8_t low_base = LowRegisterBits(raw_base); 1493 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1494 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1495 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1496} 1497 1498void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) { 1499 DCHECK_EQ(false, entry->skeleton.r8_form); 1500 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1501 DCHECK_EQ(4, entry->skeleton.immediate_bytes); 1502 code_buffer_.push_back(disp & 0xFF); 1503 code_buffer_.push_back((disp >> 8) & 0xFF); 1504 code_buffer_.push_back((disp >> 16) & 0xFF); 1505 code_buffer_.push_back((disp >> 24) & 0xFF); 1506 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1507} 1508 1509void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int32_t disp) { 1510 DCHECK_EQ(false, entry->skeleton.r8_form); 1511 DCHECK_NE(entry->skeleton.prefix1, 0); 1512 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1513 EmitModrmThread(entry->skeleton.modrm_opcode); 1514 code_buffer_.push_back(disp & 0xFF); 1515 code_buffer_.push_back((disp >> 8) & 0xFF); 1516 code_buffer_.push_back((disp >> 16) & 0xFF); 1517 code_buffer_.push_back((disp >> 24) & 0xFF); 1518 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1519 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1520} 1521 1522void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 1523 int32_t raw_index, int scale, int32_t table_or_disp) { 1524 int disp; 1525 if (entry->opcode == kX86PcRelLoadRA) { 1526 Mir2Lir::EmbeddedData *tab_rec = 1527 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); 1528 disp = tab_rec->offset; 1529 } else { 1530 DCHECK(entry->opcode == kX86PcRelAdr); 1531 Mir2Lir::EmbeddedData *tab_rec = 1532 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(raw_base_or_table)); 1533 disp = tab_rec->offset; 1534 } 1535 if (entry->opcode == kX86PcRelLoadRA) { 1536 DCHECK_EQ(false, entry->skeleton.r8_form); 1537 EmitPrefix(entry, raw_reg, raw_index, raw_base_or_table); 1538 code_buffer_.push_back(entry->skeleton.opcode); 1539 DCHECK_NE(0x0F, entry->skeleton.opcode); 1540 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1541 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1542 uint8_t low_reg = LowRegisterBits(raw_reg); 1543 uint8_t modrm = (2 << 6) | (low_reg << 3) | rs_rX86_SP.GetRegNum(); 1544 code_buffer_.push_back(modrm); 1545 DCHECK_LT(scale, 4); 1546 uint8_t low_base_or_table = LowRegisterBits(raw_base_or_table); 1547 uint8_t low_index = LowRegisterBits(raw_index); 1548 uint8_t sib = (scale << 6) | (low_index << 3) | low_base_or_table; 1549 code_buffer_.push_back(sib); 1550 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1551 } else { 1552 uint8_t low_reg = LowRegisterBits(raw_reg); 1553 code_buffer_.push_back(entry->skeleton.opcode + low_reg); 1554 } 1555 code_buffer_.push_back(disp & 0xFF); 1556 code_buffer_.push_back((disp >> 8) & 0xFF); 1557 code_buffer_.push_back((disp >> 16) & 0xFF); 1558 code_buffer_.push_back((disp >> 24) & 0xFF); 1559 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1560 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1561} 1562 1563void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset) { 1564 DCHECK_EQ(entry->opcode, kX86StartOfMethod) << entry->name; 1565 DCHECK_EQ(false, entry->skeleton.r8_form); 1566 EmitPrefix(entry, raw_reg, NO_REG, NO_REG); 1567 code_buffer_.push_back(0xE8); // call +0 1568 code_buffer_.push_back(0); 1569 code_buffer_.push_back(0); 1570 code_buffer_.push_back(0); 1571 code_buffer_.push_back(0); 1572 1573 uint8_t low_reg = LowRegisterBits(raw_reg); 1574 code_buffer_.push_back(0x58 + low_reg); // pop reg 1575 1576 EmitRegImm(&X86Mir2Lir::EncodingMap[cu_->target64 ? kX86Sub64RI : kX86Sub32RI], 1577 raw_reg, offset + 5 /* size of call +0 */); 1578} 1579 1580void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { 1581 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " 1582 << BuildInsnString(entry->fmt, lir, 0); 1583 for (size_t i = 0; i < GetInsnSize(lir); ++i) { 1584 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 1585 } 1586} 1587 1588/* 1589 * Assemble the LIR into binary instruction format. Note that we may 1590 * discover that pc-relative displacements may not fit the selected 1591 * instruction. In those cases we will try to substitute a new code 1592 * sequence or request that the trace be shortened and retried. 1593 */ 1594AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { 1595 LIR *lir; 1596 AssemblerStatus res = kSuccess; // Assume success 1597 1598 const bool kVerbosePcFixup = false; 1599 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1600 if (IsPseudoLirOp(lir->opcode)) { 1601 continue; 1602 } 1603 1604 if (lir->flags.is_nop) { 1605 continue; 1606 } 1607 1608 if (lir->flags.fixup != kFixupNone) { 1609 switch (lir->opcode) { 1610 case kX86Jcc8: { 1611 LIR *target_lir = lir->target; 1612 DCHECK(target_lir != NULL); 1613 int delta = 0; 1614 CodeOffset pc; 1615 if (IS_SIMM8(lir->operands[0])) { 1616 pc = lir->offset + 2 /* opcode + rel8 */; 1617 } else { 1618 pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1619 } 1620 CodeOffset target = target_lir->offset; 1621 delta = target - pc; 1622 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1623 if (kVerbosePcFixup) { 1624 LOG(INFO) << "Retry for JCC growth at " << lir->offset 1625 << " delta: " << delta << " old delta: " << lir->operands[0]; 1626 } 1627 lir->opcode = kX86Jcc32; 1628 lir->flags.size = GetInsnSize(lir); 1629 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); 1630 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); 1631 res = kRetryAll; 1632 } 1633 if (kVerbosePcFixup) { 1634 LOG(INFO) << "Source:"; 1635 DumpLIRInsn(lir, 0); 1636 LOG(INFO) << "Target:"; 1637 DumpLIRInsn(target_lir, 0); 1638 LOG(INFO) << "Delta " << delta; 1639 } 1640 lir->operands[0] = delta; 1641 break; 1642 } 1643 case kX86Jcc32: { 1644 LIR *target_lir = lir->target; 1645 DCHECK(target_lir != NULL); 1646 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1647 CodeOffset target = target_lir->offset; 1648 int delta = target - pc; 1649 if (kVerbosePcFixup) { 1650 LOG(INFO) << "Source:"; 1651 DumpLIRInsn(lir, 0); 1652 LOG(INFO) << "Target:"; 1653 DumpLIRInsn(target_lir, 0); 1654 LOG(INFO) << "Delta " << delta; 1655 } 1656 lir->operands[0] = delta; 1657 break; 1658 } 1659 case kX86Jecxz8: { 1660 LIR *target_lir = lir->target; 1661 DCHECK(target_lir != NULL); 1662 CodeOffset pc; 1663 pc = lir->offset + 2; // opcode + rel8 1664 CodeOffset target = target_lir->offset; 1665 int delta = target - pc; 1666 lir->operands[0] = delta; 1667 DCHECK(IS_SIMM8(delta)); 1668 break; 1669 } 1670 case kX86Jmp8: { 1671 LIR *target_lir = lir->target; 1672 DCHECK(target_lir != NULL); 1673 int delta = 0; 1674 CodeOffset pc; 1675 if (IS_SIMM8(lir->operands[0])) { 1676 pc = lir->offset + 2 /* opcode + rel8 */; 1677 } else { 1678 pc = lir->offset + 5 /* opcode + rel32 */; 1679 } 1680 CodeOffset target = target_lir->offset; 1681 delta = target - pc; 1682 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { 1683 // Useless branch 1684 NopLIR(lir); 1685 if (kVerbosePcFixup) { 1686 LOG(INFO) << "Retry for useless branch at " << lir->offset; 1687 } 1688 res = kRetryAll; 1689 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1690 if (kVerbosePcFixup) { 1691 LOG(INFO) << "Retry for JMP growth at " << lir->offset; 1692 } 1693 lir->opcode = kX86Jmp32; 1694 lir->flags.size = GetInsnSize(lir); 1695 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); 1696 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); 1697 res = kRetryAll; 1698 } 1699 lir->operands[0] = delta; 1700 break; 1701 } 1702 case kX86Jmp32: { 1703 LIR *target_lir = lir->target; 1704 DCHECK(target_lir != NULL); 1705 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; 1706 CodeOffset target = target_lir->offset; 1707 int delta = target - pc; 1708 lir->operands[0] = delta; 1709 break; 1710 } 1711 default: 1712 if (lir->flags.fixup == kFixupLoad) { 1713 LIR *target_lir = lir->target; 1714 DCHECK(target_lir != NULL); 1715 CodeOffset target = target_lir->offset; 1716 lir->operands[2] = target; 1717 int newSize = GetInsnSize(lir); 1718 if (newSize != lir->flags.size) { 1719 lir->flags.size = newSize; 1720 res = kRetryAll; 1721 } 1722 } 1723 break; 1724 } 1725 } 1726 1727 /* 1728 * If one of the pc-relative instructions expanded we'll have 1729 * to make another pass. Don't bother to fully assemble the 1730 * instruction. 1731 */ 1732 if (res != kSuccess) { 1733 continue; 1734 } 1735 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); 1736 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 1737 size_t starting_cbuf_size = code_buffer_.size(); 1738 switch (entry->kind) { 1739 case kData: // 4 bytes of data 1740 code_buffer_.push_back(lir->operands[0]); 1741 break; 1742 case kNullary: // 1 byte of opcode and possible prefixes. 1743 EmitNullary(entry); 1744 break; 1745 case kRegOpcode: // lir operands - 0: reg 1746 EmitOpRegOpcode(entry, lir->operands[0]); 1747 break; 1748 case kReg: // lir operands - 0: reg 1749 EmitOpReg(entry, lir->operands[0]); 1750 break; 1751 case kMem: // lir operands - 0: base, 1: disp 1752 EmitOpMem(entry, lir->operands[0], lir->operands[1]); 1753 break; 1754 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 1755 EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); 1756 break; 1757 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 1758 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1759 break; 1760 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 1761 EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1762 break; 1763 case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate 1764 EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1765 lir->operands[3], lir->operands[4]); 1766 break; 1767 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 1768 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1769 lir->operands[3], lir->operands[4]); 1770 break; 1771 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 1772 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1773 break; 1774 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 1775 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1776 lir->operands[3], lir->operands[4]); 1777 break; 1778 case kRegThread: // lir operands - 0: reg, 1: disp 1779 EmitRegThread(entry, lir->operands[0], lir->operands[1]); 1780 break; 1781 case kRegReg: // lir operands - 0: reg1, 1: reg2 1782 EmitRegReg(entry, lir->operands[0], lir->operands[1]); 1783 break; 1784 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 1785 EmitRegReg(entry, lir->operands[1], lir->operands[0]); 1786 break; 1787 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate 1788 EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1789 lir->operands[3]); 1790 break; 1791 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm 1792 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1793 break; 1794 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm 1795 EmitRegRegImm(entry, lir->operands[1], lir->operands[0], lir->operands[2]); 1796 break; 1797 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 1798 EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1799 lir->operands[3]); 1800 break; 1801 case kRegImm: // lir operands - 0: reg, 1: immediate 1802 EmitRegImm(entry, lir->operands[0], lir->operands[1]); 1803 break; 1804 case kThreadImm: // lir operands - 0: disp, 1: immediate 1805 EmitThreadImm(entry, lir->operands[0], lir->operands[1]); 1806 break; 1807 case kMovRegImm: // lir operands - 0: reg, 1: immediate 1808 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); 1809 break; 1810 case kMovRegQuadImm: { 1811 int64_t value = static_cast<int64_t>(static_cast<int64_t>(lir->operands[1]) << 32 | 1812 static_cast<uint32_t>(lir->operands[2])); 1813 EmitMovRegImm(entry, lir->operands[0], value); 1814 } 1815 break; 1816 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 1817 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); 1818 break; 1819 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate 1820 EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1821 break; 1822 case kShiftRegCl: // lir operands - 0: reg, 1: cl 1823 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); 1824 break; 1825 case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl 1826 EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1827 break; 1828 case kRegCond: // lir operands - 0: reg, 1: condition 1829 EmitRegCond(entry, lir->operands[0], lir->operands[1]); 1830 break; 1831 case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition 1832 EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1833 break; 1834 case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition 1835 EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1836 break; 1837 case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition 1838 EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1839 lir->operands[3]); 1840 break; 1841 case kJmp: // lir operands - 0: rel 1842 if (entry->opcode == kX86JmpT) { 1843 // This works since the instruction format for jmp and call is basically the same and 1844 // EmitCallThread loads opcode info. 1845 EmitCallThread(entry, lir->operands[0]); 1846 } else { 1847 EmitJmp(entry, lir->operands[0]); 1848 } 1849 break; 1850 case kJcc: // lir operands - 0: rel, 1: CC, target assigned 1851 EmitJcc(entry, lir->operands[0], lir->operands[1]); 1852 break; 1853 case kCall: 1854 switch (entry->opcode) { 1855 case kX86CallI: // lir operands - 0: disp 1856 EmitCallImmediate(entry, lir->operands[0]); 1857 break; 1858 case kX86CallM: // lir operands - 0: base, 1: disp 1859 EmitCallMem(entry, lir->operands[0], lir->operands[1]); 1860 break; 1861 case kX86CallT: // lir operands - 0: disp 1862 EmitCallThread(entry, lir->operands[0]); 1863 break; 1864 default: 1865 EmitUnimplemented(entry, lir); 1866 break; 1867 } 1868 break; 1869 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 1870 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1871 lir->operands[3], lir->operands[4]); 1872 break; 1873 case kMacro: // lir operands - 0: reg 1874 EmitMacro(entry, lir->operands[0], lir->offset); 1875 break; 1876 case kNop: // TODO: these instruction kinds are missing implementations. 1877 case kThreadReg: 1878 case kRegArrayImm: 1879 case kShiftArrayImm: 1880 case kShiftArrayCl: 1881 case kArrayCond: 1882 case kUnimplemented: 1883 EmitUnimplemented(entry, lir); 1884 break; 1885 } 1886 DCHECK_EQ(lir->flags.size, GetInsnSize(lir)); 1887 CHECK_EQ(lir->flags.size, code_buffer_.size() - starting_cbuf_size) 1888 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; 1889 } 1890 return res; 1891} 1892 1893// LIR offset assignment. 1894// TODO: consolidate w/ Arm assembly mechanism. 1895int X86Mir2Lir::AssignInsnOffsets() { 1896 LIR* lir; 1897 int offset = 0; 1898 1899 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1900 lir->offset = offset; 1901 if (LIKELY(!IsPseudoLirOp(lir->opcode))) { 1902 if (!lir->flags.is_nop) { 1903 offset += lir->flags.size; 1904 } 1905 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { 1906 if (offset & 0x2) { 1907 offset += 2; 1908 lir->operands[0] = 1; 1909 } else { 1910 lir->operands[0] = 0; 1911 } 1912 } 1913 /* Pseudo opcodes don't consume space */ 1914 } 1915 return offset; 1916} 1917 1918/* 1919 * Walk the compilation unit and assign offsets to instructions 1920 * and literals and compute the total size of the compiled unit. 1921 * TODO: consolidate w/ Arm assembly mechanism. 1922 */ 1923void X86Mir2Lir::AssignOffsets() { 1924 int offset = AssignInsnOffsets(); 1925 1926 if (const_vectors_ != nullptr) { 1927 /* assign offsets to vector literals */ 1928 1929 // First, get offset to 12 mod 16 to align to 16 byte boundary. 1930 // This will ensure that the vector is 16 byte aligned, as the procedure is 1931 // always aligned at at 4 mod 16. 1932 int align_size = (16-4) - (offset & 0xF); 1933 if (align_size < 0) { 1934 align_size += 16; 1935 } 1936 1937 offset += align_size; 1938 1939 // Now assign each literal the right offset. 1940 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 1941 p->offset = offset; 1942 offset += 16; 1943 } 1944 } 1945 1946 /* Const values have to be word aligned */ 1947 offset = RoundUp(offset, 4); 1948 1949 /* Set up offsets for literals */ 1950 data_offset_ = offset; 1951 1952 offset = AssignLiteralOffset(offset); 1953 1954 offset = AssignSwitchTablesOffset(offset); 1955 1956 offset = AssignFillArrayDataOffset(offset); 1957 1958 total_size_ = offset; 1959} 1960 1961/* 1962 * Go over each instruction in the list and calculate the offset from the top 1963 * before sending them off to the assembler. If out-of-range branch distance is 1964 * seen rearrange the instructions a bit to correct it. 1965 * TODO: consolidate w/ Arm assembly mechanism. 1966 */ 1967void X86Mir2Lir::AssembleLIR() { 1968 cu_->NewTimingSplit("Assemble"); 1969 1970 // We will remove the method address if we never ended up using it 1971 if (store_method_addr_ && !store_method_addr_used_) { 1972 setup_method_address_[0]->flags.is_nop = true; 1973 setup_method_address_[1]->flags.is_nop = true; 1974 } 1975 1976 AssignOffsets(); 1977 int assembler_retries = 0; 1978 /* 1979 * Assemble here. Note that we generate code with optimistic assumptions 1980 * and if found now to work, we'll have to redo the sequence and retry. 1981 */ 1982 1983 while (true) { 1984 AssemblerStatus res = AssembleInstructions(0); 1985 if (res == kSuccess) { 1986 break; 1987 } else { 1988 assembler_retries++; 1989 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 1990 CodegenDump(); 1991 LOG(FATAL) << "Assembler error - too many retries"; 1992 } 1993 // Redo offsets and try again 1994 AssignOffsets(); 1995 code_buffer_.clear(); 1996 } 1997 } 1998 1999 // Install literals 2000 InstallLiteralPools(); 2001 2002 // Install switch tables 2003 InstallSwitchTables(); 2004 2005 // Install fill array data 2006 InstallFillArrayData(); 2007 2008 // Create the mapping table and native offset to reference map. 2009 cu_->NewTimingSplit("PcMappingTable"); 2010 CreateMappingTables(); 2011 2012 cu_->NewTimingSplit("GcMap"); 2013 CreateNativeGcMap(); 2014} 2015 2016} // namespace art 2017