codegen_x86.h revision 9ee4519afd97121f893f82d41d23164fc6c9ed34
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23#include <map> 24 25namespace art { 26 27class X86Mir2Lir : public Mir2Lir { 28 protected: 29 class InToRegStorageMapper { 30 public: 31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 32 virtual ~InToRegStorageMapper() {} 33 }; 34 35 class InToRegStorageX86_64Mapper : public InToRegStorageMapper { 36 public: 37 explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} 38 virtual ~InToRegStorageX86_64Mapper() {} 39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 40 protected: 41 Mir2Lir* ml_; 42 private: 43 int cur_core_reg_; 44 int cur_fp_reg_; 45 }; 46 47 class InToRegStorageMapping { 48 public: 49 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 50 initialized_(false) {} 51 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 52 int GetMaxMappedIn() { return max_mapped_in_; } 53 bool IsThereStackMapped() { return is_there_stack_mapped_; } 54 RegStorage Get(int in_position); 55 bool IsInitialized() { return initialized_; } 56 private: 57 std::map<int, RegStorage> mapping_; 58 int max_mapped_in_; 59 bool is_there_stack_mapped_; 60 bool initialized_; 61 }; 62 63 public: 64 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 65 66 // Required for target - codegen helpers. 67 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 68 RegLocation rl_dest, int lit); 69 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 70 LIR* CheckSuspendUsingLoad() OVERRIDE; 71 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 72 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 73 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 74 OpSize size, VolatileKind is_volatile) OVERRIDE; 75 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 76 OpSize size) OVERRIDE; 77 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 78 RegStorage r_dest, OpSize size) OVERRIDE; 79 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 80 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 81 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 82 OpSize size, VolatileKind is_volatile) OVERRIDE; 83 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 84 OpSize size) OVERRIDE; 85 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 86 RegStorage r_src, OpSize size) OVERRIDE; 87 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 88 void GenImplicitNullCheck(RegStorage reg, int opt_flags); 89 90 // Required for target - register utilities. 91 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 92 RegStorage TargetReg32(SpecialTargetRegister reg); 93 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 94 if (wide_kind == kWide) { 95 if (cu_->target64) { 96 return As64BitReg(TargetReg32(symbolic_reg)); 97 } else { 98 // x86: construct a pair. 99 DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) || 100 (kFArg0 <= symbolic_reg && symbolic_reg < kFArg3) || 101 (kRet0 == symbolic_reg)); 102 return RegStorage::MakeRegPair(TargetReg32(symbolic_reg), 103 TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1))); 104 } 105 } else if (wide_kind == kRef && cu_->target64) { 106 return As64BitReg(TargetReg32(symbolic_reg)); 107 } else { 108 return TargetReg32(symbolic_reg); 109 } 110 } 111 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 112 return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide); 113 } 114 RegStorage GetArgMappingToPhysicalReg(int arg_num); 115 RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); 116 RegLocation GetReturnAlt(); 117 RegLocation GetReturnWideAlt(); 118 RegLocation LocCReturn(); 119 RegLocation LocCReturnRef(); 120 RegLocation LocCReturnDouble(); 121 RegLocation LocCReturnFloat(); 122 RegLocation LocCReturnWide(); 123 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 124 void AdjustSpillMask(); 125 void ClobberCallerSave(); 126 void FreeCallTemps(); 127 void LockCallTemps(); 128 void CompilerInitializeRegAlloc(); 129 int VectorRegisterSize(); 130 int NumReservableVectorRegisters(bool fp_used); 131 132 // Required for target - miscellaneous. 133 void AssembleLIR(); 134 int AssignInsnOffsets(); 135 void AssignOffsets(); 136 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 137 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 138 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 139 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 140 const char* GetTargetInstFmt(int opcode); 141 const char* GetTargetInstName(int opcode); 142 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 143 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 144 uint64_t GetTargetInstFlags(int opcode); 145 size_t GetInsnSize(LIR* lir) OVERRIDE; 146 bool IsUnconditionalBranch(LIR* lir); 147 148 // Get the register class for load/store of a field. 149 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 150 151 // Required for target - Dalvik-level generators. 152 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 153 RegLocation rl_src2); 154 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 155 RegLocation rl_dest, int scale); 156 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 157 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 158 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 159 RegLocation rl_src1, RegLocation rl_shift); 160 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 161 RegLocation rl_src2); 162 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 163 RegLocation rl_src2); 164 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 165 RegLocation rl_src2); 166 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 167 RegLocation rl_src2); 168 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 169 RegLocation rl_src2); 170 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); 171 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 172 RegLocation rl_src2); 173 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 174 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 175 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 176 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double); 177 bool GenInlinedSqrt(CallInfo* info); 178 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 179 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 180 bool GenInlinedPeek(CallInfo* info, OpSize size); 181 bool GenInlinedPoke(CallInfo* info, OpSize size); 182 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 183 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 184 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 185 RegLocation rl_src2); 186 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 187 RegLocation rl_src2); 188 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 189 RegLocation rl_src2); 190 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 191 RegLocation rl_src2, bool is_div); 192 // TODO: collapse reg_lo, reg_hi 193 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 194 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 195 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 196 void GenDivZeroCheckWide(RegStorage reg); 197 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 198 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 199 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 200 void GenExitSequence(); 201 void GenSpecialExitSequence(); 202 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 203 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 204 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 205 void GenSelect(BasicBlock* bb, MIR* mir); 206 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 207 int32_t true_val, int32_t false_val, RegStorage rs_dest, 208 int dest_reg_class) OVERRIDE; 209 bool GenMemBarrier(MemBarrierKind barrier_kind); 210 void GenMoveException(RegLocation rl_dest); 211 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 212 int first_bit, int second_bit); 213 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 214 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 215 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 216 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 217 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 218 219 /* 220 * @brief Generate a two address long operation with a constant value 221 * @param rl_dest location of result 222 * @param rl_src constant source operand 223 * @param op Opcode to be generated 224 * @return success or not 225 */ 226 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 227 /* 228 * @brief Generate a three address long operation with a constant value 229 * @param rl_dest location of result 230 * @param rl_src1 source operand 231 * @param rl_src2 constant source operand 232 * @param op Opcode to be generated 233 * @return success or not 234 */ 235 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 236 Instruction::Code op); 237 238 /** 239 * @brief Generate a long arithmetic operation. 240 * @param rl_dest The destination. 241 * @param rl_src1 First operand. 242 * @param rl_src2 Second operand. 243 * @param op The DEX opcode for the operation. 244 * @param is_commutative The sources can be swapped if needed. 245 */ 246 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 247 Instruction::Code op, bool is_commutative); 248 249 /** 250 * @brief Generate a two operand long arithmetic operation. 251 * @param rl_dest The destination. 252 * @param rl_src Second operand. 253 * @param op The DEX opcode for the operation. 254 */ 255 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 256 257 /** 258 * @brief Generate a long operation. 259 * @param rl_dest The destination. Must be in a register 260 * @param rl_src The other operand. May be in a register or in memory. 261 * @param op The DEX opcode for the operation. 262 */ 263 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 264 265 /** 266 * @brief Implement instanceof a final class with x86 specific code. 267 * @param use_declaring_class 'true' if we can use the class itself. 268 * @param type_idx Type index to use if use_declaring_class is 'false'. 269 * @param rl_dest Result to be set to 0 or 1. 270 * @param rl_src Object to be tested. 271 */ 272 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 273 RegLocation rl_src); 274 275 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 276 RegLocation rl_src1, RegLocation rl_shift); 277 278 // Single operation generators. 279 LIR* OpUnconditionalBranch(LIR* target); 280 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 281 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 282 LIR* OpCondBranch(ConditionCode cc, LIR* target); 283 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 284 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 285 LIR* OpIT(ConditionCode cond, const char* guide); 286 void OpEndIT(LIR* it); 287 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 288 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 289 LIR* OpReg(OpKind op, RegStorage r_dest_src); 290 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 291 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 292 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 293 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 294 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 295 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 296 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 297 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 298 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 299 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 300 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 301 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 302 LIR* OpTestSuspend(LIR* target); 303 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 304 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 305 LIR* OpVldm(RegStorage r_base, int count); 306 LIR* OpVstm(RegStorage r_base, int count); 307 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 308 void OpRegCopyWide(RegStorage dest, RegStorage src); 309 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 310 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 311 312 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 313 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 314 void SpillCoreRegs(); 315 void UnSpillCoreRegs(); 316 void UnSpillFPRegs(); 317 void SpillFPRegs(); 318 static const X86EncodingMap EncodingMap[kX86Last]; 319 bool InexpensiveConstantInt(int32_t value); 320 bool InexpensiveConstantFloat(int32_t value); 321 bool InexpensiveConstantLong(int64_t value); 322 bool InexpensiveConstantDouble(int64_t value); 323 324 /* 325 * @brief Should try to optimize for two address instructions? 326 * @return true if we try to avoid generating three operand instructions. 327 */ 328 virtual bool GenerateTwoOperandInstructions() const { return true; } 329 330 /* 331 * @brief x86 specific codegen for int operations. 332 * @param opcode Operation to perform. 333 * @param rl_dest Destination for the result. 334 * @param rl_lhs Left hand operand. 335 * @param rl_rhs Right hand operand. 336 */ 337 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 338 RegLocation rl_rhs); 339 340 /* 341 * @brief Dump a RegLocation using printf 342 * @param loc Register location to dump 343 */ 344 static void DumpRegLocation(RegLocation loc); 345 346 /* 347 * @brief Load the Method* of a dex method into the register. 348 * @param target_method The MethodReference of the method to be invoked. 349 * @param type How the method will be invoked. 350 * @param register that will contain the code address. 351 * @note register will be passed to TargetReg to get physical register. 352 */ 353 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 354 SpecialTargetRegister symbolic_reg); 355 356 /* 357 * @brief Load the Class* of a Dex Class type into the register. 358 * @param type How the method will be invoked. 359 * @param register that will contain the code address. 360 * @note register will be passed to TargetReg to get physical register. 361 */ 362 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 363 364 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 365 366 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 367 NextCallInsn next_call_insn, 368 const MethodReference& target_method, 369 uint32_t vtable_idx, 370 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 371 bool skip_this); 372 373 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 374 NextCallInsn next_call_insn, 375 const MethodReference& target_method, 376 uint32_t vtable_idx, 377 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 378 bool skip_this); 379 380 /* 381 * @brief Generate a relative call to the method that will be patched at link time. 382 * @param target_method The MethodReference of the method to be invoked. 383 * @param type How the method will be invoked. 384 * @returns Call instruction 385 */ 386 virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 387 388 /* 389 * @brief Handle x86 specific literals 390 */ 391 void InstallLiteralPools(); 392 393 /* 394 * @brief Generate the debug_frame CFI information. 395 * @returns pointer to vector containing CFE information 396 */ 397 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 398 399 /* 400 * @brief Generate the debug_frame FDE information. 401 * @returns pointer to vector containing CFE information 402 */ 403 std::vector<uint8_t>* ReturnCallFrameInformation(); 404 405 protected: 406 // Casting of RegStorage 407 RegStorage As32BitReg(RegStorage reg) { 408 DCHECK(!reg.IsPair()); 409 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 410 if (kFailOnSizeError) { 411 LOG(FATAL) << "Expected 64b register " << reg.GetReg(); 412 } else { 413 LOG(WARNING) << "Expected 64b register " << reg.GetReg(); 414 return reg; 415 } 416 } 417 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 418 reg.GetRawBits() & RegStorage::kRegTypeMask); 419 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 420 ->GetReg().GetReg(), 421 ret_val.GetReg()); 422 return ret_val; 423 } 424 425 RegStorage As64BitReg(RegStorage reg) { 426 DCHECK(!reg.IsPair()); 427 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 428 if (kFailOnSizeError) { 429 LOG(FATAL) << "Expected 32b register " << reg.GetReg(); 430 } else { 431 LOG(WARNING) << "Expected 32b register " << reg.GetReg(); 432 return reg; 433 } 434 } 435 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 436 reg.GetRawBits() & RegStorage::kRegTypeMask); 437 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 438 ->GetReg().GetReg(), 439 ret_val.GetReg()); 440 return ret_val; 441 } 442 443 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 444 int32_t raw_base, int32_t displacement); 445 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); 446 void EmitPrefix(const X86EncodingMap* entry, 447 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); 448 void EmitOpcode(const X86EncodingMap* entry); 449 void EmitPrefixAndOpcode(const X86EncodingMap* entry, 450 int32_t reg_r, int32_t reg_x, int32_t reg_b); 451 void EmitDisp(uint8_t base, int32_t disp); 452 void EmitModrmThread(uint8_t reg_or_opcode); 453 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); 454 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, 455 int32_t disp); 456 void EmitImm(const X86EncodingMap* entry, int64_t imm); 457 void EmitNullary(const X86EncodingMap* entry); 458 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); 459 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); 460 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 461 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 462 int32_t disp); 463 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); 464 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); 465 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 466 int32_t raw_index, int scale, int32_t disp); 467 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 468 int32_t disp, int32_t raw_reg); 469 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 470 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 471 int32_t raw_disp, int32_t imm); 472 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); 473 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); 474 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 475 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 476 int32_t imm); 477 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, 478 int32_t imm); 479 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 480 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 481 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 482 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 483 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); 484 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); 485 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 486 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); 487 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); 488 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); 489 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 490 int32_t cc); 491 492 void EmitJmp(const X86EncodingMap* entry, int32_t rel); 493 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); 494 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 495 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); 496 void EmitCallThread(const X86EncodingMap* entry, int32_t disp); 497 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 498 int32_t raw_index, int scale, int32_t table_or_disp); 499 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); 500 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 501 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 502 int64_t val, ConditionCode ccode); 503 void GenConstWide(RegLocation rl_dest, int64_t value); 504 void GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir); 505 void GenShiftByteVector(BasicBlock *bb, MIR *mir); 506 void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 507 void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 508 void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); 509 510 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 511 512 /* 513 * @brief Ensure that a temporary register is byte addressable. 514 * @returns a temporary guarenteed to be byte addressable. 515 */ 516 virtual RegStorage AllocateByteRegister(); 517 518 /* 519 * @brief Use a wide temporary as a 128-bit register 520 * @returns a 128-bit temporary register. 521 */ 522 virtual RegStorage Get128BitRegister(RegStorage reg); 523 524 /* 525 * @brief Check if a register is byte addressable. 526 * @returns true if a register is byte addressable. 527 */ 528 bool IsByteRegister(RegStorage reg); 529 bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; 530 531 /* 532 * @brief generate inline code for fast case of Strng.indexOf. 533 * @param info Call parameters 534 * @param zero_based 'true' if the index into the string is 0. 535 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 536 * generated. 537 */ 538 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 539 540 /** 541 * @brief Reserve a fixed number of vector registers from the register pool 542 * @details The mir->dalvikInsn.vA specifies an N such that vector registers 543 * [0..N-1] are removed from the temporary pool. The caller must call 544 * ReturnVectorRegisters before calling ReserveVectorRegisters again. 545 * Also sets the num_reserved_vector_regs_ to the specified value 546 * @param mir whose vA specifies the number of registers to reserve 547 */ 548 void ReserveVectorRegisters(MIR* mir); 549 550 /** 551 * @brief Return all the reserved vector registers to the temp pool 552 * @details Returns [0..num_reserved_vector_regs_] 553 */ 554 void ReturnVectorRegisters(); 555 556 /* 557 * @brief Load 128 bit constant into vector register. 558 * @param bb The basic block in which the MIR is from. 559 * @param mir The MIR whose opcode is kMirConstVector 560 * @note vA is the TypeSize for the register. 561 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. 562 */ 563 void GenConst128(BasicBlock* bb, MIR* mir); 564 565 /* 566 * @brief MIR to move a vectorized register to another. 567 * @param bb The basic block in which the MIR is from. 568 * @param mir The MIR whose opcode is kMirConstVector. 569 * @note vA: TypeSize 570 * @note vB: destination 571 * @note vC: source 572 */ 573 void GenMoveVector(BasicBlock *bb, MIR *mir); 574 575 /* 576 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. 577 * @param bb The basic block in which the MIR is from. 578 * @param mir The MIR whose opcode is kMirConstVector. 579 * @note vA: TypeSize 580 * @note vB: destination and source 581 * @note vC: source 582 */ 583 void GenMultiplyVector(BasicBlock *bb, MIR *mir); 584 585 /* 586 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. 587 * @param bb The basic block in which the MIR is from. 588 * @param mir The MIR whose opcode is kMirConstVector. 589 * @note vA: TypeSize 590 * @note vB: destination and source 591 * @note vC: source 592 */ 593 void GenAddVector(BasicBlock *bb, MIR *mir); 594 595 /* 596 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. 597 * @param bb The basic block in which the MIR is from. 598 * @param mir The MIR whose opcode is kMirConstVector. 599 * @note vA: TypeSize 600 * @note vB: destination and source 601 * @note vC: source 602 */ 603 void GenSubtractVector(BasicBlock *bb, MIR *mir); 604 605 /* 606 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. 607 * @param bb The basic block in which the MIR is from. 608 * @param mir The MIR whose opcode is kMirConstVector. 609 * @note vA: TypeSize 610 * @note vB: destination and source 611 * @note vC: immediate 612 */ 613 void GenShiftLeftVector(BasicBlock *bb, MIR *mir); 614 615 /* 616 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. 617 * @param bb The basic block in which the MIR is from. 618 * @param mir The MIR whose opcode is kMirConstVector. 619 * @note vA: TypeSize 620 * @note vB: destination and source 621 * @note vC: immediate 622 */ 623 void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); 624 625 /* 626 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. 627 * @param bb The basic block in which the MIR is from.. 628 * @param mir The MIR whose opcode is kMirConstVector. 629 * @note vA: TypeSize 630 * @note vB: destination and source 631 * @note vC: immediate 632 */ 633 void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); 634 635 /* 636 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. 637 * @note vA: TypeSize 638 * @note vB: destination and source 639 * @note vC: source 640 */ 641 void GenAndVector(BasicBlock *bb, MIR *mir); 642 643 /* 644 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. 645 * @param bb The basic block in which the MIR is from. 646 * @param mir The MIR whose opcode is kMirConstVector. 647 * @note vA: TypeSize 648 * @note vB: destination and source 649 * @note vC: source 650 */ 651 void GenOrVector(BasicBlock *bb, MIR *mir); 652 653 /* 654 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. 655 * @param bb The basic block in which the MIR is from. 656 * @param mir The MIR whose opcode is kMirConstVector. 657 * @note vA: TypeSize 658 * @note vB: destination and source 659 * @note vC: source 660 */ 661 void GenXorVector(BasicBlock *bb, MIR *mir); 662 663 /* 664 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits 665 * @param bb The basic block in which the MIR is from. 666 * @param mir The MIR whose opcode is kMirConstVector. 667 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. 668 * @note vA: TypeSize 669 * @note vB: destination and source VR (not vector register) 670 * @note vC: source (vector register) 671 */ 672 void GenAddReduceVector(BasicBlock *bb, MIR *mir); 673 674 /* 675 * @brief Extract a packed element into a single VR. 676 * @param bb The basic block in which the MIR is from. 677 * @param mir The MIR whose opcode is kMirConstVector. 678 * @note vA: TypeSize 679 * @note vB: destination VR (not vector register) 680 * @note vC: source (vector register) 681 * @note arg[0]: The index to use for extraction from vector register (which packed element). 682 */ 683 void GenReduceVector(BasicBlock *bb, MIR *mir); 684 685 /* 686 * @brief Create a vector value, with all TypeSize values equal to vC 687 * @param bb The basic block in which the MIR is from. 688 * @param mir The MIR whose opcode is kMirConstVector. 689 * @note vA: TypeSize. 690 * @note vB: destination vector register. 691 * @note vC: source VR (not vector register). 692 */ 693 void GenSetVector(BasicBlock *bb, MIR *mir); 694 695 /* 696 * @brief Generate code for a vector opcode. 697 * @param bb The basic block in which the MIR is from. 698 * @param mir The MIR whose opcode is a non-standard opcode. 699 */ 700 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 701 702 /* 703 * @brief Return the correct x86 opcode for the Dex operation 704 * @param op Dex opcode for the operation 705 * @param loc Register location of the operand 706 * @param is_high_op 'true' if this is an operation on the high word 707 * @param value Immediate value for the operation. Used for byte variants 708 * @returns the correct x86 opcode to perform the operation 709 */ 710 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 711 712 /* 713 * @brief Return the correct x86 opcode for the Dex operation 714 * @param op Dex opcode for the operation 715 * @param dest location of the destination. May be register or memory. 716 * @param rhs Location for the rhs of the operation. May be in register or memory. 717 * @param is_high_op 'true' if this is an operation on the high word 718 * @returns the correct x86 opcode to perform the operation 719 * @note at most one location may refer to memory 720 */ 721 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 722 bool is_high_op); 723 724 /* 725 * @brief Is this operation a no-op for this opcode and value 726 * @param op Dex opcode for the operation 727 * @param value Immediate value for the operation. 728 * @returns 'true' if the operation will have no effect 729 */ 730 bool IsNoOp(Instruction::Code op, int32_t value); 731 732 /** 733 * @brief Calculate magic number and shift for a given divisor 734 * @param divisor divisor number for calculation 735 * @param magic hold calculated magic number 736 * @param shift hold calculated shift 737 */ 738 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 739 740 /* 741 * @brief Generate an integer div or rem operation. 742 * @param rl_dest Destination Location. 743 * @param rl_src1 Numerator Location. 744 * @param rl_src2 Divisor Location. 745 * @param is_div 'true' if this is a division, 'false' for a remainder. 746 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 747 */ 748 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 749 bool is_div, bool check_zero); 750 751 /* 752 * @brief Generate an integer div or rem operation by a literal. 753 * @param rl_dest Destination Location. 754 * @param rl_src Numerator Location. 755 * @param lit Divisor. 756 * @param is_div 'true' if this is a division, 'false' for a remainder. 757 */ 758 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 759 760 /* 761 * Generate code to implement long shift operations. 762 * @param opcode The DEX opcode to specify the shift type. 763 * @param rl_dest The destination. 764 * @param rl_src The value to be shifted. 765 * @param shift_amount How much to shift. 766 * @returns the RegLocation of the result. 767 */ 768 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 769 RegLocation rl_src, int shift_amount); 770 /* 771 * Generate an imul of a register by a constant or a better sequence. 772 * @param dest Destination Register. 773 * @param src Source Register. 774 * @param val Constant multiplier. 775 */ 776 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 777 778 /* 779 * Generate an imul of a memory location by a constant or a better sequence. 780 * @param dest Destination Register. 781 * @param sreg Symbolic register. 782 * @param displacement Displacement on stack of Symbolic Register. 783 * @param val Constant multiplier. 784 */ 785 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 786 787 /* 788 * @brief Compare memory to immediate, and branch if condition true. 789 * @param cond The condition code that when true will branch to the target. 790 * @param temp_reg A temporary register that can be used if compare memory is not 791 * supported by the architecture. 792 * @param base_reg The register holding the base address. 793 * @param offset The offset from the base. 794 * @param check_value The immediate to compare to. 795 * @param target branch target (or nullptr) 796 * @param compare output for getting LIR for comparison (or nullptr) 797 */ 798 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 799 int offset, int check_value, LIR* target, LIR** compare); 800 801 /* 802 * Can this operation be using core registers without temporaries? 803 * @param rl_lhs Left hand operand. 804 * @param rl_rhs Right hand operand. 805 * @returns 'true' if the operation can proceed without needing temporary regs. 806 */ 807 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 808 809 /** 810 * @brief Generates inline code for conversion of long to FP by using x87/ 811 * @param rl_dest The destination of the FP. 812 * @param rl_src The source of the long. 813 * @param is_double 'true' if dealing with double, 'false' for float. 814 */ 815 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 816 817 /* 818 * @brief Perform MIR analysis before compiling method. 819 * @note Invokes Mir2LiR::Materialize after analysis. 820 */ 821 void Materialize(); 822 823 /* 824 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 825 * without regard to data type. In practice, this can result in UpdateLoc returning a 826 * location record for a Dalvik float value in a core register, and vis-versa. For targets 827 * which can inexpensively move data between core and float registers, this can often be a win. 828 * However, for x86 this is generally not a win. These variants of UpdateLoc() 829 * take a register class argument - and will return an in-register location record only if 830 * the value is live in a temp register of the correct class. Additionally, if the value is in 831 * a temp register of the wrong register class, it will be clobbered. 832 */ 833 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 834 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 835 836 /* 837 * @brief Analyze MIR before generating code, to prepare for the code generation. 838 */ 839 void AnalyzeMIR(); 840 841 /* 842 * @brief Analyze one basic block. 843 * @param bb Basic block to analyze. 844 */ 845 void AnalyzeBB(BasicBlock * bb); 846 847 /* 848 * @brief Analyze one extended MIR instruction 849 * @param opcode MIR instruction opcode. 850 * @param bb Basic block containing instruction. 851 * @param mir Extended instruction to analyze. 852 */ 853 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 854 855 /* 856 * @brief Analyze one MIR instruction 857 * @param opcode MIR instruction opcode. 858 * @param bb Basic block containing instruction. 859 * @param mir Instruction to analyze. 860 */ 861 virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 862 863 /* 864 * @brief Analyze one MIR float/double instruction 865 * @param opcode MIR instruction opcode. 866 * @param bb Basic block containing instruction. 867 * @param mir Instruction to analyze. 868 */ 869 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 870 871 /* 872 * @brief Analyze one use of a double operand. 873 * @param rl_use Double RegLocation for the operand. 874 */ 875 void AnalyzeDoubleUse(RegLocation rl_use); 876 877 /* 878 * @brief Analyze one invoke-static MIR instruction 879 * @param opcode MIR instruction opcode. 880 * @param bb Basic block containing instruction. 881 * @param mir Instruction to analyze. 882 */ 883 void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); 884 885 // Information derived from analysis of MIR 886 887 // The compiler temporary for the code address of the method. 888 CompilerTemp *base_of_code_; 889 890 // Have we decided to compute a ptr to code and store in temporary VR? 891 bool store_method_addr_; 892 893 // Have we used the stored method address? 894 bool store_method_addr_used_; 895 896 // Instructions to remove if we didn't use the stored method address. 897 LIR* setup_method_address_[2]; 898 899 // Instructions needing patching with Method* values. 900 GrowableArray<LIR*> method_address_insns_; 901 902 // Instructions needing patching with Class Type* values. 903 GrowableArray<LIR*> class_type_address_insns_; 904 905 // Instructions needing patching with PC relative code addresses. 906 GrowableArray<LIR*> call_method_insns_; 907 908 // Prologue decrement of stack pointer. 909 LIR* stack_decrement_; 910 911 // Epilogue increment of stack pointer. 912 LIR* stack_increment_; 913 914 // The list of const vector literals. 915 LIR *const_vectors_; 916 917 /* 918 * @brief Search for a matching vector literal 919 * @param mir A kMirOpConst128b MIR instruction to match. 920 * @returns pointer to matching LIR constant, or nullptr if not found. 921 */ 922 LIR *ScanVectorLiteral(MIR *mir); 923 924 /* 925 * @brief Add a constant vector literal 926 * @param mir A kMirOpConst128b MIR instruction to match. 927 */ 928 LIR *AddVectorLiteral(MIR *mir); 929 930 InToRegStorageMapping in_to_reg_storage_mapping_; 931 932 bool WideGPRsAreAliases() OVERRIDE { 933 return cu_->target64; // On 64b, we have 64b GPRs. 934 } 935 bool WideFPRsAreAliases() OVERRIDE { 936 return true; // xmm registers have 64b views even on x86. 937 } 938 939 private: 940 // The number of vector registers [0..N] reserved by a call to ReserveVectorRegisters 941 int num_reserved_vector_regs_; 942}; 943 944} // namespace art 945 946#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 947