target_x86.cc revision 089142cf1d0c028b5a7c703baf0b97f4a4ada3f7
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "mirror/array.h" 24#include "mirror/string.h" 25#include "x86_lir.h" 26 27namespace art { 28 29static constexpr RegStorage core_regs_arr_32[] = { 30 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, 31}; 32static constexpr RegStorage core_regs_arr_64[] = { 33 rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_64, rs_rBP, rs_rSI, rs_rDI, 34#ifdef TARGET_REX_SUPPORT 35 rs_r8, rs_r9, rs_r10, rs_r11, rs_r12, rs_r13, rs_r14, rs_r15 36#endif 37}; 38static constexpr RegStorage core_regs_arr_64q[] = { 39 rs_r0q, rs_r1q, rs_r2q, rs_r3q, rs_rX86_SP_64, rs_r5q, rs_r6q, rs_r7q, 40#ifdef TARGET_REX_SUPPORT 41 rs_r8q, rs_r9q, rs_r10q, rs_r11q, rs_r12q, rs_r13q, rs_r14q, rs_r15q 42#endif 43}; 44static constexpr RegStorage sp_regs_arr_32[] = { 45 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 46}; 47static constexpr RegStorage sp_regs_arr_64[] = { 48 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 49#ifdef TARGET_REX_SUPPORT 50 rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 51#endif 52}; 53static constexpr RegStorage dp_regs_arr_32[] = { 54 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 55}; 56static constexpr RegStorage dp_regs_arr_64[] = { 57 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 58#ifdef TARGET_REX_SUPPORT 59 rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 60#endif 61}; 62static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}; 63static constexpr RegStorage reserved_regs_arr_64[] = {rs_rX86_SP_64}; 64static constexpr RegStorage reserved_regs_arr_64q[] = {rs_rX86_SP_64}; 65static constexpr RegStorage core_temps_arr_32[] = {rs_rAX, rs_rCX, rs_rDX, rs_rBX}; 66static constexpr RegStorage core_temps_arr_64[] = { 67 rs_rAX, rs_rCX, rs_rDX, rs_rSI, rs_rDI, 68#ifdef TARGET_REX_SUPPORT 69 rs_r8, rs_r9, rs_r10, rs_r11 70#endif 71}; 72static constexpr RegStorage core_temps_arr_64q[] = { 73 rs_r0q, rs_r1q, rs_r2q, rs_r6q, rs_r7q, 74#ifdef TARGET_REX_SUPPORT 75 rs_r8q, rs_r9q, rs_r10q, rs_r11q 76#endif 77}; 78static constexpr RegStorage sp_temps_arr_32[] = { 79 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 80}; 81static constexpr RegStorage sp_temps_arr_64[] = { 82 rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, 83#ifdef TARGET_REX_SUPPORT 84 rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 85#endif 86}; 87static constexpr RegStorage dp_temps_arr_32[] = { 88 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 89}; 90static constexpr RegStorage dp_temps_arr_64[] = { 91 rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, 92#ifdef TARGET_REX_SUPPORT 93 rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 94#endif 95}; 96 97static constexpr RegStorage xp_temps_arr_32[] = { 98 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 99}; 100static constexpr RegStorage xp_temps_arr_64[] = { 101 rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, 102#ifdef TARGET_REX_SUPPORT 103 rs_xr8, rs_xr9, rs_xr10, rs_xr11, rs_xr12, rs_xr13, rs_xr14, rs_xr15 104#endif 105}; 106 107static constexpr ArrayRef<const RegStorage> empty_pool; 108static constexpr ArrayRef<const RegStorage> core_regs_32(core_regs_arr_32); 109static constexpr ArrayRef<const RegStorage> core_regs_64(core_regs_arr_64); 110static constexpr ArrayRef<const RegStorage> core_regs_64q(core_regs_arr_64q); 111static constexpr ArrayRef<const RegStorage> sp_regs_32(sp_regs_arr_32); 112static constexpr ArrayRef<const RegStorage> sp_regs_64(sp_regs_arr_64); 113static constexpr ArrayRef<const RegStorage> dp_regs_32(dp_regs_arr_32); 114static constexpr ArrayRef<const RegStorage> dp_regs_64(dp_regs_arr_64); 115static constexpr ArrayRef<const RegStorage> reserved_regs_32(reserved_regs_arr_32); 116static constexpr ArrayRef<const RegStorage> reserved_regs_64(reserved_regs_arr_64); 117static constexpr ArrayRef<const RegStorage> reserved_regs_64q(reserved_regs_arr_64q); 118static constexpr ArrayRef<const RegStorage> core_temps_32(core_temps_arr_32); 119static constexpr ArrayRef<const RegStorage> core_temps_64(core_temps_arr_64); 120static constexpr ArrayRef<const RegStorage> core_temps_64q(core_temps_arr_64q); 121static constexpr ArrayRef<const RegStorage> sp_temps_32(sp_temps_arr_32); 122static constexpr ArrayRef<const RegStorage> sp_temps_64(sp_temps_arr_64); 123static constexpr ArrayRef<const RegStorage> dp_temps_32(dp_temps_arr_32); 124static constexpr ArrayRef<const RegStorage> dp_temps_64(dp_temps_arr_64); 125 126static constexpr ArrayRef<const RegStorage> xp_temps_32(xp_temps_arr_32); 127static constexpr ArrayRef<const RegStorage> xp_temps_64(xp_temps_arr_64); 128 129RegStorage rs_rX86_SP; 130 131X86NativeRegisterPool rX86_ARG0; 132X86NativeRegisterPool rX86_ARG1; 133X86NativeRegisterPool rX86_ARG2; 134X86NativeRegisterPool rX86_ARG3; 135X86NativeRegisterPool rX86_FARG0; 136X86NativeRegisterPool rX86_FARG1; 137X86NativeRegisterPool rX86_FARG2; 138X86NativeRegisterPool rX86_FARG3; 139X86NativeRegisterPool rX86_RET0; 140X86NativeRegisterPool rX86_RET1; 141X86NativeRegisterPool rX86_INVOKE_TGT; 142X86NativeRegisterPool rX86_COUNT; 143 144RegStorage rs_rX86_ARG0; 145RegStorage rs_rX86_ARG1; 146RegStorage rs_rX86_ARG2; 147RegStorage rs_rX86_ARG3; 148RegStorage rs_rX86_FARG0; 149RegStorage rs_rX86_FARG1; 150RegStorage rs_rX86_FARG2; 151RegStorage rs_rX86_FARG3; 152RegStorage rs_rX86_RET0; 153RegStorage rs_rX86_RET1; 154RegStorage rs_rX86_INVOKE_TGT; 155RegStorage rs_rX86_COUNT; 156 157RegLocation X86Mir2Lir::LocCReturn() { 158 return x86_loc_c_return; 159} 160 161RegLocation X86Mir2Lir::LocCReturnRef() { 162 // FIXME: return x86_loc_c_return_wide for x86_64 when wide refs supported. 163 return x86_loc_c_return; 164} 165 166RegLocation X86Mir2Lir::LocCReturnWide() { 167 return x86_loc_c_return_wide; 168} 169 170RegLocation X86Mir2Lir::LocCReturnFloat() { 171 return x86_loc_c_return_float; 172} 173 174RegLocation X86Mir2Lir::LocCReturnDouble() { 175 return x86_loc_c_return_double; 176} 177 178// Return a target-dependent special register. 179RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 180 RegStorage res_reg = RegStorage::InvalidReg(); 181 switch (reg) { 182 case kSelf: res_reg = RegStorage::InvalidReg(); break; 183 case kSuspend: res_reg = RegStorage::InvalidReg(); break; 184 case kLr: res_reg = RegStorage::InvalidReg(); break; 185 case kPc: res_reg = RegStorage::InvalidReg(); break; 186 case kSp: res_reg = rs_rX86_SP; break; 187 case kArg0: res_reg = rs_rX86_ARG0; break; 188 case kArg1: res_reg = rs_rX86_ARG1; break; 189 case kArg2: res_reg = rs_rX86_ARG2; break; 190 case kArg3: res_reg = rs_rX86_ARG3; break; 191 case kFArg0: res_reg = rs_rX86_FARG0; break; 192 case kFArg1: res_reg = rs_rX86_FARG1; break; 193 case kFArg2: res_reg = rs_rX86_FARG2; break; 194 case kFArg3: res_reg = rs_rX86_FARG3; break; 195 case kRet0: res_reg = rs_rX86_RET0; break; 196 case kRet1: res_reg = rs_rX86_RET1; break; 197 case kInvokeTgt: res_reg = rs_rX86_INVOKE_TGT; break; 198 case kHiddenArg: res_reg = rs_rAX; break; 199 case kHiddenFpArg: res_reg = rs_fr0; break; 200 case kCount: res_reg = rs_rX86_COUNT; break; 201 } 202 return res_reg; 203} 204 205RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 206 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 207 // TODO: This is not 64-bit compliant and depends on new internal ABI. 208 switch (arg_num) { 209 case 0: 210 return rs_rX86_ARG1; 211 case 1: 212 return rs_rX86_ARG2; 213 case 2: 214 return rs_rX86_ARG3; 215 default: 216 return RegStorage::InvalidReg(); 217 } 218} 219 220/* 221 * Decode the register id. 222 */ 223uint64_t X86Mir2Lir::GetRegMaskCommon(RegStorage reg) { 224 uint64_t seed; 225 int shift; 226 int reg_id; 227 228 reg_id = reg.GetRegNum(); 229 /* Double registers in x86 are just a single FP register */ 230 seed = 1; 231 /* FP register starts at bit position 16 */ 232 shift = (reg.IsFloat() || reg.StorageSize() > 8) ? kX86FPReg0 : 0; 233 /* Expand the double register id into single offset */ 234 shift += reg_id; 235 return (seed << shift); 236} 237 238uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 239 /* 240 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 241 * able to clean up some of the x86/Arm_Mips differences 242 */ 243 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 244 return 0ULL; 245} 246 247void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 248 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 249 DCHECK(!lir->flags.use_def_invalid); 250 251 // X86-specific resource map setup here. 252 if (flags & REG_USE_SP) { 253 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 254 } 255 256 if (flags & REG_DEF_SP) { 257 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 258 } 259 260 if (flags & REG_DEFA) { 261 SetupRegMask(&lir->u.m.def_mask, rs_rAX.GetReg()); 262 } 263 264 if (flags & REG_DEFD) { 265 SetupRegMask(&lir->u.m.def_mask, rs_rDX.GetReg()); 266 } 267 if (flags & REG_USEA) { 268 SetupRegMask(&lir->u.m.use_mask, rs_rAX.GetReg()); 269 } 270 271 if (flags & REG_USEC) { 272 SetupRegMask(&lir->u.m.use_mask, rs_rCX.GetReg()); 273 } 274 275 if (flags & REG_USED) { 276 SetupRegMask(&lir->u.m.use_mask, rs_rDX.GetReg()); 277 } 278 279 if (flags & REG_USEB) { 280 SetupRegMask(&lir->u.m.use_mask, rs_rBX.GetReg()); 281 } 282 283 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 284 if (lir->opcode == kX86RepneScasw) { 285 SetupRegMask(&lir->u.m.use_mask, rs_rAX.GetReg()); 286 SetupRegMask(&lir->u.m.use_mask, rs_rCX.GetReg()); 287 SetupRegMask(&lir->u.m.use_mask, rs_rDI.GetReg()); 288 SetupRegMask(&lir->u.m.def_mask, rs_rDI.GetReg()); 289 } 290 291 if (flags & USE_FP_STACK) { 292 lir->u.m.use_mask |= ENCODE_X86_FP_STACK; 293 lir->u.m.def_mask |= ENCODE_X86_FP_STACK; 294 } 295} 296 297/* For dumping instructions */ 298static const char* x86RegName[] = { 299 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 300 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 301}; 302 303static const char* x86CondName[] = { 304 "O", 305 "NO", 306 "B/NAE/C", 307 "NB/AE/NC", 308 "Z/EQ", 309 "NZ/NE", 310 "BE/NA", 311 "NBE/A", 312 "S", 313 "NS", 314 "P/PE", 315 "NP/PO", 316 "L/NGE", 317 "NL/GE", 318 "LE/NG", 319 "NLE/G" 320}; 321 322/* 323 * Interpret a format string and build a string no longer than size 324 * See format key in Assemble.cc. 325 */ 326std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 327 std::string buf; 328 size_t i = 0; 329 size_t fmt_len = strlen(fmt); 330 while (i < fmt_len) { 331 if (fmt[i] != '!') { 332 buf += fmt[i]; 333 i++; 334 } else { 335 i++; 336 DCHECK_LT(i, fmt_len); 337 char operand_number_ch = fmt[i]; 338 i++; 339 if (operand_number_ch == '!') { 340 buf += "!"; 341 } else { 342 int operand_number = operand_number_ch - '0'; 343 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 344 DCHECK_LT(i, fmt_len); 345 int operand = lir->operands[operand_number]; 346 switch (fmt[i]) { 347 case 'c': 348 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 349 buf += x86CondName[operand]; 350 break; 351 case 'd': 352 buf += StringPrintf("%d", operand); 353 break; 354 case 'p': { 355 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 356 buf += StringPrintf("0x%08x", tab_rec->offset); 357 break; 358 } 359 case 'r': 360 if (RegStorage::IsFloat(operand)) { 361 int fp_reg = RegStorage::RegNum(operand); 362 buf += StringPrintf("xmm%d", fp_reg); 363 } else { 364 int reg_num = RegStorage::RegNum(operand); 365 DCHECK_LT(static_cast<size_t>(reg_num), sizeof(x86RegName)); 366 buf += x86RegName[reg_num]; 367 } 368 break; 369 case 't': 370 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 371 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 372 lir->target); 373 break; 374 default: 375 buf += StringPrintf("DecodeError '%c'", fmt[i]); 376 break; 377 } 378 i++; 379 } 380 } 381 } 382 return buf; 383} 384 385void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 386 char buf[256]; 387 buf[0] = 0; 388 389 if (mask == ENCODE_ALL) { 390 strcpy(buf, "all"); 391 } else { 392 char num[8]; 393 int i; 394 395 for (i = 0; i < kX86RegEnd; i++) { 396 if (mask & (1ULL << i)) { 397 snprintf(num, arraysize(num), "%d ", i); 398 strcat(buf, num); 399 } 400 } 401 402 if (mask & ENCODE_CCODE) { 403 strcat(buf, "cc "); 404 } 405 /* Memory bits */ 406 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 407 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 408 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 409 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 410 } 411 if (mask & ENCODE_LITERAL) { 412 strcat(buf, "lit "); 413 } 414 415 if (mask & ENCODE_HEAP_REF) { 416 strcat(buf, "heap "); 417 } 418 if (mask & ENCODE_MUST_NOT_ALIAS) { 419 strcat(buf, "noalias "); 420 } 421 } 422 if (buf[0]) { 423 LOG(INFO) << prefix << ": " << buf; 424 } 425} 426 427void X86Mir2Lir::AdjustSpillMask() { 428 // Adjustment for LR spilling, x86 has no LR so nothing to do here 429 core_spill_mask_ |= (1 << rs_rRET.GetRegNum()); 430 num_core_spills_++; 431} 432 433/* 434 * Mark a callee-save fp register as promoted. Note that 435 * vpush/vpop uses contiguous register lists so we must 436 * include any holes in the mask. Associate holes with 437 * Dalvik register INVALID_VREG (0xFFFFU). 438 */ 439void X86Mir2Lir::MarkPreservedSingle(int v_reg, RegStorage reg) { 440 UNIMPLEMENTED(FATAL) << "MarkPreservedSingle"; 441} 442 443void X86Mir2Lir::MarkPreservedDouble(int v_reg, RegStorage reg) { 444 UNIMPLEMENTED(FATAL) << "MarkPreservedDouble"; 445} 446 447RegStorage X86Mir2Lir::AllocateByteRegister() { 448 return AllocTypedTemp(false, kCoreReg); 449} 450 451/* Clobber all regs that might be used by an external C call */ 452void X86Mir2Lir::ClobberCallerSave() { 453 Clobber(rs_rAX); 454 Clobber(rs_rCX); 455 Clobber(rs_rDX); 456 Clobber(rs_rBX); 457} 458 459RegLocation X86Mir2Lir::GetReturnWideAlt() { 460 RegLocation res = LocCReturnWide(); 461 DCHECK(res.reg.GetLowReg() == rs_rAX.GetReg()); 462 DCHECK(res.reg.GetHighReg() == rs_rDX.GetReg()); 463 Clobber(rs_rAX); 464 Clobber(rs_rDX); 465 MarkInUse(rs_rAX); 466 MarkInUse(rs_rDX); 467 MarkWide(res.reg); 468 return res; 469} 470 471RegLocation X86Mir2Lir::GetReturnAlt() { 472 RegLocation res = LocCReturn(); 473 res.reg.SetReg(rs_rDX.GetReg()); 474 Clobber(rs_rDX); 475 MarkInUse(rs_rDX); 476 return res; 477} 478 479/* To be used when explicitly managing register use */ 480void X86Mir2Lir::LockCallTemps() { 481 LockTemp(rs_rX86_ARG0); 482 LockTemp(rs_rX86_ARG1); 483 LockTemp(rs_rX86_ARG2); 484 LockTemp(rs_rX86_ARG3); 485} 486 487/* To be used when explicitly managing register use */ 488void X86Mir2Lir::FreeCallTemps() { 489 FreeTemp(rs_rX86_ARG0); 490 FreeTemp(rs_rX86_ARG1); 491 FreeTemp(rs_rX86_ARG2); 492 FreeTemp(rs_rX86_ARG3); 493} 494 495bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { 496 switch (opcode) { 497 case kX86LockCmpxchgMR: 498 case kX86LockCmpxchgAR: 499 case kX86LockCmpxchg8bM: 500 case kX86LockCmpxchg8bA: 501 case kX86XchgMR: 502 case kX86Mfence: 503 // Atomic memory instructions provide full barrier. 504 return true; 505 default: 506 break; 507 } 508 509 // Conservative if cannot prove it provides full barrier. 510 return false; 511} 512 513bool X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 514#if ANDROID_SMP != 0 515 // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. 516 LIR* mem_barrier = last_lir_insn_; 517 518 bool ret = false; 519 /* 520 * According to the JSR-133 Cookbook, for x86 only StoreLoad barriers need memory fence. All other barriers 521 * (LoadLoad, LoadStore, StoreStore) are nops due to the x86 memory model. For those cases, all we need 522 * to ensure is that there is a scheduling barrier in place. 523 */ 524 if (barrier_kind == kStoreLoad) { 525 // If no LIR exists already that can be used a barrier, then generate an mfence. 526 if (mem_barrier == nullptr) { 527 mem_barrier = NewLIR0(kX86Mfence); 528 ret = true; 529 } 530 531 // If last instruction does not provide full barrier, then insert an mfence. 532 if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { 533 mem_barrier = NewLIR0(kX86Mfence); 534 ret = true; 535 } 536 } 537 538 // Now ensure that a scheduling barrier is in place. 539 if (mem_barrier == nullptr) { 540 GenBarrier(); 541 } else { 542 // Mark as a scheduling barrier. 543 DCHECK(!mem_barrier->flags.use_def_invalid); 544 mem_barrier->u.m.def_mask = ENCODE_ALL; 545 } 546 return ret; 547#else 548 return false; 549#endif 550} 551 552void X86Mir2Lir::CompilerInitializeRegAlloc() { 553 if (Gen64Bit()) { 554 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_64, empty_pool/*core_regs_64q*/, sp_regs_64, 555 dp_regs_64, reserved_regs_64, empty_pool/*reserved_regs_64q*/, 556 core_temps_64, empty_pool/*core_temps_64q*/, sp_temps_64, dp_temps_64); 557 } else { 558 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, sp_regs_32, 559 dp_regs_32, reserved_regs_32, empty_pool, 560 core_temps_32, empty_pool, sp_temps_32, dp_temps_32); 561 } 562 563 // Target-specific adjustments. 564 565 // Add in XMM registers. 566 const ArrayRef<const RegStorage> *xp_temps = Gen64Bit() ? &xp_temps_64 : &xp_temps_32; 567 for (RegStorage reg : *xp_temps) { 568 RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); 569 reginfo_map_.Put(reg.GetReg(), info); 570 info->SetIsTemp(true); 571 } 572 573 // Alias single precision xmm to double xmms. 574 // TODO: as needed, add larger vector sizes - alias all to the largest. 575 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); 576 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 577 int sp_reg_num = info->GetReg().GetRegNum(); 578 RegStorage xp_reg = RegStorage::Solo128(sp_reg_num); 579 RegisterInfo* xp_reg_info = GetRegInfo(xp_reg); 580 // 128-bit xmm vector register's master storage should refer to itself. 581 DCHECK_EQ(xp_reg_info, xp_reg_info->Master()); 582 583 // Redirect 32-bit vector's master storage to 128-bit vector. 584 info->SetMaster(xp_reg_info); 585 586 RegStorage dp_reg = RegStorage::Solo64(RegStorage::kFloatingPoint | sp_reg_num); 587 RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); 588 // Redirect 64-bit vector's master storage to 128-bit vector. 589 dp_reg_info->SetMaster(xp_reg_info); 590 } 591 592 // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. 593 // TODO: adjust for x86/hard float calling convention. 594 reg_pool_->next_core_reg_ = 2; 595 reg_pool_->next_sp_reg_ = 2; 596 reg_pool_->next_dp_reg_ = 1; 597} 598 599void X86Mir2Lir::SpillCoreRegs() { 600 if (num_core_spills_ == 0) { 601 return; 602 } 603 // Spill mask not including fake return address register 604 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 605 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 606 for (int reg = 0; mask; mask >>= 1, reg++) { 607 if (mask & 0x1) { 608 StoreWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 609 offset += GetInstructionSetPointerSize(cu_->instruction_set); 610 } 611 } 612} 613 614void X86Mir2Lir::UnSpillCoreRegs() { 615 if (num_core_spills_ == 0) { 616 return; 617 } 618 // Spill mask not including fake return address register 619 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); 620 int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); 621 for (int reg = 0; mask; mask >>= 1, reg++) { 622 if (mask & 0x1) { 623 LoadWordDisp(rs_rX86_SP, offset, RegStorage::Solo32(reg)); 624 offset += GetInstructionSetPointerSize(cu_->instruction_set); 625 } 626 } 627} 628 629bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 630 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 631} 632 633bool X86Mir2Lir::SupportsVolatileLoadStore(OpSize size) { 634 return true; 635} 636 637RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { 638 if (UNLIKELY(is_volatile)) { 639 // On x86, atomic 64-bit load/store requires an fp register. 640 // Smaller aligned load/store is atomic for both core and fp registers. 641 if (size == k64 || size == kDouble) { 642 return kFPReg; 643 } 644 } 645 return RegClassBySize(size); 646} 647 648X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena, bool gen64bit) 649 : Mir2Lir(cu, mir_graph, arena), 650 base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false), 651 method_address_insns_(arena, 100, kGrowableArrayMisc), 652 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 653 call_method_insns_(arena, 100, kGrowableArrayMisc), 654 stack_decrement_(nullptr), stack_increment_(nullptr), gen64bit_(gen64bit), 655 const_vectors_(nullptr) { 656 store_method_addr_used_ = false; 657 if (kIsDebugBuild) { 658 for (int i = 0; i < kX86Last; i++) { 659 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 660 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 661 << " is wrong: expecting " << i << ", seeing " 662 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 663 } 664 } 665 } 666 if (Gen64Bit()) { 667 rs_rX86_SP = rs_rX86_SP_64; 668 669 rs_rX86_ARG0 = rs_rDI; 670 rs_rX86_ARG1 = rs_rSI; 671 rs_rX86_ARG2 = rs_rDX; 672 rs_rX86_ARG3 = rs_rCX; 673 rX86_ARG0 = rDI; 674 rX86_ARG1 = rSI; 675 rX86_ARG2 = rDX; 676 rX86_ARG3 = rCX; 677 // TODO: ARG4(r8), ARG5(r9), floating point args. 678 } else { 679 rs_rX86_SP = rs_rX86_SP_32; 680 681 rs_rX86_ARG0 = rs_rAX; 682 rs_rX86_ARG1 = rs_rCX; 683 rs_rX86_ARG2 = rs_rDX; 684 rs_rX86_ARG3 = rs_rBX; 685 rX86_ARG0 = rAX; 686 rX86_ARG1 = rCX; 687 rX86_ARG2 = rDX; 688 rX86_ARG3 = rBX; 689 } 690 rs_rX86_FARG0 = rs_rAX; 691 rs_rX86_FARG1 = rs_rCX; 692 rs_rX86_FARG2 = rs_rDX; 693 rs_rX86_FARG3 = rs_rBX; 694 rs_rX86_RET0 = rs_rAX; 695 rs_rX86_RET1 = rs_rDX; 696 rs_rX86_INVOKE_TGT = rs_rAX; 697 rs_rX86_COUNT = rs_rCX; 698 rX86_FARG0 = rAX; 699 rX86_FARG1 = rCX; 700 rX86_FARG2 = rDX; 701 rX86_FARG3 = rBX; 702 rX86_RET0 = rAX; 703 rX86_RET1 = rDX; 704 rX86_INVOKE_TGT = rAX; 705 rX86_COUNT = rCX; 706} 707 708Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 709 ArenaAllocator* const arena) { 710 return new X86Mir2Lir(cu, mir_graph, arena, false); 711} 712 713Mir2Lir* X86_64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 714 ArenaAllocator* const arena) { 715 return new X86Mir2Lir(cu, mir_graph, arena, true); 716} 717 718// Not used in x86 719RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<4> offset) { 720 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 721 return RegStorage::InvalidReg(); 722} 723 724// Not used in x86 725RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<8> offset) { 726 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 727 return RegStorage::InvalidReg(); 728} 729 730LIR* X86Mir2Lir::CheckSuspendUsingLoad() { 731 LOG(FATAL) << "Unexpected use of CheckSuspendUsingLoad in x86"; 732 return nullptr; 733} 734 735uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 736 DCHECK(!IsPseudoLirOp(opcode)); 737 return X86Mir2Lir::EncodingMap[opcode].flags; 738} 739 740const char* X86Mir2Lir::GetTargetInstName(int opcode) { 741 DCHECK(!IsPseudoLirOp(opcode)); 742 return X86Mir2Lir::EncodingMap[opcode].name; 743} 744 745const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 746 DCHECK(!IsPseudoLirOp(opcode)); 747 return X86Mir2Lir::EncodingMap[opcode].fmt; 748} 749 750void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 751 // Can we do this directly to memory? 752 rl_dest = UpdateLocWide(rl_dest); 753 if ((rl_dest.location == kLocDalvikFrame) || 754 (rl_dest.location == kLocCompilerTemp)) { 755 int32_t val_lo = Low32Bits(value); 756 int32_t val_hi = High32Bits(value); 757 int r_base = TargetReg(kSp).GetReg(); 758 int displacement = SRegOffset(rl_dest.s_reg_low); 759 760 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 761 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 762 false /* is_load */, true /* is64bit */); 763 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); 764 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 765 false /* is_load */, true /* is64bit */); 766 return; 767 } 768 769 // Just use the standard code to do the generation. 770 Mir2Lir::GenConstWide(rl_dest, value); 771} 772 773// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 774void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 775 LOG(INFO) << "location: " << loc.location << ',' 776 << (loc.wide ? " w" : " ") 777 << (loc.defined ? " D" : " ") 778 << (loc.is_const ? " c" : " ") 779 << (loc.fp ? " F" : " ") 780 << (loc.core ? " C" : " ") 781 << (loc.ref ? " r" : " ") 782 << (loc.high_word ? " h" : " ") 783 << (loc.home ? " H" : " ") 784 << ", low: " << static_cast<int>(loc.reg.GetLowReg()) 785 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 786 << ", s_reg: " << loc.s_reg_low 787 << ", orig: " << loc.orig_sreg; 788} 789 790void X86Mir2Lir::Materialize() { 791 // A good place to put the analysis before starting. 792 AnalyzeMIR(); 793 794 // Now continue with regular code generation. 795 Mir2Lir::Materialize(); 796} 797 798void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, 799 SpecialTargetRegister symbolic_reg) { 800 /* 801 * For x86, just generate a 32 bit move immediate instruction, that will be filled 802 * in at 'link time'. For now, put a unique value based on target to ensure that 803 * code deduplication works. 804 */ 805 int target_method_idx = target_method.dex_method_index; 806 const DexFile* target_dex_file = target_method.dex_file; 807 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 808 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 809 810 // Generate the move instruction with the unique pointer and save index, dex_file, and type. 811 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg).GetReg(), 812 static_cast<int>(target_method_id_ptr), target_method_idx, 813 WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 814 AppendLIR(move); 815 method_address_insns_.Insert(move); 816} 817 818void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 819 /* 820 * For x86, just generate a 32 bit move immediate instruction, that will be filled 821 * in at 'link time'. For now, put a unique value based on target to ensure that 822 * code deduplication works. 823 */ 824 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 825 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 826 827 // Generate the move instruction with the unique pointer and save index and type. 828 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg).GetReg(), 829 static_cast<int>(ptr), type_idx); 830 AppendLIR(move); 831 class_type_address_insns_.Insert(move); 832} 833 834LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { 835 /* 836 * For x86, just generate a 32 bit call relative instruction, that will be filled 837 * in at 'link time'. For now, put a unique value based on target to ensure that 838 * code deduplication works. 839 */ 840 int target_method_idx = target_method.dex_method_index; 841 const DexFile* target_dex_file = target_method.dex_file; 842 const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); 843 uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); 844 845 // Generate the call instruction with the unique pointer and save index, dex_file, and type. 846 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), 847 target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); 848 AppendLIR(call); 849 call_method_insns_.Insert(call); 850 return call; 851} 852 853/* 854 * @brief Enter a 32 bit quantity into a buffer 855 * @param buf buffer. 856 * @param data Data value. 857 */ 858 859static void PushWord(std::vector<uint8_t>&buf, int32_t data) { 860 buf.push_back(data & 0xff); 861 buf.push_back((data >> 8) & 0xff); 862 buf.push_back((data >> 16) & 0xff); 863 buf.push_back((data >> 24) & 0xff); 864} 865 866void X86Mir2Lir::InstallLiteralPools() { 867 // These are handled differently for x86. 868 DCHECK(code_literal_list_ == nullptr); 869 DCHECK(method_literal_list_ == nullptr); 870 DCHECK(class_literal_list_ == nullptr); 871 872 // Align to 16 byte boundary. We have implicit knowledge that the start of the method is 873 // on a 4 byte boundary. How can I check this if it changes (other than aligned loads 874 // will fail at runtime)? 875 if (const_vectors_ != nullptr) { 876 int align_size = (16-4) - (code_buffer_.size() & 0xF); 877 if (align_size < 0) { 878 align_size += 16; 879 } 880 881 while (align_size > 0) { 882 code_buffer_.push_back(0); 883 align_size--; 884 } 885 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 886 PushWord(code_buffer_, p->operands[0]); 887 PushWord(code_buffer_, p->operands[1]); 888 PushWord(code_buffer_, p->operands[2]); 889 PushWord(code_buffer_, p->operands[3]); 890 } 891 } 892 893 // Handle the fixups for methods. 894 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 895 LIR* p = method_address_insns_.Get(i); 896 DCHECK_EQ(p->opcode, kX86Mov32RI); 897 uint32_t target_method_idx = p->operands[2]; 898 const DexFile* target_dex_file = 899 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); 900 901 // The offset to patch is the last 4 bytes of the instruction. 902 int patch_offset = p->offset + p->flags.size - 4; 903 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 904 cu_->method_idx, cu_->invoke_type, 905 target_method_idx, target_dex_file, 906 static_cast<InvokeType>(p->operands[4]), 907 patch_offset); 908 } 909 910 // Handle the fixups for class types. 911 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 912 LIR* p = class_type_address_insns_.Get(i); 913 DCHECK_EQ(p->opcode, kX86Mov32RI); 914 uint32_t target_method_idx = p->operands[2]; 915 916 // The offset to patch is the last 4 bytes of the instruction. 917 int patch_offset = p->offset + p->flags.size - 4; 918 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 919 cu_->method_idx, target_method_idx, patch_offset); 920 } 921 922 // And now the PC-relative calls to methods. 923 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 924 LIR* p = call_method_insns_.Get(i); 925 DCHECK_EQ(p->opcode, kX86CallI); 926 uint32_t target_method_idx = p->operands[1]; 927 const DexFile* target_dex_file = 928 reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); 929 930 // The offset to patch is the last 4 bytes of the instruction. 931 int patch_offset = p->offset + p->flags.size - 4; 932 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 933 cu_->method_idx, cu_->invoke_type, 934 target_method_idx, target_dex_file, 935 static_cast<InvokeType>(p->operands[3]), 936 patch_offset, -4 /* offset */); 937 } 938 939 // And do the normal processing. 940 Mir2Lir::InstallLiteralPools(); 941} 942 943/* 944 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 945 * otherwise bails to standard library code. 946 */ 947bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 948 ClobberCallerSave(); 949 LockCallTemps(); // Using fixed registers 950 951 // EAX: 16 bit character being searched. 952 // ECX: count: number of words to be searched. 953 // EDI: String being searched. 954 // EDX: temporary during execution. 955 // EBX: temporary during execution. 956 957 RegLocation rl_obj = info->args[0]; 958 RegLocation rl_char = info->args[1]; 959 RegLocation rl_start; // Note: only present in III flavor or IndexOf. 960 961 uint32_t char_value = 962 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 963 964 if (char_value > 0xFFFF) { 965 // We have to punt to the real String.indexOf. 966 return false; 967 } 968 969 // Okay, we are commited to inlining this. 970 RegLocation rl_return = GetReturn(kCoreReg); 971 RegLocation rl_dest = InlineTarget(info); 972 973 // Is the string non-NULL? 974 LoadValueDirectFixed(rl_obj, rs_rDX); 975 GenNullCheck(rs_rDX, info->opt_flags); 976 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 977 978 // Does the character fit in 16 bits? 979 LIR* slowpath_branch = nullptr; 980 if (rl_char.is_const) { 981 // We need the value in EAX. 982 LoadConstantNoClobber(rs_rAX, char_value); 983 } else { 984 // Character is not a constant; compare at runtime. 985 LoadValueDirectFixed(rl_char, rs_rAX); 986 slowpath_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr); 987 } 988 989 // From here down, we know that we are looking for a char that fits in 16 bits. 990 // Location of reference to data array within the String object. 991 int value_offset = mirror::String::ValueOffset().Int32Value(); 992 // Location of count within the String object. 993 int count_offset = mirror::String::CountOffset().Int32Value(); 994 // Starting offset within data array. 995 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 996 // Start of char data with array_. 997 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 998 999 // Character is in EAX. 1000 // Object pointer is in EDX. 1001 1002 // We need to preserve EDI, but have no spare registers, so push it on the stack. 1003 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 1004 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 1005 1006 // Compute the number of words to search in to rCX. 1007 Load32Disp(rs_rDX, count_offset, rs_rCX); 1008 LIR *length_compare = nullptr; 1009 int start_value = 0; 1010 bool is_index_on_stack = false; 1011 if (zero_based) { 1012 // We have to handle an empty string. Use special instruction JECXZ. 1013 length_compare = NewLIR0(kX86Jecxz8); 1014 } else { 1015 rl_start = info->args[2]; 1016 // We have to offset by the start index. 1017 if (rl_start.is_const) { 1018 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1019 start_value = std::max(start_value, 0); 1020 1021 // Is the start > count? 1022 length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr); 1023 1024 if (start_value != 0) { 1025 OpRegImm(kOpSub, rs_rCX, start_value); 1026 } 1027 } else { 1028 // Runtime start index. 1029 rl_start = UpdateLocTyped(rl_start, kCoreReg); 1030 if (rl_start.location == kLocPhysReg) { 1031 // Handle "start index < 0" case. 1032 OpRegReg(kOpXor, rs_rBX, rs_rBX); 1033 OpRegReg(kOpCmp, rl_start.reg, rs_rBX); 1034 OpCondRegReg(kOpCmov, kCondLt, rl_start.reg, rs_rBX); 1035 1036 // The length of the string should be greater than the start index. 1037 length_compare = OpCmpBranch(kCondLe, rs_rCX, rl_start.reg, nullptr); 1038 OpRegReg(kOpSub, rs_rCX, rl_start.reg); 1039 if (rl_start.reg == rs_rDI) { 1040 // The special case. We will use EDI further, so lets put start index to stack. 1041 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 1042 is_index_on_stack = true; 1043 } 1044 } else { 1045 // Load the start index from stack, remembering that we pushed EDI. 1046 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1047 Load32Disp(rs_rX86_SP, displacement, rs_rBX); 1048 OpRegReg(kOpXor, rs_rDI, rs_rDI); 1049 OpRegReg(kOpCmp, rs_rBX, rs_rDI); 1050 OpCondRegReg(kOpCmov, kCondLt, rs_rBX, rs_rDI); 1051 1052 length_compare = OpCmpBranch(kCondLe, rs_rCX, rs_rBX, nullptr); 1053 OpRegReg(kOpSub, rs_rCX, rs_rBX); 1054 // Put the start index to stack. 1055 NewLIR1(kX86Push32R, rs_rBX.GetReg()); 1056 is_index_on_stack = true; 1057 } 1058 } 1059 } 1060 DCHECK(length_compare != nullptr); 1061 1062 // ECX now contains the count in words to be searched. 1063 1064 // Load the address of the string into EBX. 1065 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1066 Load32Disp(rs_rDX, value_offset, rs_rDI); 1067 Load32Disp(rs_rDX, offset_offset, rs_rBX); 1068 OpLea(rs_rBX, rs_rDI, rs_rBX, 1, data_offset); 1069 1070 // Now compute into EDI where the search will start. 1071 if (zero_based || rl_start.is_const) { 1072 if (start_value == 0) { 1073 OpRegCopy(rs_rDI, rs_rBX); 1074 } else { 1075 NewLIR3(kX86Lea32RM, rs_rDI.GetReg(), rs_rBX.GetReg(), 2 * start_value); 1076 } 1077 } else { 1078 if (is_index_on_stack == true) { 1079 // Load the start index from stack. 1080 NewLIR1(kX86Pop32R, rs_rDX.GetReg()); 1081 OpLea(rs_rDI, rs_rBX, rs_rDX, 1, 0); 1082 } else { 1083 OpLea(rs_rDI, rs_rBX, rl_start.reg, 1, 0); 1084 } 1085 } 1086 1087 // EDI now contains the start of the string to be searched. 1088 // We are all prepared to do the search for the character. 1089 NewLIR0(kX86RepneScasw); 1090 1091 // Did we find a match? 1092 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1093 1094 // yes, we matched. Compute the index of the result. 1095 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1096 OpRegReg(kOpSub, rs_rDI, rs_rBX); 1097 OpRegImm(kOpAsr, rs_rDI, 1); 1098 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rs_rDI.GetReg(), -1); 1099 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1100 1101 // Failed to match; return -1. 1102 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1103 length_compare->target = not_found; 1104 failed_branch->target = not_found; 1105 LoadConstantNoClobber(rl_return.reg, -1); 1106 1107 // And join up at the end. 1108 all_done->target = NewLIR0(kPseudoTargetLabel); 1109 // Restore EDI from the stack. 1110 NewLIR1(kX86Pop32R, rs_rDI.GetReg()); 1111 1112 // Out of line code returns here. 1113 if (slowpath_branch != nullptr) { 1114 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1115 AddIntrinsicSlowPath(info, slowpath_branch, return_point); 1116 } 1117 1118 StoreValue(rl_dest, rl_return); 1119 return true; 1120} 1121 1122/* 1123 * @brief Enter an 'advance LOC' into the FDE buffer 1124 * @param buf FDE buffer. 1125 * @param increment Amount by which to increase the current location. 1126 */ 1127static void AdvanceLoc(std::vector<uint8_t>&buf, uint32_t increment) { 1128 if (increment < 64) { 1129 // Encoding in opcode. 1130 buf.push_back(0x1 << 6 | increment); 1131 } else if (increment < 256) { 1132 // Single byte delta. 1133 buf.push_back(0x02); 1134 buf.push_back(increment); 1135 } else if (increment < 256 * 256) { 1136 // Two byte delta. 1137 buf.push_back(0x03); 1138 buf.push_back(increment & 0xff); 1139 buf.push_back((increment >> 8) & 0xff); 1140 } else { 1141 // Four byte delta. 1142 buf.push_back(0x04); 1143 PushWord(buf, increment); 1144 } 1145} 1146 1147 1148std::vector<uint8_t>* X86CFIInitialization() { 1149 return X86Mir2Lir::ReturnCommonCallFrameInformation(); 1150} 1151 1152std::vector<uint8_t>* X86Mir2Lir::ReturnCommonCallFrameInformation() { 1153 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1154 1155 // Length of the CIE (except for this field). 1156 PushWord(*cfi_info, 16); 1157 1158 // CIE id. 1159 PushWord(*cfi_info, 0xFFFFFFFFU); 1160 1161 // Version: 3. 1162 cfi_info->push_back(0x03); 1163 1164 // Augmentation: empty string. 1165 cfi_info->push_back(0x0); 1166 1167 // Code alignment: 1. 1168 cfi_info->push_back(0x01); 1169 1170 // Data alignment: -4. 1171 cfi_info->push_back(0x7C); 1172 1173 // Return address register (R8). 1174 cfi_info->push_back(0x08); 1175 1176 // Initial return PC is 4(ESP): DW_CFA_def_cfa R4 4. 1177 cfi_info->push_back(0x0C); 1178 cfi_info->push_back(0x04); 1179 cfi_info->push_back(0x04); 1180 1181 // Return address location: 0(SP): DW_CFA_offset R8 1 (* -4);. 1182 cfi_info->push_back(0x2 << 6 | 0x08); 1183 cfi_info->push_back(0x01); 1184 1185 // And 2 Noops to align to 4 byte boundary. 1186 cfi_info->push_back(0x0); 1187 cfi_info->push_back(0x0); 1188 1189 DCHECK_EQ(cfi_info->size() & 3, 0U); 1190 return cfi_info; 1191} 1192 1193static void EncodeUnsignedLeb128(std::vector<uint8_t>& buf, uint32_t value) { 1194 uint8_t buffer[12]; 1195 uint8_t *ptr = EncodeUnsignedLeb128(buffer, value); 1196 for (uint8_t *p = buffer; p < ptr; p++) { 1197 buf.push_back(*p); 1198 } 1199} 1200 1201std::vector<uint8_t>* X86Mir2Lir::ReturnCallFrameInformation() { 1202 std::vector<uint8_t>*cfi_info = new std::vector<uint8_t>; 1203 1204 // Generate the FDE for the method. 1205 DCHECK_NE(data_offset_, 0U); 1206 1207 // Length (will be filled in later in this routine). 1208 PushWord(*cfi_info, 0); 1209 1210 // CIE_pointer (can be filled in by linker); might be left at 0 if there is only 1211 // one CIE for the whole debug_frame section. 1212 PushWord(*cfi_info, 0); 1213 1214 // 'initial_location' (filled in by linker). 1215 PushWord(*cfi_info, 0); 1216 1217 // 'address_range' (number of bytes in the method). 1218 PushWord(*cfi_info, data_offset_); 1219 1220 // The instructions in the FDE. 1221 if (stack_decrement_ != nullptr) { 1222 // Advance LOC to just past the stack decrement. 1223 uint32_t pc = NEXT_LIR(stack_decrement_)->offset; 1224 AdvanceLoc(*cfi_info, pc); 1225 1226 // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. 1227 cfi_info->push_back(0x0e); 1228 EncodeUnsignedLeb128(*cfi_info, frame_size_); 1229 1230 // We continue with that stack until the epilogue. 1231 if (stack_increment_ != nullptr) { 1232 uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; 1233 AdvanceLoc(*cfi_info, new_pc - pc); 1234 1235 // We probably have code snippets after the epilogue, so save the 1236 // current state: DW_CFA_remember_state. 1237 cfi_info->push_back(0x0a); 1238 1239 // We have now popped the stack: DW_CFA_def_cfa_offset 4. There is only the return 1240 // PC on the stack now. 1241 cfi_info->push_back(0x0e); 1242 EncodeUnsignedLeb128(*cfi_info, 4); 1243 1244 // Everything after that is the same as before the epilogue. 1245 // Stack bump was followed by RET instruction. 1246 LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); 1247 if (post_ret_insn != nullptr) { 1248 pc = new_pc; 1249 new_pc = post_ret_insn->offset; 1250 AdvanceLoc(*cfi_info, new_pc - pc); 1251 // Restore the state: DW_CFA_restore_state. 1252 cfi_info->push_back(0x0b); 1253 } 1254 } 1255 } 1256 1257 // Padding to a multiple of 4 1258 while ((cfi_info->size() & 3) != 0) { 1259 // DW_CFA_nop is encoded as 0. 1260 cfi_info->push_back(0); 1261 } 1262 1263 // Set the length of the FDE inside the generated bytes. 1264 uint32_t length = cfi_info->size() - 4; 1265 (*cfi_info)[0] = length; 1266 (*cfi_info)[1] = length >> 8; 1267 (*cfi_info)[2] = length >> 16; 1268 (*cfi_info)[3] = length >> 24; 1269 return cfi_info; 1270} 1271 1272void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { 1273 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { 1274 case kMirOpConstVector: 1275 GenConst128(bb, mir); 1276 break; 1277 case kMirOpMoveVector: 1278 GenMoveVector(bb, mir); 1279 break; 1280 case kMirOpPackedMultiply: 1281 GenMultiplyVector(bb, mir); 1282 break; 1283 case kMirOpPackedAddition: 1284 GenAddVector(bb, mir); 1285 break; 1286 case kMirOpPackedSubtract: 1287 GenSubtractVector(bb, mir); 1288 break; 1289 case kMirOpPackedShiftLeft: 1290 GenShiftLeftVector(bb, mir); 1291 break; 1292 case kMirOpPackedSignedShiftRight: 1293 GenSignedShiftRightVector(bb, mir); 1294 break; 1295 case kMirOpPackedUnsignedShiftRight: 1296 GenUnsignedShiftRightVector(bb, mir); 1297 break; 1298 case kMirOpPackedAnd: 1299 GenAndVector(bb, mir); 1300 break; 1301 case kMirOpPackedOr: 1302 GenOrVector(bb, mir); 1303 break; 1304 case kMirOpPackedXor: 1305 GenXorVector(bb, mir); 1306 break; 1307 case kMirOpPackedAddReduce: 1308 GenAddReduceVector(bb, mir); 1309 break; 1310 case kMirOpPackedReduce: 1311 GenReduceVector(bb, mir); 1312 break; 1313 case kMirOpPackedSet: 1314 GenSetVector(bb, mir); 1315 break; 1316 default: 1317 break; 1318 } 1319} 1320 1321void X86Mir2Lir::GenConst128(BasicBlock* bb, MIR* mir) { 1322 int type_size = mir->dalvikInsn.vA; 1323 // We support 128 bit vectors. 1324 DCHECK_EQ(type_size & 0xFFFF, 128); 1325 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vB); 1326 uint32_t *args = mir->dalvikInsn.arg; 1327 int reg = rs_dest.GetReg(); 1328 // Check for all 0 case. 1329 if (args[0] == 0 && args[1] == 0 && args[2] == 0 && args[3] == 0) { 1330 NewLIR2(kX86XorpsRR, reg, reg); 1331 return; 1332 } 1333 // Okay, load it from the constant vector area. 1334 LIR *data_target = ScanVectorLiteral(mir); 1335 if (data_target == nullptr) { 1336 data_target = AddVectorLiteral(mir); 1337 } 1338 1339 // Address the start of the method. 1340 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 1341 rl_method = LoadValue(rl_method, kCoreReg); 1342 1343 // Load the proper value from the literal area. 1344 // We don't know the proper offset for the value, so pick one that will force 1345 // 4 byte offset. We will fix this up in the assembler later to have the right 1346 // value. 1347 LIR *load = NewLIR3(kX86Mova128RM, reg, rl_method.reg.GetReg(), 256 /* bogus */); 1348 load->flags.fixup = kFixupLoad; 1349 load->target = data_target; 1350 SetMemRefType(load, true, kLiteral); 1351} 1352 1353void X86Mir2Lir::GenMoveVector(BasicBlock *bb, MIR *mir) { 1354 // We only support 128 bit registers. 1355 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1356 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vB); 1357 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vC); 1358 NewLIR2(kX86Mova128RR, rs_dest.GetReg(), rs_src.GetReg()); 1359} 1360 1361void X86Mir2Lir::GenMultiplyVector(BasicBlock *bb, MIR *mir) { 1362 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1363 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1364 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1365 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1366 int opcode = 0; 1367 switch (opsize) { 1368 case k32: 1369 opcode = kX86PmulldRR; 1370 break; 1371 case kSignedHalf: 1372 opcode = kX86PmullwRR; 1373 break; 1374 case kSingle: 1375 opcode = kX86MulpsRR; 1376 break; 1377 case kDouble: 1378 opcode = kX86MulpdRR; 1379 break; 1380 default: 1381 LOG(FATAL) << "Unsupported vector multiply " << opsize; 1382 break; 1383 } 1384 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1385} 1386 1387void X86Mir2Lir::GenAddVector(BasicBlock *bb, MIR *mir) { 1388 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1389 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1390 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1391 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1392 int opcode = 0; 1393 switch (opsize) { 1394 case k32: 1395 opcode = kX86PadddRR; 1396 break; 1397 case kSignedHalf: 1398 case kUnsignedHalf: 1399 opcode = kX86PaddwRR; 1400 break; 1401 case kUnsignedByte: 1402 case kSignedByte: 1403 opcode = kX86PaddbRR; 1404 break; 1405 case kSingle: 1406 opcode = kX86AddpsRR; 1407 break; 1408 case kDouble: 1409 opcode = kX86AddpdRR; 1410 break; 1411 default: 1412 LOG(FATAL) << "Unsupported vector addition " << opsize; 1413 break; 1414 } 1415 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1416} 1417 1418void X86Mir2Lir::GenSubtractVector(BasicBlock *bb, MIR *mir) { 1419 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1420 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1421 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1422 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1423 int opcode = 0; 1424 switch (opsize) { 1425 case k32: 1426 opcode = kX86PsubdRR; 1427 break; 1428 case kSignedHalf: 1429 case kUnsignedHalf: 1430 opcode = kX86PsubwRR; 1431 break; 1432 case kUnsignedByte: 1433 case kSignedByte: 1434 opcode = kX86PsubbRR; 1435 break; 1436 case kSingle: 1437 opcode = kX86SubpsRR; 1438 break; 1439 case kDouble: 1440 opcode = kX86SubpdRR; 1441 break; 1442 default: 1443 LOG(FATAL) << "Unsupported vector subtraction " << opsize; 1444 break; 1445 } 1446 NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1447} 1448 1449void X86Mir2Lir::GenShiftLeftVector(BasicBlock *bb, MIR *mir) { 1450 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1451 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1452 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1453 int imm = mir->dalvikInsn.vC; 1454 int opcode = 0; 1455 switch (opsize) { 1456 case k32: 1457 opcode = kX86PslldRI; 1458 break; 1459 case k64: 1460 opcode = kX86PsllqRI; 1461 break; 1462 case kSignedHalf: 1463 case kUnsignedHalf: 1464 opcode = kX86PsllwRI; 1465 break; 1466 default: 1467 LOG(FATAL) << "Unsupported vector shift left " << opsize; 1468 break; 1469 } 1470 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1471} 1472 1473void X86Mir2Lir::GenSignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1474 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1475 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1476 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1477 int imm = mir->dalvikInsn.vC; 1478 int opcode = 0; 1479 switch (opsize) { 1480 case k32: 1481 opcode = kX86PsradRI; 1482 break; 1483 case kSignedHalf: 1484 case kUnsignedHalf: 1485 opcode = kX86PsrawRI; 1486 break; 1487 default: 1488 LOG(FATAL) << "Unsupported vector signed shift right " << opsize; 1489 break; 1490 } 1491 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1492} 1493 1494void X86Mir2Lir::GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir) { 1495 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1496 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1497 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1498 int imm = mir->dalvikInsn.vC; 1499 int opcode = 0; 1500 switch (opsize) { 1501 case k32: 1502 opcode = kX86PsrldRI; 1503 break; 1504 case k64: 1505 opcode = kX86PsrlqRI; 1506 break; 1507 case kSignedHalf: 1508 case kUnsignedHalf: 1509 opcode = kX86PsrlwRI; 1510 break; 1511 default: 1512 LOG(FATAL) << "Unsupported vector unsigned shift right " << opsize; 1513 break; 1514 } 1515 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1516} 1517 1518void X86Mir2Lir::GenAndVector(BasicBlock *bb, MIR *mir) { 1519 // We only support 128 bit registers. 1520 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1521 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1522 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1523 NewLIR2(kX86PandRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1524} 1525 1526void X86Mir2Lir::GenOrVector(BasicBlock *bb, MIR *mir) { 1527 // We only support 128 bit registers. 1528 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1529 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1530 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1531 NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1532} 1533 1534void X86Mir2Lir::GenXorVector(BasicBlock *bb, MIR *mir) { 1535 // We only support 128 bit registers. 1536 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1537 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1538 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vC); 1539 NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); 1540} 1541 1542void X86Mir2Lir::GenAddReduceVector(BasicBlock *bb, MIR *mir) { 1543 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1544 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1545 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); 1546 int imm = mir->dalvikInsn.vC; 1547 int opcode = 0; 1548 switch (opsize) { 1549 case k32: 1550 opcode = kX86PhadddRR; 1551 break; 1552 case kSignedHalf: 1553 case kUnsignedHalf: 1554 opcode = kX86PhaddwRR; 1555 break; 1556 default: 1557 LOG(FATAL) << "Unsupported vector add reduce " << opsize; 1558 break; 1559 } 1560 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); 1561} 1562 1563void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) { 1564 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1565 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1566 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB); 1567 int index = mir->dalvikInsn.arg[0]; 1568 int opcode = 0; 1569 switch (opsize) { 1570 case k32: 1571 opcode = kX86PextrdRRI; 1572 break; 1573 case kSignedHalf: 1574 case kUnsignedHalf: 1575 opcode = kX86PextrwRRI; 1576 break; 1577 case kUnsignedByte: 1578 case kSignedByte: 1579 opcode = kX86PextrbRRI; 1580 break; 1581 default: 1582 LOG(FATAL) << "Unsupported vector reduce " << opsize; 1583 break; 1584 } 1585 // We need to extract to a GPR. 1586 RegStorage temp = AllocTemp(); 1587 NewLIR3(opcode, temp.GetReg(), rs_src.GetReg(), index); 1588 1589 // Assume that the destination VR is in the def for the mir. 1590 RegLocation rl_dest = mir_graph_->GetDest(mir); 1591 RegLocation rl_temp = 1592 {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, temp, INVALID_SREG, INVALID_SREG}; 1593 StoreValue(rl_dest, rl_temp); 1594} 1595 1596void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { 1597 DCHECK_EQ(mir->dalvikInsn.vA & 0xFFFF, 128U); 1598 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vA >> 16); 1599 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vB); 1600 int op_low = 0, op_high = 0; 1601 switch (opsize) { 1602 case k32: 1603 op_low = kX86PshufdRRI; 1604 break; 1605 case kSignedHalf: 1606 case kUnsignedHalf: 1607 // Handles low quadword. 1608 op_low = kX86PshuflwRRI; 1609 // Handles upper quadword. 1610 op_high = kX86PshufdRRI; 1611 break; 1612 default: 1613 LOG(FATAL) << "Unsupported vector set " << opsize; 1614 break; 1615 } 1616 1617 // Load the value from the VR into a GPR. 1618 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 1619 rl_src = LoadValue(rl_src, kCoreReg); 1620 1621 // Load the value into the XMM register. 1622 NewLIR2(kX86MovdxrRR, rs_dest.GetReg(), rl_src.reg.GetReg()); 1623 1624 // Now shuffle the value across the destination. 1625 NewLIR3(op_low, rs_dest.GetReg(), rs_dest.GetReg(), 0); 1626 1627 // And then repeat as needed. 1628 if (op_high != 0) { 1629 NewLIR3(op_high, rs_dest.GetReg(), rs_dest.GetReg(), 0); 1630 } 1631} 1632 1633 1634LIR *X86Mir2Lir::ScanVectorLiteral(MIR *mir) { 1635 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 1636 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 1637 if (args[0] == p->operands[0] && args[1] == p->operands[1] && 1638 args[2] == p->operands[2] && args[3] == p->operands[3]) { 1639 return p; 1640 } 1641 } 1642 return nullptr; 1643} 1644 1645LIR *X86Mir2Lir::AddVectorLiteral(MIR *mir) { 1646 LIR* new_value = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocData)); 1647 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); 1648 new_value->operands[0] = args[0]; 1649 new_value->operands[1] = args[1]; 1650 new_value->operands[2] = args[2]; 1651 new_value->operands[3] = args[3]; 1652 new_value->next = const_vectors_; 1653 if (const_vectors_ == nullptr) { 1654 estimated_native_code_size_ += 12; // Amount needed to align to 16 byte boundary. 1655 } 1656 estimated_native_code_size_ += 16; // Space for one vector. 1657 const_vectors_ = new_value; 1658 return new_value; 1659} 1660 1661} // namespace art 1662