target_x86.cc revision 2c1ed456dcdb027d097825dd98dbe48c71599b6c
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "mirror/array.h" 24#include "mirror/string.h" 25#include "x86_lir.h" 26 27namespace art { 28 29// FIXME: restore "static" when usage uncovered 30/*static*/ int core_regs[] = { 31 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 32#ifdef TARGET_REX_SUPPORT 33 r8, r9, r10, r11, r12, r13, r14, 15 34#endif 35}; 36/*static*/ int ReservedRegs[] = {rX86_SP}; 37/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 38/*static*/ int FpRegs[] = { 39 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 40#ifdef TARGET_REX_SUPPORT 41 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 42#endif 43}; 44/*static*/ int fp_temps[] = { 45 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 46#ifdef TARGET_REX_SUPPORT 47 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 48#endif 49}; 50 51RegLocation X86Mir2Lir::LocCReturn() { 52 return x86_loc_c_return; 53} 54 55RegLocation X86Mir2Lir::LocCReturnWide() { 56 return x86_loc_c_return_wide; 57} 58 59RegLocation X86Mir2Lir::LocCReturnFloat() { 60 return x86_loc_c_return_float; 61} 62 63RegLocation X86Mir2Lir::LocCReturnDouble() { 64 return x86_loc_c_return_double; 65} 66 67// Return a target-dependent special register. 68int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 69 int res = INVALID_REG; 70 switch (reg) { 71 case kSelf: res = rX86_SELF; break; 72 case kSuspend: res = rX86_SUSPEND; break; 73 case kLr: res = rX86_LR; break; 74 case kPc: res = rX86_PC; break; 75 case kSp: res = rX86_SP; break; 76 case kArg0: res = rX86_ARG0; break; 77 case kArg1: res = rX86_ARG1; break; 78 case kArg2: res = rX86_ARG2; break; 79 case kArg3: res = rX86_ARG3; break; 80 case kFArg0: res = rX86_FARG0; break; 81 case kFArg1: res = rX86_FARG1; break; 82 case kFArg2: res = rX86_FARG2; break; 83 case kFArg3: res = rX86_FARG3; break; 84 case kRet0: res = rX86_RET0; break; 85 case kRet1: res = rX86_RET1; break; 86 case kInvokeTgt: res = rX86_INVOKE_TGT; break; 87 case kHiddenArg: res = rAX; break; 88 case kHiddenFpArg: res = fr0; break; 89 case kCount: res = rX86_COUNT; break; 90 } 91 return res; 92} 93 94int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 95 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 96 // TODO: This is not 64-bit compliant and depends on new internal ABI. 97 switch (arg_num) { 98 case 0: 99 return rX86_ARG1; 100 case 1: 101 return rX86_ARG2; 102 case 2: 103 return rX86_ARG3; 104 default: 105 return INVALID_REG; 106 } 107} 108 109// Create a double from a pair of singles. 110int X86Mir2Lir::S2d(int low_reg, int high_reg) { 111 return X86_S2D(low_reg, high_reg); 112} 113 114// Return mask to strip off fp reg flags and bias. 115uint32_t X86Mir2Lir::FpRegMask() { 116 return X86_FP_REG_MASK; 117} 118 119// True if both regs single, both core or both double. 120bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 121 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 122} 123 124/* 125 * Decode the register id. 126 */ 127uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 128 uint64_t seed; 129 int shift; 130 int reg_id; 131 132 reg_id = reg & 0xf; 133 /* Double registers in x86 are just a single FP register */ 134 seed = 1; 135 /* FP register starts at bit position 16 */ 136 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 137 /* Expand the double register id into single offset */ 138 shift += reg_id; 139 return (seed << shift); 140} 141 142uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 143 /* 144 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 145 * able to clean up some of the x86/Arm_Mips differences 146 */ 147 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 148 return 0ULL; 149} 150 151void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 152 DCHECK_EQ(cu_->instruction_set, kX86); 153 DCHECK(!lir->flags.use_def_invalid); 154 155 // X86-specific resource map setup here. 156 if (flags & REG_USE_SP) { 157 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 158 } 159 160 if (flags & REG_DEF_SP) { 161 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 162 } 163 164 if (flags & REG_DEFA) { 165 SetupRegMask(&lir->u.m.def_mask, rAX); 166 } 167 168 if (flags & REG_DEFD) { 169 SetupRegMask(&lir->u.m.def_mask, rDX); 170 } 171 if (flags & REG_USEA) { 172 SetupRegMask(&lir->u.m.use_mask, rAX); 173 } 174 175 if (flags & REG_USEC) { 176 SetupRegMask(&lir->u.m.use_mask, rCX); 177 } 178 179 if (flags & REG_USED) { 180 SetupRegMask(&lir->u.m.use_mask, rDX); 181 } 182 183 if (flags & REG_USEB) { 184 SetupRegMask(&lir->u.m.use_mask, rBX); 185 } 186 187 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 188 if (lir->opcode == kX86RepneScasw) { 189 SetupRegMask(&lir->u.m.use_mask, rAX); 190 SetupRegMask(&lir->u.m.use_mask, rCX); 191 SetupRegMask(&lir->u.m.use_mask, rDI); 192 SetupRegMask(&lir->u.m.def_mask, rDI); 193 } 194} 195 196/* For dumping instructions */ 197static const char* x86RegName[] = { 198 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 199 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 200}; 201 202static const char* x86CondName[] = { 203 "O", 204 "NO", 205 "B/NAE/C", 206 "NB/AE/NC", 207 "Z/EQ", 208 "NZ/NE", 209 "BE/NA", 210 "NBE/A", 211 "S", 212 "NS", 213 "P/PE", 214 "NP/PO", 215 "L/NGE", 216 "NL/GE", 217 "LE/NG", 218 "NLE/G" 219}; 220 221/* 222 * Interpret a format string and build a string no longer than size 223 * See format key in Assemble.cc. 224 */ 225std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 226 std::string buf; 227 size_t i = 0; 228 size_t fmt_len = strlen(fmt); 229 while (i < fmt_len) { 230 if (fmt[i] != '!') { 231 buf += fmt[i]; 232 i++; 233 } else { 234 i++; 235 DCHECK_LT(i, fmt_len); 236 char operand_number_ch = fmt[i]; 237 i++; 238 if (operand_number_ch == '!') { 239 buf += "!"; 240 } else { 241 int operand_number = operand_number_ch - '0'; 242 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 243 DCHECK_LT(i, fmt_len); 244 int operand = lir->operands[operand_number]; 245 switch (fmt[i]) { 246 case 'c': 247 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 248 buf += x86CondName[operand]; 249 break; 250 case 'd': 251 buf += StringPrintf("%d", operand); 252 break; 253 case 'p': { 254 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 255 buf += StringPrintf("0x%08x", tab_rec->offset); 256 break; 257 } 258 case 'r': 259 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 260 int fp_reg = operand & X86_FP_REG_MASK; 261 buf += StringPrintf("xmm%d", fp_reg); 262 } else { 263 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 264 buf += x86RegName[operand]; 265 } 266 break; 267 case 't': 268 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 269 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 270 lir->target); 271 break; 272 default: 273 buf += StringPrintf("DecodeError '%c'", fmt[i]); 274 break; 275 } 276 i++; 277 } 278 } 279 } 280 return buf; 281} 282 283void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 284 char buf[256]; 285 buf[0] = 0; 286 287 if (mask == ENCODE_ALL) { 288 strcpy(buf, "all"); 289 } else { 290 char num[8]; 291 int i; 292 293 for (i = 0; i < kX86RegEnd; i++) { 294 if (mask & (1ULL << i)) { 295 snprintf(num, arraysize(num), "%d ", i); 296 strcat(buf, num); 297 } 298 } 299 300 if (mask & ENCODE_CCODE) { 301 strcat(buf, "cc "); 302 } 303 /* Memory bits */ 304 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 305 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 306 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 307 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 308 } 309 if (mask & ENCODE_LITERAL) { 310 strcat(buf, "lit "); 311 } 312 313 if (mask & ENCODE_HEAP_REF) { 314 strcat(buf, "heap "); 315 } 316 if (mask & ENCODE_MUST_NOT_ALIAS) { 317 strcat(buf, "noalias "); 318 } 319 } 320 if (buf[0]) { 321 LOG(INFO) << prefix << ": " << buf; 322 } 323} 324 325void X86Mir2Lir::AdjustSpillMask() { 326 // Adjustment for LR spilling, x86 has no LR so nothing to do here 327 core_spill_mask_ |= (1 << rRET); 328 num_core_spills_++; 329} 330 331/* 332 * Mark a callee-save fp register as promoted. Note that 333 * vpush/vpop uses contiguous register lists so we must 334 * include any holes in the mask. Associate holes with 335 * Dalvik register INVALID_VREG (0xFFFFU). 336 */ 337void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 338 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 339#if 0 340 LOG(FATAL) << "No support yet for promoted FP regs"; 341#endif 342} 343 344void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { 345 RegisterInfo* info1 = GetRegInfo(reg1); 346 RegisterInfo* info2 = GetRegInfo(reg2); 347 DCHECK(info1 && info2 && info1->pair && info2->pair && 348 (info1->partner == info2->reg) && 349 (info2->partner == info1->reg)); 350 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 351 if (!(info1->is_temp && info2->is_temp)) { 352 /* Should not happen. If it does, there's a problem in eval_loc */ 353 LOG(FATAL) << "Long half-temp, half-promoted"; 354 } 355 356 info1->dirty = false; 357 info2->dirty = false; 358 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 359 info1 = info2; 360 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 361 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); 362 } 363} 364 365void X86Mir2Lir::FlushReg(int reg) { 366 RegisterInfo* info = GetRegInfo(reg); 367 if (info->live && info->dirty) { 368 info->dirty = false; 369 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 370 StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); 371 } 372} 373 374/* Give access to the target-dependent FP register encoding to common code */ 375bool X86Mir2Lir::IsFpReg(int reg) { 376 return X86_FPREG(reg); 377} 378 379/* Clobber all regs that might be used by an external C call */ 380void X86Mir2Lir::ClobberCallerSave() { 381 Clobber(rAX); 382 Clobber(rCX); 383 Clobber(rDX); 384 Clobber(rBX); 385} 386 387RegLocation X86Mir2Lir::GetReturnWideAlt() { 388 RegLocation res = LocCReturnWide(); 389 CHECK(res.reg.GetReg() == rAX); 390 CHECK(res.reg.GetHighReg() == rDX); 391 Clobber(rAX); 392 Clobber(rDX); 393 MarkInUse(rAX); 394 MarkInUse(rDX); 395 MarkPair(res.reg.GetReg(), res.reg.GetHighReg()); 396 return res; 397} 398 399RegLocation X86Mir2Lir::GetReturnAlt() { 400 RegLocation res = LocCReturn(); 401 res.reg.SetReg(rDX); 402 Clobber(rDX); 403 MarkInUse(rDX); 404 return res; 405} 406 407/* To be used when explicitly managing register use */ 408void X86Mir2Lir::LockCallTemps() { 409 LockTemp(rX86_ARG0); 410 LockTemp(rX86_ARG1); 411 LockTemp(rX86_ARG2); 412 LockTemp(rX86_ARG3); 413} 414 415/* To be used when explicitly managing register use */ 416void X86Mir2Lir::FreeCallTemps() { 417 FreeTemp(rX86_ARG0); 418 FreeTemp(rX86_ARG1); 419 FreeTemp(rX86_ARG2); 420 FreeTemp(rX86_ARG3); 421} 422 423void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 424#if ANDROID_SMP != 0 425 // TODO: optimize fences 426 NewLIR0(kX86Mfence); 427#endif 428} 429 430// Alloc a pair of core registers, or a double. 431RegStorage X86Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { 432 int high_reg; 433 int low_reg; 434 435 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 436 low_reg = AllocTempDouble(); 437 high_reg = low_reg; // only one allocated! 438 // TODO: take advantage of 64-bit notation. 439 return RegStorage(RegStorage::k64BitPair, low_reg, high_reg); 440 } 441 low_reg = AllocTemp(); 442 high_reg = AllocTemp(); 443 return RegStorage(RegStorage::k64BitPair, low_reg, high_reg); 444} 445 446int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 447 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 448 return AllocTempFloat(); 449 } 450 return AllocTemp(); 451} 452 453void X86Mir2Lir::CompilerInitializeRegAlloc() { 454 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 455 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 456 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 457 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 458 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 459 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 460 ArenaAllocator::kAllocRegAlloc)); 461 reg_pool_->num_core_regs = num_regs; 462 reg_pool_->core_regs = 463 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 464 ArenaAllocator::kAllocRegAlloc)); 465 reg_pool_->num_fp_regs = num_fp_regs; 466 reg_pool_->FPRegs = 467 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 468 ArenaAllocator::kAllocRegAlloc)); 469 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 470 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 471 // Keep special registers from being allocated 472 for (int i = 0; i < num_reserved; i++) { 473 MarkInUse(ReservedRegs[i]); 474 } 475 // Mark temp regs - all others not in use can be used for promotion 476 for (int i = 0; i < num_temps; i++) { 477 MarkTemp(core_temps[i]); 478 } 479 for (int i = 0; i < num_fp_temps; i++) { 480 MarkTemp(fp_temps[i]); 481 } 482} 483 484void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, 485 RegLocation rl_free) { 486 if ((rl_free.reg.GetReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetReg() != rl_keep.reg.GetHighReg()) && 487 (rl_free.reg.GetHighReg() != rl_keep.reg.GetReg()) && (rl_free.reg.GetHighReg() != rl_keep.reg.GetHighReg())) { 488 // No overlap, free both 489 FreeTemp(rl_free.reg.GetReg()); 490 FreeTemp(rl_free.reg.GetHighReg()); 491 } 492} 493 494void X86Mir2Lir::SpillCoreRegs() { 495 if (num_core_spills_ == 0) { 496 return; 497 } 498 // Spill mask not including fake return address register 499 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 500 int offset = frame_size_ - (4 * num_core_spills_); 501 for (int reg = 0; mask; mask >>= 1, reg++) { 502 if (mask & 0x1) { 503 StoreWordDisp(rX86_SP, offset, reg); 504 offset += 4; 505 } 506 } 507} 508 509void X86Mir2Lir::UnSpillCoreRegs() { 510 if (num_core_spills_ == 0) { 511 return; 512 } 513 // Spill mask not including fake return address register 514 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 515 int offset = frame_size_ - (4 * num_core_spills_); 516 for (int reg = 0; mask; mask >>= 1, reg++) { 517 if (mask & 0x1) { 518 LoadWordDisp(rX86_SP, offset, reg); 519 offset += 4; 520 } 521 } 522} 523 524bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 525 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 526} 527 528X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 529 : Mir2Lir(cu, mir_graph, arena), 530 method_address_insns_(arena, 100, kGrowableArrayMisc), 531 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 532 call_method_insns_(arena, 100, kGrowableArrayMisc) { 533 store_method_addr_used_ = false; 534 for (int i = 0; i < kX86Last; i++) { 535 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 536 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 537 << " is wrong: expecting " << i << ", seeing " 538 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 539 } 540 } 541} 542 543Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 544 ArenaAllocator* const arena) { 545 return new X86Mir2Lir(cu, mir_graph, arena); 546} 547 548// Not used in x86 549int X86Mir2Lir::LoadHelper(ThreadOffset offset) { 550 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 551 return INVALID_REG; 552} 553 554uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 555 DCHECK(!IsPseudoLirOp(opcode)); 556 return X86Mir2Lir::EncodingMap[opcode].flags; 557} 558 559const char* X86Mir2Lir::GetTargetInstName(int opcode) { 560 DCHECK(!IsPseudoLirOp(opcode)); 561 return X86Mir2Lir::EncodingMap[opcode].name; 562} 563 564const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 565 DCHECK(!IsPseudoLirOp(opcode)); 566 return X86Mir2Lir::EncodingMap[opcode].fmt; 567} 568 569/* 570 * Return an updated location record with current in-register status. 571 * If the value lives in live temps, reflect that fact. No code 572 * is generated. If the live value is part of an older pair, 573 * clobber both low and high. 574 */ 575// TODO: Reunify with common code after 'pair mess' has been fixed 576RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) { 577 DCHECK(loc.wide); 578 DCHECK(CheckCorePoolSanity()); 579 if (loc.location != kLocPhysReg) { 580 DCHECK((loc.location == kLocDalvikFrame) || 581 (loc.location == kLocCompilerTemp)); 582 // Are the dalvik regs already live in physical registers? 583 RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); 584 585 // Handle FP registers specially on x86. 586 if (info_lo && IsFpReg(info_lo->reg)) { 587 bool match = true; 588 589 // We can't match a FP register with a pair of Core registers. 590 match = match && (info_lo->pair == 0); 591 592 if (match) { 593 // We can reuse;update the register usage info. 594 loc.location = kLocPhysReg; 595 loc.vec_len = kVectorLength8; 596 // TODO: use k64BitVector 597 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_lo->reg); 598 DCHECK(IsFpReg(loc.reg.GetReg())); 599 return loc; 600 } 601 // We can't easily reuse; clobber and free any overlaps. 602 if (info_lo) { 603 Clobber(info_lo->reg); 604 FreeTemp(info_lo->reg); 605 if (info_lo->pair) 606 Clobber(info_lo->partner); 607 } 608 } else { 609 RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); 610 bool match = true; 611 match = match && (info_lo != NULL); 612 match = match && (info_hi != NULL); 613 // Are they both core or both FP? 614 match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); 615 // If a pair of floating point singles, are they properly aligned? 616 if (match && IsFpReg(info_lo->reg)) { 617 match &= ((info_lo->reg & 0x1) == 0); 618 match &= ((info_hi->reg - info_lo->reg) == 1); 619 } 620 // If previously used as a pair, it is the same pair? 621 if (match && (info_lo->pair || info_hi->pair)) { 622 match = (info_lo->pair == info_hi->pair); 623 match &= ((info_lo->reg == info_hi->partner) && 624 (info_hi->reg == info_lo->partner)); 625 } 626 if (match) { 627 // Can reuse - update the register usage info 628 loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_hi->reg); 629 loc.location = kLocPhysReg; 630 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 631 DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); 632 return loc; 633 } 634 // Can't easily reuse - clobber and free any overlaps 635 if (info_lo) { 636 Clobber(info_lo->reg); 637 FreeTemp(info_lo->reg); 638 if (info_lo->pair) 639 Clobber(info_lo->partner); 640 } 641 if (info_hi) { 642 Clobber(info_hi->reg); 643 FreeTemp(info_hi->reg); 644 if (info_hi->pair) 645 Clobber(info_hi->partner); 646 } 647 } 648 } 649 return loc; 650} 651 652// TODO: Reunify with common code after 'pair mess' has been fixed 653RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { 654 DCHECK(loc.wide); 655 int32_t low_reg; 656 int32_t high_reg; 657 658 loc = UpdateLocWide(loc); 659 660 /* If it is already in a register, we can assume proper form. Is it the right reg class? */ 661 if (loc.location == kLocPhysReg) { 662 DCHECK_EQ(IsFpReg(loc.reg.GetReg()), loc.IsVectorScalar()); 663 if (!RegClassMatches(reg_class, loc.reg.GetReg())) { 664 /* It is the wrong register class. Reallocate and copy. */ 665 if (!IsFpReg(loc.reg.GetReg())) { 666 // We want this in a FP reg, and it is in core registers. 667 DCHECK(reg_class != kCoreReg); 668 // Allocate this into any FP reg, and mark it with the right size. 669 low_reg = AllocTypedTemp(true, reg_class); 670 OpVectorRegCopyWide(low_reg, loc.reg.GetReg(), loc.reg.GetHighReg()); 671 CopyRegInfo(low_reg, loc.reg.GetReg()); 672 Clobber(loc.reg.GetReg()); 673 Clobber(loc.reg.GetHighReg()); 674 loc.reg.SetReg(low_reg); 675 loc.reg.SetHighReg(low_reg); // Play nice with existing code. 676 loc.vec_len = kVectorLength8; 677 } else { 678 // The value is in a FP register, and we want it in a pair of core registers. 679 DCHECK_EQ(reg_class, kCoreReg); 680 DCHECK_EQ(loc.reg.GetReg(), loc.reg.GetHighReg()); 681 RegStorage new_regs = AllocTypedTempWide(false, kCoreReg); // Force to core registers. 682 low_reg = new_regs.GetReg(); 683 high_reg = new_regs.GetHighReg(); 684 DCHECK_NE(low_reg, high_reg); 685 OpRegCopyWide(low_reg, high_reg, loc.reg.GetReg(), loc.reg.GetHighReg()); 686 CopyRegInfo(low_reg, loc.reg.GetReg()); 687 CopyRegInfo(high_reg, loc.reg.GetHighReg()); 688 Clobber(loc.reg.GetReg()); 689 Clobber(loc.reg.GetHighReg()); 690 loc.reg = new_regs; 691 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 692 DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); 693 } 694 } 695 return loc; 696 } 697 698 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 699 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 700 701 loc.reg = AllocTypedTempWide(loc.fp, reg_class); 702 703 // FIXME: take advantage of RegStorage notation. 704 if (loc.reg.GetReg() == loc.reg.GetHighReg()) { 705 DCHECK(IsFpReg(loc.reg.GetReg())); 706 loc.vec_len = kVectorLength8; 707 } else { 708 MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); 709 } 710 if (update) { 711 loc.location = kLocPhysReg; 712 MarkLive(loc.reg.GetReg(), loc.s_reg_low); 713 if (loc.reg.GetReg() != loc.reg.GetHighReg()) { 714 MarkLive(loc.reg.GetHighReg(), GetSRegHi(loc.s_reg_low)); 715 } 716 } 717 return loc; 718} 719 720// TODO: Reunify with common code after 'pair mess' has been fixed 721RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { 722 int new_reg; 723 724 if (loc.wide) 725 return EvalLocWide(loc, reg_class, update); 726 727 loc = UpdateLoc(loc); 728 729 if (loc.location == kLocPhysReg) { 730 if (!RegClassMatches(reg_class, loc.reg.GetReg())) { 731 /* Wrong register class. Realloc, copy and transfer ownership. */ 732 new_reg = AllocTypedTemp(loc.fp, reg_class); 733 OpRegCopy(new_reg, loc.reg.GetReg()); 734 CopyRegInfo(new_reg, loc.reg.GetReg()); 735 Clobber(loc.reg.GetReg()); 736 loc.reg.SetReg(new_reg); 737 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 738 loc.vec_len = kVectorLength4; 739 } 740 return loc; 741 } 742 743 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 744 745 loc.reg = RegStorage(RegStorage::k32BitSolo, AllocTypedTemp(loc.fp, reg_class)); 746 if (IsFpReg(loc.reg.GetReg()) && reg_class != kCoreReg) 747 loc.vec_len = kVectorLength4; 748 749 if (update) { 750 loc.location = kLocPhysReg; 751 MarkLive(loc.reg.GetReg(), loc.s_reg_low); 752 } 753 return loc; 754} 755 756int X86Mir2Lir::AllocTempDouble() { 757 // We really don't need a pair of registers. 758 return AllocTempFloat(); 759} 760 761// TODO: Reunify with common code after 'pair mess' has been fixed 762void X86Mir2Lir::ResetDefLocWide(RegLocation rl) { 763 DCHECK(rl.wide); 764 RegisterInfo* p_low = IsTemp(rl.reg.GetReg()); 765 if (IsFpReg(rl.reg.GetReg())) { 766 // We are using only the low register. 767 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 768 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 769 } 770 ResetDef(rl.reg.GetReg()); 771 } else { 772 RegisterInfo* p_high = IsTemp(rl.reg.GetHighReg()); 773 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 774 DCHECK(p_low->pair); 775 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 776 } 777 if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { 778 DCHECK(p_high->pair); 779 } 780 ResetDef(rl.reg.GetReg()); 781 ResetDef(rl.reg.GetHighReg()); 782 } 783} 784 785void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 786 // Can we do this directly to memory? 787 rl_dest = UpdateLocWide(rl_dest); 788 if ((rl_dest.location == kLocDalvikFrame) || 789 (rl_dest.location == kLocCompilerTemp)) { 790 int32_t val_lo = Low32Bits(value); 791 int32_t val_hi = High32Bits(value); 792 int rBase = TargetReg(kSp); 793 int displacement = SRegOffset(rl_dest.s_reg_low); 794 795 LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo); 796 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 797 false /* is_load */, true /* is64bit */); 798 store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi); 799 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 800 false /* is_load */, true /* is64bit */); 801 return; 802 } 803 804 // Just use the standard code to do the generation. 805 Mir2Lir::GenConstWide(rl_dest, value); 806} 807 808// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 809void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 810 LOG(INFO) << "location: " << loc.location << ',' 811 << (loc.wide ? " w" : " ") 812 << (loc.defined ? " D" : " ") 813 << (loc.is_const ? " c" : " ") 814 << (loc.fp ? " F" : " ") 815 << (loc.core ? " C" : " ") 816 << (loc.ref ? " r" : " ") 817 << (loc.high_word ? " h" : " ") 818 << (loc.home ? " H" : " ") 819 << " vec_len: " << loc.vec_len 820 << ", low: " << static_cast<int>(loc.reg.GetReg()) 821 << ", high: " << static_cast<int>(loc.reg.GetHighReg()) 822 << ", s_reg: " << loc.s_reg_low 823 << ", orig: " << loc.orig_sreg; 824} 825 826void X86Mir2Lir::Materialize() { 827 // A good place to put the analysis before starting. 828 AnalyzeMIR(); 829 830 // Now continue with regular code generation. 831 Mir2Lir::Materialize(); 832} 833 834void X86Mir2Lir::LoadMethodAddress(int dex_method_index, InvokeType type, 835 SpecialTargetRegister symbolic_reg) { 836 /* 837 * For x86, just generate a 32 bit move immediate instruction, that will be filled 838 * in at 'link time'. For now, put a unique value based on target to ensure that 839 * code deduplication works. 840 */ 841 const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index); 842 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 843 844 // Generate the move instruction with the unique pointer and save index and type. 845 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 846 static_cast<int>(ptr), dex_method_index, type); 847 AppendLIR(move); 848 method_address_insns_.Insert(move); 849} 850 851void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 852 /* 853 * For x86, just generate a 32 bit move immediate instruction, that will be filled 854 * in at 'link time'. For now, put a unique value based on target to ensure that 855 * code deduplication works. 856 */ 857 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 858 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 859 860 // Generate the move instruction with the unique pointer and save index and type. 861 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 862 static_cast<int>(ptr), type_idx); 863 AppendLIR(move); 864 class_type_address_insns_.Insert(move); 865} 866 867LIR *X86Mir2Lir::CallWithLinkerFixup(int dex_method_index, InvokeType type) { 868 /* 869 * For x86, just generate a 32 bit call relative instruction, that will be filled 870 * in at 'link time'. For now, put a unique value based on target to ensure that 871 * code deduplication works. 872 */ 873 const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index); 874 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 875 876 // Generate the call instruction with the unique pointer and save index and type. 877 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(ptr), dex_method_index, 878 type); 879 AppendLIR(call); 880 call_method_insns_.Insert(call); 881 return call; 882} 883 884void X86Mir2Lir::InstallLiteralPools() { 885 // These are handled differently for x86. 886 DCHECK(code_literal_list_ == nullptr); 887 DCHECK(method_literal_list_ == nullptr); 888 DCHECK(class_literal_list_ == nullptr); 889 890 // Handle the fixups for methods. 891 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 892 LIR* p = method_address_insns_.Get(i); 893 DCHECK_EQ(p->opcode, kX86Mov32RI); 894 uint32_t target = p->operands[2]; 895 896 // The offset to patch is the last 4 bytes of the instruction. 897 int patch_offset = p->offset + p->flags.size - 4; 898 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 899 cu_->method_idx, cu_->invoke_type, 900 target, static_cast<InvokeType>(p->operands[3]), 901 patch_offset); 902 } 903 904 // Handle the fixups for class types. 905 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 906 LIR* p = class_type_address_insns_.Get(i); 907 DCHECK_EQ(p->opcode, kX86Mov32RI); 908 uint32_t target = p->operands[2]; 909 910 // The offset to patch is the last 4 bytes of the instruction. 911 int patch_offset = p->offset + p->flags.size - 4; 912 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 913 cu_->method_idx, target, patch_offset); 914 } 915 916 // And now the PC-relative calls to methods. 917 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 918 LIR* p = call_method_insns_.Get(i); 919 DCHECK_EQ(p->opcode, kX86CallI); 920 uint32_t target = p->operands[1]; 921 922 // The offset to patch is the last 4 bytes of the instruction. 923 int patch_offset = p->offset + p->flags.size - 4; 924 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 925 cu_->method_idx, cu_->invoke_type, target, 926 static_cast<InvokeType>(p->operands[2]), 927 patch_offset, -4 /* offset */); 928 } 929 930 // And do the normal processing. 931 Mir2Lir::InstallLiteralPools(); 932} 933 934/* 935 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 936 * otherwise bails to standard library code. 937 */ 938bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 939 ClobberCallerSave(); 940 LockCallTemps(); // Using fixed registers 941 942 // EAX: 16 bit character being searched. 943 // ECX: count: number of words to be searched. 944 // EDI: String being searched. 945 // EDX: temporary during execution. 946 // EBX: temporary during execution. 947 948 RegLocation rl_obj = info->args[0]; 949 RegLocation rl_char = info->args[1]; 950 RegLocation rl_start = info->args[2]; 951 952 uint32_t char_value = 953 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 954 955 if (char_value > 0xFFFF) { 956 // We have to punt to the real String.indexOf. 957 return false; 958 } 959 960 // Okay, we are commited to inlining this. 961 RegLocation rl_return = GetReturn(false); 962 RegLocation rl_dest = InlineTarget(info); 963 964 // Is the string non-NULL? 965 LoadValueDirectFixed(rl_obj, rDX); 966 GenNullCheck(rl_obj.s_reg_low, rDX, info->opt_flags); 967 968 // Record that we have inlined & null checked the object. 969 info->opt_flags |= (MIR_INLINED | MIR_IGNORE_NULL_CHECK); 970 971 // Does the character fit in 16 bits? 972 LIR* launch_pad = nullptr; 973 if (rl_char.is_const) { 974 // We need the value in EAX. 975 LoadConstantNoClobber(rAX, char_value); 976 } else { 977 // Character is not a constant; compare at runtime. 978 LoadValueDirectFixed(rl_char, rAX); 979 launch_pad = RawLIR(0, kPseudoIntrinsicRetry, WrapPointer(info)); 980 intrinsic_launchpads_.Insert(launch_pad); 981 OpCmpImmBranch(kCondGt, rAX, 0xFFFF, launch_pad); 982 } 983 984 // From here down, we know that we are looking for a char that fits in 16 bits. 985 // Location of reference to data array within the String object. 986 int value_offset = mirror::String::ValueOffset().Int32Value(); 987 // Location of count within the String object. 988 int count_offset = mirror::String::CountOffset().Int32Value(); 989 // Starting offset within data array. 990 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 991 // Start of char data with array_. 992 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 993 994 // Character is in EAX. 995 // Object pointer is in EDX. 996 997 // We need to preserve EDI, but have no spare registers, so push it on the stack. 998 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 999 NewLIR1(kX86Push32R, rDI); 1000 1001 // Compute the number of words to search in to rCX. 1002 LoadWordDisp(rDX, count_offset, rCX); 1003 LIR *length_compare = nullptr; 1004 int start_value = 0; 1005 if (zero_based) { 1006 // We have to handle an empty string. Use special instruction JECXZ. 1007 length_compare = NewLIR0(kX86Jecxz8); 1008 } else { 1009 // We have to offset by the start index. 1010 if (rl_start.is_const) { 1011 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1012 start_value = std::max(start_value, 0); 1013 1014 // Is the start > count? 1015 length_compare = OpCmpImmBranch(kCondLe, rCX, start_value, nullptr); 1016 1017 if (start_value != 0) { 1018 OpRegImm(kOpSub, rCX, start_value); 1019 } 1020 } else { 1021 // Runtime start index. 1022 rl_start = UpdateLoc(rl_start); 1023 if (rl_start.location == kLocPhysReg) { 1024 length_compare = OpCmpBranch(kCondLe, rCX, rl_start.reg.GetReg(), nullptr); 1025 OpRegReg(kOpSub, rCX, rl_start.reg.GetReg()); 1026 } else { 1027 // Compare to memory to avoid a register load. Handle pushed EDI. 1028 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1029 OpRegMem(kOpCmp, rDX, rX86_SP, displacement); 1030 length_compare = NewLIR2(kX86Jcc8, 0, kX86CondLe); 1031 OpRegMem(kOpSub, rCX, rX86_SP, displacement); 1032 } 1033 } 1034 } 1035 DCHECK(length_compare != nullptr); 1036 1037 // ECX now contains the count in words to be searched. 1038 1039 // Load the address of the string into EBX. 1040 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1041 LoadWordDisp(rDX, value_offset, rDI); 1042 LoadWordDisp(rDX, offset_offset, rBX); 1043 OpLea(rBX, rDI, rBX, 1, data_offset); 1044 1045 // Now compute into EDI where the search will start. 1046 if (zero_based || rl_start.is_const) { 1047 if (start_value == 0) { 1048 OpRegCopy(rDI, rBX); 1049 } else { 1050 NewLIR3(kX86Lea32RM, rDI, rBX, 2 * start_value); 1051 } 1052 } else { 1053 if (rl_start.location == kLocPhysReg) { 1054 if (rl_start.reg.GetReg() == rDI) { 1055 // We have a slight problem here. We are already using RDI! 1056 // Grab the value from the stack. 1057 LoadWordDisp(rX86_SP, 0, rDX); 1058 OpLea(rDI, rBX, rDX, 1, 0); 1059 } else { 1060 OpLea(rDI, rBX, rl_start.reg.GetReg(), 1, 0); 1061 } 1062 } else { 1063 OpRegCopy(rDI, rBX); 1064 // Load the start index from stack, remembering that we pushed EDI. 1065 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1066 LoadWordDisp(rX86_SP, displacement, rDX); 1067 OpLea(rDI, rBX, rDX, 1, 0); 1068 } 1069 } 1070 1071 // EDI now contains the start of the string to be searched. 1072 // We are all prepared to do the search for the character. 1073 NewLIR0(kX86RepneScasw); 1074 1075 // Did we find a match? 1076 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1077 1078 // yes, we matched. Compute the index of the result. 1079 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1080 OpRegReg(kOpSub, rDI, rBX); 1081 OpRegImm(kOpAsr, rDI, 1); 1082 NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rDI, -1); 1083 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1084 1085 // Failed to match; return -1. 1086 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1087 length_compare->target = not_found; 1088 failed_branch->target = not_found; 1089 LoadConstantNoClobber(rl_return.reg.GetReg(), -1); 1090 1091 // And join up at the end. 1092 all_done->target = NewLIR0(kPseudoTargetLabel); 1093 // Restore EDI from the stack. 1094 NewLIR1(kX86Pop32R, rDI); 1095 1096 // Out of line code returns here. 1097 if (launch_pad != nullptr) { 1098 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1099 launch_pad->operands[2] = WrapPointer(return_point); 1100 } 1101 1102 StoreValue(rl_dest, rl_return); 1103 return true; 1104} 1105 1106} // namespace art 1107