target_x86.cc revision 3bc01748ef1c3e43361bdf520947a9d656658bf8 
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "codegen_x86.h"
18#include "dex/compiler_internals.h"
19#include "dex/quick/mir_to_lir-inl.h"
20#include "x86_lir.h"
21
22#include <string>
23
24namespace art {
25
26// FIXME: restore "static" when usage uncovered
27/*static*/ int core_regs[] = {
28  rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI
29#ifdef TARGET_REX_SUPPORT
30  r8, r9, r10, r11, r12, r13, r14, 15
31#endif
32};
33/*static*/ int ReservedRegs[] = {rX86_SP};
34/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX};
35/*static*/ int FpRegs[] = {
36  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
37#ifdef TARGET_REX_SUPPORT
38  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
39#endif
40};
41/*static*/ int fp_temps[] = {
42  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
43#ifdef TARGET_REX_SUPPORT
44  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
45#endif
46};
47
48RegLocation X86Mir2Lir::LocCReturn() {
49  RegLocation res = X86_LOC_C_RETURN;
50  return res;
51}
52
53RegLocation X86Mir2Lir::LocCReturnWide() {
54  RegLocation res = X86_LOC_C_RETURN_WIDE;
55  return res;
56}
57
58RegLocation X86Mir2Lir::LocCReturnFloat() {
59  RegLocation res = X86_LOC_C_RETURN_FLOAT;
60  return res;
61}
62
63RegLocation X86Mir2Lir::LocCReturnDouble() {
64  RegLocation res = X86_LOC_C_RETURN_DOUBLE;
65  return res;
66}
67
68// Return a target-dependent special register.
69int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) {
70  int res = INVALID_REG;
71  switch (reg) {
72    case kSelf: res = rX86_SELF; break;
73    case kSuspend: res =  rX86_SUSPEND; break;
74    case kLr: res =  rX86_LR; break;
75    case kPc: res =  rX86_PC; break;
76    case kSp: res =  rX86_SP; break;
77    case kArg0: res = rX86_ARG0; break;
78    case kArg1: res = rX86_ARG1; break;
79    case kArg2: res = rX86_ARG2; break;
80    case kArg3: res = rX86_ARG3; break;
81    case kFArg0: res = rX86_FARG0; break;
82    case kFArg1: res = rX86_FARG1; break;
83    case kFArg2: res = rX86_FARG2; break;
84    case kFArg3: res = rX86_FARG3; break;
85    case kRet0: res = rX86_RET0; break;
86    case kRet1: res = rX86_RET1; break;
87    case kInvokeTgt: res = rX86_INVOKE_TGT; break;
88    case kHiddenArg: res = rAX; break;
89    case kHiddenFpArg: res = fr0; break;
90    case kCount: res = rX86_COUNT; break;
91  }
92  return res;
93}
94
95int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
96  // For the 32-bit internal ABI, the first 3 arguments are passed in registers.
97  // TODO: This is not 64-bit compliant and depends on new internal ABI.
98  switch (arg_num) {
99    case 0:
100      return rX86_ARG1;
101    case 1:
102      return rX86_ARG2;
103    case 2:
104      return rX86_ARG3;
105    default:
106      return INVALID_REG;
107  }
108}
109
110// Create a double from a pair of singles.
111int X86Mir2Lir::S2d(int low_reg, int high_reg) {
112  return X86_S2D(low_reg, high_reg);
113}
114
115// Return mask to strip off fp reg flags and bias.
116uint32_t X86Mir2Lir::FpRegMask() {
117  return X86_FP_REG_MASK;
118}
119
120// True if both regs single, both core or both double.
121bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
122  return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
123}
124
125/*
126 * Decode the register id.
127 */
128uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) {
129  uint64_t seed;
130  int shift;
131  int reg_id;
132
133  reg_id = reg & 0xf;
134  /* Double registers in x86 are just a single FP register */
135  seed = 1;
136  /* FP register starts at bit position 16 */
137  shift = X86_FPREG(reg) ? kX86FPReg0 : 0;
138  /* Expand the double register id into single offset */
139  shift += reg_id;
140  return (seed << shift);
141}
142
143uint64_t X86Mir2Lir::GetPCUseDefEncoding() {
144  /*
145   * FIXME: might make sense to use a virtual resource encoding bit for pc.  Might be
146   * able to clean up some of the x86/Arm_Mips differences
147   */
148  LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86";
149  return 0ULL;
150}
151
152void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) {
153  DCHECK_EQ(cu_->instruction_set, kX86);
154  DCHECK(!lir->flags.use_def_invalid);
155
156  // X86-specific resource map setup here.
157  if (flags & REG_USE_SP) {
158    lir->u.m.use_mask |= ENCODE_X86_REG_SP;
159  }
160
161  if (flags & REG_DEF_SP) {
162    lir->u.m.def_mask |= ENCODE_X86_REG_SP;
163  }
164
165  if (flags & REG_DEFA) {
166    SetupRegMask(&lir->u.m.def_mask, rAX);
167  }
168
169  if (flags & REG_DEFD) {
170    SetupRegMask(&lir->u.m.def_mask, rDX);
171  }
172  if (flags & REG_USEA) {
173    SetupRegMask(&lir->u.m.use_mask, rAX);
174  }
175
176  if (flags & REG_USEC) {
177    SetupRegMask(&lir->u.m.use_mask, rCX);
178  }
179
180  if (flags & REG_USED) {
181    SetupRegMask(&lir->u.m.use_mask, rDX);
182  }
183
184  if (flags & REG_USEB) {
185    SetupRegMask(&lir->u.m.use_mask, rBX);
186  }
187}
188
189/* For dumping instructions */
190static const char* x86RegName[] = {
191  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
192  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
193};
194
195static const char* x86CondName[] = {
196  "O",
197  "NO",
198  "B/NAE/C",
199  "NB/AE/NC",
200  "Z/EQ",
201  "NZ/NE",
202  "BE/NA",
203  "NBE/A",
204  "S",
205  "NS",
206  "P/PE",
207  "NP/PO",
208  "L/NGE",
209  "NL/GE",
210  "LE/NG",
211  "NLE/G"
212};
213
214/*
215 * Interpret a format string and build a string no longer than size
216 * See format key in Assemble.cc.
217 */
218std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
219  std::string buf;
220  size_t i = 0;
221  size_t fmt_len = strlen(fmt);
222  while (i < fmt_len) {
223    if (fmt[i] != '!') {
224      buf += fmt[i];
225      i++;
226    } else {
227      i++;
228      DCHECK_LT(i, fmt_len);
229      char operand_number_ch = fmt[i];
230      i++;
231      if (operand_number_ch == '!') {
232        buf += "!";
233      } else {
234        int operand_number = operand_number_ch - '0';
235        DCHECK_LT(operand_number, 6);  // Expect upto 6 LIR operands.
236        DCHECK_LT(i, fmt_len);
237        int operand = lir->operands[operand_number];
238        switch (fmt[i]) {
239          case 'c':
240            DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
241            buf += x86CondName[operand];
242            break;
243          case 'd':
244            buf += StringPrintf("%d", operand);
245            break;
246          case 'p': {
247            EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand));
248            buf += StringPrintf("0x%08x", tab_rec->offset);
249            break;
250          }
251          case 'r':
252            if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) {
253              int fp_reg = operand & X86_FP_REG_MASK;
254              buf += StringPrintf("xmm%d", fp_reg);
255            } else {
256              DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName));
257              buf += x86RegName[operand];
258            }
259            break;
260          case 't':
261            buf += StringPrintf("0x%08" PRIxPTR " (L%p)",
262                                reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand,
263                                lir->target);
264            break;
265          default:
266            buf += StringPrintf("DecodeError '%c'", fmt[i]);
267            break;
268        }
269        i++;
270      }
271    }
272  }
273  return buf;
274}
275
276void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) {
277  char buf[256];
278  buf[0] = 0;
279
280  if (mask == ENCODE_ALL) {
281    strcpy(buf, "all");
282  } else {
283    char num[8];
284    int i;
285
286    for (i = 0; i < kX86RegEnd; i++) {
287      if (mask & (1ULL << i)) {
288        snprintf(num, arraysize(num), "%d ", i);
289        strcat(buf, num);
290      }
291    }
292
293    if (mask & ENCODE_CCODE) {
294      strcat(buf, "cc ");
295    }
296    /* Memory bits */
297    if (x86LIR && (mask & ENCODE_DALVIK_REG)) {
298      snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
299               DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info),
300               (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : "");
301    }
302    if (mask & ENCODE_LITERAL) {
303      strcat(buf, "lit ");
304    }
305
306    if (mask & ENCODE_HEAP_REF) {
307      strcat(buf, "heap ");
308    }
309    if (mask & ENCODE_MUST_NOT_ALIAS) {
310      strcat(buf, "noalias ");
311    }
312  }
313  if (buf[0]) {
314    LOG(INFO) << prefix << ": " <<  buf;
315  }
316}
317
318void X86Mir2Lir::AdjustSpillMask() {
319  // Adjustment for LR spilling, x86 has no LR so nothing to do here
320  core_spill_mask_ |= (1 << rRET);
321  num_core_spills_++;
322}
323
324/*
325 * Mark a callee-save fp register as promoted.  Note that
326 * vpush/vpop uses contiguous register lists so we must
327 * include any holes in the mask.  Associate holes with
328 * Dalvik register INVALID_VREG (0xFFFFU).
329 */
330void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) {
331  UNIMPLEMENTED(WARNING) << "MarkPreservedSingle";
332#if 0
333  LOG(FATAL) << "No support yet for promoted FP regs";
334#endif
335}
336
337void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
338  RegisterInfo* info1 = GetRegInfo(reg1);
339  RegisterInfo* info2 = GetRegInfo(reg2);
340  DCHECK(info1 && info2 && info1->pair && info2->pair &&
341         (info1->partner == info2->reg) &&
342         (info2->partner == info1->reg));
343  if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
344    if (!(info1->is_temp && info2->is_temp)) {
345      /* Should not happen.  If it does, there's a problem in eval_loc */
346      LOG(FATAL) << "Long half-temp, half-promoted";
347    }
348
349    info1->dirty = false;
350    info2->dirty = false;
351    if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg))
352      info1 = info2;
353    int v_reg = mir_graph_->SRegToVReg(info1->s_reg);
354    StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner);
355  }
356}
357
358void X86Mir2Lir::FlushReg(int reg) {
359  RegisterInfo* info = GetRegInfo(reg);
360  if (info->live && info->dirty) {
361    info->dirty = false;
362    int v_reg = mir_graph_->SRegToVReg(info->s_reg);
363    StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord);
364  }
365}
366
367/* Give access to the target-dependent FP register encoding to common code */
368bool X86Mir2Lir::IsFpReg(int reg) {
369  return X86_FPREG(reg);
370}
371
372/* Clobber all regs that might be used by an external C call */
373void X86Mir2Lir::ClobberCallerSave() {
374  Clobber(rAX);
375  Clobber(rCX);
376  Clobber(rDX);
377  Clobber(rBX);
378}
379
380RegLocation X86Mir2Lir::GetReturnWideAlt() {
381  RegLocation res = LocCReturnWide();
382  CHECK(res.low_reg == rAX);
383  CHECK(res.high_reg == rDX);
384  Clobber(rAX);
385  Clobber(rDX);
386  MarkInUse(rAX);
387  MarkInUse(rDX);
388  MarkPair(res.low_reg, res.high_reg);
389  return res;
390}
391
392RegLocation X86Mir2Lir::GetReturnAlt() {
393  RegLocation res = LocCReturn();
394  res.low_reg = rDX;
395  Clobber(rDX);
396  MarkInUse(rDX);
397  return res;
398}
399
400/* To be used when explicitly managing register use */
401void X86Mir2Lir::LockCallTemps() {
402  LockTemp(rX86_ARG0);
403  LockTemp(rX86_ARG1);
404  LockTemp(rX86_ARG2);
405  LockTemp(rX86_ARG3);
406}
407
408/* To be used when explicitly managing register use */
409void X86Mir2Lir::FreeCallTemps() {
410  FreeTemp(rX86_ARG0);
411  FreeTemp(rX86_ARG1);
412  FreeTemp(rX86_ARG2);
413  FreeTemp(rX86_ARG3);
414}
415
416void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
417#if ANDROID_SMP != 0
418  // TODO: optimize fences
419  NewLIR0(kX86Mfence);
420#endif
421}
422/*
423 * Alloc a pair of core registers, or a double.  Low reg in low byte,
424 * high reg in next byte.
425 */
426int X86Mir2Lir::AllocTypedTempPair(bool fp_hint,
427                          int reg_class) {
428  int high_reg;
429  int low_reg;
430  int res = 0;
431
432  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
433    low_reg = AllocTempDouble();
434    high_reg = low_reg;  // only one allocated!
435    res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
436    return res;
437  }
438
439  low_reg = AllocTemp();
440  high_reg = AllocTemp();
441  res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
442  return res;
443}
444
445int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
446  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
447    return AllocTempFloat();
448  }
449  return AllocTemp();
450}
451
452void X86Mir2Lir::CompilerInitializeRegAlloc() {
453  int num_regs = sizeof(core_regs)/sizeof(*core_regs);
454  int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
455  int num_temps = sizeof(core_temps)/sizeof(*core_temps);
456  int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs);
457  int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps);
458  reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_),
459                                                       ArenaAllocator::kAllocRegAlloc));
460  reg_pool_->num_core_regs = num_regs;
461  reg_pool_->core_regs =
462      static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs),
463                                               ArenaAllocator::kAllocRegAlloc));
464  reg_pool_->num_fp_regs = num_fp_regs;
465  reg_pool_->FPRegs =
466      static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs),
467                                                ArenaAllocator::kAllocRegAlloc));
468  CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs);
469  CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs);
470  // Keep special registers from being allocated
471  for (int i = 0; i < num_reserved; i++) {
472    MarkInUse(ReservedRegs[i]);
473  }
474  // Mark temp regs - all others not in use can be used for promotion
475  for (int i = 0; i < num_temps; i++) {
476    MarkTemp(core_temps[i]);
477  }
478  for (int i = 0; i < num_fp_temps; i++) {
479    MarkTemp(fp_temps[i]);
480  }
481}
482
483void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep,
484                     RegLocation rl_free) {
485  if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
486      (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
487    // No overlap, free both
488    FreeTemp(rl_free.low_reg);
489    FreeTemp(rl_free.high_reg);
490  }
491}
492
493void X86Mir2Lir::SpillCoreRegs() {
494  if (num_core_spills_ == 0) {
495    return;
496  }
497  // Spill mask not including fake return address register
498  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
499  int offset = frame_size_ - (4 * num_core_spills_);
500  for (int reg = 0; mask; mask >>= 1, reg++) {
501    if (mask & 0x1) {
502      StoreWordDisp(rX86_SP, offset, reg);
503      offset += 4;
504    }
505  }
506}
507
508void X86Mir2Lir::UnSpillCoreRegs() {
509  if (num_core_spills_ == 0) {
510    return;
511  }
512  // Spill mask not including fake return address register
513  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
514  int offset = frame_size_ - (4 * num_core_spills_);
515  for (int reg = 0; mask; mask >>= 1, reg++) {
516    if (mask & 0x1) {
517      LoadWordDisp(rX86_SP, offset, reg);
518      offset += 4;
519    }
520  }
521}
522
523bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) {
524  return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
525}
526
527X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)
528    : Mir2Lir(cu, mir_graph, arena),
529      method_address_insns_(arena, 100, kGrowableArrayMisc),
530      class_type_address_insns_(arena, 100, kGrowableArrayMisc),
531      call_method_insns_(arena, 100, kGrowableArrayMisc) {
532  store_method_addr_used_ = false;
533  for (int i = 0; i < kX86Last; i++) {
534    if (X86Mir2Lir::EncodingMap[i].opcode != i) {
535      LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name
536                 << " is wrong: expecting " << i << ", seeing "
537                 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
538    }
539  }
540}
541
542Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
543                          ArenaAllocator* const arena) {
544  return new X86Mir2Lir(cu, mir_graph, arena);
545}
546
547// Not used in x86
548int X86Mir2Lir::LoadHelper(ThreadOffset offset) {
549  LOG(FATAL) << "Unexpected use of LoadHelper in x86";
550  return INVALID_REG;
551}
552
553uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) {
554  DCHECK(!IsPseudoLirOp(opcode));
555  return X86Mir2Lir::EncodingMap[opcode].flags;
556}
557
558const char* X86Mir2Lir::GetTargetInstName(int opcode) {
559  DCHECK(!IsPseudoLirOp(opcode));
560  return X86Mir2Lir::EncodingMap[opcode].name;
561}
562
563const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
564  DCHECK(!IsPseudoLirOp(opcode));
565  return X86Mir2Lir::EncodingMap[opcode].fmt;
566}
567
568/*
569 * Return an updated location record with current in-register status.
570 * If the value lives in live temps, reflect that fact.  No code
571 * is generated.  If the live value is part of an older pair,
572 * clobber both low and high.
573 */
574// TODO: Reunify with common code after 'pair mess' has been fixed
575RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) {
576  DCHECK(loc.wide);
577  DCHECK(CheckCorePoolSanity());
578  if (loc.location != kLocPhysReg) {
579    DCHECK((loc.location == kLocDalvikFrame) ||
580         (loc.location == kLocCompilerTemp));
581    // Are the dalvik regs already live in physical registers?
582    RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg);
583
584    // Handle FP registers specially on x86.
585    if (info_lo && IsFpReg(info_lo->reg)) {
586      bool match = true;
587
588      // We can't match a FP register with a pair of Core registers.
589      match = match && (info_lo->pair == 0);
590
591      if (match) {
592        // We can reuse;update the register usage info.
593        loc.low_reg = info_lo->reg;
594        loc.high_reg = info_lo->reg;  // Play nice with existing code.
595        loc.location = kLocPhysReg;
596        loc.vec_len = kVectorLength8;
597        DCHECK(IsFpReg(loc.low_reg));
598        return loc;
599      }
600      // We can't easily reuse; clobber and free any overlaps.
601      if (info_lo) {
602        Clobber(info_lo->reg);
603        FreeTemp(info_lo->reg);
604        if (info_lo->pair)
605          Clobber(info_lo->partner);
606      }
607    } else {
608      RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg);
609      bool match = true;
610      match = match && (info_lo != NULL);
611      match = match && (info_hi != NULL);
612      // Are they both core or both FP?
613      match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg));
614      // If a pair of floating point singles, are they properly aligned?
615      if (match && IsFpReg(info_lo->reg)) {
616        match &= ((info_lo->reg & 0x1) == 0);
617        match &= ((info_hi->reg - info_lo->reg) == 1);
618      }
619      // If previously used as a pair, it is the same pair?
620      if (match && (info_lo->pair || info_hi->pair)) {
621        match = (info_lo->pair == info_hi->pair);
622        match &= ((info_lo->reg == info_hi->partner) &&
623              (info_hi->reg == info_lo->partner));
624      }
625      if (match) {
626        // Can reuse - update the register usage info
627        loc.low_reg = info_lo->reg;
628        loc.high_reg = info_hi->reg;
629        loc.location = kLocPhysReg;
630        MarkPair(loc.low_reg, loc.high_reg);
631        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
632        return loc;
633      }
634      // Can't easily reuse - clobber and free any overlaps
635      if (info_lo) {
636        Clobber(info_lo->reg);
637        FreeTemp(info_lo->reg);
638        if (info_lo->pair)
639          Clobber(info_lo->partner);
640      }
641      if (info_hi) {
642        Clobber(info_hi->reg);
643        FreeTemp(info_hi->reg);
644        if (info_hi->pair)
645          Clobber(info_hi->partner);
646      }
647    }
648  }
649  return loc;
650}
651
652// TODO: Reunify with common code after 'pair mess' has been fixed
653RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) {
654  DCHECK(loc.wide);
655  int32_t new_regs;
656  int32_t low_reg;
657  int32_t high_reg;
658
659  loc = UpdateLocWide(loc);
660
661  /* If it is already in a register, we can assume proper form.  Is it the right reg class? */
662  if (loc.location == kLocPhysReg) {
663    DCHECK_EQ(IsFpReg(loc.low_reg), loc.IsVectorScalar());
664    if (!RegClassMatches(reg_class, loc.low_reg)) {
665      /* It is the wrong register class.  Reallocate and copy. */
666      if (!IsFpReg(loc.low_reg)) {
667        // We want this in a FP reg, and it is in core registers.
668        DCHECK(reg_class != kCoreReg);
669        // Allocate this into any FP reg, and mark it with the right size.
670        low_reg = AllocTypedTemp(true, reg_class);
671        OpVectorRegCopyWide(low_reg, loc.low_reg, loc.high_reg);
672        CopyRegInfo(low_reg, loc.low_reg);
673        Clobber(loc.low_reg);
674        Clobber(loc.high_reg);
675        loc.low_reg = low_reg;
676        loc.high_reg = low_reg;  // Play nice with existing code.
677        loc.vec_len = kVectorLength8;
678      } else {
679        // The value is in a FP register, and we want it in a pair of core registers.
680        DCHECK_EQ(reg_class, kCoreReg);
681        DCHECK_EQ(loc.low_reg, loc.high_reg);
682        new_regs = AllocTypedTempPair(false, kCoreReg);  // Force to core registers.
683        low_reg = new_regs & 0xff;
684        high_reg = (new_regs >> 8) & 0xff;
685        DCHECK_NE(low_reg, high_reg);
686        OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg);
687        CopyRegInfo(low_reg, loc.low_reg);
688        CopyRegInfo(high_reg, loc.high_reg);
689        Clobber(loc.low_reg);
690        Clobber(loc.high_reg);
691        loc.low_reg = low_reg;
692        loc.high_reg = high_reg;
693        MarkPair(loc.low_reg, loc.high_reg);
694        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
695      }
696    }
697    return loc;
698  }
699
700  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
701  DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG);
702
703  new_regs = AllocTypedTempPair(loc.fp, reg_class);
704  loc.low_reg = new_regs & 0xff;
705  loc.high_reg = (new_regs >> 8) & 0xff;
706
707  if (loc.low_reg == loc.high_reg) {
708    DCHECK(IsFpReg(loc.low_reg));
709    loc.vec_len = kVectorLength8;
710  } else {
711    MarkPair(loc.low_reg, loc.high_reg);
712  }
713  if (update) {
714    loc.location = kLocPhysReg;
715    MarkLive(loc.low_reg, loc.s_reg_low);
716    if (loc.low_reg != loc.high_reg) {
717      MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low));
718    }
719  }
720  return loc;
721}
722
723// TODO: Reunify with common code after 'pair mess' has been fixed
724RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) {
725  int new_reg;
726
727  if (loc.wide)
728    return EvalLocWide(loc, reg_class, update);
729
730  loc = UpdateLoc(loc);
731
732  if (loc.location == kLocPhysReg) {
733    if (!RegClassMatches(reg_class, loc.low_reg)) {
734      /* Wrong register class.  Realloc, copy and transfer ownership. */
735      new_reg = AllocTypedTemp(loc.fp, reg_class);
736      OpRegCopy(new_reg, loc.low_reg);
737      CopyRegInfo(new_reg, loc.low_reg);
738      Clobber(loc.low_reg);
739      loc.low_reg = new_reg;
740      if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
741        loc.vec_len = kVectorLength4;
742    }
743    return loc;
744  }
745
746  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
747
748  new_reg = AllocTypedTemp(loc.fp, reg_class);
749  loc.low_reg = new_reg;
750  if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
751    loc.vec_len = kVectorLength4;
752
753  if (update) {
754    loc.location = kLocPhysReg;
755    MarkLive(loc.low_reg, loc.s_reg_low);
756  }
757  return loc;
758}
759
760int X86Mir2Lir::AllocTempDouble() {
761  // We really don't need a pair of registers.
762  return AllocTempFloat();
763}
764
765// TODO: Reunify with common code after 'pair mess' has been fixed
766void X86Mir2Lir::ResetDefLocWide(RegLocation rl) {
767  DCHECK(rl.wide);
768  RegisterInfo* p_low = IsTemp(rl.low_reg);
769  if (IsFpReg(rl.low_reg)) {
770    // We are using only the low register.
771    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
772      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
773    }
774    ResetDef(rl.low_reg);
775  } else {
776    RegisterInfo* p_high = IsTemp(rl.high_reg);
777    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
778      DCHECK(p_low->pair);
779      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
780    }
781    if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) {
782      DCHECK(p_high->pair);
783    }
784    ResetDef(rl.low_reg);
785    ResetDef(rl.high_reg);
786  }
787}
788
789void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) {
790  // Can we do this directly to memory?
791  rl_dest = UpdateLocWide(rl_dest);
792  if ((rl_dest.location == kLocDalvikFrame) ||
793      (rl_dest.location == kLocCompilerTemp)) {
794    int32_t val_lo = Low32Bits(value);
795    int32_t val_hi = High32Bits(value);
796    int rBase = TargetReg(kSp);
797    int displacement = SRegOffset(rl_dest.s_reg_low);
798
799    LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo);
800    AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2,
801                              false /* is_load */, true /* is64bit */);
802    store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi);
803    AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2,
804                              false /* is_load */, true /* is64bit */);
805    return;
806  }
807
808  // Just use the standard code to do the generation.
809  Mir2Lir::GenConstWide(rl_dest, value);
810}
811
812// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc
813void X86Mir2Lir::DumpRegLocation(RegLocation loc) {
814  LOG(INFO)  << "location: " << loc.location << ','
815             << (loc.wide ? " w" : "  ")
816             << (loc.defined ? " D" : "  ")
817             << (loc.is_const ? " c" : "  ")
818             << (loc.fp ? " F" : "  ")
819             << (loc.core ? " C" : "  ")
820             << (loc.ref ? " r" : "  ")
821             << (loc.high_word ? " h" : "  ")
822             << (loc.home ? " H" : "  ")
823             << " vec_len: " << loc.vec_len
824             << ", low: " << static_cast<int>(loc.low_reg)
825             << ", high: " << static_cast<int>(loc.high_reg)
826             << ", s_reg: " << loc.s_reg_low
827             << ", orig: " << loc.orig_sreg;
828}
829
830void X86Mir2Lir::Materialize() {
831  // A good place to put the analysis before starting.
832  AnalyzeMIR();
833
834  // Now continue with regular code generation.
835  Mir2Lir::Materialize();
836}
837
838void X86Mir2Lir::LoadMethodAddress(int dex_method_index, InvokeType type,
839                                   SpecialTargetRegister symbolic_reg) {
840  /*
841   * For x86, just generate a 32 bit move immediate instruction, that will be filled
842   * in at 'link time'.  For now, put a unique value based on target to ensure that
843   * code deduplication works.
844   */
845  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
846  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
847
848  // Generate the move instruction with the unique pointer and save index and type.
849  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
850                     static_cast<int>(ptr), dex_method_index, type);
851  AppendLIR(move);
852  method_address_insns_.Insert(move);
853}
854
855void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) {
856  /*
857   * For x86, just generate a 32 bit move immediate instruction, that will be filled
858   * in at 'link time'.  For now, put a unique value based on target to ensure that
859   * code deduplication works.
860   */
861  const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx);
862  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
863
864  // Generate the move instruction with the unique pointer and save index and type.
865  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
866                     static_cast<int>(ptr), type_idx);
867  AppendLIR(move);
868  class_type_address_insns_.Insert(move);
869}
870
871LIR *X86Mir2Lir::CallWithLinkerFixup(int dex_method_index, InvokeType type) {
872  /*
873   * For x86, just generate a 32 bit call relative instruction, that will be filled
874   * in at 'link time'.  For now, put a unique value based on target to ensure that
875   * code deduplication works.
876   */
877  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
878  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
879
880  // Generate the call instruction with the unique pointer and save index and type.
881  LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(ptr), dex_method_index,
882                     type);
883  AppendLIR(call);
884  call_method_insns_.Insert(call);
885  return call;
886}
887
888void X86Mir2Lir::InstallLiteralPools() {
889  // These are handled differently for x86.
890  DCHECK(code_literal_list_ == nullptr);
891  DCHECK(method_literal_list_ == nullptr);
892  DCHECK(class_literal_list_ == nullptr);
893
894  // Handle the fixups for methods.
895  for (uint32_t i = 0; i < method_address_insns_.Size(); i++) {
896      LIR* p = method_address_insns_.Get(i);
897      DCHECK_EQ(p->opcode, kX86Mov32RI);
898      uint32_t target = p->operands[2];
899
900      // The offset to patch is the last 4 bytes of the instruction.
901      int patch_offset = p->offset + p->flags.size - 4;
902      cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx,
903                                           cu_->method_idx, cu_->invoke_type,
904                                           target, static_cast<InvokeType>(p->operands[3]),
905                                           patch_offset);
906  }
907
908  // Handle the fixups for class types.
909  for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) {
910      LIR* p = class_type_address_insns_.Get(i);
911      DCHECK_EQ(p->opcode, kX86Mov32RI);
912      uint32_t target = p->operands[2];
913
914      // The offset to patch is the last 4 bytes of the instruction.
915      int patch_offset = p->offset + p->flags.size - 4;
916      cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx,
917                                          cu_->method_idx, target, patch_offset);
918  }
919
920  // And now the PC-relative calls to methods.
921  for (uint32_t i = 0; i < call_method_insns_.Size(); i++) {
922      LIR* p = call_method_insns_.Get(i);
923      DCHECK_EQ(p->opcode, kX86CallI);
924      uint32_t target = p->operands[1];
925
926      // The offset to patch is the last 4 bytes of the instruction.
927      int patch_offset = p->offset + p->flags.size - 4;
928      cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx,
929                                                 cu_->method_idx, cu_->invoke_type, target,
930                                                 static_cast<InvokeType>(p->operands[2]),
931                                                 patch_offset, -4 /* offset */);
932  }
933
934  // And do the normal processing.
935  Mir2Lir::InstallLiteralPools();
936}
937
938}  // namespace art
939