target_x86.cc revision 409fe94ad529d9334587be80b9f6a3d166805508
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/compiler_internals.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "x86_lir.h" 21 22#include <string> 23 24namespace art { 25 26// FIXME: restore "static" when usage uncovered 27/*static*/ int core_regs[] = { 28 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 29#ifdef TARGET_REX_SUPPORT 30 r8, r9, r10, r11, r12, r13, r14, 15 31#endif 32}; 33/*static*/ int ReservedRegs[] = {rX86_SP}; 34/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 35/*static*/ int FpRegs[] = { 36 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 37#ifdef TARGET_REX_SUPPORT 38 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 39#endif 40}; 41/*static*/ int fp_temps[] = { 42 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 43#ifdef TARGET_REX_SUPPORT 44 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 45#endif 46}; 47 48RegLocation X86Mir2Lir::LocCReturn() { 49 RegLocation res = X86_LOC_C_RETURN; 50 return res; 51} 52 53RegLocation X86Mir2Lir::LocCReturnWide() { 54 RegLocation res = X86_LOC_C_RETURN_WIDE; 55 return res; 56} 57 58RegLocation X86Mir2Lir::LocCReturnFloat() { 59 RegLocation res = X86_LOC_C_RETURN_FLOAT; 60 return res; 61} 62 63RegLocation X86Mir2Lir::LocCReturnDouble() { 64 RegLocation res = X86_LOC_C_RETURN_DOUBLE; 65 return res; 66} 67 68// Return a target-dependent special register. 69int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 70 int res = INVALID_REG; 71 switch (reg) { 72 case kSelf: res = rX86_SELF; break; 73 case kSuspend: res = rX86_SUSPEND; break; 74 case kLr: res = rX86_LR; break; 75 case kPc: res = rX86_PC; break; 76 case kSp: res = rX86_SP; break; 77 case kArg0: res = rX86_ARG0; break; 78 case kArg1: res = rX86_ARG1; break; 79 case kArg2: res = rX86_ARG2; break; 80 case kArg3: res = rX86_ARG3; break; 81 case kFArg0: res = rX86_FARG0; break; 82 case kFArg1: res = rX86_FARG1; break; 83 case kFArg2: res = rX86_FARG2; break; 84 case kFArg3: res = rX86_FARG3; break; 85 case kRet0: res = rX86_RET0; break; 86 case kRet1: res = rX86_RET1; break; 87 case kInvokeTgt: res = rX86_INVOKE_TGT; break; 88 case kCount: res = rX86_COUNT; break; 89 } 90 return res; 91} 92 93// Create a double from a pair of singles. 94int X86Mir2Lir::S2d(int low_reg, int high_reg) { 95 return X86_S2D(low_reg, high_reg); 96} 97 98// Return mask to strip off fp reg flags and bias. 99uint32_t X86Mir2Lir::FpRegMask() { 100 return X86_FP_REG_MASK; 101} 102 103// True if both regs single, both core or both double. 104bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 105 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 106} 107 108/* 109 * Decode the register id. 110 */ 111uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 112 uint64_t seed; 113 int shift; 114 int reg_id; 115 116 reg_id = reg & 0xf; 117 /* Double registers in x86 are just a single FP register */ 118 seed = 1; 119 /* FP register starts at bit position 16 */ 120 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 121 /* Expand the double register id into single offset */ 122 shift += reg_id; 123 return (seed << shift); 124} 125 126uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 127 /* 128 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 129 * able to clean up some of the x86/Arm_Mips differences 130 */ 131 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 132 return 0ULL; 133} 134 135void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 136 DCHECK_EQ(cu_->instruction_set, kX86); 137 DCHECK(!lir->flags.use_def_invalid); 138 139 // X86-specific resource map setup here. 140 if (flags & REG_USE_SP) { 141 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 142 } 143 144 if (flags & REG_DEF_SP) { 145 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 146 } 147 148 if (flags & REG_DEFA) { 149 SetupRegMask(&lir->u.m.def_mask, rAX); 150 } 151 152 if (flags & REG_DEFD) { 153 SetupRegMask(&lir->u.m.def_mask, rDX); 154 } 155 if (flags & REG_USEA) { 156 SetupRegMask(&lir->u.m.use_mask, rAX); 157 } 158 159 if (flags & REG_USEC) { 160 SetupRegMask(&lir->u.m.use_mask, rCX); 161 } 162 163 if (flags & REG_USED) { 164 SetupRegMask(&lir->u.m.use_mask, rDX); 165 } 166} 167 168/* For dumping instructions */ 169static const char* x86RegName[] = { 170 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 172}; 173 174static const char* x86CondName[] = { 175 "O", 176 "NO", 177 "B/NAE/C", 178 "NB/AE/NC", 179 "Z/EQ", 180 "NZ/NE", 181 "BE/NA", 182 "NBE/A", 183 "S", 184 "NS", 185 "P/PE", 186 "NP/PO", 187 "L/NGE", 188 "NL/GE", 189 "LE/NG", 190 "NLE/G" 191}; 192 193/* 194 * Interpret a format string and build a string no longer than size 195 * See format key in Assemble.cc. 196 */ 197std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 198 std::string buf; 199 size_t i = 0; 200 size_t fmt_len = strlen(fmt); 201 while (i < fmt_len) { 202 if (fmt[i] != '!') { 203 buf += fmt[i]; 204 i++; 205 } else { 206 i++; 207 DCHECK_LT(i, fmt_len); 208 char operand_number_ch = fmt[i]; 209 i++; 210 if (operand_number_ch == '!') { 211 buf += "!"; 212 } else { 213 int operand_number = operand_number_ch - '0'; 214 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 215 DCHECK_LT(i, fmt_len); 216 int operand = lir->operands[operand_number]; 217 switch (fmt[i]) { 218 case 'c': 219 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 220 buf += x86CondName[operand]; 221 break; 222 case 'd': 223 buf += StringPrintf("%d", operand); 224 break; 225 case 'p': { 226 SwitchTable *tab_rec = reinterpret_cast<SwitchTable*>(operand); 227 buf += StringPrintf("0x%08x", tab_rec->offset); 228 break; 229 } 230 case 'r': 231 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 232 int fp_reg = operand & X86_FP_REG_MASK; 233 buf += StringPrintf("xmm%d", fp_reg); 234 } else { 235 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 236 buf += x86RegName[operand]; 237 } 238 break; 239 case 't': 240 buf += StringPrintf("0x%08x (L%p)", 241 reinterpret_cast<uint32_t>(base_addr) 242 + lir->offset + operand, lir->target); 243 break; 244 default: 245 buf += StringPrintf("DecodeError '%c'", fmt[i]); 246 break; 247 } 248 i++; 249 } 250 } 251 } 252 return buf; 253} 254 255void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 256 char buf[256]; 257 buf[0] = 0; 258 259 if (mask == ENCODE_ALL) { 260 strcpy(buf, "all"); 261 } else { 262 char num[8]; 263 int i; 264 265 for (i = 0; i < kX86RegEnd; i++) { 266 if (mask & (1ULL << i)) { 267 sprintf(num, "%d ", i); 268 strcat(buf, num); 269 } 270 } 271 272 if (mask & ENCODE_CCODE) { 273 strcat(buf, "cc "); 274 } 275 /* Memory bits */ 276 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 277 sprintf(buf + strlen(buf), "dr%d%s", DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 278 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 279 } 280 if (mask & ENCODE_LITERAL) { 281 strcat(buf, "lit "); 282 } 283 284 if (mask & ENCODE_HEAP_REF) { 285 strcat(buf, "heap "); 286 } 287 if (mask & ENCODE_MUST_NOT_ALIAS) { 288 strcat(buf, "noalias "); 289 } 290 } 291 if (buf[0]) { 292 LOG(INFO) << prefix << ": " << buf; 293 } 294} 295 296void X86Mir2Lir::AdjustSpillMask() { 297 // Adjustment for LR spilling, x86 has no LR so nothing to do here 298 core_spill_mask_ |= (1 << rRET); 299 num_core_spills_++; 300} 301 302/* 303 * Mark a callee-save fp register as promoted. Note that 304 * vpush/vpop uses contiguous register lists so we must 305 * include any holes in the mask. Associate holes with 306 * Dalvik register INVALID_VREG (0xFFFFU). 307 */ 308void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 309 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 310#if 0 311 LOG(FATAL) << "No support yet for promoted FP regs"; 312#endif 313} 314 315void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { 316 RegisterInfo* info1 = GetRegInfo(reg1); 317 RegisterInfo* info2 = GetRegInfo(reg2); 318 DCHECK(info1 && info2 && info1->pair && info2->pair && 319 (info1->partner == info2->reg) && 320 (info2->partner == info1->reg)); 321 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 322 if (!(info1->is_temp && info2->is_temp)) { 323 /* Should not happen. If it does, there's a problem in eval_loc */ 324 LOG(FATAL) << "Long half-temp, half-promoted"; 325 } 326 327 info1->dirty = false; 328 info2->dirty = false; 329 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 330 info1 = info2; 331 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 332 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); 333 } 334} 335 336void X86Mir2Lir::FlushReg(int reg) { 337 RegisterInfo* info = GetRegInfo(reg); 338 if (info->live && info->dirty) { 339 info->dirty = false; 340 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 341 StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); 342 } 343} 344 345/* Give access to the target-dependent FP register encoding to common code */ 346bool X86Mir2Lir::IsFpReg(int reg) { 347 return X86_FPREG(reg); 348} 349 350/* Clobber all regs that might be used by an external C call */ 351void X86Mir2Lir::ClobberCalleeSave() { 352 Clobber(rAX); 353 Clobber(rCX); 354 Clobber(rDX); 355} 356 357RegLocation X86Mir2Lir::GetReturnWideAlt() { 358 RegLocation res = LocCReturnWide(); 359 CHECK(res.low_reg == rAX); 360 CHECK(res.high_reg == rDX); 361 Clobber(rAX); 362 Clobber(rDX); 363 MarkInUse(rAX); 364 MarkInUse(rDX); 365 MarkPair(res.low_reg, res.high_reg); 366 return res; 367} 368 369RegLocation X86Mir2Lir::GetReturnAlt() { 370 RegLocation res = LocCReturn(); 371 res.low_reg = rDX; 372 Clobber(rDX); 373 MarkInUse(rDX); 374 return res; 375} 376 377/* To be used when explicitly managing register use */ 378void X86Mir2Lir::LockCallTemps() { 379 LockTemp(rX86_ARG0); 380 LockTemp(rX86_ARG1); 381 LockTemp(rX86_ARG2); 382 LockTemp(rX86_ARG3); 383} 384 385/* To be used when explicitly managing register use */ 386void X86Mir2Lir::FreeCallTemps() { 387 FreeTemp(rX86_ARG0); 388 FreeTemp(rX86_ARG1); 389 FreeTemp(rX86_ARG2); 390 FreeTemp(rX86_ARG3); 391} 392 393void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 394#if ANDROID_SMP != 0 395 // TODO: optimize fences 396 NewLIR0(kX86Mfence); 397#endif 398} 399/* 400 * Alloc a pair of core registers, or a double. Low reg in low byte, 401 * high reg in next byte. 402 */ 403int X86Mir2Lir::AllocTypedTempPair(bool fp_hint, 404 int reg_class) { 405 int high_reg; 406 int low_reg; 407 int res = 0; 408 409 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 410 low_reg = AllocTempDouble(); 411 high_reg = low_reg + 1; 412 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 413 return res; 414 } 415 416 low_reg = AllocTemp(); 417 high_reg = AllocTemp(); 418 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 419 return res; 420} 421 422int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 423 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 424 return AllocTempFloat(); 425 } 426 return AllocTemp(); 427} 428 429void X86Mir2Lir::CompilerInitializeRegAlloc() { 430 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 431 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 432 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 433 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 434 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 435 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 436 ArenaAllocator::kAllocRegAlloc)); 437 reg_pool_->num_core_regs = num_regs; 438 reg_pool_->core_regs = 439 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 440 ArenaAllocator::kAllocRegAlloc)); 441 reg_pool_->num_fp_regs = num_fp_regs; 442 reg_pool_->FPRegs = 443 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 444 ArenaAllocator::kAllocRegAlloc)); 445 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 446 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 447 // Keep special registers from being allocated 448 for (int i = 0; i < num_reserved; i++) { 449 MarkInUse(ReservedRegs[i]); 450 } 451 // Mark temp regs - all others not in use can be used for promotion 452 for (int i = 0; i < num_temps; i++) { 453 MarkTemp(core_temps[i]); 454 } 455 for (int i = 0; i < num_fp_temps; i++) { 456 MarkTemp(fp_temps[i]); 457 } 458} 459 460void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, 461 RegLocation rl_free) { 462 if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) && 463 (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) { 464 // No overlap, free both 465 FreeTemp(rl_free.low_reg); 466 FreeTemp(rl_free.high_reg); 467 } 468} 469 470void X86Mir2Lir::SpillCoreRegs() { 471 if (num_core_spills_ == 0) { 472 return; 473 } 474 // Spill mask not including fake return address register 475 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 476 int offset = frame_size_ - (4 * num_core_spills_); 477 for (int reg = 0; mask; mask >>= 1, reg++) { 478 if (mask & 0x1) { 479 StoreWordDisp(rX86_SP, offset, reg); 480 offset += 4; 481 } 482 } 483} 484 485void X86Mir2Lir::UnSpillCoreRegs() { 486 if (num_core_spills_ == 0) { 487 return; 488 } 489 // Spill mask not including fake return address register 490 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 491 int offset = frame_size_ - (4 * num_core_spills_); 492 for (int reg = 0; mask; mask >>= 1, reg++) { 493 if (mask & 0x1) { 494 LoadWordDisp(rX86_SP, offset, reg); 495 offset += 4; 496 } 497 } 498} 499 500bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 501 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 502} 503 504X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 505 : Mir2Lir(cu, mir_graph, arena) { 506 for (int i = 0; i < kX86Last; i++) { 507 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 508 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 509 << " is wrong: expecting " << i << ", seeing " 510 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 511 } 512 } 513} 514 515Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 516 ArenaAllocator* const arena) { 517 return new X86Mir2Lir(cu, mir_graph, arena); 518} 519 520// Not used in x86 521int X86Mir2Lir::LoadHelper(ThreadOffset offset) { 522 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 523 return INVALID_REG; 524} 525 526uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 527 DCHECK(!IsPseudoLirOp(opcode)); 528 return X86Mir2Lir::EncodingMap[opcode].flags; 529} 530 531const char* X86Mir2Lir::GetTargetInstName(int opcode) { 532 DCHECK(!IsPseudoLirOp(opcode)); 533 return X86Mir2Lir::EncodingMap[opcode].name; 534} 535 536const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 537 DCHECK(!IsPseudoLirOp(opcode)); 538 return X86Mir2Lir::EncodingMap[opcode].fmt; 539} 540 541} // namespace art 542