target_x86.cc revision 55d0eac918321e0525f6e6491f36a80977e0d416 
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "codegen_x86.h"
18#include "dex/compiler_internals.h"
19#include "dex/quick/mir_to_lir-inl.h"
20#include "x86_lir.h"
21
22#include <string>
23
24namespace art {
25
26// FIXME: restore "static" when usage uncovered
27/*static*/ int core_regs[] = {
28  rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI
29#ifdef TARGET_REX_SUPPORT
30  r8, r9, r10, r11, r12, r13, r14, 15
31#endif
32};
33/*static*/ int ReservedRegs[] = {rX86_SP};
34/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX};
35/*static*/ int FpRegs[] = {
36  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
37#ifdef TARGET_REX_SUPPORT
38  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
39#endif
40};
41/*static*/ int fp_temps[] = {
42  fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
43#ifdef TARGET_REX_SUPPORT
44  fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
45#endif
46};
47
48RegLocation X86Mir2Lir::LocCReturn() {
49  RegLocation res = X86_LOC_C_RETURN;
50  return res;
51}
52
53RegLocation X86Mir2Lir::LocCReturnWide() {
54  RegLocation res = X86_LOC_C_RETURN_WIDE;
55  return res;
56}
57
58RegLocation X86Mir2Lir::LocCReturnFloat() {
59  RegLocation res = X86_LOC_C_RETURN_FLOAT;
60  return res;
61}
62
63RegLocation X86Mir2Lir::LocCReturnDouble() {
64  RegLocation res = X86_LOC_C_RETURN_DOUBLE;
65  return res;
66}
67
68// Return a target-dependent special register.
69int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) {
70  int res = INVALID_REG;
71  switch (reg) {
72    case kSelf: res = rX86_SELF; break;
73    case kSuspend: res =  rX86_SUSPEND; break;
74    case kLr: res =  rX86_LR; break;
75    case kPc: res =  rX86_PC; break;
76    case kSp: res =  rX86_SP; break;
77    case kArg0: res = rX86_ARG0; break;
78    case kArg1: res = rX86_ARG1; break;
79    case kArg2: res = rX86_ARG2; break;
80    case kArg3: res = rX86_ARG3; break;
81    case kFArg0: res = rX86_FARG0; break;
82    case kFArg1: res = rX86_FARG1; break;
83    case kFArg2: res = rX86_FARG2; break;
84    case kFArg3: res = rX86_FARG3; break;
85    case kRet0: res = rX86_RET0; break;
86    case kRet1: res = rX86_RET1; break;
87    case kInvokeTgt: res = rX86_INVOKE_TGT; break;
88    case kHiddenArg: res = rAX; break;
89    case kHiddenFpArg: res = fr0; break;
90    case kCount: res = rX86_COUNT; break;
91  }
92  return res;
93}
94
95// Create a double from a pair of singles.
96int X86Mir2Lir::S2d(int low_reg, int high_reg) {
97  return X86_S2D(low_reg, high_reg);
98}
99
100// Return mask to strip off fp reg flags and bias.
101uint32_t X86Mir2Lir::FpRegMask() {
102  return X86_FP_REG_MASK;
103}
104
105// True if both regs single, both core or both double.
106bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
107  return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
108}
109
110/*
111 * Decode the register id.
112 */
113uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) {
114  uint64_t seed;
115  int shift;
116  int reg_id;
117
118  reg_id = reg & 0xf;
119  /* Double registers in x86 are just a single FP register */
120  seed = 1;
121  /* FP register starts at bit position 16 */
122  shift = X86_FPREG(reg) ? kX86FPReg0 : 0;
123  /* Expand the double register id into single offset */
124  shift += reg_id;
125  return (seed << shift);
126}
127
128uint64_t X86Mir2Lir::GetPCUseDefEncoding() {
129  /*
130   * FIXME: might make sense to use a virtual resource encoding bit for pc.  Might be
131   * able to clean up some of the x86/Arm_Mips differences
132   */
133  LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86";
134  return 0ULL;
135}
136
137void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) {
138  DCHECK_EQ(cu_->instruction_set, kX86);
139  DCHECK(!lir->flags.use_def_invalid);
140
141  // X86-specific resource map setup here.
142  if (flags & REG_USE_SP) {
143    lir->u.m.use_mask |= ENCODE_X86_REG_SP;
144  }
145
146  if (flags & REG_DEF_SP) {
147    lir->u.m.def_mask |= ENCODE_X86_REG_SP;
148  }
149
150  if (flags & REG_DEFA) {
151    SetupRegMask(&lir->u.m.def_mask, rAX);
152  }
153
154  if (flags & REG_DEFD) {
155    SetupRegMask(&lir->u.m.def_mask, rDX);
156  }
157  if (flags & REG_USEA) {
158    SetupRegMask(&lir->u.m.use_mask, rAX);
159  }
160
161  if (flags & REG_USEC) {
162    SetupRegMask(&lir->u.m.use_mask, rCX);
163  }
164
165  if (flags & REG_USED) {
166    SetupRegMask(&lir->u.m.use_mask, rDX);
167  }
168
169  if (flags & REG_USEB) {
170    SetupRegMask(&lir->u.m.use_mask, rBX);
171  }
172}
173
174/* For dumping instructions */
175static const char* x86RegName[] = {
176  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
177  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
178};
179
180static const char* x86CondName[] = {
181  "O",
182  "NO",
183  "B/NAE/C",
184  "NB/AE/NC",
185  "Z/EQ",
186  "NZ/NE",
187  "BE/NA",
188  "NBE/A",
189  "S",
190  "NS",
191  "P/PE",
192  "NP/PO",
193  "L/NGE",
194  "NL/GE",
195  "LE/NG",
196  "NLE/G"
197};
198
199/*
200 * Interpret a format string and build a string no longer than size
201 * See format key in Assemble.cc.
202 */
203std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
204  std::string buf;
205  size_t i = 0;
206  size_t fmt_len = strlen(fmt);
207  while (i < fmt_len) {
208    if (fmt[i] != '!') {
209      buf += fmt[i];
210      i++;
211    } else {
212      i++;
213      DCHECK_LT(i, fmt_len);
214      char operand_number_ch = fmt[i];
215      i++;
216      if (operand_number_ch == '!') {
217        buf += "!";
218      } else {
219        int operand_number = operand_number_ch - '0';
220        DCHECK_LT(operand_number, 6);  // Expect upto 6 LIR operands.
221        DCHECK_LT(i, fmt_len);
222        int operand = lir->operands[operand_number];
223        switch (fmt[i]) {
224          case 'c':
225            DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
226            buf += x86CondName[operand];
227            break;
228          case 'd':
229            buf += StringPrintf("%d", operand);
230            break;
231          case 'p': {
232            EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand));
233            buf += StringPrintf("0x%08x", tab_rec->offset);
234            break;
235          }
236          case 'r':
237            if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) {
238              int fp_reg = operand & X86_FP_REG_MASK;
239              buf += StringPrintf("xmm%d", fp_reg);
240            } else {
241              DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName));
242              buf += x86RegName[operand];
243            }
244            break;
245          case 't':
246            buf += StringPrintf("0x%08" PRIxPTR " (L%p)",
247                                reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand,
248                                lir->target);
249            break;
250          default:
251            buf += StringPrintf("DecodeError '%c'", fmt[i]);
252            break;
253        }
254        i++;
255      }
256    }
257  }
258  return buf;
259}
260
261void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) {
262  char buf[256];
263  buf[0] = 0;
264
265  if (mask == ENCODE_ALL) {
266    strcpy(buf, "all");
267  } else {
268    char num[8];
269    int i;
270
271    for (i = 0; i < kX86RegEnd; i++) {
272      if (mask & (1ULL << i)) {
273        snprintf(num, arraysize(num), "%d ", i);
274        strcat(buf, num);
275      }
276    }
277
278    if (mask & ENCODE_CCODE) {
279      strcat(buf, "cc ");
280    }
281    /* Memory bits */
282    if (x86LIR && (mask & ENCODE_DALVIK_REG)) {
283      snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
284               DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info),
285               (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : "");
286    }
287    if (mask & ENCODE_LITERAL) {
288      strcat(buf, "lit ");
289    }
290
291    if (mask & ENCODE_HEAP_REF) {
292      strcat(buf, "heap ");
293    }
294    if (mask & ENCODE_MUST_NOT_ALIAS) {
295      strcat(buf, "noalias ");
296    }
297  }
298  if (buf[0]) {
299    LOG(INFO) << prefix << ": " <<  buf;
300  }
301}
302
303void X86Mir2Lir::AdjustSpillMask() {
304  // Adjustment for LR spilling, x86 has no LR so nothing to do here
305  core_spill_mask_ |= (1 << rRET);
306  num_core_spills_++;
307}
308
309/*
310 * Mark a callee-save fp register as promoted.  Note that
311 * vpush/vpop uses contiguous register lists so we must
312 * include any holes in the mask.  Associate holes with
313 * Dalvik register INVALID_VREG (0xFFFFU).
314 */
315void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) {
316  UNIMPLEMENTED(WARNING) << "MarkPreservedSingle";
317#if 0
318  LOG(FATAL) << "No support yet for promoted FP regs";
319#endif
320}
321
322void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
323  RegisterInfo* info1 = GetRegInfo(reg1);
324  RegisterInfo* info2 = GetRegInfo(reg2);
325  DCHECK(info1 && info2 && info1->pair && info2->pair &&
326         (info1->partner == info2->reg) &&
327         (info2->partner == info1->reg));
328  if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
329    if (!(info1->is_temp && info2->is_temp)) {
330      /* Should not happen.  If it does, there's a problem in eval_loc */
331      LOG(FATAL) << "Long half-temp, half-promoted";
332    }
333
334    info1->dirty = false;
335    info2->dirty = false;
336    if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg))
337      info1 = info2;
338    int v_reg = mir_graph_->SRegToVReg(info1->s_reg);
339    StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner);
340  }
341}
342
343void X86Mir2Lir::FlushReg(int reg) {
344  RegisterInfo* info = GetRegInfo(reg);
345  if (info->live && info->dirty) {
346    info->dirty = false;
347    int v_reg = mir_graph_->SRegToVReg(info->s_reg);
348    StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord);
349  }
350}
351
352/* Give access to the target-dependent FP register encoding to common code */
353bool X86Mir2Lir::IsFpReg(int reg) {
354  return X86_FPREG(reg);
355}
356
357/* Clobber all regs that might be used by an external C call */
358void X86Mir2Lir::ClobberCallerSave() {
359  Clobber(rAX);
360  Clobber(rCX);
361  Clobber(rDX);
362  Clobber(rBX);
363}
364
365RegLocation X86Mir2Lir::GetReturnWideAlt() {
366  RegLocation res = LocCReturnWide();
367  CHECK(res.low_reg == rAX);
368  CHECK(res.high_reg == rDX);
369  Clobber(rAX);
370  Clobber(rDX);
371  MarkInUse(rAX);
372  MarkInUse(rDX);
373  MarkPair(res.low_reg, res.high_reg);
374  return res;
375}
376
377RegLocation X86Mir2Lir::GetReturnAlt() {
378  RegLocation res = LocCReturn();
379  res.low_reg = rDX;
380  Clobber(rDX);
381  MarkInUse(rDX);
382  return res;
383}
384
385/* To be used when explicitly managing register use */
386void X86Mir2Lir::LockCallTemps() {
387  LockTemp(rX86_ARG0);
388  LockTemp(rX86_ARG1);
389  LockTemp(rX86_ARG2);
390  LockTemp(rX86_ARG3);
391}
392
393/* To be used when explicitly managing register use */
394void X86Mir2Lir::FreeCallTemps() {
395  FreeTemp(rX86_ARG0);
396  FreeTemp(rX86_ARG1);
397  FreeTemp(rX86_ARG2);
398  FreeTemp(rX86_ARG3);
399}
400
401void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
402#if ANDROID_SMP != 0
403  // TODO: optimize fences
404  NewLIR0(kX86Mfence);
405#endif
406}
407/*
408 * Alloc a pair of core registers, or a double.  Low reg in low byte,
409 * high reg in next byte.
410 */
411int X86Mir2Lir::AllocTypedTempPair(bool fp_hint,
412                          int reg_class) {
413  int high_reg;
414  int low_reg;
415  int res = 0;
416
417  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
418    low_reg = AllocTempDouble();
419    high_reg = low_reg;  // only one allocated!
420    res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
421    return res;
422  }
423
424  low_reg = AllocTemp();
425  high_reg = AllocTemp();
426  res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
427  return res;
428}
429
430int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
431  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
432    return AllocTempFloat();
433  }
434  return AllocTemp();
435}
436
437void X86Mir2Lir::CompilerInitializeRegAlloc() {
438  int num_regs = sizeof(core_regs)/sizeof(*core_regs);
439  int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
440  int num_temps = sizeof(core_temps)/sizeof(*core_temps);
441  int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs);
442  int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps);
443  reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_),
444                                                       ArenaAllocator::kAllocRegAlloc));
445  reg_pool_->num_core_regs = num_regs;
446  reg_pool_->core_regs =
447      static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs),
448                                               ArenaAllocator::kAllocRegAlloc));
449  reg_pool_->num_fp_regs = num_fp_regs;
450  reg_pool_->FPRegs =
451      static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs),
452                                                ArenaAllocator::kAllocRegAlloc));
453  CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs);
454  CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs);
455  // Keep special registers from being allocated
456  for (int i = 0; i < num_reserved; i++) {
457    MarkInUse(ReservedRegs[i]);
458  }
459  // Mark temp regs - all others not in use can be used for promotion
460  for (int i = 0; i < num_temps; i++) {
461    MarkTemp(core_temps[i]);
462  }
463  for (int i = 0; i < num_fp_temps; i++) {
464    MarkTemp(fp_temps[i]);
465  }
466}
467
468void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep,
469                     RegLocation rl_free) {
470  if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
471      (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
472    // No overlap, free both
473    FreeTemp(rl_free.low_reg);
474    FreeTemp(rl_free.high_reg);
475  }
476}
477
478void X86Mir2Lir::SpillCoreRegs() {
479  if (num_core_spills_ == 0) {
480    return;
481  }
482  // Spill mask not including fake return address register
483  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
484  int offset = frame_size_ - (4 * num_core_spills_);
485  for (int reg = 0; mask; mask >>= 1, reg++) {
486    if (mask & 0x1) {
487      StoreWordDisp(rX86_SP, offset, reg);
488      offset += 4;
489    }
490  }
491}
492
493void X86Mir2Lir::UnSpillCoreRegs() {
494  if (num_core_spills_ == 0) {
495    return;
496  }
497  // Spill mask not including fake return address register
498  uint32_t mask = core_spill_mask_ & ~(1 << rRET);
499  int offset = frame_size_ - (4 * num_core_spills_);
500  for (int reg = 0; mask; mask >>= 1, reg++) {
501    if (mask & 0x1) {
502      LoadWordDisp(rX86_SP, offset, reg);
503      offset += 4;
504    }
505  }
506}
507
508bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) {
509  return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
510}
511
512X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)
513    : Mir2Lir(cu, mir_graph, arena),
514      method_address_insns_(arena, 100, kGrowableArrayMisc),
515      class_type_address_insns_(arena, 100, kGrowableArrayMisc),
516      call_method_insns_(arena, 100, kGrowableArrayMisc) {
517  store_method_addr_used_ = false;
518  for (int i = 0; i < kX86Last; i++) {
519    if (X86Mir2Lir::EncodingMap[i].opcode != i) {
520      LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name
521                 << " is wrong: expecting " << i << ", seeing "
522                 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
523    }
524  }
525}
526
527Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
528                          ArenaAllocator* const arena) {
529  return new X86Mir2Lir(cu, mir_graph, arena);
530}
531
532// Not used in x86
533int X86Mir2Lir::LoadHelper(ThreadOffset offset) {
534  LOG(FATAL) << "Unexpected use of LoadHelper in x86";
535  return INVALID_REG;
536}
537
538uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) {
539  DCHECK(!IsPseudoLirOp(opcode));
540  return X86Mir2Lir::EncodingMap[opcode].flags;
541}
542
543const char* X86Mir2Lir::GetTargetInstName(int opcode) {
544  DCHECK(!IsPseudoLirOp(opcode));
545  return X86Mir2Lir::EncodingMap[opcode].name;
546}
547
548const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
549  DCHECK(!IsPseudoLirOp(opcode));
550  return X86Mir2Lir::EncodingMap[opcode].fmt;
551}
552
553/*
554 * Return an updated location record with current in-register status.
555 * If the value lives in live temps, reflect that fact.  No code
556 * is generated.  If the live value is part of an older pair,
557 * clobber both low and high.
558 */
559// TODO: Reunify with common code after 'pair mess' has been fixed
560RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) {
561  DCHECK(loc.wide);
562  DCHECK(CheckCorePoolSanity());
563  if (loc.location != kLocPhysReg) {
564    DCHECK((loc.location == kLocDalvikFrame) ||
565         (loc.location == kLocCompilerTemp));
566    // Are the dalvik regs already live in physical registers?
567    RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg);
568
569    // Handle FP registers specially on x86.
570    if (info_lo && IsFpReg(info_lo->reg)) {
571      bool match = true;
572
573      // We can't match a FP register with a pair of Core registers.
574      match = match && (info_lo->pair == 0);
575
576      if (match) {
577        // We can reuse;update the register usage info.
578        loc.low_reg = info_lo->reg;
579        loc.high_reg = info_lo->reg;  // Play nice with existing code.
580        loc.location = kLocPhysReg;
581        loc.vec_len = kVectorLength8;
582        DCHECK(IsFpReg(loc.low_reg));
583        return loc;
584      }
585      // We can't easily reuse; clobber and free any overlaps.
586      if (info_lo) {
587        Clobber(info_lo->reg);
588        FreeTemp(info_lo->reg);
589        if (info_lo->pair)
590          Clobber(info_lo->partner);
591      }
592    } else {
593      RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg);
594      bool match = true;
595      match = match && (info_lo != NULL);
596      match = match && (info_hi != NULL);
597      // Are they both core or both FP?
598      match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg));
599      // If a pair of floating point singles, are they properly aligned?
600      if (match && IsFpReg(info_lo->reg)) {
601        match &= ((info_lo->reg & 0x1) == 0);
602        match &= ((info_hi->reg - info_lo->reg) == 1);
603      }
604      // If previously used as a pair, it is the same pair?
605      if (match && (info_lo->pair || info_hi->pair)) {
606        match = (info_lo->pair == info_hi->pair);
607        match &= ((info_lo->reg == info_hi->partner) &&
608              (info_hi->reg == info_lo->partner));
609      }
610      if (match) {
611        // Can reuse - update the register usage info
612        loc.low_reg = info_lo->reg;
613        loc.high_reg = info_hi->reg;
614        loc.location = kLocPhysReg;
615        MarkPair(loc.low_reg, loc.high_reg);
616        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
617        return loc;
618      }
619      // Can't easily reuse - clobber and free any overlaps
620      if (info_lo) {
621        Clobber(info_lo->reg);
622        FreeTemp(info_lo->reg);
623        if (info_lo->pair)
624          Clobber(info_lo->partner);
625      }
626      if (info_hi) {
627        Clobber(info_hi->reg);
628        FreeTemp(info_hi->reg);
629        if (info_hi->pair)
630          Clobber(info_hi->partner);
631      }
632    }
633  }
634  return loc;
635}
636
637// TODO: Reunify with common code after 'pair mess' has been fixed
638RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) {
639  DCHECK(loc.wide);
640  int32_t new_regs;
641  int32_t low_reg;
642  int32_t high_reg;
643
644  loc = UpdateLocWide(loc);
645
646  /* If it is already in a register, we can assume proper form.  Is it the right reg class? */
647  if (loc.location == kLocPhysReg) {
648    DCHECK_EQ(IsFpReg(loc.low_reg), loc.IsVectorScalar());
649    if (!RegClassMatches(reg_class, loc.low_reg)) {
650      /* It is the wrong register class.  Reallocate and copy. */
651      if (!IsFpReg(loc.low_reg)) {
652        // We want this in a FP reg, and it is in core registers.
653        DCHECK(reg_class != kCoreReg);
654        // Allocate this into any FP reg, and mark it with the right size.
655        low_reg = AllocTypedTemp(true, reg_class);
656        OpVectorRegCopyWide(low_reg, loc.low_reg, loc.high_reg);
657        CopyRegInfo(low_reg, loc.low_reg);
658        Clobber(loc.low_reg);
659        Clobber(loc.high_reg);
660        loc.low_reg = low_reg;
661        loc.high_reg = low_reg;  // Play nice with existing code.
662        loc.vec_len = kVectorLength8;
663      } else {
664        // The value is in a FP register, and we want it in a pair of core registers.
665        DCHECK_EQ(reg_class, kCoreReg);
666        DCHECK_EQ(loc.low_reg, loc.high_reg);
667        new_regs = AllocTypedTempPair(false, kCoreReg);  // Force to core registers.
668        low_reg = new_regs & 0xff;
669        high_reg = (new_regs >> 8) & 0xff;
670        DCHECK_NE(low_reg, high_reg);
671        OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg);
672        CopyRegInfo(low_reg, loc.low_reg);
673        CopyRegInfo(high_reg, loc.high_reg);
674        Clobber(loc.low_reg);
675        Clobber(loc.high_reg);
676        loc.low_reg = low_reg;
677        loc.high_reg = high_reg;
678        MarkPair(loc.low_reg, loc.high_reg);
679        DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0));
680      }
681    }
682    return loc;
683  }
684
685  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
686  DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG);
687
688  new_regs = AllocTypedTempPair(loc.fp, reg_class);
689  loc.low_reg = new_regs & 0xff;
690  loc.high_reg = (new_regs >> 8) & 0xff;
691
692  if (loc.low_reg == loc.high_reg) {
693    DCHECK(IsFpReg(loc.low_reg));
694    loc.vec_len = kVectorLength8;
695  } else {
696    MarkPair(loc.low_reg, loc.high_reg);
697  }
698  if (update) {
699    loc.location = kLocPhysReg;
700    MarkLive(loc.low_reg, loc.s_reg_low);
701    if (loc.low_reg != loc.high_reg) {
702      MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low));
703    }
704  }
705  return loc;
706}
707
708// TODO: Reunify with common code after 'pair mess' has been fixed
709RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) {
710  int new_reg;
711
712  if (loc.wide)
713    return EvalLocWide(loc, reg_class, update);
714
715  loc = UpdateLoc(loc);
716
717  if (loc.location == kLocPhysReg) {
718    if (!RegClassMatches(reg_class, loc.low_reg)) {
719      /* Wrong register class.  Realloc, copy and transfer ownership. */
720      new_reg = AllocTypedTemp(loc.fp, reg_class);
721      OpRegCopy(new_reg, loc.low_reg);
722      CopyRegInfo(new_reg, loc.low_reg);
723      Clobber(loc.low_reg);
724      loc.low_reg = new_reg;
725      if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
726        loc.vec_len = kVectorLength4;
727    }
728    return loc;
729  }
730
731  DCHECK_NE(loc.s_reg_low, INVALID_SREG);
732
733  new_reg = AllocTypedTemp(loc.fp, reg_class);
734  loc.low_reg = new_reg;
735  if (IsFpReg(loc.low_reg) && reg_class != kCoreReg)
736    loc.vec_len = kVectorLength4;
737
738  if (update) {
739    loc.location = kLocPhysReg;
740    MarkLive(loc.low_reg, loc.s_reg_low);
741  }
742  return loc;
743}
744
745int X86Mir2Lir::AllocTempDouble() {
746  // We really don't need a pair of registers.
747  return AllocTempFloat();
748}
749
750// TODO: Reunify with common code after 'pair mess' has been fixed
751void X86Mir2Lir::ResetDefLocWide(RegLocation rl) {
752  DCHECK(rl.wide);
753  RegisterInfo* p_low = IsTemp(rl.low_reg);
754  if (IsFpReg(rl.low_reg)) {
755    // We are using only the low register.
756    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
757      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
758    }
759    ResetDef(rl.low_reg);
760  } else {
761    RegisterInfo* p_high = IsTemp(rl.high_reg);
762    if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) {
763      DCHECK(p_low->pair);
764      NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low);
765    }
766    if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) {
767      DCHECK(p_high->pair);
768    }
769    ResetDef(rl.low_reg);
770    ResetDef(rl.high_reg);
771  }
772}
773
774void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) {
775  // Can we do this directly to memory?
776  rl_dest = UpdateLocWide(rl_dest);
777  if ((rl_dest.location == kLocDalvikFrame) ||
778      (rl_dest.location == kLocCompilerTemp)) {
779    int32_t val_lo = Low32Bits(value);
780    int32_t val_hi = High32Bits(value);
781    int rBase = TargetReg(kSp);
782    int displacement = SRegOffset(rl_dest.s_reg_low);
783
784    LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo);
785    AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2,
786                              false /* is_load */, true /* is64bit */);
787    store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi);
788    AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2,
789                              false /* is_load */, true /* is64bit */);
790    return;
791  }
792
793  // Just use the standard code to do the generation.
794  Mir2Lir::GenConstWide(rl_dest, value);
795}
796
797// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc
798void X86Mir2Lir::DumpRegLocation(RegLocation loc) {
799  LOG(INFO)  << "location: " << loc.location << ','
800             << (loc.wide ? " w" : "  ")
801             << (loc.defined ? " D" : "  ")
802             << (loc.is_const ? " c" : "  ")
803             << (loc.fp ? " F" : "  ")
804             << (loc.core ? " C" : "  ")
805             << (loc.ref ? " r" : "  ")
806             << (loc.high_word ? " h" : "  ")
807             << (loc.home ? " H" : "  ")
808             << " vec_len: " << loc.vec_len
809             << ", low: " << static_cast<int>(loc.low_reg)
810             << ", high: " << static_cast<int>(loc.high_reg)
811             << ", s_reg: " << loc.s_reg_low
812             << ", orig: " << loc.orig_sreg;
813}
814
815void X86Mir2Lir::Materialize() {
816  // A good place to put the analysis before starting.
817  AnalyzeMIR();
818
819  // Now continue with regular code generation.
820  Mir2Lir::Materialize();
821}
822
823void X86Mir2Lir::LoadMethodAddress(int dex_method_index, InvokeType type,
824                                   SpecialTargetRegister symbolic_reg) {
825  /*
826   * For x86, just generate a 32 bit move immediate instruction, that will be filled
827   * in at 'link time'.  For now, put a unique value based on target to ensure that
828   * code deduplication works.
829   */
830  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
831  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
832
833  // Generate the move instruction with the unique pointer and save index and type.
834  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
835                     static_cast<int>(ptr), dex_method_index, type);
836  AppendLIR(move);
837  method_address_insns_.Insert(move);
838}
839
840void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) {
841  /*
842   * For x86, just generate a 32 bit move immediate instruction, that will be filled
843   * in at 'link time'.  For now, put a unique value based on target to ensure that
844   * code deduplication works.
845   */
846  const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx);
847  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
848
849  // Generate the move instruction with the unique pointer and save index and type.
850  LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg),
851                     static_cast<int>(ptr), type_idx);
852  AppendLIR(move);
853  class_type_address_insns_.Insert(move);
854}
855
856LIR *X86Mir2Lir::CallWithLinkerFixup(int dex_method_index, InvokeType type) {
857  /*
858   * For x86, just generate a 32 bit call relative instruction, that will be filled
859   * in at 'link time'.  For now, put a unique value based on target to ensure that
860   * code deduplication works.
861   */
862  const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index);
863  uintptr_t ptr = reinterpret_cast<uintptr_t>(&id);
864
865  // Generate the call instruction with the unique pointer and save index and type.
866  LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(ptr), dex_method_index,
867                     type);
868  AppendLIR(call);
869  call_method_insns_.Insert(call);
870  return call;
871}
872
873void X86Mir2Lir::InstallLiteralPools() {
874  // These are handled differently for x86.
875  DCHECK(code_literal_list_ == nullptr);
876  DCHECK(method_literal_list_ == nullptr);
877  DCHECK(class_literal_list_ == nullptr);
878
879  // Handle the fixups for methods.
880  for (uint32_t i = 0; i < method_address_insns_.Size(); i++) {
881      LIR* p = method_address_insns_.Get(i);
882      DCHECK_EQ(p->opcode, kX86Mov32RI);
883      uint32_t target = p->operands[2];
884
885      // The offset to patch is the last 4 bytes of the instruction.
886      int patch_offset = p->offset + p->flags.size - 4;
887      cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx,
888                                           cu_->method_idx, cu_->invoke_type,
889                                           target, static_cast<InvokeType>(p->operands[3]),
890                                           patch_offset);
891  }
892
893  // Handle the fixups for class types.
894  for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) {
895      LIR* p = class_type_address_insns_.Get(i);
896      DCHECK_EQ(p->opcode, kX86Mov32RI);
897      uint32_t target = p->operands[2];
898
899      // The offset to patch is the last 4 bytes of the instruction.
900      int patch_offset = p->offset + p->flags.size - 4;
901      cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx,
902                                          cu_->method_idx, target, patch_offset);
903  }
904
905  // And now the PC-relative calls to methods.
906  for (uint32_t i = 0; i < call_method_insns_.Size(); i++) {
907      LIR* p = call_method_insns_.Get(i);
908      DCHECK_EQ(p->opcode, kX86CallI);
909      uint32_t target = p->operands[1];
910
911      // The offset to patch is the last 4 bytes of the instruction.
912      int patch_offset = p->offset + p->flags.size - 4;
913      cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx,
914                                                 cu_->method_idx, cu_->invoke_type, target,
915                                                 static_cast<InvokeType>(p->operands[2]),
916                                                 patch_offset, -4 /* offset */);
917  }
918
919  // And do the normal processing.
920  Mir2Lir::InstallLiteralPools();
921}
922
923}  // namespace art
924