target_x86.cc revision 70b797d998f2a28e39f7d6ffc8a07c9cbc47da14
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/compiler_internals.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "x86_lir.h" 21 22#include <string> 23 24namespace art { 25 26// FIXME: restore "static" when usage uncovered 27/*static*/ int core_regs[] = { 28 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 29#ifdef TARGET_REX_SUPPORT 30 r8, r9, r10, r11, r12, r13, r14, 15 31#endif 32}; 33/*static*/ int ReservedRegs[] = {rX86_SP}; 34/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 35/*static*/ int FpRegs[] = { 36 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 37#ifdef TARGET_REX_SUPPORT 38 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 39#endif 40}; 41/*static*/ int fp_temps[] = { 42 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 43#ifdef TARGET_REX_SUPPORT 44 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 45#endif 46}; 47 48RegLocation X86Mir2Lir::LocCReturn() { 49 RegLocation res = X86_LOC_C_RETURN; 50 return res; 51} 52 53RegLocation X86Mir2Lir::LocCReturnWide() { 54 RegLocation res = X86_LOC_C_RETURN_WIDE; 55 return res; 56} 57 58RegLocation X86Mir2Lir::LocCReturnFloat() { 59 RegLocation res = X86_LOC_C_RETURN_FLOAT; 60 return res; 61} 62 63RegLocation X86Mir2Lir::LocCReturnDouble() { 64 RegLocation res = X86_LOC_C_RETURN_DOUBLE; 65 return res; 66} 67 68// Return a target-dependent special register. 69int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 70 int res = INVALID_REG; 71 switch (reg) { 72 case kSelf: res = rX86_SELF; break; 73 case kSuspend: res = rX86_SUSPEND; break; 74 case kLr: res = rX86_LR; break; 75 case kPc: res = rX86_PC; break; 76 case kSp: res = rX86_SP; break; 77 case kArg0: res = rX86_ARG0; break; 78 case kArg1: res = rX86_ARG1; break; 79 case kArg2: res = rX86_ARG2; break; 80 case kArg3: res = rX86_ARG3; break; 81 case kFArg0: res = rX86_FARG0; break; 82 case kFArg1: res = rX86_FARG1; break; 83 case kFArg2: res = rX86_FARG2; break; 84 case kFArg3: res = rX86_FARG3; break; 85 case kRet0: res = rX86_RET0; break; 86 case kRet1: res = rX86_RET1; break; 87 case kInvokeTgt: res = rX86_INVOKE_TGT; break; 88 case kHiddenArg: res = rAX; break; 89 case kHiddenFpArg: res = fr0; break; 90 case kCount: res = rX86_COUNT; break; 91 } 92 return res; 93} 94 95// Create a double from a pair of singles. 96int X86Mir2Lir::S2d(int low_reg, int high_reg) { 97 return X86_S2D(low_reg, high_reg); 98} 99 100// Return mask to strip off fp reg flags and bias. 101uint32_t X86Mir2Lir::FpRegMask() { 102 return X86_FP_REG_MASK; 103} 104 105// True if both regs single, both core or both double. 106bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 107 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 108} 109 110/* 111 * Decode the register id. 112 */ 113uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 114 uint64_t seed; 115 int shift; 116 int reg_id; 117 118 reg_id = reg & 0xf; 119 /* Double registers in x86 are just a single FP register */ 120 seed = 1; 121 /* FP register starts at bit position 16 */ 122 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 123 /* Expand the double register id into single offset */ 124 shift += reg_id; 125 return (seed << shift); 126} 127 128uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 129 /* 130 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 131 * able to clean up some of the x86/Arm_Mips differences 132 */ 133 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 134 return 0ULL; 135} 136 137void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 138 DCHECK_EQ(cu_->instruction_set, kX86); 139 DCHECK(!lir->flags.use_def_invalid); 140 141 // X86-specific resource map setup here. 142 if (flags & REG_USE_SP) { 143 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 144 } 145 146 if (flags & REG_DEF_SP) { 147 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 148 } 149 150 if (flags & REG_DEFA) { 151 SetupRegMask(&lir->u.m.def_mask, rAX); 152 } 153 154 if (flags & REG_DEFD) { 155 SetupRegMask(&lir->u.m.def_mask, rDX); 156 } 157 if (flags & REG_USEA) { 158 SetupRegMask(&lir->u.m.use_mask, rAX); 159 } 160 161 if (flags & REG_USEC) { 162 SetupRegMask(&lir->u.m.use_mask, rCX); 163 } 164 165 if (flags & REG_USED) { 166 SetupRegMask(&lir->u.m.use_mask, rDX); 167 } 168 169 if (flags & REG_USEB) { 170 SetupRegMask(&lir->u.m.use_mask, rBX); 171 } 172} 173 174/* For dumping instructions */ 175static const char* x86RegName[] = { 176 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 177 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 178}; 179 180static const char* x86CondName[] = { 181 "O", 182 "NO", 183 "B/NAE/C", 184 "NB/AE/NC", 185 "Z/EQ", 186 "NZ/NE", 187 "BE/NA", 188 "NBE/A", 189 "S", 190 "NS", 191 "P/PE", 192 "NP/PO", 193 "L/NGE", 194 "NL/GE", 195 "LE/NG", 196 "NLE/G" 197}; 198 199/* 200 * Interpret a format string and build a string no longer than size 201 * See format key in Assemble.cc. 202 */ 203std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 204 std::string buf; 205 size_t i = 0; 206 size_t fmt_len = strlen(fmt); 207 while (i < fmt_len) { 208 if (fmt[i] != '!') { 209 buf += fmt[i]; 210 i++; 211 } else { 212 i++; 213 DCHECK_LT(i, fmt_len); 214 char operand_number_ch = fmt[i]; 215 i++; 216 if (operand_number_ch == '!') { 217 buf += "!"; 218 } else { 219 int operand_number = operand_number_ch - '0'; 220 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 221 DCHECK_LT(i, fmt_len); 222 int operand = lir->operands[operand_number]; 223 switch (fmt[i]) { 224 case 'c': 225 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 226 buf += x86CondName[operand]; 227 break; 228 case 'd': 229 buf += StringPrintf("%d", operand); 230 break; 231 case 'p': { 232 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 233 buf += StringPrintf("0x%08x", tab_rec->offset); 234 break; 235 } 236 case 'r': 237 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 238 int fp_reg = operand & X86_FP_REG_MASK; 239 buf += StringPrintf("xmm%d", fp_reg); 240 } else { 241 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 242 buf += x86RegName[operand]; 243 } 244 break; 245 case 't': 246 buf += StringPrintf("0x%08x (L%p)", 247 reinterpret_cast<uintptr_t>(base_addr) 248 + lir->offset + operand, lir->target); 249 break; 250 default: 251 buf += StringPrintf("DecodeError '%c'", fmt[i]); 252 break; 253 } 254 i++; 255 } 256 } 257 } 258 return buf; 259} 260 261void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 262 char buf[256]; 263 buf[0] = 0; 264 265 if (mask == ENCODE_ALL) { 266 strcpy(buf, "all"); 267 } else { 268 char num[8]; 269 int i; 270 271 for (i = 0; i < kX86RegEnd; i++) { 272 if (mask & (1ULL << i)) { 273 sprintf(num, "%d ", i); 274 strcat(buf, num); 275 } 276 } 277 278 if (mask & ENCODE_CCODE) { 279 strcat(buf, "cc "); 280 } 281 /* Memory bits */ 282 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 283 sprintf(buf + strlen(buf), "dr%d%s", DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 284 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 285 } 286 if (mask & ENCODE_LITERAL) { 287 strcat(buf, "lit "); 288 } 289 290 if (mask & ENCODE_HEAP_REF) { 291 strcat(buf, "heap "); 292 } 293 if (mask & ENCODE_MUST_NOT_ALIAS) { 294 strcat(buf, "noalias "); 295 } 296 } 297 if (buf[0]) { 298 LOG(INFO) << prefix << ": " << buf; 299 } 300} 301 302void X86Mir2Lir::AdjustSpillMask() { 303 // Adjustment for LR spilling, x86 has no LR so nothing to do here 304 core_spill_mask_ |= (1 << rRET); 305 num_core_spills_++; 306} 307 308/* 309 * Mark a callee-save fp register as promoted. Note that 310 * vpush/vpop uses contiguous register lists so we must 311 * include any holes in the mask. Associate holes with 312 * Dalvik register INVALID_VREG (0xFFFFU). 313 */ 314void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 315 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 316#if 0 317 LOG(FATAL) << "No support yet for promoted FP regs"; 318#endif 319} 320 321void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { 322 RegisterInfo* info1 = GetRegInfo(reg1); 323 RegisterInfo* info2 = GetRegInfo(reg2); 324 DCHECK(info1 && info2 && info1->pair && info2->pair && 325 (info1->partner == info2->reg) && 326 (info2->partner == info1->reg)); 327 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 328 if (!(info1->is_temp && info2->is_temp)) { 329 /* Should not happen. If it does, there's a problem in eval_loc */ 330 LOG(FATAL) << "Long half-temp, half-promoted"; 331 } 332 333 info1->dirty = false; 334 info2->dirty = false; 335 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 336 info1 = info2; 337 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 338 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); 339 } 340} 341 342void X86Mir2Lir::FlushReg(int reg) { 343 RegisterInfo* info = GetRegInfo(reg); 344 if (info->live && info->dirty) { 345 info->dirty = false; 346 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 347 StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); 348 } 349} 350 351/* Give access to the target-dependent FP register encoding to common code */ 352bool X86Mir2Lir::IsFpReg(int reg) { 353 return X86_FPREG(reg); 354} 355 356/* Clobber all regs that might be used by an external C call */ 357void X86Mir2Lir::ClobberCalleeSave() { 358 Clobber(rAX); 359 Clobber(rCX); 360 Clobber(rDX); 361} 362 363RegLocation X86Mir2Lir::GetReturnWideAlt() { 364 RegLocation res = LocCReturnWide(); 365 CHECK(res.low_reg == rAX); 366 CHECK(res.high_reg == rDX); 367 Clobber(rAX); 368 Clobber(rDX); 369 MarkInUse(rAX); 370 MarkInUse(rDX); 371 MarkPair(res.low_reg, res.high_reg); 372 return res; 373} 374 375RegLocation X86Mir2Lir::GetReturnAlt() { 376 RegLocation res = LocCReturn(); 377 res.low_reg = rDX; 378 Clobber(rDX); 379 MarkInUse(rDX); 380 return res; 381} 382 383/* To be used when explicitly managing register use */ 384void X86Mir2Lir::LockCallTemps() { 385 LockTemp(rX86_ARG0); 386 LockTemp(rX86_ARG1); 387 LockTemp(rX86_ARG2); 388 LockTemp(rX86_ARG3); 389} 390 391/* To be used when explicitly managing register use */ 392void X86Mir2Lir::FreeCallTemps() { 393 FreeTemp(rX86_ARG0); 394 FreeTemp(rX86_ARG1); 395 FreeTemp(rX86_ARG2); 396 FreeTemp(rX86_ARG3); 397} 398 399void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 400#if ANDROID_SMP != 0 401 // TODO: optimize fences 402 NewLIR0(kX86Mfence); 403#endif 404} 405/* 406 * Alloc a pair of core registers, or a double. Low reg in low byte, 407 * high reg in next byte. 408 */ 409int X86Mir2Lir::AllocTypedTempPair(bool fp_hint, 410 int reg_class) { 411 int high_reg; 412 int low_reg; 413 int res = 0; 414 415 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 416 low_reg = AllocTempDouble(); 417 high_reg = low_reg + 1; 418 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 419 return res; 420 } 421 422 low_reg = AllocTemp(); 423 high_reg = AllocTemp(); 424 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 425 return res; 426} 427 428int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 429 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 430 return AllocTempFloat(); 431 } 432 return AllocTemp(); 433} 434 435void X86Mir2Lir::CompilerInitializeRegAlloc() { 436 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 437 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 438 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 439 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 440 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 441 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 442 ArenaAllocator::kAllocRegAlloc)); 443 reg_pool_->num_core_regs = num_regs; 444 reg_pool_->core_regs = 445 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 446 ArenaAllocator::kAllocRegAlloc)); 447 reg_pool_->num_fp_regs = num_fp_regs; 448 reg_pool_->FPRegs = 449 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 450 ArenaAllocator::kAllocRegAlloc)); 451 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 452 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 453 // Keep special registers from being allocated 454 for (int i = 0; i < num_reserved; i++) { 455 MarkInUse(ReservedRegs[i]); 456 } 457 // Mark temp regs - all others not in use can be used for promotion 458 for (int i = 0; i < num_temps; i++) { 459 MarkTemp(core_temps[i]); 460 } 461 for (int i = 0; i < num_fp_temps; i++) { 462 MarkTemp(fp_temps[i]); 463 } 464} 465 466void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, 467 RegLocation rl_free) { 468 if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) && 469 (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) { 470 // No overlap, free both 471 FreeTemp(rl_free.low_reg); 472 FreeTemp(rl_free.high_reg); 473 } 474} 475 476void X86Mir2Lir::SpillCoreRegs() { 477 if (num_core_spills_ == 0) { 478 return; 479 } 480 // Spill mask not including fake return address register 481 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 482 int offset = frame_size_ - (4 * num_core_spills_); 483 for (int reg = 0; mask; mask >>= 1, reg++) { 484 if (mask & 0x1) { 485 StoreWordDisp(rX86_SP, offset, reg); 486 offset += 4; 487 } 488 } 489} 490 491void X86Mir2Lir::UnSpillCoreRegs() { 492 if (num_core_spills_ == 0) { 493 return; 494 } 495 // Spill mask not including fake return address register 496 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 497 int offset = frame_size_ - (4 * num_core_spills_); 498 for (int reg = 0; mask; mask >>= 1, reg++) { 499 if (mask & 0x1) { 500 LoadWordDisp(rX86_SP, offset, reg); 501 offset += 4; 502 } 503 } 504} 505 506bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 507 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 508} 509 510X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 511 : Mir2Lir(cu, mir_graph, arena) { 512 for (int i = 0; i < kX86Last; i++) { 513 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 514 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 515 << " is wrong: expecting " << i << ", seeing " 516 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 517 } 518 } 519} 520 521Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 522 ArenaAllocator* const arena) { 523 return new X86Mir2Lir(cu, mir_graph, arena); 524} 525 526// Not used in x86 527int X86Mir2Lir::LoadHelper(ThreadOffset offset) { 528 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 529 return INVALID_REG; 530} 531 532uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 533 DCHECK(!IsPseudoLirOp(opcode)); 534 return X86Mir2Lir::EncodingMap[opcode].flags; 535} 536 537const char* X86Mir2Lir::GetTargetInstName(int opcode) { 538 DCHECK(!IsPseudoLirOp(opcode)); 539 return X86Mir2Lir::EncodingMap[opcode].name; 540} 541 542const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 543 DCHECK(!IsPseudoLirOp(opcode)); 544 return X86Mir2Lir::EncodingMap[opcode].fmt; 545} 546 547} // namespace art 548